1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SystemZTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZISelLowering.h"
14 #include "SystemZCallingConv.h"
15 #include "SystemZConstantPoolValue.h"
16 #include "SystemZMachineFunctionInfo.h"
17 #include "SystemZTargetMachine.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/IR/IntrinsicInst.h"
23 #include "llvm/IR/Intrinsics.h"
24 #include "llvm/IR/IntrinsicsS390.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/KnownBits.h"
27 #include <cctype>
28
29 using namespace llvm;
30
31 #define DEBUG_TYPE "systemz-lower"
32
33 namespace {
34 // Represents information about a comparison.
35 struct Comparison {
Comparison__anonc30c8ddf0111::Comparison36 Comparison(SDValue Op0In, SDValue Op1In, SDValue ChainIn)
37 : Op0(Op0In), Op1(Op1In), Chain(ChainIn),
38 Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
39
40 // The operands to the comparison.
41 SDValue Op0, Op1;
42
43 // Chain if this is a strict floating-point comparison.
44 SDValue Chain;
45
46 // The opcode that should be used to compare Op0 and Op1.
47 unsigned Opcode;
48
49 // A SystemZICMP value. Only used for integer comparisons.
50 unsigned ICmpType;
51
52 // The mask of CC values that Opcode can produce.
53 unsigned CCValid;
54
55 // The mask of CC values for which the original condition is true.
56 unsigned CCMask;
57 };
58 } // end anonymous namespace
59
60 // Classify VT as either 32 or 64 bit.
is32Bit(EVT VT)61 static bool is32Bit(EVT VT) {
62 switch (VT.getSimpleVT().SimpleTy) {
63 case MVT::i32:
64 return true;
65 case MVT::i64:
66 return false;
67 default:
68 llvm_unreachable("Unsupported type");
69 }
70 }
71
72 // Return a version of MachineOperand that can be safely used before the
73 // final use.
earlyUseOperand(MachineOperand Op)74 static MachineOperand earlyUseOperand(MachineOperand Op) {
75 if (Op.isReg())
76 Op.setIsKill(false);
77 return Op;
78 }
79
SystemZTargetLowering(const TargetMachine & TM,const SystemZSubtarget & STI)80 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
81 const SystemZSubtarget &STI)
82 : TargetLowering(TM), Subtarget(STI) {
83 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));
84
85 // Set up the register classes.
86 if (Subtarget.hasHighWord())
87 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
88 else
89 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
90 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
91 if (!useSoftFloat()) {
92 if (Subtarget.hasVector()) {
93 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
94 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
95 } else {
96 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
98 }
99 if (Subtarget.hasVectorEnhancements1())
100 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
101 else
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
103
104 if (Subtarget.hasVector()) {
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
106 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
107 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
109 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
110 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
111 }
112 }
113
114 // Compute derived properties from the register classes
115 computeRegisterProperties(Subtarget.getRegisterInfo());
116
117 // Set up special registers.
118 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
119
120 // TODO: It may be better to default to latency-oriented scheduling, however
121 // LLVM's current latency-oriented scheduler can't handle physreg definitions
122 // such as SystemZ has with CC, so set this to the register-pressure
123 // scheduler, because it can.
124 setSchedulingPreference(Sched::RegPressure);
125
126 setBooleanContents(ZeroOrOneBooleanContent);
127 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
128
129 // Instructions are strings of 2-byte aligned 2-byte values.
130 setMinFunctionAlignment(Align(2));
131 // For performance reasons we prefer 16-byte alignment.
132 setPrefFunctionAlignment(Align(16));
133
134 // Handle operations that are handled in a similar way for all types.
135 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
136 I <= MVT::LAST_FP_VALUETYPE;
137 ++I) {
138 MVT VT = MVT::SimpleValueType(I);
139 if (isTypeLegal(VT)) {
140 // Lower SET_CC into an IPM-based sequence.
141 setOperationAction(ISD::SETCC, VT, Custom);
142 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
143 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
144
145 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
146 setOperationAction(ISD::SELECT, VT, Expand);
147
148 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
149 setOperationAction(ISD::SELECT_CC, VT, Custom);
150 setOperationAction(ISD::BR_CC, VT, Custom);
151 }
152 }
153
154 // Expand jump table branches as address arithmetic followed by an
155 // indirect jump.
156 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
157
158 // Expand BRCOND into a BR_CC (see above).
159 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
160
161 // Handle integer types.
162 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
163 I <= MVT::LAST_INTEGER_VALUETYPE;
164 ++I) {
165 MVT VT = MVT::SimpleValueType(I);
166 if (isTypeLegal(VT)) {
167 setOperationAction(ISD::ABS, VT, Legal);
168
169 // Expand individual DIV and REMs into DIVREMs.
170 setOperationAction(ISD::SDIV, VT, Expand);
171 setOperationAction(ISD::UDIV, VT, Expand);
172 setOperationAction(ISD::SREM, VT, Expand);
173 setOperationAction(ISD::UREM, VT, Expand);
174 setOperationAction(ISD::SDIVREM, VT, Custom);
175 setOperationAction(ISD::UDIVREM, VT, Custom);
176
177 // Support addition/subtraction with overflow.
178 setOperationAction(ISD::SADDO, VT, Custom);
179 setOperationAction(ISD::SSUBO, VT, Custom);
180
181 // Support addition/subtraction with carry.
182 setOperationAction(ISD::UADDO, VT, Custom);
183 setOperationAction(ISD::USUBO, VT, Custom);
184
185 // Support carry in as value rather than glue.
186 setOperationAction(ISD::ADDCARRY, VT, Custom);
187 setOperationAction(ISD::SUBCARRY, VT, Custom);
188
189 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
190 // stores, putting a serialization instruction after the stores.
191 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
192 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
193
194 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
195 // available, or if the operand is constant.
196 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
197
198 // Use POPCNT on z196 and above.
199 if (Subtarget.hasPopulationCount())
200 setOperationAction(ISD::CTPOP, VT, Custom);
201 else
202 setOperationAction(ISD::CTPOP, VT, Expand);
203
204 // No special instructions for these.
205 setOperationAction(ISD::CTTZ, VT, Expand);
206 setOperationAction(ISD::ROTR, VT, Expand);
207
208 // Use *MUL_LOHI where possible instead of MULH*.
209 setOperationAction(ISD::MULHS, VT, Expand);
210 setOperationAction(ISD::MULHU, VT, Expand);
211 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
212 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
213
214 // Only z196 and above have native support for conversions to unsigned.
215 // On z10, promoting to i64 doesn't generate an inexact condition for
216 // values that are outside the i32 range but in the i64 range, so use
217 // the default expansion.
218 if (!Subtarget.hasFPExtension())
219 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
220
221 // Mirror those settings for STRICT_FP_TO_[SU]INT. Note that these all
222 // default to Expand, so need to be modified to Legal where appropriate.
223 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Legal);
224 if (Subtarget.hasFPExtension())
225 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Legal);
226
227 // And similarly for STRICT_[SU]INT_TO_FP.
228 setOperationAction(ISD::STRICT_SINT_TO_FP, VT, Legal);
229 if (Subtarget.hasFPExtension())
230 setOperationAction(ISD::STRICT_UINT_TO_FP, VT, Legal);
231 }
232 }
233
234 // Type legalization will convert 8- and 16-bit atomic operations into
235 // forms that operate on i32s (but still keeping the original memory VT).
236 // Lower them into full i32 operations.
237 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
238 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
239 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
240 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
241 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
242 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
243 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
244 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
245 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
246 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
247 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
248
249 // Even though i128 is not a legal type, we still need to custom lower
250 // the atomic operations in order to exploit SystemZ instructions.
251 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
252 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
253
254 // We can use the CC result of compare-and-swap to implement
255 // the "success" result of ATOMIC_CMP_SWAP_WITH_SUCCESS.
256 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Custom);
257 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Custom);
258 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
259
260 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
261
262 // Traps are legal, as we will convert them to "j .+2".
263 setOperationAction(ISD::TRAP, MVT::Other, Legal);
264
265 // z10 has instructions for signed but not unsigned FP conversion.
266 // Handle unsigned 32-bit types as signed 64-bit types.
267 if (!Subtarget.hasFPExtension()) {
268 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
269 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
270 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Promote);
271 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
272 }
273
274 // We have native support for a 64-bit CTLZ, via FLOGR.
275 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
276 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
277 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
278
279 // On z15 we have native support for a 64-bit CTPOP.
280 if (Subtarget.hasMiscellaneousExtensions3()) {
281 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
282 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
283 }
284
285 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
286 setOperationAction(ISD::OR, MVT::i64, Custom);
287
288 // Expand 128 bit shifts without using a libcall.
289 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
290 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
291 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
292 setLibcallName(RTLIB::SRL_I128, nullptr);
293 setLibcallName(RTLIB::SHL_I128, nullptr);
294 setLibcallName(RTLIB::SRA_I128, nullptr);
295
296 // We have native instructions for i8, i16 and i32 extensions, but not i1.
297 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
298 for (MVT VT : MVT::integer_valuetypes()) {
299 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
300 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
301 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
302 }
303
304 // Handle the various types of symbolic address.
305 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
306 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
307 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
308 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
309 setOperationAction(ISD::JumpTable, PtrVT, Custom);
310
311 // We need to handle dynamic allocations specially because of the
312 // 160-byte area at the bottom of the stack.
313 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
314 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, PtrVT, Custom);
315
316 // Use custom expanders so that we can force the function to use
317 // a frame pointer.
318 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
319 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
320
321 // Handle prefetches with PFD or PFDRL.
322 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
323
324 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
325 // Assume by default that all vector operations need to be expanded.
326 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
327 if (getOperationAction(Opcode, VT) == Legal)
328 setOperationAction(Opcode, VT, Expand);
329
330 // Likewise all truncating stores and extending loads.
331 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
332 setTruncStoreAction(VT, InnerVT, Expand);
333 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
334 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
335 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
336 }
337
338 if (isTypeLegal(VT)) {
339 // These operations are legal for anything that can be stored in a
340 // vector register, even if there is no native support for the format
341 // as such. In particular, we can do these for v4f32 even though there
342 // are no specific instructions for that format.
343 setOperationAction(ISD::LOAD, VT, Legal);
344 setOperationAction(ISD::STORE, VT, Legal);
345 setOperationAction(ISD::VSELECT, VT, Legal);
346 setOperationAction(ISD::BITCAST, VT, Legal);
347 setOperationAction(ISD::UNDEF, VT, Legal);
348
349 // Likewise, except that we need to replace the nodes with something
350 // more specific.
351 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
352 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
353 }
354 }
355
356 // Handle integer vector types.
357 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
358 if (isTypeLegal(VT)) {
359 // These operations have direct equivalents.
360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
361 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
362 setOperationAction(ISD::ADD, VT, Legal);
363 setOperationAction(ISD::SUB, VT, Legal);
364 if (VT != MVT::v2i64)
365 setOperationAction(ISD::MUL, VT, Legal);
366 setOperationAction(ISD::ABS, VT, Legal);
367 setOperationAction(ISD::AND, VT, Legal);
368 setOperationAction(ISD::OR, VT, Legal);
369 setOperationAction(ISD::XOR, VT, Legal);
370 if (Subtarget.hasVectorEnhancements1())
371 setOperationAction(ISD::CTPOP, VT, Legal);
372 else
373 setOperationAction(ISD::CTPOP, VT, Custom);
374 setOperationAction(ISD::CTTZ, VT, Legal);
375 setOperationAction(ISD::CTLZ, VT, Legal);
376
377 // Convert a GPR scalar to a vector by inserting it into element 0.
378 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
379
380 // Use a series of unpacks for extensions.
381 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
382 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
383
384 // Detect shifts by a scalar amount and convert them into
385 // V*_BY_SCALAR.
386 setOperationAction(ISD::SHL, VT, Custom);
387 setOperationAction(ISD::SRA, VT, Custom);
388 setOperationAction(ISD::SRL, VT, Custom);
389
390 // At present ROTL isn't matched by DAGCombiner. ROTR should be
391 // converted into ROTL.
392 setOperationAction(ISD::ROTL, VT, Expand);
393 setOperationAction(ISD::ROTR, VT, Expand);
394
395 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
396 // and inverting the result as necessary.
397 setOperationAction(ISD::SETCC, VT, Custom);
398 setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
399 if (Subtarget.hasVectorEnhancements1())
400 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
401 }
402 }
403
404 if (Subtarget.hasVector()) {
405 // There should be no need to check for float types other than v2f64
406 // since <2 x f32> isn't a legal type.
407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
408 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal);
409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
410 setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal);
411 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
412 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal);
413 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
414 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal);
415
416 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
417 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f64, Legal);
418 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
419 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f64, Legal);
420 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
421 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f64, Legal);
422 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
423 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f64, Legal);
424 }
425
426 if (Subtarget.hasVectorEnhancements2()) {
427 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
428 setOperationAction(ISD::FP_TO_SINT, MVT::v4f32, Legal);
429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
430 setOperationAction(ISD::FP_TO_UINT, MVT::v4f32, Legal);
431 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
434 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal);
435
436 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
437 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4f32, Legal);
438 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
439 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4f32, Legal);
440 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
441 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4f32, Legal);
442 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
443 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4f32, Legal);
444 }
445
446 // Handle floating-point types.
447 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
448 I <= MVT::LAST_FP_VALUETYPE;
449 ++I) {
450 MVT VT = MVT::SimpleValueType(I);
451 if (isTypeLegal(VT)) {
452 // We can use FI for FRINT.
453 setOperationAction(ISD::FRINT, VT, Legal);
454
455 // We can use the extended form of FI for other rounding operations.
456 if (Subtarget.hasFPExtension()) {
457 setOperationAction(ISD::FNEARBYINT, VT, Legal);
458 setOperationAction(ISD::FFLOOR, VT, Legal);
459 setOperationAction(ISD::FCEIL, VT, Legal);
460 setOperationAction(ISD::FTRUNC, VT, Legal);
461 setOperationAction(ISD::FROUND, VT, Legal);
462 }
463
464 // No special instructions for these.
465 setOperationAction(ISD::FSIN, VT, Expand);
466 setOperationAction(ISD::FCOS, VT, Expand);
467 setOperationAction(ISD::FSINCOS, VT, Expand);
468 setOperationAction(ISD::FREM, VT, Expand);
469 setOperationAction(ISD::FPOW, VT, Expand);
470
471 // Handle constrained floating-point operations.
472 setOperationAction(ISD::STRICT_FADD, VT, Legal);
473 setOperationAction(ISD::STRICT_FSUB, VT, Legal);
474 setOperationAction(ISD::STRICT_FMUL, VT, Legal);
475 setOperationAction(ISD::STRICT_FDIV, VT, Legal);
476 setOperationAction(ISD::STRICT_FMA, VT, Legal);
477 setOperationAction(ISD::STRICT_FSQRT, VT, Legal);
478 setOperationAction(ISD::STRICT_FRINT, VT, Legal);
479 setOperationAction(ISD::STRICT_FP_ROUND, VT, Legal);
480 setOperationAction(ISD::STRICT_FP_EXTEND, VT, Legal);
481 if (Subtarget.hasFPExtension()) {
482 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Legal);
483 setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
484 setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
485 setOperationAction(ISD::STRICT_FROUND, VT, Legal);
486 setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
487 }
488 }
489 }
490
491 // Handle floating-point vector types.
492 if (Subtarget.hasVector()) {
493 // Scalar-to-vector conversion is just a subreg.
494 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
495 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
496
497 // Some insertions and extractions can be done directly but others
498 // need to go via integers.
499 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
500 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
501 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
502 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
503
504 // These operations have direct equivalents.
505 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
506 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
507 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
508 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
509 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
510 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
511 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
512 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
513 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
514 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
515 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
516 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
517 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
518 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
519
520 // Handle constrained floating-point operations.
521 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
522 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
523 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
524 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
525 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
526 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
527 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
528 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v2f64, Legal);
529 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
531 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
532 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
533 }
534
535 // The vector enhancements facility 1 has instructions for these.
536 if (Subtarget.hasVectorEnhancements1()) {
537 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
538 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
539 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
540 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
541 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
542 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
543 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
544 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
545 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
546 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
547 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
548 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
549 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
550 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
551
552 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
553 setOperationAction(ISD::FMAXIMUM, MVT::f64, Legal);
554 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
555 setOperationAction(ISD::FMINIMUM, MVT::f64, Legal);
556
557 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal);
558 setOperationAction(ISD::FMAXIMUM, MVT::v2f64, Legal);
559 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
560 setOperationAction(ISD::FMINIMUM, MVT::v2f64, Legal);
561
562 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
563 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
564 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
565 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
566
567 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
568 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
569 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
570 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
571
572 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal);
573 setOperationAction(ISD::FMAXIMUM, MVT::f128, Legal);
574 setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
575 setOperationAction(ISD::FMINIMUM, MVT::f128, Legal);
576
577 // Handle constrained floating-point operations.
578 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
579 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
580 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
581 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
582 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
583 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
584 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
585 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v4f32, Legal);
586 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
587 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
588 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
589 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
590 for (auto VT : { MVT::f32, MVT::f64, MVT::f128,
591 MVT::v4f32, MVT::v2f64 }) {
592 setOperationAction(ISD::STRICT_FMAXNUM, VT, Legal);
593 setOperationAction(ISD::STRICT_FMINNUM, VT, Legal);
594 setOperationAction(ISD::STRICT_FMAXIMUM, VT, Legal);
595 setOperationAction(ISD::STRICT_FMINIMUM, VT, Legal);
596 }
597 }
598
599 // We only have fused f128 multiply-addition on vector registers.
600 if (!Subtarget.hasVectorEnhancements1()) {
601 setOperationAction(ISD::FMA, MVT::f128, Expand);
602 setOperationAction(ISD::STRICT_FMA, MVT::f128, Expand);
603 }
604
605 // We don't have a copysign instruction on vector registers.
606 if (Subtarget.hasVectorEnhancements1())
607 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
608
609 // Needed so that we don't try to implement f128 constant loads using
610 // a load-and-extend of a f80 constant (in cases where the constant
611 // would fit in an f80).
612 for (MVT VT : MVT::fp_valuetypes())
613 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
614
615 // We don't have extending load instruction on vector registers.
616 if (Subtarget.hasVectorEnhancements1()) {
617 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
618 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
619 }
620
621 // Floating-point truncation and stores need to be done separately.
622 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
623 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
624 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
625
626 // We have 64-bit FPR<->GPR moves, but need special handling for
627 // 32-bit forms.
628 if (!Subtarget.hasVector()) {
629 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
630 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
631 }
632
633 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
634 // structure, but VAEND is a no-op.
635 setOperationAction(ISD::VASTART, MVT::Other, Custom);
636 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
637 setOperationAction(ISD::VAEND, MVT::Other, Expand);
638
639 // Codes for which we want to perform some z-specific combinations.
640 setTargetDAGCombine(ISD::ZERO_EXTEND);
641 setTargetDAGCombine(ISD::SIGN_EXTEND);
642 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
643 setTargetDAGCombine(ISD::LOAD);
644 setTargetDAGCombine(ISD::STORE);
645 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
646 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
647 setTargetDAGCombine(ISD::FP_ROUND);
648 setTargetDAGCombine(ISD::STRICT_FP_ROUND);
649 setTargetDAGCombine(ISD::FP_EXTEND);
650 setTargetDAGCombine(ISD::SINT_TO_FP);
651 setTargetDAGCombine(ISD::UINT_TO_FP);
652 setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
653 setTargetDAGCombine(ISD::BSWAP);
654 setTargetDAGCombine(ISD::SDIV);
655 setTargetDAGCombine(ISD::UDIV);
656 setTargetDAGCombine(ISD::SREM);
657 setTargetDAGCombine(ISD::UREM);
658 setTargetDAGCombine(ISD::INTRINSIC_VOID);
659 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
660
661 // Handle intrinsics.
662 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
663 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
664
665 // We want to use MVC in preference to even a single load/store pair.
666 MaxStoresPerMemcpy = 0;
667 MaxStoresPerMemcpyOptSize = 0;
668
669 // The main memset sequence is a byte store followed by an MVC.
670 // Two STC or MV..I stores win over that, but the kind of fused stores
671 // generated by target-independent code don't when the byte value is
672 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
673 // than "STC;MVC". Handle the choice in target-specific code instead.
674 MaxStoresPerMemset = 0;
675 MaxStoresPerMemsetOptSize = 0;
676
677 // Default to having -disable-strictnode-mutation on
678 IsStrictFPEnabled = true;
679 }
680
useSoftFloat() const681 bool SystemZTargetLowering::useSoftFloat() const {
682 return Subtarget.hasSoftFloat();
683 }
684
getSetCCResultType(const DataLayout & DL,LLVMContext &,EVT VT) const685 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
686 LLVMContext &, EVT VT) const {
687 if (!VT.isVector())
688 return MVT::i32;
689 return VT.changeVectorElementTypeToInteger();
690 }
691
isFMAFasterThanFMulAndFAdd(const MachineFunction & MF,EVT VT) const692 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(
693 const MachineFunction &MF, EVT VT) const {
694 VT = VT.getScalarType();
695
696 if (!VT.isSimple())
697 return false;
698
699 switch (VT.getSimpleVT().SimpleTy) {
700 case MVT::f32:
701 case MVT::f64:
702 return true;
703 case MVT::f128:
704 return Subtarget.hasVectorEnhancements1();
705 default:
706 break;
707 }
708
709 return false;
710 }
711
712 // Return true if the constant can be generated with a vector instruction,
713 // such as VGM, VGMB or VREPI.
isVectorConstantLegal(const SystemZSubtarget & Subtarget)714 bool SystemZVectorConstantInfo::isVectorConstantLegal(
715 const SystemZSubtarget &Subtarget) {
716 const SystemZInstrInfo *TII =
717 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
718 if (!Subtarget.hasVector() ||
719 (isFP128 && !Subtarget.hasVectorEnhancements1()))
720 return false;
721
722 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
723 // preferred way of creating all-zero and all-one vectors so give it
724 // priority over other methods below.
725 unsigned Mask = 0;
726 unsigned I = 0;
727 for (; I < SystemZ::VectorBytes; ++I) {
728 uint64_t Byte = IntBits.lshr(I * 8).trunc(8).getZExtValue();
729 if (Byte == 0xff)
730 Mask |= 1ULL << I;
731 else if (Byte != 0)
732 break;
733 }
734 if (I == SystemZ::VectorBytes) {
735 Opcode = SystemZISD::BYTE_MASK;
736 OpVals.push_back(Mask);
737 VecVT = MVT::getVectorVT(MVT::getIntegerVT(8), 16);
738 return true;
739 }
740
741 if (SplatBitSize > 64)
742 return false;
743
744 auto tryValue = [&](uint64_t Value) -> bool {
745 // Try VECTOR REPLICATE IMMEDIATE
746 int64_t SignedValue = SignExtend64(Value, SplatBitSize);
747 if (isInt<16>(SignedValue)) {
748 OpVals.push_back(((unsigned) SignedValue));
749 Opcode = SystemZISD::REPLICATE;
750 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize),
751 SystemZ::VectorBits / SplatBitSize);
752 return true;
753 }
754 // Try VECTOR GENERATE MASK
755 unsigned Start, End;
756 if (TII->isRxSBGMask(Value, SplatBitSize, Start, End)) {
757 // isRxSBGMask returns the bit numbers for a full 64-bit value, with 0
758 // denoting 1 << 63 and 63 denoting 1. Convert them to bit numbers for
759 // an SplatBitSize value, so that 0 denotes 1 << (SplatBitSize-1).
760 OpVals.push_back(Start - (64 - SplatBitSize));
761 OpVals.push_back(End - (64 - SplatBitSize));
762 Opcode = SystemZISD::ROTATE_MASK;
763 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize),
764 SystemZ::VectorBits / SplatBitSize);
765 return true;
766 }
767 return false;
768 };
769
770 // First try assuming that any undefined bits above the highest set bit
771 // and below the lowest set bit are 1s. This increases the likelihood of
772 // being able to use a sign-extended element value in VECTOR REPLICATE
773 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
774 uint64_t SplatBitsZ = SplatBits.getZExtValue();
775 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
776 uint64_t Lower =
777 (SplatUndefZ & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
778 uint64_t Upper =
779 (SplatUndefZ & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
780 if (tryValue(SplatBitsZ | Upper | Lower))
781 return true;
782
783 // Now try assuming that any undefined bits between the first and
784 // last defined set bits are set. This increases the chances of
785 // using a non-wraparound mask.
786 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
787 return tryValue(SplatBitsZ | Middle);
788 }
789
SystemZVectorConstantInfo(APFloat FPImm)790 SystemZVectorConstantInfo::SystemZVectorConstantInfo(APFloat FPImm) {
791 IntBits = FPImm.bitcastToAPInt().zextOrSelf(128);
792 isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
793 SplatBits = FPImm.bitcastToAPInt();
794 unsigned Width = SplatBits.getBitWidth();
795 IntBits <<= (SystemZ::VectorBits - Width);
796
797 // Find the smallest splat.
798 while (Width > 8) {
799 unsigned HalfSize = Width / 2;
800 APInt HighValue = SplatBits.lshr(HalfSize).trunc(HalfSize);
801 APInt LowValue = SplatBits.trunc(HalfSize);
802
803 // If the two halves do not match, stop here.
804 if (HighValue != LowValue || 8 > HalfSize)
805 break;
806
807 SplatBits = HighValue;
808 Width = HalfSize;
809 }
810 SplatUndef = 0;
811 SplatBitSize = Width;
812 }
813
SystemZVectorConstantInfo(BuildVectorSDNode * BVN)814 SystemZVectorConstantInfo::SystemZVectorConstantInfo(BuildVectorSDNode *BVN) {
815 assert(BVN->isConstant() && "Expected a constant BUILD_VECTOR");
816 bool HasAnyUndefs;
817
818 // Get IntBits by finding the 128 bit splat.
819 BVN->isConstantSplat(IntBits, SplatUndef, SplatBitSize, HasAnyUndefs, 128,
820 true);
821
822 // Get SplatBits by finding the 8 bit or greater splat.
823 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs, 8,
824 true);
825 }
826
isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const827 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
828 bool ForCodeSize) const {
829 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
830 if (Imm.isZero() || Imm.isNegZero())
831 return true;
832
833 return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
834 }
835
836 /// Returns true if stack probing through inline assembly is requested.
hasInlineStackProbe(MachineFunction & MF) const837 bool SystemZTargetLowering::hasInlineStackProbe(MachineFunction &MF) const {
838 // If the function specifically requests inline stack probes, emit them.
839 if (MF.getFunction().hasFnAttribute("probe-stack"))
840 return MF.getFunction().getFnAttribute("probe-stack").getValueAsString() ==
841 "inline-asm";
842 return false;
843 }
844
isLegalICmpImmediate(int64_t Imm) const845 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
846 // We can use CGFI or CLGFI.
847 return isInt<32>(Imm) || isUInt<32>(Imm);
848 }
849
isLegalAddImmediate(int64_t Imm) const850 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
851 // We can use ALGFI or SLGFI.
852 return isUInt<32>(Imm) || isUInt<32>(-Imm);
853 }
854
allowsMisalignedMemoryAccesses(EVT VT,unsigned,unsigned,MachineMemOperand::Flags,bool * Fast) const855 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(
856 EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
857 // Unaligned accesses should never be slower than the expanded version.
858 // We check specifically for aligned accesses in the few cases where
859 // they are required.
860 if (Fast)
861 *Fast = true;
862 return true;
863 }
864
865 // Information about the addressing mode for a memory access.
866 struct AddressingMode {
867 // True if a long displacement is supported.
868 bool LongDisplacement;
869
870 // True if use of index register is supported.
871 bool IndexReg;
872
AddressingModeAddressingMode873 AddressingMode(bool LongDispl, bool IdxReg) :
874 LongDisplacement(LongDispl), IndexReg(IdxReg) {}
875 };
876
877 // Return the desired addressing mode for a Load which has only one use (in
878 // the same block) which is a Store.
getLoadStoreAddrMode(bool HasVector,Type * Ty)879 static AddressingMode getLoadStoreAddrMode(bool HasVector,
880 Type *Ty) {
881 // With vector support a Load->Store combination may be combined to either
882 // an MVC or vector operations and it seems to work best to allow the
883 // vector addressing mode.
884 if (HasVector)
885 return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
886
887 // Otherwise only the MVC case is special.
888 bool MVC = Ty->isIntegerTy(8);
889 return AddressingMode(!MVC/*LongDispl*/, !MVC/*IdxReg*/);
890 }
891
892 // Return the addressing mode which seems most desirable given an LLVM
893 // Instruction pointer.
894 static AddressingMode
supportedAddressingMode(Instruction * I,bool HasVector)895 supportedAddressingMode(Instruction *I, bool HasVector) {
896 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
897 switch (II->getIntrinsicID()) {
898 default: break;
899 case Intrinsic::memset:
900 case Intrinsic::memmove:
901 case Intrinsic::memcpy:
902 return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
903 }
904 }
905
906 if (isa<LoadInst>(I) && I->hasOneUse()) {
907 auto *SingleUser = cast<Instruction>(*I->user_begin());
908 if (SingleUser->getParent() == I->getParent()) {
909 if (isa<ICmpInst>(SingleUser)) {
910 if (auto *C = dyn_cast<ConstantInt>(SingleUser->getOperand(1)))
911 if (C->getBitWidth() <= 64 &&
912 (isInt<16>(C->getSExtValue()) || isUInt<16>(C->getZExtValue())))
913 // Comparison of memory with 16 bit signed / unsigned immediate
914 return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
915 } else if (isa<StoreInst>(SingleUser))
916 // Load->Store
917 return getLoadStoreAddrMode(HasVector, I->getType());
918 }
919 } else if (auto *StoreI = dyn_cast<StoreInst>(I)) {
920 if (auto *LoadI = dyn_cast<LoadInst>(StoreI->getValueOperand()))
921 if (LoadI->hasOneUse() && LoadI->getParent() == I->getParent())
922 // Load->Store
923 return getLoadStoreAddrMode(HasVector, LoadI->getType());
924 }
925
926 if (HasVector && (isa<LoadInst>(I) || isa<StoreInst>(I))) {
927
928 // * Use LDE instead of LE/LEY for z13 to avoid partial register
929 // dependencies (LDE only supports small offsets).
930 // * Utilize the vector registers to hold floating point
931 // values (vector load / store instructions only support small
932 // offsets).
933
934 Type *MemAccessTy = (isa<LoadInst>(I) ? I->getType() :
935 I->getOperand(0)->getType());
936 bool IsFPAccess = MemAccessTy->isFloatingPointTy();
937 bool IsVectorAccess = MemAccessTy->isVectorTy();
938
939 // A store of an extracted vector element will be combined into a VSTE type
940 // instruction.
941 if (!IsVectorAccess && isa<StoreInst>(I)) {
942 Value *DataOp = I->getOperand(0);
943 if (isa<ExtractElementInst>(DataOp))
944 IsVectorAccess = true;
945 }
946
947 // A load which gets inserted into a vector element will be combined into a
948 // VLE type instruction.
949 if (!IsVectorAccess && isa<LoadInst>(I) && I->hasOneUse()) {
950 User *LoadUser = *I->user_begin();
951 if (isa<InsertElementInst>(LoadUser))
952 IsVectorAccess = true;
953 }
954
955 if (IsFPAccess || IsVectorAccess)
956 return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
957 }
958
959 return AddressingMode(true/*LongDispl*/, true/*IdxReg*/);
960 }
961
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS,Instruction * I) const962 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
963 const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {
964 // Punt on globals for now, although they can be used in limited
965 // RELATIVE LONG cases.
966 if (AM.BaseGV)
967 return false;
968
969 // Require a 20-bit signed offset.
970 if (!isInt<20>(AM.BaseOffs))
971 return false;
972
973 AddressingMode SupportedAM(true, true);
974 if (I != nullptr)
975 SupportedAM = supportedAddressingMode(I, Subtarget.hasVector());
976
977 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs))
978 return false;
979
980 if (!SupportedAM.IndexReg)
981 // No indexing allowed.
982 return AM.Scale == 0;
983 else
984 // Indexing is OK but no scale factor can be applied.
985 return AM.Scale == 0 || AM.Scale == 1;
986 }
987
isTruncateFree(Type * FromType,Type * ToType) const988 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
989 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
990 return false;
991 unsigned FromBits = FromType->getPrimitiveSizeInBits().getFixedSize();
992 unsigned ToBits = ToType->getPrimitiveSizeInBits().getFixedSize();
993 return FromBits > ToBits;
994 }
995
isTruncateFree(EVT FromVT,EVT ToVT) const996 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
997 if (!FromVT.isInteger() || !ToVT.isInteger())
998 return false;
999 unsigned FromBits = FromVT.getFixedSizeInBits();
1000 unsigned ToBits = ToVT.getFixedSizeInBits();
1001 return FromBits > ToBits;
1002 }
1003
1004 //===----------------------------------------------------------------------===//
1005 // Inline asm support
1006 //===----------------------------------------------------------------------===//
1007
1008 TargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const1009 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
1010 if (Constraint.size() == 1) {
1011 switch (Constraint[0]) {
1012 case 'a': // Address register
1013 case 'd': // Data register (equivalent to 'r')
1014 case 'f': // Floating-point register
1015 case 'h': // High-part register
1016 case 'r': // General-purpose register
1017 case 'v': // Vector register
1018 return C_RegisterClass;
1019
1020 case 'Q': // Memory with base and unsigned 12-bit displacement
1021 case 'R': // Likewise, plus an index
1022 case 'S': // Memory with base and signed 20-bit displacement
1023 case 'T': // Likewise, plus an index
1024 case 'm': // Equivalent to 'T'.
1025 return C_Memory;
1026
1027 case 'I': // Unsigned 8-bit constant
1028 case 'J': // Unsigned 12-bit constant
1029 case 'K': // Signed 16-bit constant
1030 case 'L': // Signed 20-bit displacement (on all targets we support)
1031 case 'M': // 0x7fffffff
1032 return C_Immediate;
1033
1034 default:
1035 break;
1036 }
1037 }
1038 return TargetLowering::getConstraintType(Constraint);
1039 }
1040
1041 TargetLowering::ConstraintWeight SystemZTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const1042 getSingleConstraintMatchWeight(AsmOperandInfo &info,
1043 const char *constraint) const {
1044 ConstraintWeight weight = CW_Invalid;
1045 Value *CallOperandVal = info.CallOperandVal;
1046 // If we don't have a value, we can't do a match,
1047 // but allow it at the lowest weight.
1048 if (!CallOperandVal)
1049 return CW_Default;
1050 Type *type = CallOperandVal->getType();
1051 // Look at the constraint type.
1052 switch (*constraint) {
1053 default:
1054 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1055 break;
1056
1057 case 'a': // Address register
1058 case 'd': // Data register (equivalent to 'r')
1059 case 'h': // High-part register
1060 case 'r': // General-purpose register
1061 if (CallOperandVal->getType()->isIntegerTy())
1062 weight = CW_Register;
1063 break;
1064
1065 case 'f': // Floating-point register
1066 if (type->isFloatingPointTy())
1067 weight = CW_Register;
1068 break;
1069
1070 case 'v': // Vector register
1071 if ((type->isVectorTy() || type->isFloatingPointTy()) &&
1072 Subtarget.hasVector())
1073 weight = CW_Register;
1074 break;
1075
1076 case 'I': // Unsigned 8-bit constant
1077 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
1078 if (isUInt<8>(C->getZExtValue()))
1079 weight = CW_Constant;
1080 break;
1081
1082 case 'J': // Unsigned 12-bit constant
1083 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
1084 if (isUInt<12>(C->getZExtValue()))
1085 weight = CW_Constant;
1086 break;
1087
1088 case 'K': // Signed 16-bit constant
1089 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
1090 if (isInt<16>(C->getSExtValue()))
1091 weight = CW_Constant;
1092 break;
1093
1094 case 'L': // Signed 20-bit displacement (on all targets we support)
1095 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
1096 if (isInt<20>(C->getSExtValue()))
1097 weight = CW_Constant;
1098 break;
1099
1100 case 'M': // 0x7fffffff
1101 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
1102 if (C->getZExtValue() == 0x7fffffff)
1103 weight = CW_Constant;
1104 break;
1105 }
1106 return weight;
1107 }
1108
1109 // Parse a "{tNNN}" register constraint for which the register type "t"
1110 // has already been verified. MC is the class associated with "t" and
1111 // Map maps 0-based register numbers to LLVM register numbers.
1112 static std::pair<unsigned, const TargetRegisterClass *>
parseRegisterNumber(StringRef Constraint,const TargetRegisterClass * RC,const unsigned * Map,unsigned Size)1113 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
1114 const unsigned *Map, unsigned Size) {
1115 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
1116 if (isdigit(Constraint[2])) {
1117 unsigned Index;
1118 bool Failed =
1119 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
1120 if (!Failed && Index < Size && Map[Index])
1121 return std::make_pair(Map[Index], RC);
1122 }
1123 return std::make_pair(0U, nullptr);
1124 }
1125
1126 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const1127 SystemZTargetLowering::getRegForInlineAsmConstraint(
1128 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
1129 if (Constraint.size() == 1) {
1130 // GCC Constraint Letters
1131 switch (Constraint[0]) {
1132 default: break;
1133 case 'd': // Data register (equivalent to 'r')
1134 case 'r': // General-purpose register
1135 if (VT == MVT::i64)
1136 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
1137 else if (VT == MVT::i128)
1138 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
1139 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
1140
1141 case 'a': // Address register
1142 if (VT == MVT::i64)
1143 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
1144 else if (VT == MVT::i128)
1145 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
1146 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
1147
1148 case 'h': // High-part register (an LLVM extension)
1149 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
1150
1151 case 'f': // Floating-point register
1152 if (!useSoftFloat()) {
1153 if (VT == MVT::f64)
1154 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
1155 else if (VT == MVT::f128)
1156 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
1157 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
1158 }
1159 break;
1160 case 'v': // Vector register
1161 if (Subtarget.hasVector()) {
1162 if (VT == MVT::f32)
1163 return std::make_pair(0U, &SystemZ::VR32BitRegClass);
1164 if (VT == MVT::f64)
1165 return std::make_pair(0U, &SystemZ::VR64BitRegClass);
1166 return std::make_pair(0U, &SystemZ::VR128BitRegClass);
1167 }
1168 break;
1169 }
1170 }
1171 if (Constraint.size() > 0 && Constraint[0] == '{') {
1172 // We need to override the default register parsing for GPRs and FPRs
1173 // because the interpretation depends on VT. The internal names of
1174 // the registers are also different from the external names
1175 // (F0D and F0S instead of F0, etc.).
1176 if (Constraint[1] == 'r') {
1177 if (VT == MVT::i32)
1178 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
1179 SystemZMC::GR32Regs, 16);
1180 if (VT == MVT::i128)
1181 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
1182 SystemZMC::GR128Regs, 16);
1183 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
1184 SystemZMC::GR64Regs, 16);
1185 }
1186 if (Constraint[1] == 'f') {
1187 if (useSoftFloat())
1188 return std::make_pair(
1189 0u, static_cast<const TargetRegisterClass *>(nullptr));
1190 if (VT == MVT::f32)
1191 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
1192 SystemZMC::FP32Regs, 16);
1193 if (VT == MVT::f128)
1194 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
1195 SystemZMC::FP128Regs, 16);
1196 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
1197 SystemZMC::FP64Regs, 16);
1198 }
1199 if (Constraint[1] == 'v') {
1200 if (!Subtarget.hasVector())
1201 return std::make_pair(
1202 0u, static_cast<const TargetRegisterClass *>(nullptr));
1203 if (VT == MVT::f32)
1204 return parseRegisterNumber(Constraint, &SystemZ::VR32BitRegClass,
1205 SystemZMC::VR32Regs, 32);
1206 if (VT == MVT::f64)
1207 return parseRegisterNumber(Constraint, &SystemZ::VR64BitRegClass,
1208 SystemZMC::VR64Regs, 32);
1209 return parseRegisterNumber(Constraint, &SystemZ::VR128BitRegClass,
1210 SystemZMC::VR128Regs, 32);
1211 }
1212 }
1213 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1214 }
1215
1216 // FIXME? Maybe this could be a TableGen attribute on some registers and
1217 // this table could be generated automatically from RegInfo.
getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const1218 Register SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT,
1219 const MachineFunction &MF) const {
1220
1221 Register Reg = StringSwitch<Register>(RegName)
1222 .Case("r15", SystemZ::R15D)
1223 .Default(0);
1224 if (Reg)
1225 return Reg;
1226 report_fatal_error("Invalid register name global variable");
1227 }
1228
1229 void SystemZTargetLowering::
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const1230 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1231 std::vector<SDValue> &Ops,
1232 SelectionDAG &DAG) const {
1233 // Only support length 1 constraints for now.
1234 if (Constraint.length() == 1) {
1235 switch (Constraint[0]) {
1236 case 'I': // Unsigned 8-bit constant
1237 if (auto *C = dyn_cast<ConstantSDNode>(Op))
1238 if (isUInt<8>(C->getZExtValue()))
1239 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
1240 Op.getValueType()));
1241 return;
1242
1243 case 'J': // Unsigned 12-bit constant
1244 if (auto *C = dyn_cast<ConstantSDNode>(Op))
1245 if (isUInt<12>(C->getZExtValue()))
1246 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
1247 Op.getValueType()));
1248 return;
1249
1250 case 'K': // Signed 16-bit constant
1251 if (auto *C = dyn_cast<ConstantSDNode>(Op))
1252 if (isInt<16>(C->getSExtValue()))
1253 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
1254 Op.getValueType()));
1255 return;
1256
1257 case 'L': // Signed 20-bit displacement (on all targets we support)
1258 if (auto *C = dyn_cast<ConstantSDNode>(Op))
1259 if (isInt<20>(C->getSExtValue()))
1260 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
1261 Op.getValueType()));
1262 return;
1263
1264 case 'M': // 0x7fffffff
1265 if (auto *C = dyn_cast<ConstantSDNode>(Op))
1266 if (C->getZExtValue() == 0x7fffffff)
1267 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
1268 Op.getValueType()));
1269 return;
1270 }
1271 }
1272 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1273 }
1274
1275 //===----------------------------------------------------------------------===//
1276 // Calling conventions
1277 //===----------------------------------------------------------------------===//
1278
1279 #include "SystemZGenCallingConv.inc"
1280
getScratchRegisters(CallingConv::ID) const1281 const MCPhysReg *SystemZTargetLowering::getScratchRegisters(
1282 CallingConv::ID) const {
1283 static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
1284 SystemZ::R14D, 0 };
1285 return ScratchRegs;
1286 }
1287
allowTruncateForTailCall(Type * FromType,Type * ToType) const1288 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
1289 Type *ToType) const {
1290 return isTruncateFree(FromType, ToType);
1291 }
1292
mayBeEmittedAsTailCall(const CallInst * CI) const1293 bool SystemZTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
1294 return CI->isTailCall();
1295 }
1296
1297 // We do not yet support 128-bit single-element vector types. If the user
1298 // attempts to use such types as function argument or return type, prefer
1299 // to error out instead of emitting code violating the ABI.
VerifyVectorType(MVT VT,EVT ArgVT)1300 static void VerifyVectorType(MVT VT, EVT ArgVT) {
1301 if (ArgVT.isVector() && !VT.isVector())
1302 report_fatal_error("Unsupported vector argument or return type");
1303 }
1304
VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> & Ins)1305 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
1306 for (unsigned i = 0; i < Ins.size(); ++i)
1307 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
1308 }
1309
VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> & Outs)1310 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1311 for (unsigned i = 0; i < Outs.size(); ++i)
1312 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
1313 }
1314
1315 // Value is a value that has been passed to us in the location described by VA
1316 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
1317 // any loads onto Chain.
convertLocVTToValVT(SelectionDAG & DAG,const SDLoc & DL,CCValAssign & VA,SDValue Chain,SDValue Value)1318 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL,
1319 CCValAssign &VA, SDValue Chain,
1320 SDValue Value) {
1321 // If the argument has been promoted from a smaller type, insert an
1322 // assertion to capture this.
1323 if (VA.getLocInfo() == CCValAssign::SExt)
1324 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
1325 DAG.getValueType(VA.getValVT()));
1326 else if (VA.getLocInfo() == CCValAssign::ZExt)
1327 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
1328 DAG.getValueType(VA.getValVT()));
1329
1330 if (VA.isExtInLoc())
1331 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
1332 else if (VA.getLocInfo() == CCValAssign::BCvt) {
1333 // If this is a short vector argument loaded from the stack,
1334 // extend from i64 to full vector size and then bitcast.
1335 assert(VA.getLocVT() == MVT::i64);
1336 assert(VA.getValVT().isVector());
1337 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
1338 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
1339 } else
1340 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
1341 return Value;
1342 }
1343
1344 // Value is a value of type VA.getValVT() that we need to copy into
1345 // the location described by VA. Return a copy of Value converted to
1346 // VA.getValVT(). The caller is responsible for handling indirect values.
convertValVTToLocVT(SelectionDAG & DAG,const SDLoc & DL,CCValAssign & VA,SDValue Value)1347 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
1348 CCValAssign &VA, SDValue Value) {
1349 switch (VA.getLocInfo()) {
1350 case CCValAssign::SExt:
1351 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
1352 case CCValAssign::ZExt:
1353 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
1354 case CCValAssign::AExt:
1355 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
1356 case CCValAssign::BCvt:
1357 // If this is a short vector argument to be stored to the stack,
1358 // bitcast to v2i64 and then extract first element.
1359 assert(VA.getLocVT() == MVT::i64);
1360 assert(VA.getValVT().isVector());
1361 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
1362 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
1363 DAG.getConstant(0, DL, MVT::i32));
1364 case CCValAssign::Full:
1365 return Value;
1366 default:
1367 llvm_unreachable("Unhandled getLocInfo()");
1368 }
1369 }
1370
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1371 SDValue SystemZTargetLowering::LowerFormalArguments(
1372 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1373 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1374 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1375 MachineFunction &MF = DAG.getMachineFunction();
1376 MachineFrameInfo &MFI = MF.getFrameInfo();
1377 MachineRegisterInfo &MRI = MF.getRegInfo();
1378 SystemZMachineFunctionInfo *FuncInfo =
1379 MF.getInfo<SystemZMachineFunctionInfo>();
1380 auto *TFL =
1381 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
1382 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1383
1384 // Detect unsupported vector argument types.
1385 if (Subtarget.hasVector())
1386 VerifyVectorTypes(Ins);
1387
1388 // Assign locations to all of the incoming arguments.
1389 SmallVector<CCValAssign, 16> ArgLocs;
1390 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1391 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
1392
1393 unsigned NumFixedGPRs = 0;
1394 unsigned NumFixedFPRs = 0;
1395 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1396 SDValue ArgValue;
1397 CCValAssign &VA = ArgLocs[I];
1398 EVT LocVT = VA.getLocVT();
1399 if (VA.isRegLoc()) {
1400 // Arguments passed in registers
1401 const TargetRegisterClass *RC;
1402 switch (LocVT.getSimpleVT().SimpleTy) {
1403 default:
1404 // Integers smaller than i64 should be promoted to i64.
1405 llvm_unreachable("Unexpected argument type");
1406 case MVT::i32:
1407 NumFixedGPRs += 1;
1408 RC = &SystemZ::GR32BitRegClass;
1409 break;
1410 case MVT::i64:
1411 NumFixedGPRs += 1;
1412 RC = &SystemZ::GR64BitRegClass;
1413 break;
1414 case MVT::f32:
1415 NumFixedFPRs += 1;
1416 RC = &SystemZ::FP32BitRegClass;
1417 break;
1418 case MVT::f64:
1419 NumFixedFPRs += 1;
1420 RC = &SystemZ::FP64BitRegClass;
1421 break;
1422 case MVT::v16i8:
1423 case MVT::v8i16:
1424 case MVT::v4i32:
1425 case MVT::v2i64:
1426 case MVT::v4f32:
1427 case MVT::v2f64:
1428 RC = &SystemZ::VR128BitRegClass;
1429 break;
1430 }
1431
1432 Register VReg = MRI.createVirtualRegister(RC);
1433 MRI.addLiveIn(VA.getLocReg(), VReg);
1434 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1435 } else {
1436 assert(VA.isMemLoc() && "Argument not register or memory");
1437
1438 // Create the frame index object for this incoming parameter.
1439 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1440 VA.getLocMemOffset(), true);
1441
1442 // Create the SelectionDAG nodes corresponding to a load
1443 // from this parameter. Unpromoted ints and floats are
1444 // passed as right-justified 8-byte values.
1445 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1446 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1447 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
1448 DAG.getIntPtrConstant(4, DL));
1449 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
1450 MachinePointerInfo::getFixedStack(MF, FI));
1451 }
1452
1453 // Convert the value of the argument register into the value that's
1454 // being passed.
1455 if (VA.getLocInfo() == CCValAssign::Indirect) {
1456 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1457 MachinePointerInfo()));
1458 // If the original argument was split (e.g. i128), we need
1459 // to load all parts of it here (using the same address).
1460 unsigned ArgIndex = Ins[I].OrigArgIndex;
1461 assert (Ins[I].PartOffset == 0);
1462 while (I + 1 != E && Ins[I + 1].OrigArgIndex == ArgIndex) {
1463 CCValAssign &PartVA = ArgLocs[I + 1];
1464 unsigned PartOffset = Ins[I + 1].PartOffset;
1465 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1466 DAG.getIntPtrConstant(PartOffset, DL));
1467 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1468 MachinePointerInfo()));
1469 ++I;
1470 }
1471 } else
1472 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
1473 }
1474
1475 if (IsVarArg) {
1476 // Save the number of non-varargs registers for later use by va_start, etc.
1477 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
1478 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
1479
1480 // Likewise the address (in the form of a frame index) of where the
1481 // first stack vararg would be. The 1-byte size here is arbitrary.
1482 int64_t StackSize = CCInfo.getNextStackOffset();
1483 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
1484
1485 // ...and a similar frame index for the caller-allocated save area
1486 // that will be used to store the incoming registers.
1487 int64_t RegSaveOffset =
1488 -SystemZMC::CallFrameSize + TFL->getRegSpillOffset(MF, SystemZ::R2D) - 16;
1489 unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
1490 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
1491
1492 // Store the FPR varargs in the reserved frame slots. (We store the
1493 // GPRs as part of the prologue.)
1494 if (NumFixedFPRs < SystemZ::NumArgFPRs && !useSoftFloat()) {
1495 SDValue MemOps[SystemZ::NumArgFPRs];
1496 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
1497 unsigned Offset = TFL->getRegSpillOffset(MF, SystemZ::ArgFPRs[I]);
1498 int FI =
1499 MFI.CreateFixedObject(8, -SystemZMC::CallFrameSize + Offset, true);
1500 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1501 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
1502 &SystemZ::FP64BitRegClass);
1503 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
1504 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
1505 MachinePointerInfo::getFixedStack(MF, FI));
1506 }
1507 // Join the stores, which are independent of one another.
1508 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1509 makeArrayRef(&MemOps[NumFixedFPRs],
1510 SystemZ::NumArgFPRs-NumFixedFPRs));
1511 }
1512 }
1513
1514 return Chain;
1515 }
1516
canUseSiblingCall(const CCState & ArgCCInfo,SmallVectorImpl<CCValAssign> & ArgLocs,SmallVectorImpl<ISD::OutputArg> & Outs)1517 static bool canUseSiblingCall(const CCState &ArgCCInfo,
1518 SmallVectorImpl<CCValAssign> &ArgLocs,
1519 SmallVectorImpl<ISD::OutputArg> &Outs) {
1520 // Punt if there are any indirect or stack arguments, or if the call
1521 // needs the callee-saved argument register R6, or if the call uses
1522 // the callee-saved register arguments SwiftSelf and SwiftError.
1523 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1524 CCValAssign &VA = ArgLocs[I];
1525 if (VA.getLocInfo() == CCValAssign::Indirect)
1526 return false;
1527 if (!VA.isRegLoc())
1528 return false;
1529 Register Reg = VA.getLocReg();
1530 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1531 return false;
1532 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1533 return false;
1534 }
1535 return true;
1536 }
1537
1538 SDValue
LowerCall(CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1539 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
1540 SmallVectorImpl<SDValue> &InVals) const {
1541 SelectionDAG &DAG = CLI.DAG;
1542 SDLoc &DL = CLI.DL;
1543 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1544 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1545 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1546 SDValue Chain = CLI.Chain;
1547 SDValue Callee = CLI.Callee;
1548 bool &IsTailCall = CLI.IsTailCall;
1549 CallingConv::ID CallConv = CLI.CallConv;
1550 bool IsVarArg = CLI.IsVarArg;
1551 MachineFunction &MF = DAG.getMachineFunction();
1552 EVT PtrVT = getPointerTy(MF.getDataLayout());
1553 LLVMContext &Ctx = *DAG.getContext();
1554
1555 // Detect unsupported vector argument and return types.
1556 if (Subtarget.hasVector()) {
1557 VerifyVectorTypes(Outs);
1558 VerifyVectorTypes(Ins);
1559 }
1560
1561 // Analyze the operands of the call, assigning locations to each operand.
1562 SmallVector<CCValAssign, 16> ArgLocs;
1563 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx);
1564 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1565
1566 // We don't support GuaranteedTailCallOpt, only automatically-detected
1567 // sibling calls.
1568 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
1569 IsTailCall = false;
1570
1571 // Get a count of how many bytes are to be pushed on the stack.
1572 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1573
1574 // Mark the start of the call.
1575 if (!IsTailCall)
1576 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1577
1578 // Copy argument values to their designated locations.
1579 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
1580 SmallVector<SDValue, 8> MemOpChains;
1581 SDValue StackPtr;
1582 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1583 CCValAssign &VA = ArgLocs[I];
1584 SDValue ArgValue = OutVals[I];
1585
1586 if (VA.getLocInfo() == CCValAssign::Indirect) {
1587 // Store the argument in a stack slot and pass its address.
1588 unsigned ArgIndex = Outs[I].OrigArgIndex;
1589 EVT SlotVT;
1590 if (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
1591 // Allocate the full stack space for a promoted (and split) argument.
1592 Type *OrigArgType = CLI.Args[Outs[I].OrigArgIndex].Ty;
1593 EVT OrigArgVT = getValueType(MF.getDataLayout(), OrigArgType);
1594 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT);
1595 unsigned N = getNumRegistersForCallingConv(Ctx, CLI.CallConv, OrigArgVT);
1596 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N);
1597 } else {
1598 SlotVT = Outs[I].ArgVT;
1599 }
1600 SDValue SpillSlot = DAG.CreateStackTemporary(SlotVT);
1601 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1602 MemOpChains.push_back(
1603 DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1604 MachinePointerInfo::getFixedStack(MF, FI)));
1605 // If the original argument was split (e.g. i128), we need
1606 // to store all parts of it here (and pass just one address).
1607 assert (Outs[I].PartOffset == 0);
1608 while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
1609 SDValue PartValue = OutVals[I + 1];
1610 unsigned PartOffset = Outs[I + 1].PartOffset;
1611 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1612 DAG.getIntPtrConstant(PartOffset, DL));
1613 MemOpChains.push_back(
1614 DAG.getStore(Chain, DL, PartValue, Address,
1615 MachinePointerInfo::getFixedStack(MF, FI)));
1616 assert((PartOffset + PartValue.getValueType().getStoreSize() <=
1617 SlotVT.getStoreSize()) && "Not enough space for argument part!");
1618 ++I;
1619 }
1620 ArgValue = SpillSlot;
1621 } else
1622 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1623
1624 if (VA.isRegLoc())
1625 // Queue up the argument copies and emit them at the end.
1626 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1627 else {
1628 assert(VA.isMemLoc() && "Argument not register or memory");
1629
1630 // Work out the address of the stack slot. Unpromoted ints and
1631 // floats are passed as right-justified 8-byte values.
1632 if (!StackPtr.getNode())
1633 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1634 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
1635 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1636 Offset += 4;
1637 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1638 DAG.getIntPtrConstant(Offset, DL));
1639
1640 // Emit the store.
1641 MemOpChains.push_back(
1642 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1643 }
1644 }
1645
1646 // Join the stores, which are independent of one another.
1647 if (!MemOpChains.empty())
1648 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1649
1650 // Accept direct calls by converting symbolic call addresses to the
1651 // associated Target* opcodes. Force %r1 to be used for indirect
1652 // tail calls.
1653 SDValue Glue;
1654 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1655 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1656 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1657 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1658 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1659 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1660 } else if (IsTailCall) {
1661 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1662 Glue = Chain.getValue(1);
1663 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1664 }
1665
1666 // Build a sequence of copy-to-reg nodes, chained and glued together.
1667 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1668 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1669 RegsToPass[I].second, Glue);
1670 Glue = Chain.getValue(1);
1671 }
1672
1673 // The first call operand is the chain and the second is the target address.
1674 SmallVector<SDValue, 8> Ops;
1675 Ops.push_back(Chain);
1676 Ops.push_back(Callee);
1677
1678 // Add argument registers to the end of the list so that they are
1679 // known live into the call.
1680 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1681 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1682 RegsToPass[I].second.getValueType()));
1683
1684 // Add a register mask operand representing the call-preserved registers.
1685 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1686 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1687 assert(Mask && "Missing call preserved mask for calling convention");
1688 Ops.push_back(DAG.getRegisterMask(Mask));
1689
1690 // Glue the call to the argument copies, if any.
1691 if (Glue.getNode())
1692 Ops.push_back(Glue);
1693
1694 // Emit the call.
1695 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1696 if (IsTailCall)
1697 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1698 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1699 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
1700 Glue = Chain.getValue(1);
1701
1702 // Mark the end of the call, which is glued to the call itself.
1703 Chain = DAG.getCALLSEQ_END(Chain,
1704 DAG.getConstant(NumBytes, DL, PtrVT, true),
1705 DAG.getConstant(0, DL, PtrVT, true),
1706 Glue, DL);
1707 Glue = Chain.getValue(1);
1708
1709 // Assign locations to each value returned by this call.
1710 SmallVector<CCValAssign, 16> RetLocs;
1711 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, Ctx);
1712 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1713
1714 // Copy all of the result registers out of their specified physreg.
1715 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1716 CCValAssign &VA = RetLocs[I];
1717
1718 // Copy the value out, gluing the copy to the end of the call sequence.
1719 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1720 VA.getLocVT(), Glue);
1721 Chain = RetValue.getValue(1);
1722 Glue = RetValue.getValue(2);
1723
1724 // Convert the value of the return register into the value that's
1725 // being returned.
1726 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1727 }
1728
1729 return Chain;
1730 }
1731
1732 bool SystemZTargetLowering::
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const1733 CanLowerReturn(CallingConv::ID CallConv,
1734 MachineFunction &MF, bool isVarArg,
1735 const SmallVectorImpl<ISD::OutputArg> &Outs,
1736 LLVMContext &Context) const {
1737 // Detect unsupported vector return types.
1738 if (Subtarget.hasVector())
1739 VerifyVectorTypes(Outs);
1740
1741 // Special case that we cannot easily detect in RetCC_SystemZ since
1742 // i128 is not a legal type.
1743 for (auto &Out : Outs)
1744 if (Out.ArgVT == MVT::i128)
1745 return false;
1746
1747 SmallVector<CCValAssign, 16> RetLocs;
1748 CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1749 return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1750 }
1751
1752 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const1753 SystemZTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1754 bool IsVarArg,
1755 const SmallVectorImpl<ISD::OutputArg> &Outs,
1756 const SmallVectorImpl<SDValue> &OutVals,
1757 const SDLoc &DL, SelectionDAG &DAG) const {
1758 MachineFunction &MF = DAG.getMachineFunction();
1759
1760 // Detect unsupported vector return types.
1761 if (Subtarget.hasVector())
1762 VerifyVectorTypes(Outs);
1763
1764 // Assign locations to each returned value.
1765 SmallVector<CCValAssign, 16> RetLocs;
1766 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1767 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1768
1769 // Quick exit for void returns
1770 if (RetLocs.empty())
1771 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1772
1773 if (CallConv == CallingConv::GHC)
1774 report_fatal_error("GHC functions return void only");
1775
1776 // Copy the result values into the output registers.
1777 SDValue Glue;
1778 SmallVector<SDValue, 4> RetOps;
1779 RetOps.push_back(Chain);
1780 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1781 CCValAssign &VA = RetLocs[I];
1782 SDValue RetValue = OutVals[I];
1783
1784 // Make the return register live on exit.
1785 assert(VA.isRegLoc() && "Can only return in registers!");
1786
1787 // Promote the value as required.
1788 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1789
1790 // Chain and glue the copies together.
1791 Register Reg = VA.getLocReg();
1792 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1793 Glue = Chain.getValue(1);
1794 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1795 }
1796
1797 // Update chain and glue.
1798 RetOps[0] = Chain;
1799 if (Glue.getNode())
1800 RetOps.push_back(Glue);
1801
1802 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1803 }
1804
1805 // Return true if Op is an intrinsic node with chain that returns the CC value
1806 // as its only (other) argument. Provide the associated SystemZISD opcode and
1807 // the mask of valid CC values if so.
isIntrinsicWithCCAndChain(SDValue Op,unsigned & Opcode,unsigned & CCValid)1808 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1809 unsigned &CCValid) {
1810 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1811 switch (Id) {
1812 case Intrinsic::s390_tbegin:
1813 Opcode = SystemZISD::TBEGIN;
1814 CCValid = SystemZ::CCMASK_TBEGIN;
1815 return true;
1816
1817 case Intrinsic::s390_tbegin_nofloat:
1818 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1819 CCValid = SystemZ::CCMASK_TBEGIN;
1820 return true;
1821
1822 case Intrinsic::s390_tend:
1823 Opcode = SystemZISD::TEND;
1824 CCValid = SystemZ::CCMASK_TEND;
1825 return true;
1826
1827 default:
1828 return false;
1829 }
1830 }
1831
1832 // Return true if Op is an intrinsic node without chain that returns the
1833 // CC value as its final argument. Provide the associated SystemZISD
1834 // opcode and the mask of valid CC values if so.
isIntrinsicWithCC(SDValue Op,unsigned & Opcode,unsigned & CCValid)1835 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1836 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1837 switch (Id) {
1838 case Intrinsic::s390_vpkshs:
1839 case Intrinsic::s390_vpksfs:
1840 case Intrinsic::s390_vpksgs:
1841 Opcode = SystemZISD::PACKS_CC;
1842 CCValid = SystemZ::CCMASK_VCMP;
1843 return true;
1844
1845 case Intrinsic::s390_vpklshs:
1846 case Intrinsic::s390_vpklsfs:
1847 case Intrinsic::s390_vpklsgs:
1848 Opcode = SystemZISD::PACKLS_CC;
1849 CCValid = SystemZ::CCMASK_VCMP;
1850 return true;
1851
1852 case Intrinsic::s390_vceqbs:
1853 case Intrinsic::s390_vceqhs:
1854 case Intrinsic::s390_vceqfs:
1855 case Intrinsic::s390_vceqgs:
1856 Opcode = SystemZISD::VICMPES;
1857 CCValid = SystemZ::CCMASK_VCMP;
1858 return true;
1859
1860 case Intrinsic::s390_vchbs:
1861 case Intrinsic::s390_vchhs:
1862 case Intrinsic::s390_vchfs:
1863 case Intrinsic::s390_vchgs:
1864 Opcode = SystemZISD::VICMPHS;
1865 CCValid = SystemZ::CCMASK_VCMP;
1866 return true;
1867
1868 case Intrinsic::s390_vchlbs:
1869 case Intrinsic::s390_vchlhs:
1870 case Intrinsic::s390_vchlfs:
1871 case Intrinsic::s390_vchlgs:
1872 Opcode = SystemZISD::VICMPHLS;
1873 CCValid = SystemZ::CCMASK_VCMP;
1874 return true;
1875
1876 case Intrinsic::s390_vtm:
1877 Opcode = SystemZISD::VTM;
1878 CCValid = SystemZ::CCMASK_VCMP;
1879 return true;
1880
1881 case Intrinsic::s390_vfaebs:
1882 case Intrinsic::s390_vfaehs:
1883 case Intrinsic::s390_vfaefs:
1884 Opcode = SystemZISD::VFAE_CC;
1885 CCValid = SystemZ::CCMASK_ANY;
1886 return true;
1887
1888 case Intrinsic::s390_vfaezbs:
1889 case Intrinsic::s390_vfaezhs:
1890 case Intrinsic::s390_vfaezfs:
1891 Opcode = SystemZISD::VFAEZ_CC;
1892 CCValid = SystemZ::CCMASK_ANY;
1893 return true;
1894
1895 case Intrinsic::s390_vfeebs:
1896 case Intrinsic::s390_vfeehs:
1897 case Intrinsic::s390_vfeefs:
1898 Opcode = SystemZISD::VFEE_CC;
1899 CCValid = SystemZ::CCMASK_ANY;
1900 return true;
1901
1902 case Intrinsic::s390_vfeezbs:
1903 case Intrinsic::s390_vfeezhs:
1904 case Intrinsic::s390_vfeezfs:
1905 Opcode = SystemZISD::VFEEZ_CC;
1906 CCValid = SystemZ::CCMASK_ANY;
1907 return true;
1908
1909 case Intrinsic::s390_vfenebs:
1910 case Intrinsic::s390_vfenehs:
1911 case Intrinsic::s390_vfenefs:
1912 Opcode = SystemZISD::VFENE_CC;
1913 CCValid = SystemZ::CCMASK_ANY;
1914 return true;
1915
1916 case Intrinsic::s390_vfenezbs:
1917 case Intrinsic::s390_vfenezhs:
1918 case Intrinsic::s390_vfenezfs:
1919 Opcode = SystemZISD::VFENEZ_CC;
1920 CCValid = SystemZ::CCMASK_ANY;
1921 return true;
1922
1923 case Intrinsic::s390_vistrbs:
1924 case Intrinsic::s390_vistrhs:
1925 case Intrinsic::s390_vistrfs:
1926 Opcode = SystemZISD::VISTR_CC;
1927 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
1928 return true;
1929
1930 case Intrinsic::s390_vstrcbs:
1931 case Intrinsic::s390_vstrchs:
1932 case Intrinsic::s390_vstrcfs:
1933 Opcode = SystemZISD::VSTRC_CC;
1934 CCValid = SystemZ::CCMASK_ANY;
1935 return true;
1936
1937 case Intrinsic::s390_vstrczbs:
1938 case Intrinsic::s390_vstrczhs:
1939 case Intrinsic::s390_vstrczfs:
1940 Opcode = SystemZISD::VSTRCZ_CC;
1941 CCValid = SystemZ::CCMASK_ANY;
1942 return true;
1943
1944 case Intrinsic::s390_vstrsb:
1945 case Intrinsic::s390_vstrsh:
1946 case Intrinsic::s390_vstrsf:
1947 Opcode = SystemZISD::VSTRS_CC;
1948 CCValid = SystemZ::CCMASK_ANY;
1949 return true;
1950
1951 case Intrinsic::s390_vstrszb:
1952 case Intrinsic::s390_vstrszh:
1953 case Intrinsic::s390_vstrszf:
1954 Opcode = SystemZISD::VSTRSZ_CC;
1955 CCValid = SystemZ::CCMASK_ANY;
1956 return true;
1957
1958 case Intrinsic::s390_vfcedbs:
1959 case Intrinsic::s390_vfcesbs:
1960 Opcode = SystemZISD::VFCMPES;
1961 CCValid = SystemZ::CCMASK_VCMP;
1962 return true;
1963
1964 case Intrinsic::s390_vfchdbs:
1965 case Intrinsic::s390_vfchsbs:
1966 Opcode = SystemZISD::VFCMPHS;
1967 CCValid = SystemZ::CCMASK_VCMP;
1968 return true;
1969
1970 case Intrinsic::s390_vfchedbs:
1971 case Intrinsic::s390_vfchesbs:
1972 Opcode = SystemZISD::VFCMPHES;
1973 CCValid = SystemZ::CCMASK_VCMP;
1974 return true;
1975
1976 case Intrinsic::s390_vftcidb:
1977 case Intrinsic::s390_vftcisb:
1978 Opcode = SystemZISD::VFTCI;
1979 CCValid = SystemZ::CCMASK_VCMP;
1980 return true;
1981
1982 case Intrinsic::s390_tdc:
1983 Opcode = SystemZISD::TDC;
1984 CCValid = SystemZ::CCMASK_TDC;
1985 return true;
1986
1987 default:
1988 return false;
1989 }
1990 }
1991
1992 // Emit an intrinsic with chain and an explicit CC register result.
emitIntrinsicWithCCAndChain(SelectionDAG & DAG,SDValue Op,unsigned Opcode)1993 static SDNode *emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op,
1994 unsigned Opcode) {
1995 // Copy all operands except the intrinsic ID.
1996 unsigned NumOps = Op.getNumOperands();
1997 SmallVector<SDValue, 6> Ops;
1998 Ops.reserve(NumOps - 1);
1999 Ops.push_back(Op.getOperand(0));
2000 for (unsigned I = 2; I < NumOps; ++I)
2001 Ops.push_back(Op.getOperand(I));
2002
2003 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
2004 SDVTList RawVTs = DAG.getVTList(MVT::i32, MVT::Other);
2005 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
2006 SDValue OldChain = SDValue(Op.getNode(), 1);
2007 SDValue NewChain = SDValue(Intr.getNode(), 1);
2008 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
2009 return Intr.getNode();
2010 }
2011
2012 // Emit an intrinsic with an explicit CC register result.
emitIntrinsicWithCC(SelectionDAG & DAG,SDValue Op,unsigned Opcode)2013 static SDNode *emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op,
2014 unsigned Opcode) {
2015 // Copy all operands except the intrinsic ID.
2016 unsigned NumOps = Op.getNumOperands();
2017 SmallVector<SDValue, 6> Ops;
2018 Ops.reserve(NumOps - 1);
2019 for (unsigned I = 1; I < NumOps; ++I)
2020 Ops.push_back(Op.getOperand(I));
2021
2022 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), Op->getVTList(), Ops);
2023 return Intr.getNode();
2024 }
2025
2026 // CC is a comparison that will be implemented using an integer or
2027 // floating-point comparison. Return the condition code mask for
2028 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
2029 // unsigned comparisons and clear for signed ones. In the floating-point
2030 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
CCMaskForCondCode(ISD::CondCode CC)2031 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
2032 #define CONV(X) \
2033 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
2034 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
2035 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
2036
2037 switch (CC) {
2038 default:
2039 llvm_unreachable("Invalid integer condition!");
2040
2041 CONV(EQ);
2042 CONV(NE);
2043 CONV(GT);
2044 CONV(GE);
2045 CONV(LT);
2046 CONV(LE);
2047
2048 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
2049 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
2050 }
2051 #undef CONV
2052 }
2053
2054 // If C can be converted to a comparison against zero, adjust the operands
2055 // as necessary.
adjustZeroCmp(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2056 static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2057 if (C.ICmpType == SystemZICMP::UnsignedOnly)
2058 return;
2059
2060 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
2061 if (!ConstOp1)
2062 return;
2063
2064 int64_t Value = ConstOp1->getSExtValue();
2065 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
2066 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
2067 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
2068 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
2069 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2070 C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
2071 }
2072 }
2073
2074 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
2075 // adjust the operands as necessary.
adjustSubwordCmp(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2076 static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
2077 Comparison &C) {
2078 // For us to make any changes, it must a comparison between a single-use
2079 // load and a constant.
2080 if (!C.Op0.hasOneUse() ||
2081 C.Op0.getOpcode() != ISD::LOAD ||
2082 C.Op1.getOpcode() != ISD::Constant)
2083 return;
2084
2085 // We must have an 8- or 16-bit load.
2086 auto *Load = cast<LoadSDNode>(C.Op0);
2087 unsigned NumBits = Load->getMemoryVT().getSizeInBits();
2088 if ((NumBits != 8 && NumBits != 16) ||
2089 NumBits != Load->getMemoryVT().getStoreSizeInBits())
2090 return;
2091
2092 // The load must be an extending one and the constant must be within the
2093 // range of the unextended value.
2094 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
2095 uint64_t Value = ConstOp1->getZExtValue();
2096 uint64_t Mask = (1 << NumBits) - 1;
2097 if (Load->getExtensionType() == ISD::SEXTLOAD) {
2098 // Make sure that ConstOp1 is in range of C.Op0.
2099 int64_t SignedValue = ConstOp1->getSExtValue();
2100 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
2101 return;
2102 if (C.ICmpType != SystemZICMP::SignedOnly) {
2103 // Unsigned comparison between two sign-extended values is equivalent
2104 // to unsigned comparison between two zero-extended values.
2105 Value &= Mask;
2106 } else if (NumBits == 8) {
2107 // Try to treat the comparison as unsigned, so that we can use CLI.
2108 // Adjust CCMask and Value as necessary.
2109 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
2110 // Test whether the high bit of the byte is set.
2111 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
2112 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
2113 // Test whether the high bit of the byte is clear.
2114 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
2115 else
2116 // No instruction exists for this combination.
2117 return;
2118 C.ICmpType = SystemZICMP::UnsignedOnly;
2119 }
2120 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
2121 if (Value > Mask)
2122 return;
2123 // If the constant is in range, we can use any comparison.
2124 C.ICmpType = SystemZICMP::Any;
2125 } else
2126 return;
2127
2128 // Make sure that the first operand is an i32 of the right extension type.
2129 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
2130 ISD::SEXTLOAD :
2131 ISD::ZEXTLOAD);
2132 if (C.Op0.getValueType() != MVT::i32 ||
2133 Load->getExtensionType() != ExtType) {
2134 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(),
2135 Load->getBasePtr(), Load->getPointerInfo(),
2136 Load->getMemoryVT(), Load->getAlignment(),
2137 Load->getMemOperand()->getFlags());
2138 // Update the chain uses.
2139 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), C.Op0.getValue(1));
2140 }
2141
2142 // Make sure that the second operand is an i32 with the right value.
2143 if (C.Op1.getValueType() != MVT::i32 ||
2144 Value != ConstOp1->getZExtValue())
2145 C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
2146 }
2147
2148 // Return true if Op is either an unextended load, or a load suitable
2149 // for integer register-memory comparisons of type ICmpType.
isNaturalMemoryOperand(SDValue Op,unsigned ICmpType)2150 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
2151 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
2152 if (Load) {
2153 // There are no instructions to compare a register with a memory byte.
2154 if (Load->getMemoryVT() == MVT::i8)
2155 return false;
2156 // Otherwise decide on extension type.
2157 switch (Load->getExtensionType()) {
2158 case ISD::NON_EXTLOAD:
2159 return true;
2160 case ISD::SEXTLOAD:
2161 return ICmpType != SystemZICMP::UnsignedOnly;
2162 case ISD::ZEXTLOAD:
2163 return ICmpType != SystemZICMP::SignedOnly;
2164 default:
2165 break;
2166 }
2167 }
2168 return false;
2169 }
2170
2171 // Return true if it is better to swap the operands of C.
shouldSwapCmpOperands(const Comparison & C)2172 static bool shouldSwapCmpOperands(const Comparison &C) {
2173 // Leave f128 comparisons alone, since they have no memory forms.
2174 if (C.Op0.getValueType() == MVT::f128)
2175 return false;
2176
2177 // Always keep a floating-point constant second, since comparisons with
2178 // zero can use LOAD TEST and comparisons with other constants make a
2179 // natural memory operand.
2180 if (isa<ConstantFPSDNode>(C.Op1))
2181 return false;
2182
2183 // Never swap comparisons with zero since there are many ways to optimize
2184 // those later.
2185 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
2186 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
2187 return false;
2188
2189 // Also keep natural memory operands second if the loaded value is
2190 // only used here. Several comparisons have memory forms.
2191 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
2192 return false;
2193
2194 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
2195 // In that case we generally prefer the memory to be second.
2196 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
2197 // The only exceptions are when the second operand is a constant and
2198 // we can use things like CHHSI.
2199 if (!ConstOp1)
2200 return true;
2201 // The unsigned memory-immediate instructions can handle 16-bit
2202 // unsigned integers.
2203 if (C.ICmpType != SystemZICMP::SignedOnly &&
2204 isUInt<16>(ConstOp1->getZExtValue()))
2205 return false;
2206 // The signed memory-immediate instructions can handle 16-bit
2207 // signed integers.
2208 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
2209 isInt<16>(ConstOp1->getSExtValue()))
2210 return false;
2211 return true;
2212 }
2213
2214 // Try to promote the use of CGFR and CLGFR.
2215 unsigned Opcode0 = C.Op0.getOpcode();
2216 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
2217 return true;
2218 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
2219 return true;
2220 if (C.ICmpType != SystemZICMP::SignedOnly &&
2221 Opcode0 == ISD::AND &&
2222 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
2223 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
2224 return true;
2225
2226 return false;
2227 }
2228
2229 // Check whether C tests for equality between X and Y and whether X - Y
2230 // or Y - X is also computed. In that case it's better to compare the
2231 // result of the subtraction against zero.
adjustForSubtraction(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2232 static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
2233 Comparison &C) {
2234 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2235 C.CCMask == SystemZ::CCMASK_CMP_NE) {
2236 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
2237 SDNode *N = *I;
2238 if (N->getOpcode() == ISD::SUB &&
2239 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
2240 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
2241 C.Op0 = SDValue(N, 0);
2242 C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
2243 return;
2244 }
2245 }
2246 }
2247 }
2248
2249 // Check whether C compares a floating-point value with zero and if that
2250 // floating-point value is also negated. In this case we can use the
2251 // negation to set CC, so avoiding separate LOAD AND TEST and
2252 // LOAD (NEGATIVE/COMPLEMENT) instructions.
adjustForFNeg(Comparison & C)2253 static void adjustForFNeg(Comparison &C) {
2254 // This optimization is invalid for strict comparisons, since FNEG
2255 // does not raise any exceptions.
2256 if (C.Chain)
2257 return;
2258 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
2259 if (C1 && C1->isZero()) {
2260 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
2261 SDNode *N = *I;
2262 if (N->getOpcode() == ISD::FNEG) {
2263 C.Op0 = SDValue(N, 0);
2264 C.CCMask = SystemZ::reverseCCMask(C.CCMask);
2265 return;
2266 }
2267 }
2268 }
2269 }
2270
2271 // Check whether C compares (shl X, 32) with 0 and whether X is
2272 // also sign-extended. In that case it is better to test the result
2273 // of the sign extension using LTGFR.
2274 //
2275 // This case is important because InstCombine transforms a comparison
2276 // with (sext (trunc X)) into a comparison with (shl X, 32).
adjustForLTGFR(Comparison & C)2277 static void adjustForLTGFR(Comparison &C) {
2278 // Check for a comparison between (shl X, 32) and 0.
2279 if (C.Op0.getOpcode() == ISD::SHL &&
2280 C.Op0.getValueType() == MVT::i64 &&
2281 C.Op1.getOpcode() == ISD::Constant &&
2282 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2283 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
2284 if (C1 && C1->getZExtValue() == 32) {
2285 SDValue ShlOp0 = C.Op0.getOperand(0);
2286 // See whether X has any SIGN_EXTEND_INREG uses.
2287 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
2288 SDNode *N = *I;
2289 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
2290 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
2291 C.Op0 = SDValue(N, 0);
2292 return;
2293 }
2294 }
2295 }
2296 }
2297 }
2298
2299 // If C compares the truncation of an extending load, try to compare
2300 // the untruncated value instead. This exposes more opportunities to
2301 // reuse CC.
adjustICmpTruncate(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2302 static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
2303 Comparison &C) {
2304 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
2305 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
2306 C.Op1.getOpcode() == ISD::Constant &&
2307 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2308 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
2309 if (L->getMemoryVT().getStoreSizeInBits().getFixedSize() <=
2310 C.Op0.getValueSizeInBits().getFixedSize()) {
2311 unsigned Type = L->getExtensionType();
2312 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
2313 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
2314 C.Op0 = C.Op0.getOperand(0);
2315 C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
2316 }
2317 }
2318 }
2319 }
2320
2321 // Return true if shift operation N has an in-range constant shift value.
2322 // Store it in ShiftVal if so.
isSimpleShift(SDValue N,unsigned & ShiftVal)2323 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
2324 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
2325 if (!Shift)
2326 return false;
2327
2328 uint64_t Amount = Shift->getZExtValue();
2329 if (Amount >= N.getValueSizeInBits())
2330 return false;
2331
2332 ShiftVal = Amount;
2333 return true;
2334 }
2335
2336 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
2337 // instruction and whether the CC value is descriptive enough to handle
2338 // a comparison of type Opcode between the AND result and CmpVal.
2339 // CCMask says which comparison result is being tested and BitSize is
2340 // the number of bits in the operands. If TEST UNDER MASK can be used,
2341 // return the corresponding CC mask, otherwise return 0.
getTestUnderMaskCond(unsigned BitSize,unsigned CCMask,uint64_t Mask,uint64_t CmpVal,unsigned ICmpType)2342 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
2343 uint64_t Mask, uint64_t CmpVal,
2344 unsigned ICmpType) {
2345 assert(Mask != 0 && "ANDs with zero should have been removed by now");
2346
2347 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
2348 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
2349 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
2350 return 0;
2351
2352 // Work out the masks for the lowest and highest bits.
2353 unsigned HighShift = 63 - countLeadingZeros(Mask);
2354 uint64_t High = uint64_t(1) << HighShift;
2355 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
2356
2357 // Signed ordered comparisons are effectively unsigned if the sign
2358 // bit is dropped.
2359 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
2360
2361 // Check for equality comparisons with 0, or the equivalent.
2362 if (CmpVal == 0) {
2363 if (CCMask == SystemZ::CCMASK_CMP_EQ)
2364 return SystemZ::CCMASK_TM_ALL_0;
2365 if (CCMask == SystemZ::CCMASK_CMP_NE)
2366 return SystemZ::CCMASK_TM_SOME_1;
2367 }
2368 if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
2369 if (CCMask == SystemZ::CCMASK_CMP_LT)
2370 return SystemZ::CCMASK_TM_ALL_0;
2371 if (CCMask == SystemZ::CCMASK_CMP_GE)
2372 return SystemZ::CCMASK_TM_SOME_1;
2373 }
2374 if (EffectivelyUnsigned && CmpVal < Low) {
2375 if (CCMask == SystemZ::CCMASK_CMP_LE)
2376 return SystemZ::CCMASK_TM_ALL_0;
2377 if (CCMask == SystemZ::CCMASK_CMP_GT)
2378 return SystemZ::CCMASK_TM_SOME_1;
2379 }
2380
2381 // Check for equality comparisons with the mask, or the equivalent.
2382 if (CmpVal == Mask) {
2383 if (CCMask == SystemZ::CCMASK_CMP_EQ)
2384 return SystemZ::CCMASK_TM_ALL_1;
2385 if (CCMask == SystemZ::CCMASK_CMP_NE)
2386 return SystemZ::CCMASK_TM_SOME_0;
2387 }
2388 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
2389 if (CCMask == SystemZ::CCMASK_CMP_GT)
2390 return SystemZ::CCMASK_TM_ALL_1;
2391 if (CCMask == SystemZ::CCMASK_CMP_LE)
2392 return SystemZ::CCMASK_TM_SOME_0;
2393 }
2394 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
2395 if (CCMask == SystemZ::CCMASK_CMP_GE)
2396 return SystemZ::CCMASK_TM_ALL_1;
2397 if (CCMask == SystemZ::CCMASK_CMP_LT)
2398 return SystemZ::CCMASK_TM_SOME_0;
2399 }
2400
2401 // Check for ordered comparisons with the top bit.
2402 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
2403 if (CCMask == SystemZ::CCMASK_CMP_LE)
2404 return SystemZ::CCMASK_TM_MSB_0;
2405 if (CCMask == SystemZ::CCMASK_CMP_GT)
2406 return SystemZ::CCMASK_TM_MSB_1;
2407 }
2408 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
2409 if (CCMask == SystemZ::CCMASK_CMP_LT)
2410 return SystemZ::CCMASK_TM_MSB_0;
2411 if (CCMask == SystemZ::CCMASK_CMP_GE)
2412 return SystemZ::CCMASK_TM_MSB_1;
2413 }
2414
2415 // If there are just two bits, we can do equality checks for Low and High
2416 // as well.
2417 if (Mask == Low + High) {
2418 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
2419 return SystemZ::CCMASK_TM_MIXED_MSB_0;
2420 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
2421 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
2422 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
2423 return SystemZ::CCMASK_TM_MIXED_MSB_1;
2424 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
2425 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
2426 }
2427
2428 // Looks like we've exhausted our options.
2429 return 0;
2430 }
2431
2432 // See whether C can be implemented as a TEST UNDER MASK instruction.
2433 // Update the arguments with the TM version if so.
adjustForTestUnderMask(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2434 static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
2435 Comparison &C) {
2436 // Check that we have a comparison with a constant.
2437 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
2438 if (!ConstOp1)
2439 return;
2440 uint64_t CmpVal = ConstOp1->getZExtValue();
2441
2442 // Check whether the nonconstant input is an AND with a constant mask.
2443 Comparison NewC(C);
2444 uint64_t MaskVal;
2445 ConstantSDNode *Mask = nullptr;
2446 if (C.Op0.getOpcode() == ISD::AND) {
2447 NewC.Op0 = C.Op0.getOperand(0);
2448 NewC.Op1 = C.Op0.getOperand(1);
2449 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
2450 if (!Mask)
2451 return;
2452 MaskVal = Mask->getZExtValue();
2453 } else {
2454 // There is no instruction to compare with a 64-bit immediate
2455 // so use TMHH instead if possible. We need an unsigned ordered
2456 // comparison with an i64 immediate.
2457 if (NewC.Op0.getValueType() != MVT::i64 ||
2458 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
2459 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
2460 NewC.ICmpType == SystemZICMP::SignedOnly)
2461 return;
2462 // Convert LE and GT comparisons into LT and GE.
2463 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
2464 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
2465 if (CmpVal == uint64_t(-1))
2466 return;
2467 CmpVal += 1;
2468 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2469 }
2470 // If the low N bits of Op1 are zero than the low N bits of Op0 can
2471 // be masked off without changing the result.
2472 MaskVal = -(CmpVal & -CmpVal);
2473 NewC.ICmpType = SystemZICMP::UnsignedOnly;
2474 }
2475 if (!MaskVal)
2476 return;
2477
2478 // Check whether the combination of mask, comparison value and comparison
2479 // type are suitable.
2480 unsigned BitSize = NewC.Op0.getValueSizeInBits();
2481 unsigned NewCCMask, ShiftVal;
2482 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2483 NewC.Op0.getOpcode() == ISD::SHL &&
2484 isSimpleShift(NewC.Op0, ShiftVal) &&
2485 (MaskVal >> ShiftVal != 0) &&
2486 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
2487 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2488 MaskVal >> ShiftVal,
2489 CmpVal >> ShiftVal,
2490 SystemZICMP::Any))) {
2491 NewC.Op0 = NewC.Op0.getOperand(0);
2492 MaskVal >>= ShiftVal;
2493 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2494 NewC.Op0.getOpcode() == ISD::SRL &&
2495 isSimpleShift(NewC.Op0, ShiftVal) &&
2496 (MaskVal << ShiftVal != 0) &&
2497 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal &&
2498 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2499 MaskVal << ShiftVal,
2500 CmpVal << ShiftVal,
2501 SystemZICMP::UnsignedOnly))) {
2502 NewC.Op0 = NewC.Op0.getOperand(0);
2503 MaskVal <<= ShiftVal;
2504 } else {
2505 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
2506 NewC.ICmpType);
2507 if (!NewCCMask)
2508 return;
2509 }
2510
2511 // Go ahead and make the change.
2512 C.Opcode = SystemZISD::TM;
2513 C.Op0 = NewC.Op0;
2514 if (Mask && Mask->getZExtValue() == MaskVal)
2515 C.Op1 = SDValue(Mask, 0);
2516 else
2517 C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
2518 C.CCValid = SystemZ::CCMASK_TM;
2519 C.CCMask = NewCCMask;
2520 }
2521
2522 // See whether the comparison argument contains a redundant AND
2523 // and remove it if so. This sometimes happens due to the generic
2524 // BRCOND expansion.
adjustForRedundantAnd(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2525 static void adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL,
2526 Comparison &C) {
2527 if (C.Op0.getOpcode() != ISD::AND)
2528 return;
2529 auto *Mask = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
2530 if (!Mask)
2531 return;
2532 KnownBits Known = DAG.computeKnownBits(C.Op0.getOperand(0));
2533 if ((~Known.Zero).getZExtValue() & ~Mask->getZExtValue())
2534 return;
2535
2536 C.Op0 = C.Op0.getOperand(0);
2537 }
2538
2539 // Return a Comparison that tests the condition-code result of intrinsic
2540 // node Call against constant integer CC using comparison code Cond.
2541 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2542 // and CCValid is the set of possible condition-code results.
getIntrinsicCmp(SelectionDAG & DAG,unsigned Opcode,SDValue Call,unsigned CCValid,uint64_t CC,ISD::CondCode Cond)2543 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2544 SDValue Call, unsigned CCValid, uint64_t CC,
2545 ISD::CondCode Cond) {
2546 Comparison C(Call, SDValue(), SDValue());
2547 C.Opcode = Opcode;
2548 C.CCValid = CCValid;
2549 if (Cond == ISD::SETEQ)
2550 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2551 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2552 else if (Cond == ISD::SETNE)
2553 // ...and the inverse of that.
2554 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2555 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2556 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2557 // always true for CC>3.
2558 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2559 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2560 // ...and the inverse of that.
2561 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2562 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2563 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2564 // always true for CC>3.
2565 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2566 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2567 // ...and the inverse of that.
2568 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2569 else
2570 llvm_unreachable("Unexpected integer comparison type");
2571 C.CCMask &= CCValid;
2572 return C;
2573 }
2574
2575 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
getCmp(SelectionDAG & DAG,SDValue CmpOp0,SDValue CmpOp1,ISD::CondCode Cond,const SDLoc & DL,SDValue Chain=SDValue (),bool IsSignaling=false)2576 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2577 ISD::CondCode Cond, const SDLoc &DL,
2578 SDValue Chain = SDValue(),
2579 bool IsSignaling = false) {
2580 if (CmpOp1.getOpcode() == ISD::Constant) {
2581 assert(!Chain);
2582 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2583 unsigned Opcode, CCValid;
2584 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2585 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2586 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2587 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2588 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2589 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2590 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2591 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2592 }
2593 Comparison C(CmpOp0, CmpOp1, Chain);
2594 C.CCMask = CCMaskForCondCode(Cond);
2595 if (C.Op0.getValueType().isFloatingPoint()) {
2596 C.CCValid = SystemZ::CCMASK_FCMP;
2597 if (!C.Chain)
2598 C.Opcode = SystemZISD::FCMP;
2599 else if (!IsSignaling)
2600 C.Opcode = SystemZISD::STRICT_FCMP;
2601 else
2602 C.Opcode = SystemZISD::STRICT_FCMPS;
2603 adjustForFNeg(C);
2604 } else {
2605 assert(!C.Chain);
2606 C.CCValid = SystemZ::CCMASK_ICMP;
2607 C.Opcode = SystemZISD::ICMP;
2608 // Choose the type of comparison. Equality and inequality tests can
2609 // use either signed or unsigned comparisons. The choice also doesn't
2610 // matter if both sign bits are known to be clear. In those cases we
2611 // want to give the main isel code the freedom to choose whichever
2612 // form fits best.
2613 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2614 C.CCMask == SystemZ::CCMASK_CMP_NE ||
2615 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2616 C.ICmpType = SystemZICMP::Any;
2617 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2618 C.ICmpType = SystemZICMP::UnsignedOnly;
2619 else
2620 C.ICmpType = SystemZICMP::SignedOnly;
2621 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2622 adjustForRedundantAnd(DAG, DL, C);
2623 adjustZeroCmp(DAG, DL, C);
2624 adjustSubwordCmp(DAG, DL, C);
2625 adjustForSubtraction(DAG, DL, C);
2626 adjustForLTGFR(C);
2627 adjustICmpTruncate(DAG, DL, C);
2628 }
2629
2630 if (shouldSwapCmpOperands(C)) {
2631 std::swap(C.Op0, C.Op1);
2632 C.CCMask = SystemZ::reverseCCMask(C.CCMask);
2633 }
2634
2635 adjustForTestUnderMask(DAG, DL, C);
2636 return C;
2637 }
2638
2639 // Emit the comparison instruction described by C.
emitCmp(SelectionDAG & DAG,const SDLoc & DL,Comparison & C)2640 static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2641 if (!C.Op1.getNode()) {
2642 SDNode *Node;
2643 switch (C.Op0.getOpcode()) {
2644 case ISD::INTRINSIC_W_CHAIN:
2645 Node = emitIntrinsicWithCCAndChain(DAG, C.Op0, C.Opcode);
2646 return SDValue(Node, 0);
2647 case ISD::INTRINSIC_WO_CHAIN:
2648 Node = emitIntrinsicWithCC(DAG, C.Op0, C.Opcode);
2649 return SDValue(Node, Node->getNumValues() - 1);
2650 default:
2651 llvm_unreachable("Invalid comparison operands");
2652 }
2653 }
2654 if (C.Opcode == SystemZISD::ICMP)
2655 return DAG.getNode(SystemZISD::ICMP, DL, MVT::i32, C.Op0, C.Op1,
2656 DAG.getTargetConstant(C.ICmpType, DL, MVT::i32));
2657 if (C.Opcode == SystemZISD::TM) {
2658 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2659 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2660 return DAG.getNode(SystemZISD::TM, DL, MVT::i32, C.Op0, C.Op1,
2661 DAG.getTargetConstant(RegisterOnly, DL, MVT::i32));
2662 }
2663 if (C.Chain) {
2664 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
2665 return DAG.getNode(C.Opcode, DL, VTs, C.Chain, C.Op0, C.Op1);
2666 }
2667 return DAG.getNode(C.Opcode, DL, MVT::i32, C.Op0, C.Op1);
2668 }
2669
2670 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2671 // 64 bits. Extend is the extension type to use. Store the high part
2672 // in Hi and the low part in Lo.
lowerMUL_LOHI32(SelectionDAG & DAG,const SDLoc & DL,unsigned Extend,SDValue Op0,SDValue Op1,SDValue & Hi,SDValue & Lo)2673 static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
2674 SDValue Op0, SDValue Op1, SDValue &Hi,
2675 SDValue &Lo) {
2676 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2677 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2678 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2679 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2680 DAG.getConstant(32, DL, MVT::i64));
2681 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2682 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2683 }
2684
2685 // Lower a binary operation that produces two VT results, one in each
2686 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2687 // and Opcode performs the GR128 operation. Store the even register result
2688 // in Even and the odd register result in Odd.
lowerGR128Binary(SelectionDAG & DAG,const SDLoc & DL,EVT VT,unsigned Opcode,SDValue Op0,SDValue Op1,SDValue & Even,SDValue & Odd)2689 static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2690 unsigned Opcode, SDValue Op0, SDValue Op1,
2691 SDValue &Even, SDValue &Odd) {
2692 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1);
2693 bool Is32Bit = is32Bit(VT);
2694 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2695 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2696 }
2697
2698 // Return an i32 value that is 1 if the CC value produced by CCReg is
2699 // in the mask CCMask and 0 otherwise. CC is known to have a value
2700 // in CCValid, so other values can be ignored.
emitSETCC(SelectionDAG & DAG,const SDLoc & DL,SDValue CCReg,unsigned CCValid,unsigned CCMask)2701 static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue CCReg,
2702 unsigned CCValid, unsigned CCMask) {
2703 SDValue Ops[] = {DAG.getConstant(1, DL, MVT::i32),
2704 DAG.getConstant(0, DL, MVT::i32),
2705 DAG.getTargetConstant(CCValid, DL, MVT::i32),
2706 DAG.getTargetConstant(CCMask, DL, MVT::i32), CCReg};
2707 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, MVT::i32, Ops);
2708 }
2709
2710 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2711 // be done directly. Mode is CmpMode::Int for integer comparisons, CmpMode::FP
2712 // for regular floating-point comparisons, CmpMode::StrictFP for strict (quiet)
2713 // floating-point comparisons, and CmpMode::SignalingFP for strict signaling
2714 // floating-point comparisons.
2715 enum class CmpMode { Int, FP, StrictFP, SignalingFP };
getVectorComparison(ISD::CondCode CC,CmpMode Mode)2716 static unsigned getVectorComparison(ISD::CondCode CC, CmpMode Mode) {
2717 switch (CC) {
2718 case ISD::SETOEQ:
2719 case ISD::SETEQ:
2720 switch (Mode) {
2721 case CmpMode::Int: return SystemZISD::VICMPE;
2722 case CmpMode::FP: return SystemZISD::VFCMPE;
2723 case CmpMode::StrictFP: return SystemZISD::STRICT_VFCMPE;
2724 case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPES;
2725 }
2726 llvm_unreachable("Bad mode");
2727
2728 case ISD::SETOGE:
2729 case ISD::SETGE:
2730 switch (Mode) {
2731 case CmpMode::Int: return 0;
2732 case CmpMode::FP: return SystemZISD::VFCMPHE;
2733 case CmpMode::StrictFP: return SystemZISD::STRICT_VFCMPHE;
2734 case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPHES;
2735 }
2736 llvm_unreachable("Bad mode");
2737
2738 case ISD::SETOGT:
2739 case ISD::SETGT:
2740 switch (Mode) {
2741 case CmpMode::Int: return SystemZISD::VICMPH;
2742 case CmpMode::FP: return SystemZISD::VFCMPH;
2743 case CmpMode::StrictFP: return SystemZISD::STRICT_VFCMPH;
2744 case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPHS;
2745 }
2746 llvm_unreachable("Bad mode");
2747
2748 case ISD::SETUGT:
2749 switch (Mode) {
2750 case CmpMode::Int: return SystemZISD::VICMPHL;
2751 case CmpMode::FP: return 0;
2752 case CmpMode::StrictFP: return 0;
2753 case CmpMode::SignalingFP: return 0;
2754 }
2755 llvm_unreachable("Bad mode");
2756
2757 default:
2758 return 0;
2759 }
2760 }
2761
2762 // Return the SystemZISD vector comparison operation for CC or its inverse,
2763 // or 0 if neither can be done directly. Indicate in Invert whether the
2764 // result is for the inverse of CC. Mode is as above.
getVectorComparisonOrInvert(ISD::CondCode CC,CmpMode Mode,bool & Invert)2765 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode,
2766 bool &Invert) {
2767 if (unsigned Opcode = getVectorComparison(CC, Mode)) {
2768 Invert = false;
2769 return Opcode;
2770 }
2771
2772 CC = ISD::getSetCCInverse(CC, Mode == CmpMode::Int ? MVT::i32 : MVT::f32);
2773 if (unsigned Opcode = getVectorComparison(CC, Mode)) {
2774 Invert = true;
2775 return Opcode;
2776 }
2777
2778 return 0;
2779 }
2780
2781 // Return a v2f64 that contains the extended form of elements Start and Start+1
2782 // of v4f32 value Op. If Chain is nonnull, return the strict form.
expandV4F32ToV2F64(SelectionDAG & DAG,int Start,const SDLoc & DL,SDValue Op,SDValue Chain)2783 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
2784 SDValue Op, SDValue Chain) {
2785 int Mask[] = { Start, -1, Start + 1, -1 };
2786 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2787 if (Chain) {
2788 SDVTList VTs = DAG.getVTList(MVT::v2f64, MVT::Other);
2789 return DAG.getNode(SystemZISD::STRICT_VEXTEND, DL, VTs, Chain, Op);
2790 }
2791 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2792 }
2793
2794 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2795 // producing a result of type VT. If Chain is nonnull, return the strict form.
getVectorCmp(SelectionDAG & DAG,unsigned Opcode,const SDLoc & DL,EVT VT,SDValue CmpOp0,SDValue CmpOp1,SDValue Chain) const2796 SDValue SystemZTargetLowering::getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
2797 const SDLoc &DL, EVT VT,
2798 SDValue CmpOp0,
2799 SDValue CmpOp1,
2800 SDValue Chain) const {
2801 // There is no hardware support for v4f32 (unless we have the vector
2802 // enhancements facility 1), so extend the vector into two v2f64s
2803 // and compare those.
2804 if (CmpOp0.getValueType() == MVT::v4f32 &&
2805 !Subtarget.hasVectorEnhancements1()) {
2806 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0, Chain);
2807 SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0, Chain);
2808 SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1, Chain);
2809 SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1, Chain);
2810 if (Chain) {
2811 SDVTList VTs = DAG.getVTList(MVT::v2i64, MVT::Other);
2812 SDValue HRes = DAG.getNode(Opcode, DL, VTs, Chain, H0, H1);
2813 SDValue LRes = DAG.getNode(Opcode, DL, VTs, Chain, L0, L1);
2814 SDValue Res = DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2815 SDValue Chains[6] = { H0.getValue(1), L0.getValue(1),
2816 H1.getValue(1), L1.getValue(1),
2817 HRes.getValue(1), LRes.getValue(1) };
2818 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2819 SDValue Ops[2] = { Res, NewChain };
2820 return DAG.getMergeValues(Ops, DL);
2821 }
2822 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2823 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2824 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2825 }
2826 if (Chain) {
2827 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2828 return DAG.getNode(Opcode, DL, VTs, Chain, CmpOp0, CmpOp1);
2829 }
2830 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2831 }
2832
2833 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2834 // an integer mask of type VT. If Chain is nonnull, we have a strict
2835 // floating-point comparison. If in addition IsSignaling is true, we have
2836 // a strict signaling floating-point comparison.
lowerVectorSETCC(SelectionDAG & DAG,const SDLoc & DL,EVT VT,ISD::CondCode CC,SDValue CmpOp0,SDValue CmpOp1,SDValue Chain,bool IsSignaling) const2837 SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
2838 const SDLoc &DL, EVT VT,
2839 ISD::CondCode CC,
2840 SDValue CmpOp0,
2841 SDValue CmpOp1,
2842 SDValue Chain,
2843 bool IsSignaling) const {
2844 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2845 assert (!Chain || IsFP);
2846 assert (!IsSignaling || Chain);
2847 CmpMode Mode = IsSignaling ? CmpMode::SignalingFP :
2848 Chain ? CmpMode::StrictFP : IsFP ? CmpMode::FP : CmpMode::Int;
2849 bool Invert = false;
2850 SDValue Cmp;
2851 switch (CC) {
2852 // Handle tests for order using (or (ogt y x) (oge x y)).
2853 case ISD::SETUO:
2854 Invert = true;
2855 LLVM_FALLTHROUGH;
2856 case ISD::SETO: {
2857 assert(IsFP && "Unexpected integer comparison");
2858 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
2859 DL, VT, CmpOp1, CmpOp0, Chain);
2860 SDValue GE = getVectorCmp(DAG, getVectorComparison(ISD::SETOGE, Mode),
2861 DL, VT, CmpOp0, CmpOp1, Chain);
2862 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2863 if (Chain)
2864 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2865 LT.getValue(1), GE.getValue(1));
2866 break;
2867 }
2868
2869 // Handle <> tests using (or (ogt y x) (ogt x y)).
2870 case ISD::SETUEQ:
2871 Invert = true;
2872 LLVM_FALLTHROUGH;
2873 case ISD::SETONE: {
2874 assert(IsFP && "Unexpected integer comparison");
2875 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
2876 DL, VT, CmpOp1, CmpOp0, Chain);
2877 SDValue GT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
2878 DL, VT, CmpOp0, CmpOp1, Chain);
2879 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2880 if (Chain)
2881 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2882 LT.getValue(1), GT.getValue(1));
2883 break;
2884 }
2885
2886 // Otherwise a single comparison is enough. It doesn't really
2887 // matter whether we try the inversion or the swap first, since
2888 // there are no cases where both work.
2889 default:
2890 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
2891 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1, Chain);
2892 else {
2893 CC = ISD::getSetCCSwappedOperands(CC);
2894 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
2895 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0, Chain);
2896 else
2897 llvm_unreachable("Unhandled comparison");
2898 }
2899 if (Chain)
2900 Chain = Cmp.getValue(1);
2901 break;
2902 }
2903 if (Invert) {
2904 SDValue Mask =
2905 DAG.getSplatBuildVector(VT, DL, DAG.getConstant(-1, DL, MVT::i64));
2906 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2907 }
2908 if (Chain && Chain.getNode() != Cmp.getNode()) {
2909 SDValue Ops[2] = { Cmp, Chain };
2910 Cmp = DAG.getMergeValues(Ops, DL);
2911 }
2912 return Cmp;
2913 }
2914
lowerSETCC(SDValue Op,SelectionDAG & DAG) const2915 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2916 SelectionDAG &DAG) const {
2917 SDValue CmpOp0 = Op.getOperand(0);
2918 SDValue CmpOp1 = Op.getOperand(1);
2919 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2920 SDLoc DL(Op);
2921 EVT VT = Op.getValueType();
2922 if (VT.isVector())
2923 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2924
2925 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2926 SDValue CCReg = emitCmp(DAG, DL, C);
2927 return emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
2928 }
2929
lowerSTRICT_FSETCC(SDValue Op,SelectionDAG & DAG,bool IsSignaling) const2930 SDValue SystemZTargetLowering::lowerSTRICT_FSETCC(SDValue Op,
2931 SelectionDAG &DAG,
2932 bool IsSignaling) const {
2933 SDValue Chain = Op.getOperand(0);
2934 SDValue CmpOp0 = Op.getOperand(1);
2935 SDValue CmpOp1 = Op.getOperand(2);
2936 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
2937 SDLoc DL(Op);
2938 EVT VT = Op.getNode()->getValueType(0);
2939 if (VT.isVector()) {
2940 SDValue Res = lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1,
2941 Chain, IsSignaling);
2942 return Res.getValue(Op.getResNo());
2943 }
2944
2945 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL, Chain, IsSignaling));
2946 SDValue CCReg = emitCmp(DAG, DL, C);
2947 CCReg->setFlags(Op->getFlags());
2948 SDValue Result = emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
2949 SDValue Ops[2] = { Result, CCReg.getValue(1) };
2950 return DAG.getMergeValues(Ops, DL);
2951 }
2952
lowerBR_CC(SDValue Op,SelectionDAG & DAG) const2953 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2954 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2955 SDValue CmpOp0 = Op.getOperand(2);
2956 SDValue CmpOp1 = Op.getOperand(3);
2957 SDValue Dest = Op.getOperand(4);
2958 SDLoc DL(Op);
2959
2960 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2961 SDValue CCReg = emitCmp(DAG, DL, C);
2962 return DAG.getNode(
2963 SystemZISD::BR_CCMASK, DL, Op.getValueType(), Op.getOperand(0),
2964 DAG.getTargetConstant(C.CCValid, DL, MVT::i32),
2965 DAG.getTargetConstant(C.CCMask, DL, MVT::i32), Dest, CCReg);
2966 }
2967
2968 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2969 // allowing Pos and Neg to be wider than CmpOp.
isAbsolute(SDValue CmpOp,SDValue Pos,SDValue Neg)2970 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2971 return (Neg.getOpcode() == ISD::SUB &&
2972 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2973 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2974 Neg.getOperand(1) == Pos &&
2975 (Pos == CmpOp ||
2976 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2977 Pos.getOperand(0) == CmpOp)));
2978 }
2979
2980 // Return the absolute or negative absolute of Op; IsNegative decides which.
getAbsolute(SelectionDAG & DAG,const SDLoc & DL,SDValue Op,bool IsNegative)2981 static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
2982 bool IsNegative) {
2983 Op = DAG.getNode(ISD::ABS, DL, Op.getValueType(), Op);
2984 if (IsNegative)
2985 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2986 DAG.getConstant(0, DL, Op.getValueType()), Op);
2987 return Op;
2988 }
2989
lowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const2990 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2991 SelectionDAG &DAG) const {
2992 SDValue CmpOp0 = Op.getOperand(0);
2993 SDValue CmpOp1 = Op.getOperand(1);
2994 SDValue TrueOp = Op.getOperand(2);
2995 SDValue FalseOp = Op.getOperand(3);
2996 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2997 SDLoc DL(Op);
2998
2999 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
3000
3001 // Check for absolute and negative-absolute selections, including those
3002 // where the comparison value is sign-extended (for LPGFR and LNGFR).
3003 // This check supplements the one in DAGCombiner.
3004 if (C.Opcode == SystemZISD::ICMP &&
3005 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
3006 C.CCMask != SystemZ::CCMASK_CMP_NE &&
3007 C.Op1.getOpcode() == ISD::Constant &&
3008 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
3009 if (isAbsolute(C.Op0, TrueOp, FalseOp))
3010 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
3011 if (isAbsolute(C.Op0, FalseOp, TrueOp))
3012 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
3013 }
3014
3015 SDValue CCReg = emitCmp(DAG, DL, C);
3016 SDValue Ops[] = {TrueOp, FalseOp,
3017 DAG.getTargetConstant(C.CCValid, DL, MVT::i32),
3018 DAG.getTargetConstant(C.CCMask, DL, MVT::i32), CCReg};
3019
3020 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, Op.getValueType(), Ops);
3021 }
3022
lowerGlobalAddress(GlobalAddressSDNode * Node,SelectionDAG & DAG) const3023 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
3024 SelectionDAG &DAG) const {
3025 SDLoc DL(Node);
3026 const GlobalValue *GV = Node->getGlobal();
3027 int64_t Offset = Node->getOffset();
3028 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3029 CodeModel::Model CM = DAG.getTarget().getCodeModel();
3030
3031 SDValue Result;
3032 if (Subtarget.isPC32DBLSymbol(GV, CM)) {
3033 if (isInt<32>(Offset)) {
3034 // Assign anchors at 1<<12 byte boundaries.
3035 uint64_t Anchor = Offset & ~uint64_t(0xfff);
3036 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
3037 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3038
3039 // The offset can be folded into the address if it is aligned to a
3040 // halfword.
3041 Offset -= Anchor;
3042 if (Offset != 0 && (Offset & 1) == 0) {
3043 SDValue Full =
3044 DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
3045 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
3046 Offset = 0;
3047 }
3048 } else {
3049 // Conservatively load a constant offset greater than 32 bits into a
3050 // register below.
3051 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT);
3052 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3053 }
3054 } else {
3055 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
3056 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3057 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3058 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3059 }
3060
3061 // If there was a non-zero offset that we didn't fold, create an explicit
3062 // addition for it.
3063 if (Offset != 0)
3064 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
3065 DAG.getConstant(Offset, DL, PtrVT));
3066
3067 return Result;
3068 }
3069
lowerTLSGetOffset(GlobalAddressSDNode * Node,SelectionDAG & DAG,unsigned Opcode,SDValue GOTOffset) const3070 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
3071 SelectionDAG &DAG,
3072 unsigned Opcode,
3073 SDValue GOTOffset) const {
3074 SDLoc DL(Node);
3075 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3076 SDValue Chain = DAG.getEntryNode();
3077 SDValue Glue;
3078
3079 if (DAG.getMachineFunction().getFunction().getCallingConv() ==
3080 CallingConv::GHC)
3081 report_fatal_error("In GHC calling convention TLS is not supported");
3082
3083 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
3084 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
3085 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
3086 Glue = Chain.getValue(1);
3087 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
3088 Glue = Chain.getValue(1);
3089
3090 // The first call operand is the chain and the second is the TLS symbol.
3091 SmallVector<SDValue, 8> Ops;
3092 Ops.push_back(Chain);
3093 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
3094 Node->getValueType(0),
3095 0, 0));
3096
3097 // Add argument registers to the end of the list so that they are
3098 // known live into the call.
3099 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
3100 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
3101
3102 // Add a register mask operand representing the call-preserved registers.
3103 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3104 const uint32_t *Mask =
3105 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3106 assert(Mask && "Missing call preserved mask for calling convention");
3107 Ops.push_back(DAG.getRegisterMask(Mask));
3108
3109 // Glue the call to the argument copies.
3110 Ops.push_back(Glue);
3111
3112 // Emit the call.
3113 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3114 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
3115 Glue = Chain.getValue(1);
3116
3117 // Copy the return value from %r2.
3118 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
3119 }
3120
lowerThreadPointer(const SDLoc & DL,SelectionDAG & DAG) const3121 SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
3122 SelectionDAG &DAG) const {
3123 SDValue Chain = DAG.getEntryNode();
3124 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3125
3126 // The high part of the thread pointer is in access register 0.
3127 SDValue TPHi = DAG.getCopyFromReg(Chain, DL, SystemZ::A0, MVT::i32);
3128 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
3129
3130 // The low part of the thread pointer is in access register 1.
3131 SDValue TPLo = DAG.getCopyFromReg(Chain, DL, SystemZ::A1, MVT::i32);
3132 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
3133
3134 // Merge them into a single 64-bit address.
3135 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
3136 DAG.getConstant(32, DL, PtrVT));
3137 return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
3138 }
3139
lowerGlobalTLSAddress(GlobalAddressSDNode * Node,SelectionDAG & DAG) const3140 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
3141 SelectionDAG &DAG) const {
3142 if (DAG.getTarget().useEmulatedTLS())
3143 return LowerToTLSEmulatedModel(Node, DAG);
3144 SDLoc DL(Node);
3145 const GlobalValue *GV = Node->getGlobal();
3146 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3147 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
3148
3149 if (DAG.getMachineFunction().getFunction().getCallingConv() ==
3150 CallingConv::GHC)
3151 report_fatal_error("In GHC calling convention TLS is not supported");
3152
3153 SDValue TP = lowerThreadPointer(DL, DAG);
3154
3155 // Get the offset of GA from the thread pointer, based on the TLS model.
3156 SDValue Offset;
3157 switch (model) {
3158 case TLSModel::GeneralDynamic: {
3159 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
3160 SystemZConstantPoolValue *CPV =
3161 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
3162
3163 Offset = DAG.getConstantPool(CPV, PtrVT, Align(8));
3164 Offset = DAG.getLoad(
3165 PtrVT, DL, DAG.getEntryNode(), Offset,
3166 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3167
3168 // Call __tls_get_offset to retrieve the offset.
3169 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
3170 break;
3171 }
3172
3173 case TLSModel::LocalDynamic: {
3174 // Load the GOT offset of the module ID.
3175 SystemZConstantPoolValue *CPV =
3176 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
3177
3178 Offset = DAG.getConstantPool(CPV, PtrVT, Align(8));
3179 Offset = DAG.getLoad(
3180 PtrVT, DL, DAG.getEntryNode(), Offset,
3181 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3182
3183 // Call __tls_get_offset to retrieve the module base offset.
3184 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
3185
3186 // Note: The SystemZLDCleanupPass will remove redundant computations
3187 // of the module base offset. Count total number of local-dynamic
3188 // accesses to trigger execution of that pass.
3189 SystemZMachineFunctionInfo* MFI =
3190 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
3191 MFI->incNumLocalDynamicTLSAccesses();
3192
3193 // Add the per-symbol offset.
3194 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
3195
3196 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, Align(8));
3197 DTPOffset = DAG.getLoad(
3198 PtrVT, DL, DAG.getEntryNode(), DTPOffset,
3199 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3200
3201 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
3202 break;
3203 }
3204
3205 case TLSModel::InitialExec: {
3206 // Load the offset from the GOT.
3207 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3208 SystemZII::MO_INDNTPOFF);
3209 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
3210 Offset =
3211 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
3212 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3213 break;
3214 }
3215
3216 case TLSModel::LocalExec: {
3217 // Force the offset into the constant pool and load it from there.
3218 SystemZConstantPoolValue *CPV =
3219 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
3220
3221 Offset = DAG.getConstantPool(CPV, PtrVT, Align(8));
3222 Offset = DAG.getLoad(
3223 PtrVT, DL, DAG.getEntryNode(), Offset,
3224 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3225 break;
3226 }
3227 }
3228
3229 // Add the base and offset together.
3230 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
3231 }
3232
lowerBlockAddress(BlockAddressSDNode * Node,SelectionDAG & DAG) const3233 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
3234 SelectionDAG &DAG) const {
3235 SDLoc DL(Node);
3236 const BlockAddress *BA = Node->getBlockAddress();
3237 int64_t Offset = Node->getOffset();
3238 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3239
3240 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
3241 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3242 return Result;
3243 }
3244
lowerJumpTable(JumpTableSDNode * JT,SelectionDAG & DAG) const3245 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
3246 SelectionDAG &DAG) const {
3247 SDLoc DL(JT);
3248 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3249 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3250
3251 // Use LARL to load the address of the table.
3252 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3253 }
3254
lowerConstantPool(ConstantPoolSDNode * CP,SelectionDAG & DAG) const3255 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
3256 SelectionDAG &DAG) const {
3257 SDLoc DL(CP);
3258 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3259
3260 SDValue Result;
3261 if (CP->isMachineConstantPoolEntry())
3262 Result =
3263 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3264 else
3265 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(),
3266 CP->getOffset());
3267
3268 // Use LARL to load the address of the constant pool entry.
3269 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
3270 }
3271
lowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const3272 SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
3273 SelectionDAG &DAG) const {
3274 auto *TFL =
3275 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
3276 MachineFunction &MF = DAG.getMachineFunction();
3277 MachineFrameInfo &MFI = MF.getFrameInfo();
3278 MFI.setFrameAddressIsTaken(true);
3279
3280 SDLoc DL(Op);
3281 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3282 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3283
3284 // Return null if the back chain is not present.
3285 bool HasBackChain = MF.getFunction().hasFnAttribute("backchain");
3286 if (TFL->usePackedStack(MF) && !HasBackChain)
3287 return DAG.getConstant(0, DL, PtrVT);
3288
3289 // By definition, the frame address is the address of the back chain.
3290 int BackChainIdx = TFL->getOrCreateFramePointerSaveIndex(MF);
3291 SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
3292
3293 // FIXME The frontend should detect this case.
3294 if (Depth > 0) {
3295 report_fatal_error("Unsupported stack frame traversal count");
3296 }
3297
3298 return BackChain;
3299 }
3300
lowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const3301 SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
3302 SelectionDAG &DAG) const {
3303 MachineFunction &MF = DAG.getMachineFunction();
3304 MachineFrameInfo &MFI = MF.getFrameInfo();
3305 MFI.setReturnAddressIsTaken(true);
3306
3307 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
3308 return SDValue();
3309
3310 SDLoc DL(Op);
3311 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3312 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3313
3314 // FIXME The frontend should detect this case.
3315 if (Depth > 0) {
3316 report_fatal_error("Unsupported stack frame traversal count");
3317 }
3318
3319 // Return R14D, which has the return address. Mark it an implicit live-in.
3320 unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
3321 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
3322 }
3323
lowerBITCAST(SDValue Op,SelectionDAG & DAG) const3324 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
3325 SelectionDAG &DAG) const {
3326 SDLoc DL(Op);
3327 SDValue In = Op.getOperand(0);
3328 EVT InVT = In.getValueType();
3329 EVT ResVT = Op.getValueType();
3330
3331 // Convert loads directly. This is normally done by DAGCombiner,
3332 // but we need this case for bitcasts that are created during lowering
3333 // and which are then lowered themselves.
3334 if (auto *LoadN = dyn_cast<LoadSDNode>(In))
3335 if (ISD::isNormalLoad(LoadN)) {
3336 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(),
3337 LoadN->getBasePtr(), LoadN->getMemOperand());
3338 // Update the chain uses.
3339 DAG.ReplaceAllUsesOfValueWith(SDValue(LoadN, 1), NewLoad.getValue(1));
3340 return NewLoad;
3341 }
3342
3343 if (InVT == MVT::i32 && ResVT == MVT::f32) {
3344 SDValue In64;
3345 if (Subtarget.hasHighWord()) {
3346 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
3347 MVT::i64);
3348 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
3349 MVT::i64, SDValue(U64, 0), In);
3350 } else {
3351 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
3352 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
3353 DAG.getConstant(32, DL, MVT::i64));
3354 }
3355 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
3356 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
3357 DL, MVT::f32, Out64);
3358 }
3359 if (InVT == MVT::f32 && ResVT == MVT::i32) {
3360 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
3361 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
3362 MVT::f64, SDValue(U64, 0), In);
3363 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
3364 if (Subtarget.hasHighWord())
3365 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
3366 MVT::i32, Out64);
3367 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
3368 DAG.getConstant(32, DL, MVT::i64));
3369 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
3370 }
3371 llvm_unreachable("Unexpected bitcast combination");
3372 }
3373
lowerVASTART(SDValue Op,SelectionDAG & DAG) const3374 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
3375 SelectionDAG &DAG) const {
3376 MachineFunction &MF = DAG.getMachineFunction();
3377 SystemZMachineFunctionInfo *FuncInfo =
3378 MF.getInfo<SystemZMachineFunctionInfo>();
3379 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3380
3381 SDValue Chain = Op.getOperand(0);
3382 SDValue Addr = Op.getOperand(1);
3383 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3384 SDLoc DL(Op);
3385
3386 // The initial values of each field.
3387 const unsigned NumFields = 4;
3388 SDValue Fields[NumFields] = {
3389 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
3390 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
3391 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
3392 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
3393 };
3394
3395 // Store each field into its respective slot.
3396 SDValue MemOps[NumFields];
3397 unsigned Offset = 0;
3398 for (unsigned I = 0; I < NumFields; ++I) {
3399 SDValue FieldAddr = Addr;
3400 if (Offset != 0)
3401 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
3402 DAG.getIntPtrConstant(Offset, DL));
3403 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
3404 MachinePointerInfo(SV, Offset));
3405 Offset += 8;
3406 }
3407 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3408 }
3409
lowerVACOPY(SDValue Op,SelectionDAG & DAG) const3410 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
3411 SelectionDAG &DAG) const {
3412 SDValue Chain = Op.getOperand(0);
3413 SDValue DstPtr = Op.getOperand(1);
3414 SDValue SrcPtr = Op.getOperand(2);
3415 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3416 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3417 SDLoc DL(Op);
3418
3419 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
3420 Align(8), /*isVolatile*/ false, /*AlwaysInline*/ false,
3421 /*isTailCall*/ false, MachinePointerInfo(DstSV),
3422 MachinePointerInfo(SrcSV));
3423 }
3424
3425 SDValue SystemZTargetLowering::
lowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG) const3426 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
3427 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
3428 MachineFunction &MF = DAG.getMachineFunction();
3429 bool RealignOpt = !MF.getFunction().hasFnAttribute("no-realign-stack");
3430 bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
3431
3432 SDValue Chain = Op.getOperand(0);
3433 SDValue Size = Op.getOperand(1);
3434 SDValue Align = Op.getOperand(2);
3435 SDLoc DL(Op);
3436
3437 // If user has set the no alignment function attribute, ignore
3438 // alloca alignments.
3439 uint64_t AlignVal =
3440 (RealignOpt ? cast<ConstantSDNode>(Align)->getZExtValue() : 0);
3441
3442 uint64_t StackAlign = TFI->getStackAlignment();
3443 uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
3444 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
3445
3446 Register SPReg = getStackPointerRegisterToSaveRestore();
3447 SDValue NeededSpace = Size;
3448
3449 // Get a reference to the stack pointer.
3450 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
3451
3452 // If we need a backchain, save it now.
3453 SDValue Backchain;
3454 if (StoreBackchain)
3455 Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP, DAG),
3456 MachinePointerInfo());
3457
3458 // Add extra space for alignment if needed.
3459 if (ExtraAlignSpace)
3460 NeededSpace = DAG.getNode(ISD::ADD, DL, MVT::i64, NeededSpace,
3461 DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
3462
3463 // Get the new stack pointer value.
3464 SDValue NewSP;
3465 if (hasInlineStackProbe(MF)) {
3466 NewSP = DAG.getNode(SystemZISD::PROBED_ALLOCA, DL,
3467 DAG.getVTList(MVT::i64, MVT::Other), Chain, OldSP, NeededSpace);
3468 Chain = NewSP.getValue(1);
3469 }
3470 else {
3471 NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
3472 // Copy the new stack pointer back.
3473 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
3474 }
3475
3476 // The allocated data lives above the 160 bytes allocated for the standard
3477 // frame, plus any outgoing stack arguments. We don't know how much that
3478 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
3479 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
3480 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
3481
3482 // Dynamically realign if needed.
3483 if (RequiredAlign > StackAlign) {
3484 Result =
3485 DAG.getNode(ISD::ADD, DL, MVT::i64, Result,
3486 DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
3487 Result =
3488 DAG.getNode(ISD::AND, DL, MVT::i64, Result,
3489 DAG.getConstant(~(RequiredAlign - 1), DL, MVT::i64));
3490 }
3491
3492 if (StoreBackchain)
3493 Chain = DAG.getStore(Chain, DL, Backchain, getBackchainAddress(NewSP, DAG),
3494 MachinePointerInfo());
3495
3496 SDValue Ops[2] = { Result, Chain };
3497 return DAG.getMergeValues(Ops, DL);
3498 }
3499
lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op,SelectionDAG & DAG) const3500 SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
3501 SDValue Op, SelectionDAG &DAG) const {
3502 SDLoc DL(Op);
3503
3504 return DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
3505 }
3506
lowerSMUL_LOHI(SDValue Op,SelectionDAG & DAG) const3507 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
3508 SelectionDAG &DAG) const {
3509 EVT VT = Op.getValueType();
3510 SDLoc DL(Op);
3511 SDValue Ops[2];
3512 if (is32Bit(VT))
3513 // Just do a normal 64-bit multiplication and extract the results.
3514 // We define this so that it can be used for constant division.
3515 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
3516 Op.getOperand(1), Ops[1], Ops[0]);
3517 else if (Subtarget.hasMiscellaneousExtensions2())
3518 // SystemZISD::SMUL_LOHI returns the low result in the odd register and
3519 // the high result in the even register. ISD::SMUL_LOHI is defined to
3520 // return the low half first, so the results are in reverse order.
3521 lowerGR128Binary(DAG, DL, VT, SystemZISD::SMUL_LOHI,
3522 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3523 else {
3524 // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
3525 //
3526 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
3527 //
3528 // but using the fact that the upper halves are either all zeros
3529 // or all ones:
3530 //
3531 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
3532 //
3533 // and grouping the right terms together since they are quicker than the
3534 // multiplication:
3535 //
3536 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
3537 SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
3538 SDValue LL = Op.getOperand(0);
3539 SDValue RL = Op.getOperand(1);
3540 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
3541 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
3542 // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3543 // the high result in the even register. ISD::SMUL_LOHI is defined to
3544 // return the low half first, so the results are in reverse order.
3545 lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
3546 LL, RL, Ops[1], Ops[0]);
3547 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
3548 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
3549 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
3550 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
3551 }
3552 return DAG.getMergeValues(Ops, DL);
3553 }
3554
lowerUMUL_LOHI(SDValue Op,SelectionDAG & DAG) const3555 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
3556 SelectionDAG &DAG) const {
3557 EVT VT = Op.getValueType();
3558 SDLoc DL(Op);
3559 SDValue Ops[2];
3560 if (is32Bit(VT))
3561 // Just do a normal 64-bit multiplication and extract the results.
3562 // We define this so that it can be used for constant division.
3563 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
3564 Op.getOperand(1), Ops[1], Ops[0]);
3565 else
3566 // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3567 // the high result in the even register. ISD::UMUL_LOHI is defined to
3568 // return the low half first, so the results are in reverse order.
3569 lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
3570 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3571 return DAG.getMergeValues(Ops, DL);
3572 }
3573
lowerSDIVREM(SDValue Op,SelectionDAG & DAG) const3574 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
3575 SelectionDAG &DAG) const {
3576 SDValue Op0 = Op.getOperand(0);
3577 SDValue Op1 = Op.getOperand(1);
3578 EVT VT = Op.getValueType();
3579 SDLoc DL(Op);
3580
3581 // We use DSGF for 32-bit division. This means the first operand must
3582 // always be 64-bit, and the second operand should be 32-bit whenever
3583 // that is possible, to improve performance.
3584 if (is32Bit(VT))
3585 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
3586 else if (DAG.ComputeNumSignBits(Op1) > 32)
3587 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
3588
3589 // DSG(F) returns the remainder in the even register and the
3590 // quotient in the odd register.
3591 SDValue Ops[2];
3592 lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]);
3593 return DAG.getMergeValues(Ops, DL);
3594 }
3595
lowerUDIVREM(SDValue Op,SelectionDAG & DAG) const3596 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
3597 SelectionDAG &DAG) const {
3598 EVT VT = Op.getValueType();
3599 SDLoc DL(Op);
3600
3601 // DL(G) returns the remainder in the even register and the
3602 // quotient in the odd register.
3603 SDValue Ops[2];
3604 lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM,
3605 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3606 return DAG.getMergeValues(Ops, DL);
3607 }
3608
lowerOR(SDValue Op,SelectionDAG & DAG) const3609 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
3610 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3611
3612 // Get the known-zero masks for each operand.
3613 SDValue Ops[] = {Op.getOperand(0), Op.getOperand(1)};
3614 KnownBits Known[2] = {DAG.computeKnownBits(Ops[0]),
3615 DAG.computeKnownBits(Ops[1])};
3616
3617 // See if the upper 32 bits of one operand and the lower 32 bits of the
3618 // other are known zero. They are the low and high operands respectively.
3619 uint64_t Masks[] = { Known[0].Zero.getZExtValue(),
3620 Known[1].Zero.getZExtValue() };
3621 unsigned High, Low;
3622 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
3623 High = 1, Low = 0;
3624 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
3625 High = 0, Low = 1;
3626 else
3627 return Op;
3628
3629 SDValue LowOp = Ops[Low];
3630 SDValue HighOp = Ops[High];
3631
3632 // If the high part is a constant, we're better off using IILH.
3633 if (HighOp.getOpcode() == ISD::Constant)
3634 return Op;
3635
3636 // If the low part is a constant that is outside the range of LHI,
3637 // then we're better off using IILF.
3638 if (LowOp.getOpcode() == ISD::Constant) {
3639 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
3640 if (!isInt<16>(Value))
3641 return Op;
3642 }
3643
3644 // Check whether the high part is an AND that doesn't change the
3645 // high 32 bits and just masks out low bits. We can skip it if so.
3646 if (HighOp.getOpcode() == ISD::AND &&
3647 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
3648 SDValue HighOp0 = HighOp.getOperand(0);
3649 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
3650 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
3651 HighOp = HighOp0;
3652 }
3653
3654 // Take advantage of the fact that all GR32 operations only change the
3655 // low 32 bits by truncating Low to an i32 and inserting it directly
3656 // using a subreg. The interesting cases are those where the truncation
3657 // can be folded.
3658 SDLoc DL(Op);
3659 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
3660 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
3661 MVT::i64, HighOp, Low32);
3662 }
3663
3664 // Lower SADDO/SSUBO/UADDO/USUBO nodes.
lowerXALUO(SDValue Op,SelectionDAG & DAG) const3665 SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
3666 SelectionDAG &DAG) const {
3667 SDNode *N = Op.getNode();
3668 SDValue LHS = N->getOperand(0);
3669 SDValue RHS = N->getOperand(1);
3670 SDLoc DL(N);
3671 unsigned BaseOp = 0;
3672 unsigned CCValid = 0;
3673 unsigned CCMask = 0;
3674
3675 switch (Op.getOpcode()) {
3676 default: llvm_unreachable("Unknown instruction!");
3677 case ISD::SADDO:
3678 BaseOp = SystemZISD::SADDO;
3679 CCValid = SystemZ::CCMASK_ARITH;
3680 CCMask = SystemZ::CCMASK_ARITH_OVERFLOW;
3681 break;
3682 case ISD::SSUBO:
3683 BaseOp = SystemZISD::SSUBO;
3684 CCValid = SystemZ::CCMASK_ARITH;
3685 CCMask = SystemZ::CCMASK_ARITH_OVERFLOW;
3686 break;
3687 case ISD::UADDO:
3688 BaseOp = SystemZISD::UADDO;
3689 CCValid = SystemZ::CCMASK_LOGICAL;
3690 CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
3691 break;
3692 case ISD::USUBO:
3693 BaseOp = SystemZISD::USUBO;
3694 CCValid = SystemZ::CCMASK_LOGICAL;
3695 CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
3696 break;
3697 }
3698
3699 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
3700 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
3701
3702 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
3703 if (N->getValueType(1) == MVT::i1)
3704 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3705
3706 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3707 }
3708
isAddCarryChain(SDValue Carry)3709 static bool isAddCarryChain(SDValue Carry) {
3710 while (Carry.getOpcode() == ISD::ADDCARRY)
3711 Carry = Carry.getOperand(2);
3712 return Carry.getOpcode() == ISD::UADDO;
3713 }
3714
isSubBorrowChain(SDValue Carry)3715 static bool isSubBorrowChain(SDValue Carry) {
3716 while (Carry.getOpcode() == ISD::SUBCARRY)
3717 Carry = Carry.getOperand(2);
3718 return Carry.getOpcode() == ISD::USUBO;
3719 }
3720
3721 // Lower ADDCARRY/SUBCARRY nodes.
lowerADDSUBCARRY(SDValue Op,SelectionDAG & DAG) const3722 SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
3723 SelectionDAG &DAG) const {
3724
3725 SDNode *N = Op.getNode();
3726 MVT VT = N->getSimpleValueType(0);
3727
3728 // Let legalize expand this if it isn't a legal type yet.
3729 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3730 return SDValue();
3731
3732 SDValue LHS = N->getOperand(0);
3733 SDValue RHS = N->getOperand(1);
3734 SDValue Carry = Op.getOperand(2);
3735 SDLoc DL(N);
3736 unsigned BaseOp = 0;
3737 unsigned CCValid = 0;
3738 unsigned CCMask = 0;
3739
3740 switch (Op.getOpcode()) {
3741 default: llvm_unreachable("Unknown instruction!");
3742 case ISD::ADDCARRY:
3743 if (!isAddCarryChain(Carry))
3744 return SDValue();
3745
3746 BaseOp = SystemZISD::ADDCARRY;
3747 CCValid = SystemZ::CCMASK_LOGICAL;
3748 CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
3749 break;
3750 case ISD::SUBCARRY:
3751 if (!isSubBorrowChain(Carry))
3752 return SDValue();
3753
3754 BaseOp = SystemZISD::SUBCARRY;
3755 CCValid = SystemZ::CCMASK_LOGICAL;
3756 CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
3757 break;
3758 }
3759
3760 // Set the condition code from the carry flag.
3761 Carry = DAG.getNode(SystemZISD::GET_CCMASK, DL, MVT::i32, Carry,
3762 DAG.getConstant(CCValid, DL, MVT::i32),
3763 DAG.getConstant(CCMask, DL, MVT::i32));
3764
3765 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3766 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry);
3767
3768 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
3769 if (N->getValueType(1) == MVT::i1)
3770 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3771
3772 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3773 }
3774
lowerCTPOP(SDValue Op,SelectionDAG & DAG) const3775 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
3776 SelectionDAG &DAG) const {
3777 EVT VT = Op.getValueType();
3778 SDLoc DL(Op);
3779 Op = Op.getOperand(0);
3780
3781 // Handle vector types via VPOPCT.
3782 if (VT.isVector()) {
3783 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3784 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3785 switch (VT.getScalarSizeInBits()) {
3786 case 8:
3787 break;
3788 case 16: {
3789 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3790 SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
3791 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3792 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3793 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3794 break;
3795 }
3796 case 32: {
3797 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL,
3798 DAG.getConstant(0, DL, MVT::i32));
3799 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3800 break;
3801 }
3802 case 64: {
3803 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL,
3804 DAG.getConstant(0, DL, MVT::i32));
3805 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
3806 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3807 break;
3808 }
3809 default:
3810 llvm_unreachable("Unexpected type");
3811 }
3812 return Op;
3813 }
3814
3815 // Get the known-zero mask for the operand.
3816 KnownBits Known = DAG.computeKnownBits(Op);
3817 unsigned NumSignificantBits = Known.getMaxValue().getActiveBits();
3818 if (NumSignificantBits == 0)
3819 return DAG.getConstant(0, DL, VT);
3820
3821 // Skip known-zero high parts of the operand.
3822 int64_t OrigBitSize = VT.getSizeInBits();
3823 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
3824 BitSize = std::min(BitSize, OrigBitSize);
3825
3826 // The POPCNT instruction counts the number of bits in each byte.
3827 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
3828 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
3829 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3830
3831 // Add up per-byte counts in a binary tree. All bits of Op at
3832 // position larger than BitSize remain zero throughout.
3833 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
3834 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3835 if (BitSize != OrigBitSize)
3836 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3837 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3838 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3839 }
3840
3841 // Extract overall result from high byte.
3842 if (BitSize > 8)
3843 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3844 DAG.getConstant(BitSize - 8, DL, VT));
3845
3846 return Op;
3847 }
3848
lowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const3849 SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
3850 SelectionDAG &DAG) const {
3851 SDLoc DL(Op);
3852 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
3853 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
3854 SyncScope::ID FenceSSID = static_cast<SyncScope::ID>(
3855 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
3856
3857 // The only fence that needs an instruction is a sequentially-consistent
3858 // cross-thread fence.
3859 if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
3860 FenceSSID == SyncScope::System) {
3861 return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
3862 Op.getOperand(0)),
3863 0);
3864 }
3865
3866 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
3867 return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3868 }
3869
3870 // Op is an atomic load. Lower it into a normal volatile load.
lowerATOMIC_LOAD(SDValue Op,SelectionDAG & DAG) const3871 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3872 SelectionDAG &DAG) const {
3873 auto *Node = cast<AtomicSDNode>(Op.getNode());
3874 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3875 Node->getChain(), Node->getBasePtr(),
3876 Node->getMemoryVT(), Node->getMemOperand());
3877 }
3878
3879 // Op is an atomic store. Lower it into a normal volatile store.
lowerATOMIC_STORE(SDValue Op,SelectionDAG & DAG) const3880 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3881 SelectionDAG &DAG) const {
3882 auto *Node = cast<AtomicSDNode>(Op.getNode());
3883 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3884 Node->getBasePtr(), Node->getMemoryVT(),
3885 Node->getMemOperand());
3886 // We have to enforce sequential consistency by performing a
3887 // serialization operation after the store.
3888 if (Node->getOrdering() == AtomicOrdering::SequentiallyConsistent)
3889 Chain = SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op),
3890 MVT::Other, Chain), 0);
3891 return Chain;
3892 }
3893
3894 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3895 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
lowerATOMIC_LOAD_OP(SDValue Op,SelectionDAG & DAG,unsigned Opcode) const3896 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3897 SelectionDAG &DAG,
3898 unsigned Opcode) const {
3899 auto *Node = cast<AtomicSDNode>(Op.getNode());
3900
3901 // 32-bit operations need no code outside the main loop.
3902 EVT NarrowVT = Node->getMemoryVT();
3903 EVT WideVT = MVT::i32;
3904 if (NarrowVT == WideVT)
3905 return Op;
3906
3907 int64_t BitSize = NarrowVT.getSizeInBits();
3908 SDValue ChainIn = Node->getChain();
3909 SDValue Addr = Node->getBasePtr();
3910 SDValue Src2 = Node->getVal();
3911 MachineMemOperand *MMO = Node->getMemOperand();
3912 SDLoc DL(Node);
3913 EVT PtrVT = Addr.getValueType();
3914
3915 // Convert atomic subtracts of constants into additions.
3916 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3917 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3918 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3919 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3920 }
3921
3922 // Get the address of the containing word.
3923 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3924 DAG.getConstant(-4, DL, PtrVT));
3925
3926 // Get the number of bits that the word must be rotated left in order
3927 // to bring the field to the top bits of a GR32.
3928 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3929 DAG.getConstant(3, DL, PtrVT));
3930 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3931
3932 // Get the complementing shift amount, for rotating a field in the top
3933 // bits back to its proper position.
3934 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3935 DAG.getConstant(0, DL, WideVT), BitShift);
3936
3937 // Extend the source operand to 32 bits and prepare it for the inner loop.
3938 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3939 // operations require the source to be shifted in advance. (This shift
3940 // can be folded if the source is constant.) For AND and NAND, the lower
3941 // bits must be set, while for other opcodes they should be left clear.
3942 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3943 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3944 DAG.getConstant(32 - BitSize, DL, WideVT));
3945 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3946 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3947 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3948 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3949
3950 // Construct the ATOMIC_LOADW_* node.
3951 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3952 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3953 DAG.getConstant(BitSize, DL, WideVT) };
3954 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3955 NarrowVT, MMO);
3956
3957 // Rotate the result of the final CS so that the field is in the lower
3958 // bits of a GR32, then truncate it.
3959 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3960 DAG.getConstant(BitSize, DL, WideVT));
3961 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3962
3963 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3964 return DAG.getMergeValues(RetOps, DL);
3965 }
3966
3967 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3968 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3969 // operations into additions.
lowerATOMIC_LOAD_SUB(SDValue Op,SelectionDAG & DAG) const3970 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3971 SelectionDAG &DAG) const {
3972 auto *Node = cast<AtomicSDNode>(Op.getNode());
3973 EVT MemVT = Node->getMemoryVT();
3974 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3975 // A full-width operation.
3976 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3977 SDValue Src2 = Node->getVal();
3978 SDValue NegSrc2;
3979 SDLoc DL(Src2);
3980
3981 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3982 // Use an addition if the operand is constant and either LAA(G) is
3983 // available or the negative value is in the range of A(G)FHI.
3984 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3985 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3986 NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3987 } else if (Subtarget.hasInterlockedAccess1())
3988 // Use LAA(G) if available.
3989 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3990 Src2);
3991
3992 if (NegSrc2.getNode())
3993 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3994 Node->getChain(), Node->getBasePtr(), NegSrc2,
3995 Node->getMemOperand());
3996
3997 // Use the node as-is.
3998 return Op;
3999 }
4000
4001 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
4002 }
4003
4004 // Lower 8/16/32/64-bit ATOMIC_CMP_SWAP_WITH_SUCCESS node.
lowerATOMIC_CMP_SWAP(SDValue Op,SelectionDAG & DAG) const4005 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
4006 SelectionDAG &DAG) const {
4007 auto *Node = cast<AtomicSDNode>(Op.getNode());
4008 SDValue ChainIn = Node->getOperand(0);
4009 SDValue Addr = Node->getOperand(1);
4010 SDValue CmpVal = Node->getOperand(2);
4011 SDValue SwapVal = Node->getOperand(3);
4012 MachineMemOperand *MMO = Node->getMemOperand();
4013 SDLoc DL(Node);
4014
4015 // We have native support for 32-bit and 64-bit compare and swap, but we
4016 // still need to expand extracting the "success" result from the CC.
4017 EVT NarrowVT = Node->getMemoryVT();
4018 EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32;
4019 if (NarrowVT == WideVT) {
4020 SDVTList Tys = DAG.getVTList(WideVT, MVT::i32, MVT::Other);
4021 SDValue Ops[] = { ChainIn, Addr, CmpVal, SwapVal };
4022 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAP,
4023 DL, Tys, Ops, NarrowVT, MMO);
4024 SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(1),
4025 SystemZ::CCMASK_CS, SystemZ::CCMASK_CS_EQ);
4026
4027 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
4028 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
4029 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(2));
4030 return SDValue();
4031 }
4032
4033 // Convert 8-bit and 16-bit compare and swap to a loop, implemented
4034 // via a fullword ATOMIC_CMP_SWAPW operation.
4035 int64_t BitSize = NarrowVT.getSizeInBits();
4036 EVT PtrVT = Addr.getValueType();
4037
4038 // Get the address of the containing word.
4039 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
4040 DAG.getConstant(-4, DL, PtrVT));
4041
4042 // Get the number of bits that the word must be rotated left in order
4043 // to bring the field to the top bits of a GR32.
4044 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
4045 DAG.getConstant(3, DL, PtrVT));
4046 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
4047
4048 // Get the complementing shift amount, for rotating a field in the top
4049 // bits back to its proper position.
4050 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
4051 DAG.getConstant(0, DL, WideVT), BitShift);
4052
4053 // Construct the ATOMIC_CMP_SWAPW node.
4054 SDVTList VTList = DAG.getVTList(WideVT, MVT::i32, MVT::Other);
4055 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
4056 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
4057 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
4058 VTList, Ops, NarrowVT, MMO);
4059 SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(1),
4060 SystemZ::CCMASK_ICMP, SystemZ::CCMASK_CMP_EQ);
4061
4062 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
4063 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
4064 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(2));
4065 return SDValue();
4066 }
4067
4068 MachineMemOperand::Flags
getTargetMMOFlags(const Instruction & I) const4069 SystemZTargetLowering::getTargetMMOFlags(const Instruction &I) const {
4070 // Because of how we convert atomic_load and atomic_store to normal loads and
4071 // stores in the DAG, we need to ensure that the MMOs are marked volatile
4072 // since DAGCombine hasn't been updated to account for atomic, but non
4073 // volatile loads. (See D57601)
4074 if (auto *SI = dyn_cast<StoreInst>(&I))
4075 if (SI->isAtomic())
4076 return MachineMemOperand::MOVolatile;
4077 if (auto *LI = dyn_cast<LoadInst>(&I))
4078 if (LI->isAtomic())
4079 return MachineMemOperand::MOVolatile;
4080 if (auto *AI = dyn_cast<AtomicRMWInst>(&I))
4081 if (AI->isAtomic())
4082 return MachineMemOperand::MOVolatile;
4083 if (auto *AI = dyn_cast<AtomicCmpXchgInst>(&I))
4084 if (AI->isAtomic())
4085 return MachineMemOperand::MOVolatile;
4086 return MachineMemOperand::MONone;
4087 }
4088
lowerSTACKSAVE(SDValue Op,SelectionDAG & DAG) const4089 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
4090 SelectionDAG &DAG) const {
4091 MachineFunction &MF = DAG.getMachineFunction();
4092 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
4093 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
4094 report_fatal_error("Variable-sized stack allocations are not supported "
4095 "in GHC calling convention");
4096 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
4097 SystemZ::R15D, Op.getValueType());
4098 }
4099
lowerSTACKRESTORE(SDValue Op,SelectionDAG & DAG) const4100 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
4101 SelectionDAG &DAG) const {
4102 MachineFunction &MF = DAG.getMachineFunction();
4103 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
4104 bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
4105
4106 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
4107 report_fatal_error("Variable-sized stack allocations are not supported "
4108 "in GHC calling convention");
4109
4110 SDValue Chain = Op.getOperand(0);
4111 SDValue NewSP = Op.getOperand(1);
4112 SDValue Backchain;
4113 SDLoc DL(Op);
4114
4115 if (StoreBackchain) {
4116 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
4117 Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP, DAG),
4118 MachinePointerInfo());
4119 }
4120
4121 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);
4122
4123 if (StoreBackchain)
4124 Chain = DAG.getStore(Chain, DL, Backchain, getBackchainAddress(NewSP, DAG),
4125 MachinePointerInfo());
4126
4127 return Chain;
4128 }
4129
lowerPREFETCH(SDValue Op,SelectionDAG & DAG) const4130 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
4131 SelectionDAG &DAG) const {
4132 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4133 if (!IsData)
4134 // Just preserve the chain.
4135 return Op.getOperand(0);
4136
4137 SDLoc DL(Op);
4138 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
4139 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
4140 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
4141 SDValue Ops[] = {Op.getOperand(0), DAG.getTargetConstant(Code, DL, MVT::i32),
4142 Op.getOperand(1)};
4143 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
4144 Node->getVTList(), Ops,
4145 Node->getMemoryVT(), Node->getMemOperand());
4146 }
4147
4148 // Convert condition code in CCReg to an i32 value.
getCCResult(SelectionDAG & DAG,SDValue CCReg)4149 static SDValue getCCResult(SelectionDAG &DAG, SDValue CCReg) {
4150 SDLoc DL(CCReg);
4151 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
4152 return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
4153 DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
4154 }
4155
4156 SDValue
lowerINTRINSIC_W_CHAIN(SDValue Op,SelectionDAG & DAG) const4157 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
4158 SelectionDAG &DAG) const {
4159 unsigned Opcode, CCValid;
4160 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
4161 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
4162 SDNode *Node = emitIntrinsicWithCCAndChain(DAG, Op, Opcode);
4163 SDValue CC = getCCResult(DAG, SDValue(Node, 0));
4164 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
4165 return SDValue();
4166 }
4167
4168 return SDValue();
4169 }
4170
4171 SDValue
lowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const4172 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
4173 SelectionDAG &DAG) const {
4174 unsigned Opcode, CCValid;
4175 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
4176 SDNode *Node = emitIntrinsicWithCC(DAG, Op, Opcode);
4177 if (Op->getNumValues() == 1)
4178 return getCCResult(DAG, SDValue(Node, 0));
4179 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
4180 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
4181 SDValue(Node, 0), getCCResult(DAG, SDValue(Node, 1)));
4182 }
4183
4184 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4185 switch (Id) {
4186 case Intrinsic::thread_pointer:
4187 return lowerThreadPointer(SDLoc(Op), DAG);
4188
4189 case Intrinsic::s390_vpdi:
4190 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
4191 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4192
4193 case Intrinsic::s390_vperm:
4194 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
4195 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4196
4197 case Intrinsic::s390_vuphb:
4198 case Intrinsic::s390_vuphh:
4199 case Intrinsic::s390_vuphf:
4200 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
4201 Op.getOperand(1));
4202
4203 case Intrinsic::s390_vuplhb:
4204 case Intrinsic::s390_vuplhh:
4205 case Intrinsic::s390_vuplhf:
4206 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
4207 Op.getOperand(1));
4208
4209 case Intrinsic::s390_vuplb:
4210 case Intrinsic::s390_vuplhw:
4211 case Intrinsic::s390_vuplf:
4212 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
4213 Op.getOperand(1));
4214
4215 case Intrinsic::s390_vupllb:
4216 case Intrinsic::s390_vupllh:
4217 case Intrinsic::s390_vupllf:
4218 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
4219 Op.getOperand(1));
4220
4221 case Intrinsic::s390_vsumb:
4222 case Intrinsic::s390_vsumh:
4223 case Intrinsic::s390_vsumgh:
4224 case Intrinsic::s390_vsumgf:
4225 case Intrinsic::s390_vsumqf:
4226 case Intrinsic::s390_vsumqg:
4227 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
4228 Op.getOperand(1), Op.getOperand(2));
4229 }
4230
4231 return SDValue();
4232 }
4233
4234 namespace {
4235 // Says that SystemZISD operation Opcode can be used to perform the equivalent
4236 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
4237 // Operand is the constant third operand, otherwise it is the number of
4238 // bytes in each element of the result.
4239 struct Permute {
4240 unsigned Opcode;
4241 unsigned Operand;
4242 unsigned char Bytes[SystemZ::VectorBytes];
4243 };
4244 }
4245
4246 static const Permute PermuteForms[] = {
4247 // VMRHG
4248 { SystemZISD::MERGE_HIGH, 8,
4249 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
4250 // VMRHF
4251 { SystemZISD::MERGE_HIGH, 4,
4252 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
4253 // VMRHH
4254 { SystemZISD::MERGE_HIGH, 2,
4255 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
4256 // VMRHB
4257 { SystemZISD::MERGE_HIGH, 1,
4258 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
4259 // VMRLG
4260 { SystemZISD::MERGE_LOW, 8,
4261 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
4262 // VMRLF
4263 { SystemZISD::MERGE_LOW, 4,
4264 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
4265 // VMRLH
4266 { SystemZISD::MERGE_LOW, 2,
4267 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
4268 // VMRLB
4269 { SystemZISD::MERGE_LOW, 1,
4270 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
4271 // VPKG
4272 { SystemZISD::PACK, 4,
4273 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
4274 // VPKF
4275 { SystemZISD::PACK, 2,
4276 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
4277 // VPKH
4278 { SystemZISD::PACK, 1,
4279 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
4280 // VPDI V1, V2, 4 (low half of V1, high half of V2)
4281 { SystemZISD::PERMUTE_DWORDS, 4,
4282 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
4283 // VPDI V1, V2, 1 (high half of V1, low half of V2)
4284 { SystemZISD::PERMUTE_DWORDS, 1,
4285 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
4286 };
4287
4288 // Called after matching a vector shuffle against a particular pattern.
4289 // Both the original shuffle and the pattern have two vector operands.
4290 // OpNos[0] is the operand of the original shuffle that should be used for
4291 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
4292 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
4293 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
4294 // for operands 0 and 1 of the pattern.
chooseShuffleOpNos(int * OpNos,unsigned & OpNo0,unsigned & OpNo1)4295 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
4296 if (OpNos[0] < 0) {
4297 if (OpNos[1] < 0)
4298 return false;
4299 OpNo0 = OpNo1 = OpNos[1];
4300 } else if (OpNos[1] < 0) {
4301 OpNo0 = OpNo1 = OpNos[0];
4302 } else {
4303 OpNo0 = OpNos[0];
4304 OpNo1 = OpNos[1];
4305 }
4306 return true;
4307 }
4308
4309 // Bytes is a VPERM-like permute vector, except that -1 is used for
4310 // undefined bytes. Return true if the VPERM can be implemented using P.
4311 // When returning true set OpNo0 to the VPERM operand that should be
4312 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
4313 //
4314 // For example, if swapping the VPERM operands allows P to match, OpNo0
4315 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
4316 // operand, but rewriting it to use two duplicated operands allows it to
4317 // match P, then OpNo0 and OpNo1 will be the same.
matchPermute(const SmallVectorImpl<int> & Bytes,const Permute & P,unsigned & OpNo0,unsigned & OpNo1)4318 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
4319 unsigned &OpNo0, unsigned &OpNo1) {
4320 int OpNos[] = { -1, -1 };
4321 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
4322 int Elt = Bytes[I];
4323 if (Elt >= 0) {
4324 // Make sure that the two permute vectors use the same suboperand
4325 // byte number. Only the operand numbers (the high bits) are
4326 // allowed to differ.
4327 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
4328 return false;
4329 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
4330 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
4331 // Make sure that the operand mappings are consistent with previous
4332 // elements.
4333 if (OpNos[ModelOpNo] == 1 - RealOpNo)
4334 return false;
4335 OpNos[ModelOpNo] = RealOpNo;
4336 }
4337 }
4338 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
4339 }
4340
4341 // As above, but search for a matching permute.
matchPermute(const SmallVectorImpl<int> & Bytes,unsigned & OpNo0,unsigned & OpNo1)4342 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
4343 unsigned &OpNo0, unsigned &OpNo1) {
4344 for (auto &P : PermuteForms)
4345 if (matchPermute(Bytes, P, OpNo0, OpNo1))
4346 return &P;
4347 return nullptr;
4348 }
4349
4350 // Bytes is a VPERM-like permute vector, except that -1 is used for
4351 // undefined bytes. This permute is an operand of an outer permute.
4352 // See whether redistributing the -1 bytes gives a shuffle that can be
4353 // implemented using P. If so, set Transform to a VPERM-like permute vector
4354 // that, when applied to the result of P, gives the original permute in Bytes.
matchDoublePermute(const SmallVectorImpl<int> & Bytes,const Permute & P,SmallVectorImpl<int> & Transform)4355 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
4356 const Permute &P,
4357 SmallVectorImpl<int> &Transform) {
4358 unsigned To = 0;
4359 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
4360 int Elt = Bytes[From];
4361 if (Elt < 0)
4362 // Byte number From of the result is undefined.
4363 Transform[From] = -1;
4364 else {
4365 while (P.Bytes[To] != Elt) {
4366 To += 1;
4367 if (To == SystemZ::VectorBytes)
4368 return false;
4369 }
4370 Transform[From] = To;
4371 }
4372 }
4373 return true;
4374 }
4375
4376 // As above, but search for a matching permute.
matchDoublePermute(const SmallVectorImpl<int> & Bytes,SmallVectorImpl<int> & Transform)4377 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
4378 SmallVectorImpl<int> &Transform) {
4379 for (auto &P : PermuteForms)
4380 if (matchDoublePermute(Bytes, P, Transform))
4381 return &P;
4382 return nullptr;
4383 }
4384
4385 // Convert the mask of the given shuffle op into a byte-level mask,
4386 // as if it had type vNi8.
getVPermMask(SDValue ShuffleOp,SmallVectorImpl<int> & Bytes)4387 static bool getVPermMask(SDValue ShuffleOp,
4388 SmallVectorImpl<int> &Bytes) {
4389 EVT VT = ShuffleOp.getValueType();
4390 unsigned NumElements = VT.getVectorNumElements();
4391 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
4392
4393 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(ShuffleOp)) {
4394 Bytes.resize(NumElements * BytesPerElement, -1);
4395 for (unsigned I = 0; I < NumElements; ++I) {
4396 int Index = VSN->getMaskElt(I);
4397 if (Index >= 0)
4398 for (unsigned J = 0; J < BytesPerElement; ++J)
4399 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
4400 }
4401 return true;
4402 }
4403 if (SystemZISD::SPLAT == ShuffleOp.getOpcode() &&
4404 isa<ConstantSDNode>(ShuffleOp.getOperand(1))) {
4405 unsigned Index = ShuffleOp.getConstantOperandVal(1);
4406 Bytes.resize(NumElements * BytesPerElement, -1);
4407 for (unsigned I = 0; I < NumElements; ++I)
4408 for (unsigned J = 0; J < BytesPerElement; ++J)
4409 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
4410 return true;
4411 }
4412 return false;
4413 }
4414
4415 // Bytes is a VPERM-like permute vector, except that -1 is used for
4416 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
4417 // the result come from a contiguous sequence of bytes from one input.
4418 // Set Base to the selector for the first byte if so.
getShuffleInput(const SmallVectorImpl<int> & Bytes,unsigned Start,unsigned BytesPerElement,int & Base)4419 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
4420 unsigned BytesPerElement, int &Base) {
4421 Base = -1;
4422 for (unsigned I = 0; I < BytesPerElement; ++I) {
4423 if (Bytes[Start + I] >= 0) {
4424 unsigned Elem = Bytes[Start + I];
4425 if (Base < 0) {
4426 Base = Elem - I;
4427 // Make sure the bytes would come from one input operand.
4428 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
4429 return false;
4430 } else if (unsigned(Base) != Elem - I)
4431 return false;
4432 }
4433 }
4434 return true;
4435 }
4436
4437 // Bytes is a VPERM-like permute vector, except that -1 is used for
4438 // undefined bytes. Return true if it can be performed using VSLDB.
4439 // When returning true, set StartIndex to the shift amount and OpNo0
4440 // and OpNo1 to the VPERM operands that should be used as the first
4441 // and second shift operand respectively.
isShlDoublePermute(const SmallVectorImpl<int> & Bytes,unsigned & StartIndex,unsigned & OpNo0,unsigned & OpNo1)4442 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
4443 unsigned &StartIndex, unsigned &OpNo0,
4444 unsigned &OpNo1) {
4445 int OpNos[] = { -1, -1 };
4446 int Shift = -1;
4447 for (unsigned I = 0; I < 16; ++I) {
4448 int Index = Bytes[I];
4449 if (Index >= 0) {
4450 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
4451 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
4452 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
4453 if (Shift < 0)
4454 Shift = ExpectedShift;
4455 else if (Shift != ExpectedShift)
4456 return false;
4457 // Make sure that the operand mappings are consistent with previous
4458 // elements.
4459 if (OpNos[ModelOpNo] == 1 - RealOpNo)
4460 return false;
4461 OpNos[ModelOpNo] = RealOpNo;
4462 }
4463 }
4464 StartIndex = Shift;
4465 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
4466 }
4467
4468 // Create a node that performs P on operands Op0 and Op1, casting the
4469 // operands to the appropriate type. The type of the result is determined by P.
getPermuteNode(SelectionDAG & DAG,const SDLoc & DL,const Permute & P,SDValue Op0,SDValue Op1)4470 static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
4471 const Permute &P, SDValue Op0, SDValue Op1) {
4472 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
4473 // elements of a PACK are twice as wide as the outputs.
4474 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
4475 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
4476 P.Operand);
4477 // Cast both operands to the appropriate type.
4478 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
4479 SystemZ::VectorBytes / InBytes);
4480 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
4481 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
4482 SDValue Op;
4483 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
4484 SDValue Op2 = DAG.getTargetConstant(P.Operand, DL, MVT::i32);
4485 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
4486 } else if (P.Opcode == SystemZISD::PACK) {
4487 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
4488 SystemZ::VectorBytes / P.Operand);
4489 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
4490 } else {
4491 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
4492 }
4493 return Op;
4494 }
4495
isZeroVector(SDValue N)4496 static bool isZeroVector(SDValue N) {
4497 if (N->getOpcode() == ISD::BITCAST)
4498 N = N->getOperand(0);
4499 if (N->getOpcode() == ISD::SPLAT_VECTOR)
4500 if (auto *Op = dyn_cast<ConstantSDNode>(N->getOperand(0)))
4501 return Op->getZExtValue() == 0;
4502 return ISD::isBuildVectorAllZeros(N.getNode());
4503 }
4504
4505 // Return the index of the zero/undef vector, or UINT32_MAX if not found.
findZeroVectorIdx(SDValue * Ops,unsigned Num)4506 static uint32_t findZeroVectorIdx(SDValue *Ops, unsigned Num) {
4507 for (unsigned I = 0; I < Num ; I++)
4508 if (isZeroVector(Ops[I]))
4509 return I;
4510 return UINT32_MAX;
4511 }
4512
4513 // Bytes is a VPERM-like permute vector, except that -1 is used for
4514 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
4515 // VSLDB or VPERM.
getGeneralPermuteNode(SelectionDAG & DAG,const SDLoc & DL,SDValue * Ops,const SmallVectorImpl<int> & Bytes)4516 static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
4517 SDValue *Ops,
4518 const SmallVectorImpl<int> &Bytes) {
4519 for (unsigned I = 0; I < 2; ++I)
4520 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
4521
4522 // First see whether VSLDB can be used.
4523 unsigned StartIndex, OpNo0, OpNo1;
4524 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
4525 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
4526 Ops[OpNo1],
4527 DAG.getTargetConstant(StartIndex, DL, MVT::i32));
4528
4529 // Fall back on VPERM. Construct an SDNode for the permute vector. Try to
4530 // eliminate a zero vector by reusing any zero index in the permute vector.
4531 unsigned ZeroVecIdx = findZeroVectorIdx(&Ops[0], 2);
4532 if (ZeroVecIdx != UINT32_MAX) {
4533 bool MaskFirst = true;
4534 int ZeroIdx = -1;
4535 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
4536 unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
4537 unsigned Byte = unsigned(Bytes[I]) % SystemZ::VectorBytes;
4538 if (OpNo == ZeroVecIdx && I == 0) {
4539 // If the first byte is zero, use mask as first operand.
4540 ZeroIdx = 0;
4541 break;
4542 }
4543 if (OpNo != ZeroVecIdx && Byte == 0) {
4544 // If mask contains a zero, use it by placing that vector first.
4545 ZeroIdx = I + SystemZ::VectorBytes;
4546 MaskFirst = false;
4547 break;
4548 }
4549 }
4550 if (ZeroIdx != -1) {
4551 SDValue IndexNodes[SystemZ::VectorBytes];
4552 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
4553 if (Bytes[I] >= 0) {
4554 unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
4555 unsigned Byte = unsigned(Bytes[I]) % SystemZ::VectorBytes;
4556 if (OpNo == ZeroVecIdx)
4557 IndexNodes[I] = DAG.getConstant(ZeroIdx, DL, MVT::i32);
4558 else {
4559 unsigned BIdx = MaskFirst ? Byte + SystemZ::VectorBytes : Byte;
4560 IndexNodes[I] = DAG.getConstant(BIdx, DL, MVT::i32);
4561 }
4562 } else
4563 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
4564 }
4565 SDValue Mask = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
4566 SDValue Src = ZeroVecIdx == 0 ? Ops[1] : Ops[0];
4567 if (MaskFirst)
4568 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Mask, Src,
4569 Mask);
4570 else
4571 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Src, Mask,
4572 Mask);
4573 }
4574 }
4575
4576 SDValue IndexNodes[SystemZ::VectorBytes];
4577 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
4578 if (Bytes[I] >= 0)
4579 IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
4580 else
4581 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
4582 SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
4583 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0],
4584 (!Ops[1].isUndef() ? Ops[1] : Ops[0]), Op2);
4585 }
4586
4587 namespace {
4588 // Describes a general N-operand vector shuffle.
4589 struct GeneralShuffle {
GeneralShuffle__anonc30c8ddf0411::GeneralShuffle4590 GeneralShuffle(EVT vt) : VT(vt), UnpackFromEltSize(UINT_MAX) {}
4591 void addUndef();
4592 bool add(SDValue, unsigned);
4593 SDValue getNode(SelectionDAG &, const SDLoc &);
4594 void tryPrepareForUnpack();
unpackWasPrepared__anonc30c8ddf0411::GeneralShuffle4595 bool unpackWasPrepared() { return UnpackFromEltSize <= 4; }
4596 SDValue insertUnpackIfPrepared(SelectionDAG &DAG, const SDLoc &DL, SDValue Op);
4597
4598 // The operands of the shuffle.
4599 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
4600
4601 // Index I is -1 if byte I of the result is undefined. Otherwise the
4602 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
4603 // Bytes[I] / SystemZ::VectorBytes.
4604 SmallVector<int, SystemZ::VectorBytes> Bytes;
4605
4606 // The type of the shuffle result.
4607 EVT VT;
4608
4609 // Holds a value of 1, 2 or 4 if a final unpack has been prepared for.
4610 unsigned UnpackFromEltSize;
4611 };
4612 }
4613
4614 // Add an extra undefined element to the shuffle.
addUndef()4615 void GeneralShuffle::addUndef() {
4616 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
4617 for (unsigned I = 0; I < BytesPerElement; ++I)
4618 Bytes.push_back(-1);
4619 }
4620
4621 // Add an extra element to the shuffle, taking it from element Elem of Op.
4622 // A null Op indicates a vector input whose value will be calculated later;
4623 // there is at most one such input per shuffle and it always has the same
4624 // type as the result. Aborts and returns false if the source vector elements
4625 // of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
4626 // LLVM they become implicitly extended, but this is rare and not optimized.
add(SDValue Op,unsigned Elem)4627 bool GeneralShuffle::add(SDValue Op, unsigned Elem) {
4628 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
4629
4630 // The source vector can have wider elements than the result,
4631 // either through an explicit TRUNCATE or because of type legalization.
4632 // We want the least significant part.
4633 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
4634 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
4635
4636 // Return false if the source elements are smaller than their destination
4637 // elements.
4638 if (FromBytesPerElement < BytesPerElement)
4639 return false;
4640
4641 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
4642 (FromBytesPerElement - BytesPerElement));
4643
4644 // Look through things like shuffles and bitcasts.
4645 while (Op.getNode()) {
4646 if (Op.getOpcode() == ISD::BITCAST)
4647 Op = Op.getOperand(0);
4648 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
4649 // See whether the bytes we need come from a contiguous part of one
4650 // operand.
4651 SmallVector<int, SystemZ::VectorBytes> OpBytes;
4652 if (!getVPermMask(Op, OpBytes))
4653 break;
4654 int NewByte;
4655 if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
4656 break;
4657 if (NewByte < 0) {
4658 addUndef();
4659 return true;
4660 }
4661 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
4662 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
4663 } else if (Op.isUndef()) {
4664 addUndef();
4665 return true;
4666 } else
4667 break;
4668 }
4669
4670 // Make sure that the source of the extraction is in Ops.
4671 unsigned OpNo = 0;
4672 for (; OpNo < Ops.size(); ++OpNo)
4673 if (Ops[OpNo] == Op)
4674 break;
4675 if (OpNo == Ops.size())
4676 Ops.push_back(Op);
4677
4678 // Add the element to Bytes.
4679 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
4680 for (unsigned I = 0; I < BytesPerElement; ++I)
4681 Bytes.push_back(Base + I);
4682
4683 return true;
4684 }
4685
4686 // Return SDNodes for the completed shuffle.
getNode(SelectionDAG & DAG,const SDLoc & DL)4687 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
4688 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
4689
4690 if (Ops.size() == 0)
4691 return DAG.getUNDEF(VT);
4692
4693 // Use a single unpack if possible as the last operation.
4694 tryPrepareForUnpack();
4695
4696 // Make sure that there are at least two shuffle operands.
4697 if (Ops.size() == 1)
4698 Ops.push_back(DAG.getUNDEF(MVT::v16i8));
4699
4700 // Create a tree of shuffles, deferring root node until after the loop.
4701 // Try to redistribute the undefined elements of non-root nodes so that
4702 // the non-root shuffles match something like a pack or merge, then adjust
4703 // the parent node's permute vector to compensate for the new order.
4704 // Among other things, this copes with vectors like <2 x i16> that were
4705 // padded with undefined elements during type legalization.
4706 //
4707 // In the best case this redistribution will lead to the whole tree
4708 // using packs and merges. It should rarely be a loss in other cases.
4709 unsigned Stride = 1;
4710 for (; Stride * 2 < Ops.size(); Stride *= 2) {
4711 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
4712 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
4713
4714 // Create a mask for just these two operands.
4715 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
4716 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
4717 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
4718 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
4719 if (OpNo == I)
4720 NewBytes[J] = Byte;
4721 else if (OpNo == I + Stride)
4722 NewBytes[J] = SystemZ::VectorBytes + Byte;
4723 else
4724 NewBytes[J] = -1;
4725 }
4726 // See if it would be better to reorganize NewMask to avoid using VPERM.
4727 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
4728 if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
4729 Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
4730 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
4731 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
4732 if (NewBytes[J] >= 0) {
4733 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
4734 "Invalid double permute");
4735 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
4736 } else
4737 assert(NewBytesMap[J] < 0 && "Invalid double permute");
4738 }
4739 } else {
4740 // Just use NewBytes on the operands.
4741 Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
4742 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
4743 if (NewBytes[J] >= 0)
4744 Bytes[J] = I * SystemZ::VectorBytes + J;
4745 }
4746 }
4747 }
4748
4749 // Now we just have 2 inputs. Put the second operand in Ops[1].
4750 if (Stride > 1) {
4751 Ops[1] = Ops[Stride];
4752 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
4753 if (Bytes[I] >= int(SystemZ::VectorBytes))
4754 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
4755 }
4756
4757 // Look for an instruction that can do the permute without resorting
4758 // to VPERM.
4759 unsigned OpNo0, OpNo1;
4760 SDValue Op;
4761 if (unpackWasPrepared() && Ops[1].isUndef())
4762 Op = Ops[0];
4763 else if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
4764 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
4765 else
4766 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
4767
4768 Op = insertUnpackIfPrepared(DAG, DL, Op);
4769
4770 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4771 }
4772
4773 #ifndef NDEBUG
dumpBytes(const SmallVectorImpl<int> & Bytes,std::string Msg)4774 static void dumpBytes(const SmallVectorImpl<int> &Bytes, std::string Msg) {
4775 dbgs() << Msg.c_str() << " { ";
4776 for (unsigned i = 0; i < Bytes.size(); i++)
4777 dbgs() << Bytes[i] << " ";
4778 dbgs() << "}\n";
4779 }
4780 #endif
4781
4782 // If the Bytes vector matches an unpack operation, prepare to do the unpack
4783 // after all else by removing the zero vector and the effect of the unpack on
4784 // Bytes.
tryPrepareForUnpack()4785 void GeneralShuffle::tryPrepareForUnpack() {
4786 uint32_t ZeroVecOpNo = findZeroVectorIdx(&Ops[0], Ops.size());
4787 if (ZeroVecOpNo == UINT32_MAX || Ops.size() == 1)
4788 return;
4789
4790 // Only do this if removing the zero vector reduces the depth, otherwise
4791 // the critical path will increase with the final unpack.
4792 if (Ops.size() > 2 &&
4793 Log2_32_Ceil(Ops.size()) == Log2_32_Ceil(Ops.size() - 1))
4794 return;
4795
4796 // Find an unpack that would allow removing the zero vector from Ops.
4797 UnpackFromEltSize = 1;
4798 for (; UnpackFromEltSize <= 4; UnpackFromEltSize *= 2) {
4799 bool MatchUnpack = true;
4800 SmallVector<int, SystemZ::VectorBytes> SrcBytes;
4801 for (unsigned Elt = 0; Elt < SystemZ::VectorBytes; Elt++) {
4802 unsigned ToEltSize = UnpackFromEltSize * 2;
4803 bool IsZextByte = (Elt % ToEltSize) < UnpackFromEltSize;
4804 if (!IsZextByte)
4805 SrcBytes.push_back(Bytes[Elt]);
4806 if (Bytes[Elt] != -1) {
4807 unsigned OpNo = unsigned(Bytes[Elt]) / SystemZ::VectorBytes;
4808 if (IsZextByte != (OpNo == ZeroVecOpNo)) {
4809 MatchUnpack = false;
4810 break;
4811 }
4812 }
4813 }
4814 if (MatchUnpack) {
4815 if (Ops.size() == 2) {
4816 // Don't use unpack if a single source operand needs rearrangement.
4817 for (unsigned i = 0; i < SystemZ::VectorBytes / 2; i++)
4818 if (SrcBytes[i] != -1 && SrcBytes[i] % 16 != int(i)) {
4819 UnpackFromEltSize = UINT_MAX;
4820 return;
4821 }
4822 }
4823 break;
4824 }
4825 }
4826 if (UnpackFromEltSize > 4)
4827 return;
4828
4829 LLVM_DEBUG(dbgs() << "Preparing for final unpack of element size "
4830 << UnpackFromEltSize << ". Zero vector is Op#" << ZeroVecOpNo
4831 << ".\n";
4832 dumpBytes(Bytes, "Original Bytes vector:"););
4833
4834 // Apply the unpack in reverse to the Bytes array.
4835 unsigned B = 0;
4836 for (unsigned Elt = 0; Elt < SystemZ::VectorBytes;) {
4837 Elt += UnpackFromEltSize;
4838 for (unsigned i = 0; i < UnpackFromEltSize; i++, Elt++, B++)
4839 Bytes[B] = Bytes[Elt];
4840 }
4841 while (B < SystemZ::VectorBytes)
4842 Bytes[B++] = -1;
4843
4844 // Remove the zero vector from Ops
4845 Ops.erase(&Ops[ZeroVecOpNo]);
4846 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
4847 if (Bytes[I] >= 0) {
4848 unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
4849 if (OpNo > ZeroVecOpNo)
4850 Bytes[I] -= SystemZ::VectorBytes;
4851 }
4852
4853 LLVM_DEBUG(dumpBytes(Bytes, "Resulting Bytes vector, zero vector removed:");
4854 dbgs() << "\n";);
4855 }
4856
insertUnpackIfPrepared(SelectionDAG & DAG,const SDLoc & DL,SDValue Op)4857 SDValue GeneralShuffle::insertUnpackIfPrepared(SelectionDAG &DAG,
4858 const SDLoc &DL,
4859 SDValue Op) {
4860 if (!unpackWasPrepared())
4861 return Op;
4862 unsigned InBits = UnpackFromEltSize * 8;
4863 EVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBits),
4864 SystemZ::VectorBits / InBits);
4865 SDValue PackedOp = DAG.getNode(ISD::BITCAST, DL, InVT, Op);
4866 unsigned OutBits = InBits * 2;
4867 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits),
4868 SystemZ::VectorBits / OutBits);
4869 return DAG.getNode(SystemZISD::UNPACKL_HIGH, DL, OutVT, PackedOp);
4870 }
4871
4872 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
isScalarToVector(SDValue Op)4873 static bool isScalarToVector(SDValue Op) {
4874 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
4875 if (!Op.getOperand(I).isUndef())
4876 return false;
4877 return true;
4878 }
4879
4880 // Return a vector of type VT that contains Value in the first element.
4881 // The other elements don't matter.
buildScalarToVector(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SDValue Value)4882 static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4883 SDValue Value) {
4884 // If we have a constant, replicate it to all elements and let the
4885 // BUILD_VECTOR lowering take care of it.
4886 if (Value.getOpcode() == ISD::Constant ||
4887 Value.getOpcode() == ISD::ConstantFP) {
4888 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
4889 return DAG.getBuildVector(VT, DL, Ops);
4890 }
4891 if (Value.isUndef())
4892 return DAG.getUNDEF(VT);
4893 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4894 }
4895
4896 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
4897 // element 1. Used for cases in which replication is cheap.
buildMergeScalars(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SDValue Op0,SDValue Op1)4898 static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4899 SDValue Op0, SDValue Op1) {
4900 if (Op0.isUndef()) {
4901 if (Op1.isUndef())
4902 return DAG.getUNDEF(VT);
4903 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
4904 }
4905 if (Op1.isUndef())
4906 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
4907 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
4908 buildScalarToVector(DAG, DL, VT, Op0),
4909 buildScalarToVector(DAG, DL, VT, Op1));
4910 }
4911
4912 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
4913 // vector for them.
joinDwords(SelectionDAG & DAG,const SDLoc & DL,SDValue Op0,SDValue Op1)4914 static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
4915 SDValue Op1) {
4916 if (Op0.isUndef() && Op1.isUndef())
4917 return DAG.getUNDEF(MVT::v2i64);
4918 // If one of the two inputs is undefined then replicate the other one,
4919 // in order to avoid using another register unnecessarily.
4920 if (Op0.isUndef())
4921 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4922 else if (Op1.isUndef())
4923 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4924 else {
4925 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4926 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4927 }
4928 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4929 }
4930
4931 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4932 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4933 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4934 // would benefit from this representation and return it if so.
tryBuildVectorShuffle(SelectionDAG & DAG,BuildVectorSDNode * BVN)4935 static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
4936 BuildVectorSDNode *BVN) {
4937 EVT VT = BVN->getValueType(0);
4938 unsigned NumElements = VT.getVectorNumElements();
4939
4940 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
4941 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
4942 // need a BUILD_VECTOR, add an additional placeholder operand for that
4943 // BUILD_VECTOR and store its operands in ResidueOps.
4944 GeneralShuffle GS(VT);
4945 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
4946 bool FoundOne = false;
4947 for (unsigned I = 0; I < NumElements; ++I) {
4948 SDValue Op = BVN->getOperand(I);
4949 if (Op.getOpcode() == ISD::TRUNCATE)
4950 Op = Op.getOperand(0);
4951 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4952 Op.getOperand(1).getOpcode() == ISD::Constant) {
4953 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4954 if (!GS.add(Op.getOperand(0), Elem))
4955 return SDValue();
4956 FoundOne = true;
4957 } else if (Op.isUndef()) {
4958 GS.addUndef();
4959 } else {
4960 if (!GS.add(SDValue(), ResidueOps.size()))
4961 return SDValue();
4962 ResidueOps.push_back(BVN->getOperand(I));
4963 }
4964 }
4965
4966 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
4967 if (!FoundOne)
4968 return SDValue();
4969
4970 // Create the BUILD_VECTOR for the remaining elements, if any.
4971 if (!ResidueOps.empty()) {
4972 while (ResidueOps.size() < NumElements)
4973 ResidueOps.push_back(DAG.getUNDEF(ResidueOps[0].getValueType()));
4974 for (auto &Op : GS.Ops) {
4975 if (!Op.getNode()) {
4976 Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
4977 break;
4978 }
4979 }
4980 }
4981 return GS.getNode(DAG, SDLoc(BVN));
4982 }
4983
isVectorElementLoad(SDValue Op) const4984 bool SystemZTargetLowering::isVectorElementLoad(SDValue Op) const {
4985 if (Op.getOpcode() == ISD::LOAD && cast<LoadSDNode>(Op)->isUnindexed())
4986 return true;
4987 if (Subtarget.hasVectorEnhancements2() && Op.getOpcode() == SystemZISD::LRV)
4988 return true;
4989 return false;
4990 }
4991
4992 // Combine GPR scalar values Elems into a vector of type VT.
4993 SDValue
buildVector(SelectionDAG & DAG,const SDLoc & DL,EVT VT,SmallVectorImpl<SDValue> & Elems) const4994 SystemZTargetLowering::buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4995 SmallVectorImpl<SDValue> &Elems) const {
4996 // See whether there is a single replicated value.
4997 SDValue Single;
4998 unsigned int NumElements = Elems.size();
4999 unsigned int Count = 0;
5000 for (auto Elem : Elems) {
5001 if (!Elem.isUndef()) {
5002 if (!Single.getNode())
5003 Single = Elem;
5004 else if (Elem != Single) {
5005 Single = SDValue();
5006 break;
5007 }
5008 Count += 1;
5009 }
5010 }
5011 // There are three cases here:
5012 //
5013 // - if the only defined element is a loaded one, the best sequence
5014 // is a replicating load.
5015 //
5016 // - otherwise, if the only defined element is an i64 value, we will
5017 // end up with the same VLVGP sequence regardless of whether we short-cut
5018 // for replication or fall through to the later code.
5019 //
5020 // - otherwise, if the only defined element is an i32 or smaller value,
5021 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
5022 // This is only a win if the single defined element is used more than once.
5023 // In other cases we're better off using a single VLVGx.
5024 if (Single.getNode() && (Count > 1 || isVectorElementLoad(Single)))
5025 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
5026
5027 // If all elements are loads, use VLREP/VLEs (below).
5028 bool AllLoads = true;
5029 for (auto Elem : Elems)
5030 if (!isVectorElementLoad(Elem)) {
5031 AllLoads = false;
5032 break;
5033 }
5034
5035 // The best way of building a v2i64 from two i64s is to use VLVGP.
5036 if (VT == MVT::v2i64 && !AllLoads)
5037 return joinDwords(DAG, DL, Elems[0], Elems[1]);
5038
5039 // Use a 64-bit merge high to combine two doubles.
5040 if (VT == MVT::v2f64 && !AllLoads)
5041 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
5042
5043 // Build v4f32 values directly from the FPRs:
5044 //
5045 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
5046 // V V VMRHF
5047 // <ABxx> <CDxx>
5048 // V VMRHG
5049 // <ABCD>
5050 if (VT == MVT::v4f32 && !AllLoads) {
5051 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
5052 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
5053 // Avoid unnecessary undefs by reusing the other operand.
5054 if (Op01.isUndef())
5055 Op01 = Op23;
5056 else if (Op23.isUndef())
5057 Op23 = Op01;
5058 // Merging identical replications is a no-op.
5059 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
5060 return Op01;
5061 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
5062 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
5063 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
5064 DL, MVT::v2i64, Op01, Op23);
5065 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
5066 }
5067
5068 // Collect the constant terms.
5069 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
5070 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
5071
5072 unsigned NumConstants = 0;
5073 for (unsigned I = 0; I < NumElements; ++I) {
5074 SDValue Elem = Elems[I];
5075 if (Elem.getOpcode() == ISD::Constant ||
5076 Elem.getOpcode() == ISD::ConstantFP) {
5077 NumConstants += 1;
5078 Constants[I] = Elem;
5079 Done[I] = true;
5080 }
5081 }
5082 // If there was at least one constant, fill in the other elements of
5083 // Constants with undefs to get a full vector constant and use that
5084 // as the starting point.
5085 SDValue Result;
5086 SDValue ReplicatedVal;
5087 if (NumConstants > 0) {
5088 for (unsigned I = 0; I < NumElements; ++I)
5089 if (!Constants[I].getNode())
5090 Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
5091 Result = DAG.getBuildVector(VT, DL, Constants);
5092 } else {
5093 // Otherwise try to use VLREP or VLVGP to start the sequence in order to
5094 // avoid a false dependency on any previous contents of the vector
5095 // register.
5096
5097 // Use a VLREP if at least one element is a load. Make sure to replicate
5098 // the load with the most elements having its value.
5099 std::map<const SDNode*, unsigned> UseCounts;
5100 SDNode *LoadMaxUses = nullptr;
5101 for (unsigned I = 0; I < NumElements; ++I)
5102 if (isVectorElementLoad(Elems[I])) {
5103 SDNode *Ld = Elems[I].getNode();
5104 UseCounts[Ld]++;
5105 if (LoadMaxUses == nullptr || UseCounts[LoadMaxUses] < UseCounts[Ld])
5106 LoadMaxUses = Ld;
5107 }
5108 if (LoadMaxUses != nullptr) {
5109 ReplicatedVal = SDValue(LoadMaxUses, 0);
5110 Result = DAG.getNode(SystemZISD::REPLICATE, DL, VT, ReplicatedVal);
5111 } else {
5112 // Try to use VLVGP.
5113 unsigned I1 = NumElements / 2 - 1;
5114 unsigned I2 = NumElements - 1;
5115 bool Def1 = !Elems[I1].isUndef();
5116 bool Def2 = !Elems[I2].isUndef();
5117 if (Def1 || Def2) {
5118 SDValue Elem1 = Elems[Def1 ? I1 : I2];
5119 SDValue Elem2 = Elems[Def2 ? I2 : I1];
5120 Result = DAG.getNode(ISD::BITCAST, DL, VT,
5121 joinDwords(DAG, DL, Elem1, Elem2));
5122 Done[I1] = true;
5123 Done[I2] = true;
5124 } else
5125 Result = DAG.getUNDEF(VT);
5126 }
5127 }
5128
5129 // Use VLVGx to insert the other elements.
5130 for (unsigned I = 0; I < NumElements; ++I)
5131 if (!Done[I] && !Elems[I].isUndef() && Elems[I] != ReplicatedVal)
5132 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
5133 DAG.getConstant(I, DL, MVT::i32));
5134 return Result;
5135 }
5136
lowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG) const5137 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
5138 SelectionDAG &DAG) const {
5139 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
5140 SDLoc DL(Op);
5141 EVT VT = Op.getValueType();
5142
5143 if (BVN->isConstant()) {
5144 if (SystemZVectorConstantInfo(BVN).isVectorConstantLegal(Subtarget))
5145 return Op;
5146
5147 // Fall back to loading it from memory.
5148 return SDValue();
5149 }
5150
5151 // See if we should use shuffles to construct the vector from other vectors.
5152 if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
5153 return Res;
5154
5155 // Detect SCALAR_TO_VECTOR conversions.
5156 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
5157 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
5158
5159 // Otherwise use buildVector to build the vector up from GPRs.
5160 unsigned NumElements = Op.getNumOperands();
5161 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
5162 for (unsigned I = 0; I < NumElements; ++I)
5163 Ops[I] = Op.getOperand(I);
5164 return buildVector(DAG, DL, VT, Ops);
5165 }
5166
lowerVECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG) const5167 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
5168 SelectionDAG &DAG) const {
5169 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
5170 SDLoc DL(Op);
5171 EVT VT = Op.getValueType();
5172 unsigned NumElements = VT.getVectorNumElements();
5173
5174 if (VSN->isSplat()) {
5175 SDValue Op0 = Op.getOperand(0);
5176 unsigned Index = VSN->getSplatIndex();
5177 assert(Index < VT.getVectorNumElements() &&
5178 "Splat index should be defined and in first operand");
5179 // See whether the value we're splatting is directly available as a scalar.
5180 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5181 Op0.getOpcode() == ISD::BUILD_VECTOR)
5182 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
5183 // Otherwise keep it as a vector-to-vector operation.
5184 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
5185 DAG.getTargetConstant(Index, DL, MVT::i32));
5186 }
5187
5188 GeneralShuffle GS(VT);
5189 for (unsigned I = 0; I < NumElements; ++I) {
5190 int Elt = VSN->getMaskElt(I);
5191 if (Elt < 0)
5192 GS.addUndef();
5193 else if (!GS.add(Op.getOperand(unsigned(Elt) / NumElements),
5194 unsigned(Elt) % NumElements))
5195 return SDValue();
5196 }
5197 return GS.getNode(DAG, SDLoc(VSN));
5198 }
5199
lowerSCALAR_TO_VECTOR(SDValue Op,SelectionDAG & DAG) const5200 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
5201 SelectionDAG &DAG) const {
5202 SDLoc DL(Op);
5203 // Just insert the scalar into element 0 of an undefined vector.
5204 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
5205 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
5206 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
5207 }
5208
lowerINSERT_VECTOR_ELT(SDValue Op,SelectionDAG & DAG) const5209 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
5210 SelectionDAG &DAG) const {
5211 // Handle insertions of floating-point values.
5212 SDLoc DL(Op);
5213 SDValue Op0 = Op.getOperand(0);
5214 SDValue Op1 = Op.getOperand(1);
5215 SDValue Op2 = Op.getOperand(2);
5216 EVT VT = Op.getValueType();
5217
5218 // Insertions into constant indices of a v2f64 can be done using VPDI.
5219 // However, if the inserted value is a bitcast or a constant then it's
5220 // better to use GPRs, as below.
5221 if (VT == MVT::v2f64 &&
5222 Op1.getOpcode() != ISD::BITCAST &&
5223 Op1.getOpcode() != ISD::ConstantFP &&
5224 Op2.getOpcode() == ISD::Constant) {
5225 uint64_t Index = cast<ConstantSDNode>(Op2)->getZExtValue();
5226 unsigned Mask = VT.getVectorNumElements() - 1;
5227 if (Index <= Mask)
5228 return Op;
5229 }
5230
5231 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
5232 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
5233 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
5234 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
5235 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
5236 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
5237 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
5238 }
5239
5240 SDValue
lowerEXTRACT_VECTOR_ELT(SDValue Op,SelectionDAG & DAG) const5241 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
5242 SelectionDAG &DAG) const {
5243 // Handle extractions of floating-point values.
5244 SDLoc DL(Op);
5245 SDValue Op0 = Op.getOperand(0);
5246 SDValue Op1 = Op.getOperand(1);
5247 EVT VT = Op.getValueType();
5248 EVT VecVT = Op0.getValueType();
5249
5250 // Extractions of constant indices can be done directly.
5251 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
5252 uint64_t Index = CIndexN->getZExtValue();
5253 unsigned Mask = VecVT.getVectorNumElements() - 1;
5254 if (Index <= Mask)
5255 return Op;
5256 }
5257
5258 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
5259 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
5260 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
5261 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
5262 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
5263 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
5264 }
5265
5266 SDValue SystemZTargetLowering::
lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,SelectionDAG & DAG) const5267 lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
5268 SDValue PackedOp = Op.getOperand(0);
5269 EVT OutVT = Op.getValueType();
5270 EVT InVT = PackedOp.getValueType();
5271 unsigned ToBits = OutVT.getScalarSizeInBits();
5272 unsigned FromBits = InVT.getScalarSizeInBits();
5273 do {
5274 FromBits *= 2;
5275 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
5276 SystemZ::VectorBits / FromBits);
5277 PackedOp =
5278 DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(PackedOp), OutVT, PackedOp);
5279 } while (FromBits != ToBits);
5280 return PackedOp;
5281 }
5282
5283 // Lower a ZERO_EXTEND_VECTOR_INREG to a vector shuffle with a zero vector.
5284 SDValue SystemZTargetLowering::
lowerZERO_EXTEND_VECTOR_INREG(SDValue Op,SelectionDAG & DAG) const5285 lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
5286 SDValue PackedOp = Op.getOperand(0);
5287 SDLoc DL(Op);
5288 EVT OutVT = Op.getValueType();
5289 EVT InVT = PackedOp.getValueType();
5290 unsigned InNumElts = InVT.getVectorNumElements();
5291 unsigned OutNumElts = OutVT.getVectorNumElements();
5292 unsigned NumInPerOut = InNumElts / OutNumElts;
5293
5294 SDValue ZeroVec =
5295 DAG.getSplatVector(InVT, DL, DAG.getConstant(0, DL, InVT.getScalarType()));
5296
5297 SmallVector<int, 16> Mask(InNumElts);
5298 unsigned ZeroVecElt = InNumElts;
5299 for (unsigned PackedElt = 0; PackedElt < OutNumElts; PackedElt++) {
5300 unsigned MaskElt = PackedElt * NumInPerOut;
5301 unsigned End = MaskElt + NumInPerOut - 1;
5302 for (; MaskElt < End; MaskElt++)
5303 Mask[MaskElt] = ZeroVecElt++;
5304 Mask[MaskElt] = PackedElt;
5305 }
5306 SDValue Shuf = DAG.getVectorShuffle(InVT, DL, PackedOp, ZeroVec, Mask);
5307 return DAG.getNode(ISD::BITCAST, DL, OutVT, Shuf);
5308 }
5309
lowerShift(SDValue Op,SelectionDAG & DAG,unsigned ByScalar) const5310 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
5311 unsigned ByScalar) const {
5312 // Look for cases where a vector shift can use the *_BY_SCALAR form.
5313 SDValue Op0 = Op.getOperand(0);
5314 SDValue Op1 = Op.getOperand(1);
5315 SDLoc DL(Op);
5316 EVT VT = Op.getValueType();
5317 unsigned ElemBitSize = VT.getScalarSizeInBits();
5318
5319 // See whether the shift vector is a splat represented as BUILD_VECTOR.
5320 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
5321 APInt SplatBits, SplatUndef;
5322 unsigned SplatBitSize;
5323 bool HasAnyUndefs;
5324 // Check for constant splats. Use ElemBitSize as the minimum element
5325 // width and reject splats that need wider elements.
5326 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
5327 ElemBitSize, true) &&
5328 SplatBitSize == ElemBitSize) {
5329 SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
5330 DL, MVT::i32);
5331 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
5332 }
5333 // Check for variable splats.
5334 BitVector UndefElements;
5335 SDValue Splat = BVN->getSplatValue(&UndefElements);
5336 if (Splat) {
5337 // Since i32 is the smallest legal type, we either need a no-op
5338 // or a truncation.
5339 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
5340 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
5341 }
5342 }
5343
5344 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
5345 // and the shift amount is directly available in a GPR.
5346 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
5347 if (VSN->isSplat()) {
5348 SDValue VSNOp0 = VSN->getOperand(0);
5349 unsigned Index = VSN->getSplatIndex();
5350 assert(Index < VT.getVectorNumElements() &&
5351 "Splat index should be defined and in first operand");
5352 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5353 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
5354 // Since i32 is the smallest legal type, we either need a no-op
5355 // or a truncation.
5356 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
5357 VSNOp0.getOperand(Index));
5358 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
5359 }
5360 }
5361 }
5362
5363 // Otherwise just treat the current form as legal.
5364 return Op;
5365 }
5366
LowerOperation(SDValue Op,SelectionDAG & DAG) const5367 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
5368 SelectionDAG &DAG) const {
5369 switch (Op.getOpcode()) {
5370 case ISD::FRAMEADDR:
5371 return lowerFRAMEADDR(Op, DAG);
5372 case ISD::RETURNADDR:
5373 return lowerRETURNADDR(Op, DAG);
5374 case ISD::BR_CC:
5375 return lowerBR_CC(Op, DAG);
5376 case ISD::SELECT_CC:
5377 return lowerSELECT_CC(Op, DAG);
5378 case ISD::SETCC:
5379 return lowerSETCC(Op, DAG);
5380 case ISD::STRICT_FSETCC:
5381 return lowerSTRICT_FSETCC(Op, DAG, false);
5382 case ISD::STRICT_FSETCCS:
5383 return lowerSTRICT_FSETCC(Op, DAG, true);
5384 case ISD::GlobalAddress:
5385 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
5386 case ISD::GlobalTLSAddress:
5387 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
5388 case ISD::BlockAddress:
5389 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
5390 case ISD::JumpTable:
5391 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
5392 case ISD::ConstantPool:
5393 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
5394 case ISD::BITCAST:
5395 return lowerBITCAST(Op, DAG);
5396 case ISD::VASTART:
5397 return lowerVASTART(Op, DAG);
5398 case ISD::VACOPY:
5399 return lowerVACOPY(Op, DAG);
5400 case ISD::DYNAMIC_STACKALLOC:
5401 return lowerDYNAMIC_STACKALLOC(Op, DAG);
5402 case ISD::GET_DYNAMIC_AREA_OFFSET:
5403 return lowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
5404 case ISD::SMUL_LOHI:
5405 return lowerSMUL_LOHI(Op, DAG);
5406 case ISD::UMUL_LOHI:
5407 return lowerUMUL_LOHI(Op, DAG);
5408 case ISD::SDIVREM:
5409 return lowerSDIVREM(Op, DAG);
5410 case ISD::UDIVREM:
5411 return lowerUDIVREM(Op, DAG);
5412 case ISD::SADDO:
5413 case ISD::SSUBO:
5414 case ISD::UADDO:
5415 case ISD::USUBO:
5416 return lowerXALUO(Op, DAG);
5417 case ISD::ADDCARRY:
5418 case ISD::SUBCARRY:
5419 return lowerADDSUBCARRY(Op, DAG);
5420 case ISD::OR:
5421 return lowerOR(Op, DAG);
5422 case ISD::CTPOP:
5423 return lowerCTPOP(Op, DAG);
5424 case ISD::ATOMIC_FENCE:
5425 return lowerATOMIC_FENCE(Op, DAG);
5426 case ISD::ATOMIC_SWAP:
5427 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
5428 case ISD::ATOMIC_STORE:
5429 return lowerATOMIC_STORE(Op, DAG);
5430 case ISD::ATOMIC_LOAD:
5431 return lowerATOMIC_LOAD(Op, DAG);
5432 case ISD::ATOMIC_LOAD_ADD:
5433 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
5434 case ISD::ATOMIC_LOAD_SUB:
5435 return lowerATOMIC_LOAD_SUB(Op, DAG);
5436 case ISD::ATOMIC_LOAD_AND:
5437 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
5438 case ISD::ATOMIC_LOAD_OR:
5439 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
5440 case ISD::ATOMIC_LOAD_XOR:
5441 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
5442 case ISD::ATOMIC_LOAD_NAND:
5443 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
5444 case ISD::ATOMIC_LOAD_MIN:
5445 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
5446 case ISD::ATOMIC_LOAD_MAX:
5447 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
5448 case ISD::ATOMIC_LOAD_UMIN:
5449 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
5450 case ISD::ATOMIC_LOAD_UMAX:
5451 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
5452 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
5453 return lowerATOMIC_CMP_SWAP(Op, DAG);
5454 case ISD::STACKSAVE:
5455 return lowerSTACKSAVE(Op, DAG);
5456 case ISD::STACKRESTORE:
5457 return lowerSTACKRESTORE(Op, DAG);
5458 case ISD::PREFETCH:
5459 return lowerPREFETCH(Op, DAG);
5460 case ISD::INTRINSIC_W_CHAIN:
5461 return lowerINTRINSIC_W_CHAIN(Op, DAG);
5462 case ISD::INTRINSIC_WO_CHAIN:
5463 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
5464 case ISD::BUILD_VECTOR:
5465 return lowerBUILD_VECTOR(Op, DAG);
5466 case ISD::VECTOR_SHUFFLE:
5467 return lowerVECTOR_SHUFFLE(Op, DAG);
5468 case ISD::SCALAR_TO_VECTOR:
5469 return lowerSCALAR_TO_VECTOR(Op, DAG);
5470 case ISD::INSERT_VECTOR_ELT:
5471 return lowerINSERT_VECTOR_ELT(Op, DAG);
5472 case ISD::EXTRACT_VECTOR_ELT:
5473 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
5474 case ISD::SIGN_EXTEND_VECTOR_INREG:
5475 return lowerSIGN_EXTEND_VECTOR_INREG(Op, DAG);
5476 case ISD::ZERO_EXTEND_VECTOR_INREG:
5477 return lowerZERO_EXTEND_VECTOR_INREG(Op, DAG);
5478 case ISD::SHL:
5479 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
5480 case ISD::SRL:
5481 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
5482 case ISD::SRA:
5483 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
5484 default:
5485 llvm_unreachable("Unexpected node to lower");
5486 }
5487 }
5488
5489 // Lower operations with invalid operand or result types (currently used
5490 // only for 128-bit integer types).
5491
lowerI128ToGR128(SelectionDAG & DAG,SDValue In)5492 static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In) {
5493 SDLoc DL(In);
5494 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, In,
5495 DAG.getIntPtrConstant(0, DL));
5496 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, In,
5497 DAG.getIntPtrConstant(1, DL));
5498 SDNode *Pair = DAG.getMachineNode(SystemZ::PAIR128, DL,
5499 MVT::Untyped, Hi, Lo);
5500 return SDValue(Pair, 0);
5501 }
5502
lowerGR128ToI128(SelectionDAG & DAG,SDValue In)5503 static SDValue lowerGR128ToI128(SelectionDAG &DAG, SDValue In) {
5504 SDLoc DL(In);
5505 SDValue Hi = DAG.getTargetExtractSubreg(SystemZ::subreg_h64,
5506 DL, MVT::i64, In);
5507 SDValue Lo = DAG.getTargetExtractSubreg(SystemZ::subreg_l64,
5508 DL, MVT::i64, In);
5509 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, Lo, Hi);
5510 }
5511
5512 void
LowerOperationWrapper(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const5513 SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
5514 SmallVectorImpl<SDValue> &Results,
5515 SelectionDAG &DAG) const {
5516 switch (N->getOpcode()) {
5517 case ISD::ATOMIC_LOAD: {
5518 SDLoc DL(N);
5519 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::Other);
5520 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
5521 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
5522 SDValue Res = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_LOAD_128,
5523 DL, Tys, Ops, MVT::i128, MMO);
5524 Results.push_back(lowerGR128ToI128(DAG, Res));
5525 Results.push_back(Res.getValue(1));
5526 break;
5527 }
5528 case ISD::ATOMIC_STORE: {
5529 SDLoc DL(N);
5530 SDVTList Tys = DAG.getVTList(MVT::Other);
5531 SDValue Ops[] = { N->getOperand(0),
5532 lowerI128ToGR128(DAG, N->getOperand(2)),
5533 N->getOperand(1) };
5534 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
5535 SDValue Res = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_STORE_128,
5536 DL, Tys, Ops, MVT::i128, MMO);
5537 // We have to enforce sequential consistency by performing a
5538 // serialization operation after the store.
5539 if (cast<AtomicSDNode>(N)->getOrdering() ==
5540 AtomicOrdering::SequentiallyConsistent)
5541 Res = SDValue(DAG.getMachineNode(SystemZ::Serialize, DL,
5542 MVT::Other, Res), 0);
5543 Results.push_back(Res);
5544 break;
5545 }
5546 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
5547 SDLoc DL(N);
5548 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other);
5549 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
5550 lowerI128ToGR128(DAG, N->getOperand(2)),
5551 lowerI128ToGR128(DAG, N->getOperand(3)) };
5552 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
5553 SDValue Res = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAP_128,
5554 DL, Tys, Ops, MVT::i128, MMO);
5555 SDValue Success = emitSETCC(DAG, DL, Res.getValue(1),
5556 SystemZ::CCMASK_CS, SystemZ::CCMASK_CS_EQ);
5557 Success = DAG.getZExtOrTrunc(Success, DL, N->getValueType(1));
5558 Results.push_back(lowerGR128ToI128(DAG, Res));
5559 Results.push_back(Success);
5560 Results.push_back(Res.getValue(2));
5561 break;
5562 }
5563 default:
5564 llvm_unreachable("Unexpected node to lower");
5565 }
5566 }
5567
5568 void
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const5569 SystemZTargetLowering::ReplaceNodeResults(SDNode *N,
5570 SmallVectorImpl<SDValue> &Results,
5571 SelectionDAG &DAG) const {
5572 return LowerOperationWrapper(N, Results, DAG);
5573 }
5574
getTargetNodeName(unsigned Opcode) const5575 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
5576 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
5577 switch ((SystemZISD::NodeType)Opcode) {
5578 case SystemZISD::FIRST_NUMBER: break;
5579 OPCODE(RET_FLAG);
5580 OPCODE(CALL);
5581 OPCODE(SIBCALL);
5582 OPCODE(TLS_GDCALL);
5583 OPCODE(TLS_LDCALL);
5584 OPCODE(PCREL_WRAPPER);
5585 OPCODE(PCREL_OFFSET);
5586 OPCODE(ICMP);
5587 OPCODE(FCMP);
5588 OPCODE(STRICT_FCMP);
5589 OPCODE(STRICT_FCMPS);
5590 OPCODE(TM);
5591 OPCODE(BR_CCMASK);
5592 OPCODE(SELECT_CCMASK);
5593 OPCODE(ADJDYNALLOC);
5594 OPCODE(PROBED_ALLOCA);
5595 OPCODE(POPCNT);
5596 OPCODE(SMUL_LOHI);
5597 OPCODE(UMUL_LOHI);
5598 OPCODE(SDIVREM);
5599 OPCODE(UDIVREM);
5600 OPCODE(SADDO);
5601 OPCODE(SSUBO);
5602 OPCODE(UADDO);
5603 OPCODE(USUBO);
5604 OPCODE(ADDCARRY);
5605 OPCODE(SUBCARRY);
5606 OPCODE(GET_CCMASK);
5607 OPCODE(MVC);
5608 OPCODE(MVC_LOOP);
5609 OPCODE(NC);
5610 OPCODE(NC_LOOP);
5611 OPCODE(OC);
5612 OPCODE(OC_LOOP);
5613 OPCODE(XC);
5614 OPCODE(XC_LOOP);
5615 OPCODE(CLC);
5616 OPCODE(CLC_LOOP);
5617 OPCODE(STPCPY);
5618 OPCODE(STRCMP);
5619 OPCODE(SEARCH_STRING);
5620 OPCODE(IPM);
5621 OPCODE(MEMBARRIER);
5622 OPCODE(TBEGIN);
5623 OPCODE(TBEGIN_NOFLOAT);
5624 OPCODE(TEND);
5625 OPCODE(BYTE_MASK);
5626 OPCODE(ROTATE_MASK);
5627 OPCODE(REPLICATE);
5628 OPCODE(JOIN_DWORDS);
5629 OPCODE(SPLAT);
5630 OPCODE(MERGE_HIGH);
5631 OPCODE(MERGE_LOW);
5632 OPCODE(SHL_DOUBLE);
5633 OPCODE(PERMUTE_DWORDS);
5634 OPCODE(PERMUTE);
5635 OPCODE(PACK);
5636 OPCODE(PACKS_CC);
5637 OPCODE(PACKLS_CC);
5638 OPCODE(UNPACK_HIGH);
5639 OPCODE(UNPACKL_HIGH);
5640 OPCODE(UNPACK_LOW);
5641 OPCODE(UNPACKL_LOW);
5642 OPCODE(VSHL_BY_SCALAR);
5643 OPCODE(VSRL_BY_SCALAR);
5644 OPCODE(VSRA_BY_SCALAR);
5645 OPCODE(VSUM);
5646 OPCODE(VICMPE);
5647 OPCODE(VICMPH);
5648 OPCODE(VICMPHL);
5649 OPCODE(VICMPES);
5650 OPCODE(VICMPHS);
5651 OPCODE(VICMPHLS);
5652 OPCODE(VFCMPE);
5653 OPCODE(STRICT_VFCMPE);
5654 OPCODE(STRICT_VFCMPES);
5655 OPCODE(VFCMPH);
5656 OPCODE(STRICT_VFCMPH);
5657 OPCODE(STRICT_VFCMPHS);
5658 OPCODE(VFCMPHE);
5659 OPCODE(STRICT_VFCMPHE);
5660 OPCODE(STRICT_VFCMPHES);
5661 OPCODE(VFCMPES);
5662 OPCODE(VFCMPHS);
5663 OPCODE(VFCMPHES);
5664 OPCODE(VFTCI);
5665 OPCODE(VEXTEND);
5666 OPCODE(STRICT_VEXTEND);
5667 OPCODE(VROUND);
5668 OPCODE(STRICT_VROUND);
5669 OPCODE(VTM);
5670 OPCODE(VFAE_CC);
5671 OPCODE(VFAEZ_CC);
5672 OPCODE(VFEE_CC);
5673 OPCODE(VFEEZ_CC);
5674 OPCODE(VFENE_CC);
5675 OPCODE(VFENEZ_CC);
5676 OPCODE(VISTR_CC);
5677 OPCODE(VSTRC_CC);
5678 OPCODE(VSTRCZ_CC);
5679 OPCODE(VSTRS_CC);
5680 OPCODE(VSTRSZ_CC);
5681 OPCODE(TDC);
5682 OPCODE(ATOMIC_SWAPW);
5683 OPCODE(ATOMIC_LOADW_ADD);
5684 OPCODE(ATOMIC_LOADW_SUB);
5685 OPCODE(ATOMIC_LOADW_AND);
5686 OPCODE(ATOMIC_LOADW_OR);
5687 OPCODE(ATOMIC_LOADW_XOR);
5688 OPCODE(ATOMIC_LOADW_NAND);
5689 OPCODE(ATOMIC_LOADW_MIN);
5690 OPCODE(ATOMIC_LOADW_MAX);
5691 OPCODE(ATOMIC_LOADW_UMIN);
5692 OPCODE(ATOMIC_LOADW_UMAX);
5693 OPCODE(ATOMIC_CMP_SWAPW);
5694 OPCODE(ATOMIC_CMP_SWAP);
5695 OPCODE(ATOMIC_LOAD_128);
5696 OPCODE(ATOMIC_STORE_128);
5697 OPCODE(ATOMIC_CMP_SWAP_128);
5698 OPCODE(LRV);
5699 OPCODE(STRV);
5700 OPCODE(VLER);
5701 OPCODE(VSTER);
5702 OPCODE(PREFETCH);
5703 }
5704 return nullptr;
5705 #undef OPCODE
5706 }
5707
5708 // Return true if VT is a vector whose elements are a whole number of bytes
5709 // in width. Also check for presence of vector support.
canTreatAsByteVector(EVT VT) const5710 bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const {
5711 if (!Subtarget.hasVector())
5712 return false;
5713
5714 return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple();
5715 }
5716
5717 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
5718 // producing a result of type ResVT. Op is a possibly bitcast version
5719 // of the input vector and Index is the index (based on type VecVT) that
5720 // should be extracted. Return the new extraction if a simplification
5721 // was possible or if Force is true.
combineExtract(const SDLoc & DL,EVT ResVT,EVT VecVT,SDValue Op,unsigned Index,DAGCombinerInfo & DCI,bool Force) const5722 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT,
5723 EVT VecVT, SDValue Op,
5724 unsigned Index,
5725 DAGCombinerInfo &DCI,
5726 bool Force) const {
5727 SelectionDAG &DAG = DCI.DAG;
5728
5729 // The number of bytes being extracted.
5730 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
5731
5732 for (;;) {
5733 unsigned Opcode = Op.getOpcode();
5734 if (Opcode == ISD::BITCAST)
5735 // Look through bitcasts.
5736 Op = Op.getOperand(0);
5737 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) &&
5738 canTreatAsByteVector(Op.getValueType())) {
5739 // Get a VPERM-like permute mask and see whether the bytes covered
5740 // by the extracted element are a contiguous sequence from one
5741 // source operand.
5742 SmallVector<int, SystemZ::VectorBytes> Bytes;
5743 if (!getVPermMask(Op, Bytes))
5744 break;
5745 int First;
5746 if (!getShuffleInput(Bytes, Index * BytesPerElement,
5747 BytesPerElement, First))
5748 break;
5749 if (First < 0)
5750 return DAG.getUNDEF(ResVT);
5751 // Make sure the contiguous sequence starts at a multiple of the
5752 // original element size.
5753 unsigned Byte = unsigned(First) % Bytes.size();
5754 if (Byte % BytesPerElement != 0)
5755 break;
5756 // We can get the extracted value directly from an input.
5757 Index = Byte / BytesPerElement;
5758 Op = Op.getOperand(unsigned(First) / Bytes.size());
5759 Force = true;
5760 } else if (Opcode == ISD::BUILD_VECTOR &&
5761 canTreatAsByteVector(Op.getValueType())) {
5762 // We can only optimize this case if the BUILD_VECTOR elements are
5763 // at least as wide as the extracted value.
5764 EVT OpVT = Op.getValueType();
5765 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
5766 if (OpBytesPerElement < BytesPerElement)
5767 break;
5768 // Make sure that the least-significant bit of the extracted value
5769 // is the least significant bit of an input.
5770 unsigned End = (Index + 1) * BytesPerElement;
5771 if (End % OpBytesPerElement != 0)
5772 break;
5773 // We're extracting the low part of one operand of the BUILD_VECTOR.
5774 Op = Op.getOperand(End / OpBytesPerElement - 1);
5775 if (!Op.getValueType().isInteger()) {
5776 EVT VT = MVT::getIntegerVT(Op.getValueSizeInBits());
5777 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
5778 DCI.AddToWorklist(Op.getNode());
5779 }
5780 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
5781 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
5782 if (VT != ResVT) {
5783 DCI.AddToWorklist(Op.getNode());
5784 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
5785 }
5786 return Op;
5787 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
5788 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
5789 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
5790 canTreatAsByteVector(Op.getValueType()) &&
5791 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
5792 // Make sure that only the unextended bits are significant.
5793 EVT ExtVT = Op.getValueType();
5794 EVT OpVT = Op.getOperand(0).getValueType();
5795 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
5796 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
5797 unsigned Byte = Index * BytesPerElement;
5798 unsigned SubByte = Byte % ExtBytesPerElement;
5799 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
5800 if (SubByte < MinSubByte ||
5801 SubByte + BytesPerElement > ExtBytesPerElement)
5802 break;
5803 // Get the byte offset of the unextended element
5804 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
5805 // ...then add the byte offset relative to that element.
5806 Byte += SubByte - MinSubByte;
5807 if (Byte % BytesPerElement != 0)
5808 break;
5809 Op = Op.getOperand(0);
5810 Index = Byte / BytesPerElement;
5811 Force = true;
5812 } else
5813 break;
5814 }
5815 if (Force) {
5816 if (Op.getValueType() != VecVT) {
5817 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
5818 DCI.AddToWorklist(Op.getNode());
5819 }
5820 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
5821 DAG.getConstant(Index, DL, MVT::i32));
5822 }
5823 return SDValue();
5824 }
5825
5826 // Optimize vector operations in scalar value Op on the basis that Op
5827 // is truncated to TruncVT.
combineTruncateExtract(const SDLoc & DL,EVT TruncVT,SDValue Op,DAGCombinerInfo & DCI) const5828 SDValue SystemZTargetLowering::combineTruncateExtract(
5829 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const {
5830 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
5831 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
5832 // of type TruncVT.
5833 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5834 TruncVT.getSizeInBits() % 8 == 0) {
5835 SDValue Vec = Op.getOperand(0);
5836 EVT VecVT = Vec.getValueType();
5837 if (canTreatAsByteVector(VecVT)) {
5838 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
5839 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
5840 unsigned TruncBytes = TruncVT.getStoreSize();
5841 if (BytesPerElement % TruncBytes == 0) {
5842 // Calculate the value of Y' in the above description. We are
5843 // splitting the original elements into Scale equal-sized pieces
5844 // and for truncation purposes want the last (least-significant)
5845 // of these pieces for IndexN. This is easiest to do by calculating
5846 // the start index of the following element and then subtracting 1.
5847 unsigned Scale = BytesPerElement / TruncBytes;
5848 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
5849
5850 // Defer the creation of the bitcast from X to combineExtract,
5851 // which might be able to optimize the extraction.
5852 VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
5853 VecVT.getStoreSize() / TruncBytes);
5854 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
5855 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
5856 }
5857 }
5858 }
5859 }
5860 return SDValue();
5861 }
5862
combineZERO_EXTEND(SDNode * N,DAGCombinerInfo & DCI) const5863 SDValue SystemZTargetLowering::combineZERO_EXTEND(
5864 SDNode *N, DAGCombinerInfo &DCI) const {
5865 // Convert (zext (select_ccmask C1, C2)) into (select_ccmask C1', C2')
5866 SelectionDAG &DAG = DCI.DAG;
5867 SDValue N0 = N->getOperand(0);
5868 EVT VT = N->getValueType(0);
5869 if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) {
5870 auto *TrueOp = dyn_cast<ConstantSDNode>(N0.getOperand(0));
5871 auto *FalseOp = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5872 if (TrueOp && FalseOp) {
5873 SDLoc DL(N0);
5874 SDValue Ops[] = { DAG.getConstant(TrueOp->getZExtValue(), DL, VT),
5875 DAG.getConstant(FalseOp->getZExtValue(), DL, VT),
5876 N0.getOperand(2), N0.getOperand(3), N0.getOperand(4) };
5877 SDValue NewSelect = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VT, Ops);
5878 // If N0 has multiple uses, change other uses as well.
5879 if (!N0.hasOneUse()) {
5880 SDValue TruncSelect =
5881 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), NewSelect);
5882 DCI.CombineTo(N0.getNode(), TruncSelect);
5883 }
5884 return NewSelect;
5885 }
5886 }
5887 return SDValue();
5888 }
5889
combineSIGN_EXTEND_INREG(SDNode * N,DAGCombinerInfo & DCI) const5890 SDValue SystemZTargetLowering::combineSIGN_EXTEND_INREG(
5891 SDNode *N, DAGCombinerInfo &DCI) const {
5892 // Convert (sext_in_reg (setcc LHS, RHS, COND), i1)
5893 // and (sext_in_reg (any_extend (setcc LHS, RHS, COND)), i1)
5894 // into (select_cc LHS, RHS, -1, 0, COND)
5895 SelectionDAG &DAG = DCI.DAG;
5896 SDValue N0 = N->getOperand(0);
5897 EVT VT = N->getValueType(0);
5898 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5899 if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND)
5900 N0 = N0.getOperand(0);
5901 if (EVT == MVT::i1 && N0.hasOneUse() && N0.getOpcode() == ISD::SETCC) {
5902 SDLoc DL(N0);
5903 SDValue Ops[] = { N0.getOperand(0), N0.getOperand(1),
5904 DAG.getConstant(-1, DL, VT), DAG.getConstant(0, DL, VT),
5905 N0.getOperand(2) };
5906 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
5907 }
5908 return SDValue();
5909 }
5910
combineSIGN_EXTEND(SDNode * N,DAGCombinerInfo & DCI) const5911 SDValue SystemZTargetLowering::combineSIGN_EXTEND(
5912 SDNode *N, DAGCombinerInfo &DCI) const {
5913 // Convert (sext (ashr (shl X, C1), C2)) to
5914 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
5915 // cheap as narrower ones.
5916 SelectionDAG &DAG = DCI.DAG;
5917 SDValue N0 = N->getOperand(0);
5918 EVT VT = N->getValueType(0);
5919 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
5920 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5921 SDValue Inner = N0.getOperand(0);
5922 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
5923 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
5924 unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits());
5925 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
5926 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
5927 EVT ShiftVT = N0.getOperand(1).getValueType();
5928 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
5929 Inner.getOperand(0));
5930 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
5931 DAG.getConstant(NewShlAmt, SDLoc(Inner),
5932 ShiftVT));
5933 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
5934 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
5935 }
5936 }
5937 }
5938 return SDValue();
5939 }
5940
combineMERGE(SDNode * N,DAGCombinerInfo & DCI) const5941 SDValue SystemZTargetLowering::combineMERGE(
5942 SDNode *N, DAGCombinerInfo &DCI) const {
5943 SelectionDAG &DAG = DCI.DAG;
5944 unsigned Opcode = N->getOpcode();
5945 SDValue Op0 = N->getOperand(0);
5946 SDValue Op1 = N->getOperand(1);
5947 if (Op0.getOpcode() == ISD::BITCAST)
5948 Op0 = Op0.getOperand(0);
5949 if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5950 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
5951 // for v4f32.
5952 if (Op1 == N->getOperand(0))
5953 return Op1;
5954 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
5955 EVT VT = Op1.getValueType();
5956 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
5957 if (ElemBytes <= 4) {
5958 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
5959 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
5960 EVT InVT = VT.changeVectorElementTypeToInteger();
5961 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
5962 SystemZ::VectorBytes / ElemBytes / 2);
5963 if (VT != InVT) {
5964 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
5965 DCI.AddToWorklist(Op1.getNode());
5966 }
5967 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
5968 DCI.AddToWorklist(Op.getNode());
5969 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
5970 }
5971 }
5972 return SDValue();
5973 }
5974
combineLOAD(SDNode * N,DAGCombinerInfo & DCI) const5975 SDValue SystemZTargetLowering::combineLOAD(
5976 SDNode *N, DAGCombinerInfo &DCI) const {
5977 SelectionDAG &DAG = DCI.DAG;
5978 EVT LdVT = N->getValueType(0);
5979 if (LdVT.isVector() || LdVT.isInteger())
5980 return SDValue();
5981 // Transform a scalar load that is REPLICATEd as well as having other
5982 // use(s) to the form where the other use(s) use the first element of the
5983 // REPLICATE instead of the load. Otherwise instruction selection will not
5984 // produce a VLREP. Avoid extracting to a GPR, so only do this for floating
5985 // point loads.
5986
5987 SDValue Replicate;
5988 SmallVector<SDNode*, 8> OtherUses;
5989 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5990 UI != UE; ++UI) {
5991 if (UI->getOpcode() == SystemZISD::REPLICATE) {
5992 if (Replicate)
5993 return SDValue(); // Should never happen
5994 Replicate = SDValue(*UI, 0);
5995 }
5996 else if (UI.getUse().getResNo() == 0)
5997 OtherUses.push_back(*UI);
5998 }
5999 if (!Replicate || OtherUses.empty())
6000 return SDValue();
6001
6002 SDLoc DL(N);
6003 SDValue Extract0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, LdVT,
6004 Replicate, DAG.getConstant(0, DL, MVT::i32));
6005 // Update uses of the loaded Value while preserving old chains.
6006 for (SDNode *U : OtherUses) {
6007 SmallVector<SDValue, 8> Ops;
6008 for (SDValue Op : U->ops())
6009 Ops.push_back((Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op);
6010 DAG.UpdateNodeOperands(U, Ops);
6011 }
6012 return SDValue(N, 0);
6013 }
6014
canLoadStoreByteSwapped(EVT VT) const6015 bool SystemZTargetLowering::canLoadStoreByteSwapped(EVT VT) const {
6016 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)
6017 return true;
6018 if (Subtarget.hasVectorEnhancements2())
6019 if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64)
6020 return true;
6021 return false;
6022 }
6023
isVectorElementSwap(ArrayRef<int> M,EVT VT)6024 static bool isVectorElementSwap(ArrayRef<int> M, EVT VT) {
6025 if (!VT.isVector() || !VT.isSimple() ||
6026 VT.getSizeInBits() != 128 ||
6027 VT.getScalarSizeInBits() % 8 != 0)
6028 return false;
6029
6030 unsigned NumElts = VT.getVectorNumElements();
6031 for (unsigned i = 0; i < NumElts; ++i) {
6032 if (M[i] < 0) continue; // ignore UNDEF indices
6033 if ((unsigned) M[i] != NumElts - 1 - i)
6034 return false;
6035 }
6036
6037 return true;
6038 }
6039
combineSTORE(SDNode * N,DAGCombinerInfo & DCI) const6040 SDValue SystemZTargetLowering::combineSTORE(
6041 SDNode *N, DAGCombinerInfo &DCI) const {
6042 SelectionDAG &DAG = DCI.DAG;
6043 auto *SN = cast<StoreSDNode>(N);
6044 auto &Op1 = N->getOperand(1);
6045 EVT MemVT = SN->getMemoryVT();
6046 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
6047 // for the extraction to be done on a vMiN value, so that we can use VSTE.
6048 // If X has wider elements then convert it to:
6049 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
6050 if (MemVT.isInteger() && SN->isTruncatingStore()) {
6051 if (SDValue Value =
6052 combineTruncateExtract(SDLoc(N), MemVT, SN->getValue(), DCI)) {
6053 DCI.AddToWorklist(Value.getNode());
6054
6055 // Rewrite the store with the new form of stored value.
6056 return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
6057 SN->getBasePtr(), SN->getMemoryVT(),
6058 SN->getMemOperand());
6059 }
6060 }
6061 // Combine STORE (BSWAP) into STRVH/STRV/STRVG/VSTBR
6062 if (!SN->isTruncatingStore() &&
6063 Op1.getOpcode() == ISD::BSWAP &&
6064 Op1.getNode()->hasOneUse() &&
6065 canLoadStoreByteSwapped(Op1.getValueType())) {
6066
6067 SDValue BSwapOp = Op1.getOperand(0);
6068
6069 if (BSwapOp.getValueType() == MVT::i16)
6070 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), MVT::i32, BSwapOp);
6071
6072 SDValue Ops[] = {
6073 N->getOperand(0), BSwapOp, N->getOperand(2)
6074 };
6075
6076 return
6077 DAG.getMemIntrinsicNode(SystemZISD::STRV, SDLoc(N), DAG.getVTList(MVT::Other),
6078 Ops, MemVT, SN->getMemOperand());
6079 }
6080 // Combine STORE (element-swap) into VSTER
6081 if (!SN->isTruncatingStore() &&
6082 Op1.getOpcode() == ISD::VECTOR_SHUFFLE &&
6083 Op1.getNode()->hasOneUse() &&
6084 Subtarget.hasVectorEnhancements2()) {
6085 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op1.getNode());
6086 ArrayRef<int> ShuffleMask = SVN->getMask();
6087 if (isVectorElementSwap(ShuffleMask, Op1.getValueType())) {
6088 SDValue Ops[] = {
6089 N->getOperand(0), Op1.getOperand(0), N->getOperand(2)
6090 };
6091
6092 return DAG.getMemIntrinsicNode(SystemZISD::VSTER, SDLoc(N),
6093 DAG.getVTList(MVT::Other),
6094 Ops, MemVT, SN->getMemOperand());
6095 }
6096 }
6097
6098 return SDValue();
6099 }
6100
combineVECTOR_SHUFFLE(SDNode * N,DAGCombinerInfo & DCI) const6101 SDValue SystemZTargetLowering::combineVECTOR_SHUFFLE(
6102 SDNode *N, DAGCombinerInfo &DCI) const {
6103 SelectionDAG &DAG = DCI.DAG;
6104 // Combine element-swap (LOAD) into VLER
6105 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6106 N->getOperand(0).hasOneUse() &&
6107 Subtarget.hasVectorEnhancements2()) {
6108 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6109 ArrayRef<int> ShuffleMask = SVN->getMask();
6110 if (isVectorElementSwap(ShuffleMask, N->getValueType(0))) {
6111 SDValue Load = N->getOperand(0);
6112 LoadSDNode *LD = cast<LoadSDNode>(Load);
6113
6114 // Create the element-swapping load.
6115 SDValue Ops[] = {
6116 LD->getChain(), // Chain
6117 LD->getBasePtr() // Ptr
6118 };
6119 SDValue ESLoad =
6120 DAG.getMemIntrinsicNode(SystemZISD::VLER, SDLoc(N),
6121 DAG.getVTList(LD->getValueType(0), MVT::Other),
6122 Ops, LD->getMemoryVT(), LD->getMemOperand());
6123
6124 // First, combine the VECTOR_SHUFFLE away. This makes the value produced
6125 // by the load dead.
6126 DCI.CombineTo(N, ESLoad);
6127
6128 // Next, combine the load away, we give it a bogus result value but a real
6129 // chain result. The result value is dead because the shuffle is dead.
6130 DCI.CombineTo(Load.getNode(), ESLoad, ESLoad.getValue(1));
6131
6132 // Return N so it doesn't get rechecked!
6133 return SDValue(N, 0);
6134 }
6135 }
6136
6137 return SDValue();
6138 }
6139
combineEXTRACT_VECTOR_ELT(SDNode * N,DAGCombinerInfo & DCI) const6140 SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
6141 SDNode *N, DAGCombinerInfo &DCI) const {
6142 SelectionDAG &DAG = DCI.DAG;
6143
6144 if (!Subtarget.hasVector())
6145 return SDValue();
6146
6147 // Look through bitcasts that retain the number of vector elements.
6148 SDValue Op = N->getOperand(0);
6149 if (Op.getOpcode() == ISD::BITCAST &&
6150 Op.getValueType().isVector() &&
6151 Op.getOperand(0).getValueType().isVector() &&
6152 Op.getValueType().getVectorNumElements() ==
6153 Op.getOperand(0).getValueType().getVectorNumElements())
6154 Op = Op.getOperand(0);
6155
6156 // Pull BSWAP out of a vector extraction.
6157 if (Op.getOpcode() == ISD::BSWAP && Op.hasOneUse()) {
6158 EVT VecVT = Op.getValueType();
6159 EVT EltVT = VecVT.getVectorElementType();
6160 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), EltVT,
6161 Op.getOperand(0), N->getOperand(1));
6162 DCI.AddToWorklist(Op.getNode());
6163 Op = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Op);
6164 if (EltVT != N->getValueType(0)) {
6165 DCI.AddToWorklist(Op.getNode());
6166 Op = DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op);
6167 }
6168 return Op;
6169 }
6170
6171 // Try to simplify a vector extraction.
6172 if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6173 SDValue Op0 = N->getOperand(0);
6174 EVT VecVT = Op0.getValueType();
6175 return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
6176 IndexN->getZExtValue(), DCI, false);
6177 }
6178 return SDValue();
6179 }
6180
combineJOIN_DWORDS(SDNode * N,DAGCombinerInfo & DCI) const6181 SDValue SystemZTargetLowering::combineJOIN_DWORDS(
6182 SDNode *N, DAGCombinerInfo &DCI) const {
6183 SelectionDAG &DAG = DCI.DAG;
6184 // (join_dwords X, X) == (replicate X)
6185 if (N->getOperand(0) == N->getOperand(1))
6186 return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
6187 N->getOperand(0));
6188 return SDValue();
6189 }
6190
MergeInputChains(SDNode * N1,SDNode * N2)6191 static SDValue MergeInputChains(SDNode *N1, SDNode *N2) {
6192 SDValue Chain1 = N1->getOperand(0);
6193 SDValue Chain2 = N2->getOperand(0);
6194
6195 // Trivial case: both nodes take the same chain.
6196 if (Chain1 == Chain2)
6197 return Chain1;
6198
6199 // FIXME - we could handle more complex cases via TokenFactor,
6200 // assuming we can verify that this would not create a cycle.
6201 return SDValue();
6202 }
6203
combineFP_ROUND(SDNode * N,DAGCombinerInfo & DCI) const6204 SDValue SystemZTargetLowering::combineFP_ROUND(
6205 SDNode *N, DAGCombinerInfo &DCI) const {
6206
6207 if (!Subtarget.hasVector())
6208 return SDValue();
6209
6210 // (fpround (extract_vector_elt X 0))
6211 // (fpround (extract_vector_elt X 1)) ->
6212 // (extract_vector_elt (VROUND X) 0)
6213 // (extract_vector_elt (VROUND X) 2)
6214 //
6215 // This is a special case since the target doesn't really support v2f32s.
6216 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
6217 SelectionDAG &DAG = DCI.DAG;
6218 SDValue Op0 = N->getOperand(OpNo);
6219 if (N->getValueType(0) == MVT::f32 &&
6220 Op0.hasOneUse() &&
6221 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6222 Op0.getOperand(0).getValueType() == MVT::v2f64 &&
6223 Op0.getOperand(1).getOpcode() == ISD::Constant &&
6224 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
6225 SDValue Vec = Op0.getOperand(0);
6226 for (auto *U : Vec->uses()) {
6227 if (U != Op0.getNode() &&
6228 U->hasOneUse() &&
6229 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6230 U->getOperand(0) == Vec &&
6231 U->getOperand(1).getOpcode() == ISD::Constant &&
6232 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
6233 SDValue OtherRound = SDValue(*U->use_begin(), 0);
6234 if (OtherRound.getOpcode() == N->getOpcode() &&
6235 OtherRound.getOperand(OpNo) == SDValue(U, 0) &&
6236 OtherRound.getValueType() == MVT::f32) {
6237 SDValue VRound, Chain;
6238 if (N->isStrictFPOpcode()) {
6239 Chain = MergeInputChains(N, OtherRound.getNode());
6240 if (!Chain)
6241 continue;
6242 VRound = DAG.getNode(SystemZISD::STRICT_VROUND, SDLoc(N),
6243 {MVT::v4f32, MVT::Other}, {Chain, Vec});
6244 Chain = VRound.getValue(1);
6245 } else
6246 VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
6247 MVT::v4f32, Vec);
6248 DCI.AddToWorklist(VRound.getNode());
6249 SDValue Extract1 =
6250 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
6251 VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
6252 DCI.AddToWorklist(Extract1.getNode());
6253 DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
6254 if (Chain)
6255 DAG.ReplaceAllUsesOfValueWith(OtherRound.getValue(1), Chain);
6256 SDValue Extract0 =
6257 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
6258 VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
6259 if (Chain)
6260 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0),
6261 N->getVTList(), Extract0, Chain);
6262 return Extract0;
6263 }
6264 }
6265 }
6266 }
6267 return SDValue();
6268 }
6269
combineFP_EXTEND(SDNode * N,DAGCombinerInfo & DCI) const6270 SDValue SystemZTargetLowering::combineFP_EXTEND(
6271 SDNode *N, DAGCombinerInfo &DCI) const {
6272
6273 if (!Subtarget.hasVector())
6274 return SDValue();
6275
6276 // (fpextend (extract_vector_elt X 0))
6277 // (fpextend (extract_vector_elt X 2)) ->
6278 // (extract_vector_elt (VEXTEND X) 0)
6279 // (extract_vector_elt (VEXTEND X) 1)
6280 //
6281 // This is a special case since the target doesn't really support v2f32s.
6282 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
6283 SelectionDAG &DAG = DCI.DAG;
6284 SDValue Op0 = N->getOperand(OpNo);
6285 if (N->getValueType(0) == MVT::f64 &&
6286 Op0.hasOneUse() &&
6287 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6288 Op0.getOperand(0).getValueType() == MVT::v4f32 &&
6289 Op0.getOperand(1).getOpcode() == ISD::Constant &&
6290 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
6291 SDValue Vec = Op0.getOperand(0);
6292 for (auto *U : Vec->uses()) {
6293 if (U != Op0.getNode() &&
6294 U->hasOneUse() &&
6295 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6296 U->getOperand(0) == Vec &&
6297 U->getOperand(1).getOpcode() == ISD::Constant &&
6298 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 2) {
6299 SDValue OtherExtend = SDValue(*U->use_begin(), 0);
6300 if (OtherExtend.getOpcode() == N->getOpcode() &&
6301 OtherExtend.getOperand(OpNo) == SDValue(U, 0) &&
6302 OtherExtend.getValueType() == MVT::f64) {
6303 SDValue VExtend, Chain;
6304 if (N->isStrictFPOpcode()) {
6305 Chain = MergeInputChains(N, OtherExtend.getNode());
6306 if (!Chain)
6307 continue;
6308 VExtend = DAG.getNode(SystemZISD::STRICT_VEXTEND, SDLoc(N),
6309 {MVT::v2f64, MVT::Other}, {Chain, Vec});
6310 Chain = VExtend.getValue(1);
6311 } else
6312 VExtend = DAG.getNode(SystemZISD::VEXTEND, SDLoc(N),
6313 MVT::v2f64, Vec);
6314 DCI.AddToWorklist(VExtend.getNode());
6315 SDValue Extract1 =
6316 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f64,
6317 VExtend, DAG.getConstant(1, SDLoc(U), MVT::i32));
6318 DCI.AddToWorklist(Extract1.getNode());
6319 DAG.ReplaceAllUsesOfValueWith(OtherExtend, Extract1);
6320 if (Chain)
6321 DAG.ReplaceAllUsesOfValueWith(OtherExtend.getValue(1), Chain);
6322 SDValue Extract0 =
6323 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f64,
6324 VExtend, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
6325 if (Chain)
6326 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0),
6327 N->getVTList(), Extract0, Chain);
6328 return Extract0;
6329 }
6330 }
6331 }
6332 }
6333 return SDValue();
6334 }
6335
combineINT_TO_FP(SDNode * N,DAGCombinerInfo & DCI) const6336 SDValue SystemZTargetLowering::combineINT_TO_FP(
6337 SDNode *N, DAGCombinerInfo &DCI) const {
6338 if (DCI.Level != BeforeLegalizeTypes)
6339 return SDValue();
6340 unsigned Opcode = N->getOpcode();
6341 EVT OutVT = N->getValueType(0);
6342 SelectionDAG &DAG = DCI.DAG;
6343 SDValue Op = N->getOperand(0);
6344 unsigned OutScalarBits = OutVT.getScalarSizeInBits();
6345 unsigned InScalarBits = Op->getValueType(0).getScalarSizeInBits();
6346
6347 // Insert an extension before type-legalization to avoid scalarization, e.g.:
6348 // v2f64 = uint_to_fp v2i16
6349 // =>
6350 // v2f64 = uint_to_fp (v2i64 zero_extend v2i16)
6351 if (OutVT.isVector() && OutScalarBits > InScalarBits) {
6352 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(OutVT.getScalarSizeInBits()),
6353 OutVT.getVectorNumElements());
6354 unsigned ExtOpcode =
6355 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND);
6356 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op);
6357 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp);
6358 }
6359 return SDValue();
6360 }
6361
combineBSWAP(SDNode * N,DAGCombinerInfo & DCI) const6362 SDValue SystemZTargetLowering::combineBSWAP(
6363 SDNode *N, DAGCombinerInfo &DCI) const {
6364 SelectionDAG &DAG = DCI.DAG;
6365 // Combine BSWAP (LOAD) into LRVH/LRV/LRVG/VLBR
6366 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6367 N->getOperand(0).hasOneUse() &&
6368 canLoadStoreByteSwapped(N->getValueType(0))) {
6369 SDValue Load = N->getOperand(0);
6370 LoadSDNode *LD = cast<LoadSDNode>(Load);
6371
6372 // Create the byte-swapping load.
6373 SDValue Ops[] = {
6374 LD->getChain(), // Chain
6375 LD->getBasePtr() // Ptr
6376 };
6377 EVT LoadVT = N->getValueType(0);
6378 if (LoadVT == MVT::i16)
6379 LoadVT = MVT::i32;
6380 SDValue BSLoad =
6381 DAG.getMemIntrinsicNode(SystemZISD::LRV, SDLoc(N),
6382 DAG.getVTList(LoadVT, MVT::Other),
6383 Ops, LD->getMemoryVT(), LD->getMemOperand());
6384
6385 // If this is an i16 load, insert the truncate.
6386 SDValue ResVal = BSLoad;
6387 if (N->getValueType(0) == MVT::i16)
6388 ResVal = DAG.getNode(ISD::TRUNCATE, SDLoc(N), MVT::i16, BSLoad);
6389
6390 // First, combine the bswap away. This makes the value produced by the
6391 // load dead.
6392 DCI.CombineTo(N, ResVal);
6393
6394 // Next, combine the load away, we give it a bogus result value but a real
6395 // chain result. The result value is dead because the bswap is dead.
6396 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
6397
6398 // Return N so it doesn't get rechecked!
6399 return SDValue(N, 0);
6400 }
6401
6402 // Look through bitcasts that retain the number of vector elements.
6403 SDValue Op = N->getOperand(0);
6404 if (Op.getOpcode() == ISD::BITCAST &&
6405 Op.getValueType().isVector() &&
6406 Op.getOperand(0).getValueType().isVector() &&
6407 Op.getValueType().getVectorNumElements() ==
6408 Op.getOperand(0).getValueType().getVectorNumElements())
6409 Op = Op.getOperand(0);
6410
6411 // Push BSWAP into a vector insertion if at least one side then simplifies.
6412 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) {
6413 SDValue Vec = Op.getOperand(0);
6414 SDValue Elt = Op.getOperand(1);
6415 SDValue Idx = Op.getOperand(2);
6416
6417 if (DAG.isConstantIntBuildVectorOrConstantInt(Vec) ||
6418 Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() ||
6419 DAG.isConstantIntBuildVectorOrConstantInt(Elt) ||
6420 Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() ||
6421 (canLoadStoreByteSwapped(N->getValueType(0)) &&
6422 ISD::isNON_EXTLoad(Elt.getNode()) && Elt.hasOneUse())) {
6423 EVT VecVT = N->getValueType(0);
6424 EVT EltVT = N->getValueType(0).getVectorElementType();
6425 if (VecVT != Vec.getValueType()) {
6426 Vec = DAG.getNode(ISD::BITCAST, SDLoc(N), VecVT, Vec);
6427 DCI.AddToWorklist(Vec.getNode());
6428 }
6429 if (EltVT != Elt.getValueType()) {
6430 Elt = DAG.getNode(ISD::BITCAST, SDLoc(N), EltVT, Elt);
6431 DCI.AddToWorklist(Elt.getNode());
6432 }
6433 Vec = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Vec);
6434 DCI.AddToWorklist(Vec.getNode());
6435 Elt = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Elt);
6436 DCI.AddToWorklist(Elt.getNode());
6437 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT,
6438 Vec, Elt, Idx);
6439 }
6440 }
6441
6442 // Push BSWAP into a vector shuffle if at least one side then simplifies.
6443 ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(Op);
6444 if (SV && Op.hasOneUse()) {
6445 SDValue Op0 = Op.getOperand(0);
6446 SDValue Op1 = Op.getOperand(1);
6447
6448 if (DAG.isConstantIntBuildVectorOrConstantInt(Op0) ||
6449 Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() ||
6450 DAG.isConstantIntBuildVectorOrConstantInt(Op1) ||
6451 Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) {
6452 EVT VecVT = N->getValueType(0);
6453 if (VecVT != Op0.getValueType()) {
6454 Op0 = DAG.getNode(ISD::BITCAST, SDLoc(N), VecVT, Op0);
6455 DCI.AddToWorklist(Op0.getNode());
6456 }
6457 if (VecVT != Op1.getValueType()) {
6458 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), VecVT, Op1);
6459 DCI.AddToWorklist(Op1.getNode());
6460 }
6461 Op0 = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Op0);
6462 DCI.AddToWorklist(Op0.getNode());
6463 Op1 = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Op1);
6464 DCI.AddToWorklist(Op1.getNode());
6465 return DAG.getVectorShuffle(VecVT, SDLoc(N), Op0, Op1, SV->getMask());
6466 }
6467 }
6468
6469 return SDValue();
6470 }
6471
combineCCMask(SDValue & CCReg,int & CCValid,int & CCMask)6472 static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
6473 // We have a SELECT_CCMASK or BR_CCMASK comparing the condition code
6474 // set by the CCReg instruction using the CCValid / CCMask masks,
6475 // If the CCReg instruction is itself a ICMP testing the condition
6476 // code set by some other instruction, see whether we can directly
6477 // use that condition code.
6478
6479 // Verify that we have an ICMP against some constant.
6480 if (CCValid != SystemZ::CCMASK_ICMP)
6481 return false;
6482 auto *ICmp = CCReg.getNode();
6483 if (ICmp->getOpcode() != SystemZISD::ICMP)
6484 return false;
6485 auto *CompareLHS = ICmp->getOperand(0).getNode();
6486 auto *CompareRHS = dyn_cast<ConstantSDNode>(ICmp->getOperand(1));
6487 if (!CompareRHS)
6488 return false;
6489
6490 // Optimize the case where CompareLHS is a SELECT_CCMASK.
6491 if (CompareLHS->getOpcode() == SystemZISD::SELECT_CCMASK) {
6492 // Verify that we have an appropriate mask for a EQ or NE comparison.
6493 bool Invert = false;
6494 if (CCMask == SystemZ::CCMASK_CMP_NE)
6495 Invert = !Invert;
6496 else if (CCMask != SystemZ::CCMASK_CMP_EQ)
6497 return false;
6498
6499 // Verify that the ICMP compares against one of select values.
6500 auto *TrueVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(0));
6501 if (!TrueVal)
6502 return false;
6503 auto *FalseVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
6504 if (!FalseVal)
6505 return false;
6506 if (CompareRHS->getZExtValue() == FalseVal->getZExtValue())
6507 Invert = !Invert;
6508 else if (CompareRHS->getZExtValue() != TrueVal->getZExtValue())
6509 return false;
6510
6511 // Compute the effective CC mask for the new branch or select.
6512 auto *NewCCValid = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(2));
6513 auto *NewCCMask = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(3));
6514 if (!NewCCValid || !NewCCMask)
6515 return false;
6516 CCValid = NewCCValid->getZExtValue();
6517 CCMask = NewCCMask->getZExtValue();
6518 if (Invert)
6519 CCMask ^= CCValid;
6520
6521 // Return the updated CCReg link.
6522 CCReg = CompareLHS->getOperand(4);
6523 return true;
6524 }
6525
6526 // Optimize the case where CompareRHS is (SRA (SHL (IPM))).
6527 if (CompareLHS->getOpcode() == ISD::SRA) {
6528 auto *SRACount = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
6529 if (!SRACount || SRACount->getZExtValue() != 30)
6530 return false;
6531 auto *SHL = CompareLHS->getOperand(0).getNode();
6532 if (SHL->getOpcode() != ISD::SHL)
6533 return false;
6534 auto *SHLCount = dyn_cast<ConstantSDNode>(SHL->getOperand(1));
6535 if (!SHLCount || SHLCount->getZExtValue() != 30 - SystemZ::IPM_CC)
6536 return false;
6537 auto *IPM = SHL->getOperand(0).getNode();
6538 if (IPM->getOpcode() != SystemZISD::IPM)
6539 return false;
6540
6541 // Avoid introducing CC spills (because SRA would clobber CC).
6542 if (!CompareLHS->hasOneUse())
6543 return false;
6544 // Verify that the ICMP compares against zero.
6545 if (CompareRHS->getZExtValue() != 0)
6546 return false;
6547
6548 // Compute the effective CC mask for the new branch or select.
6549 CCMask = SystemZ::reverseCCMask(CCMask);
6550
6551 // Return the updated CCReg link.
6552 CCReg = IPM->getOperand(0);
6553 return true;
6554 }
6555
6556 return false;
6557 }
6558
combineBR_CCMASK(SDNode * N,DAGCombinerInfo & DCI) const6559 SDValue SystemZTargetLowering::combineBR_CCMASK(
6560 SDNode *N, DAGCombinerInfo &DCI) const {
6561 SelectionDAG &DAG = DCI.DAG;
6562
6563 // Combine BR_CCMASK (ICMP (SELECT_CCMASK)) into a single BR_CCMASK.
6564 auto *CCValid = dyn_cast<ConstantSDNode>(N->getOperand(1));
6565 auto *CCMask = dyn_cast<ConstantSDNode>(N->getOperand(2));
6566 if (!CCValid || !CCMask)
6567 return SDValue();
6568
6569 int CCValidVal = CCValid->getZExtValue();
6570 int CCMaskVal = CCMask->getZExtValue();
6571 SDValue Chain = N->getOperand(0);
6572 SDValue CCReg = N->getOperand(4);
6573
6574 if (combineCCMask(CCReg, CCValidVal, CCMaskVal))
6575 return DAG.getNode(SystemZISD::BR_CCMASK, SDLoc(N), N->getValueType(0),
6576 Chain,
6577 DAG.getTargetConstant(CCValidVal, SDLoc(N), MVT::i32),
6578 DAG.getTargetConstant(CCMaskVal, SDLoc(N), MVT::i32),
6579 N->getOperand(3), CCReg);
6580 return SDValue();
6581 }
6582
combineSELECT_CCMASK(SDNode * N,DAGCombinerInfo & DCI) const6583 SDValue SystemZTargetLowering::combineSELECT_CCMASK(
6584 SDNode *N, DAGCombinerInfo &DCI) const {
6585 SelectionDAG &DAG = DCI.DAG;
6586
6587 // Combine SELECT_CCMASK (ICMP (SELECT_CCMASK)) into a single SELECT_CCMASK.
6588 auto *CCValid = dyn_cast<ConstantSDNode>(N->getOperand(2));
6589 auto *CCMask = dyn_cast<ConstantSDNode>(N->getOperand(3));
6590 if (!CCValid || !CCMask)
6591 return SDValue();
6592
6593 int CCValidVal = CCValid->getZExtValue();
6594 int CCMaskVal = CCMask->getZExtValue();
6595 SDValue CCReg = N->getOperand(4);
6596
6597 if (combineCCMask(CCReg, CCValidVal, CCMaskVal))
6598 return DAG.getNode(SystemZISD::SELECT_CCMASK, SDLoc(N), N->getValueType(0),
6599 N->getOperand(0), N->getOperand(1),
6600 DAG.getTargetConstant(CCValidVal, SDLoc(N), MVT::i32),
6601 DAG.getTargetConstant(CCMaskVal, SDLoc(N), MVT::i32),
6602 CCReg);
6603 return SDValue();
6604 }
6605
6606
combineGET_CCMASK(SDNode * N,DAGCombinerInfo & DCI) const6607 SDValue SystemZTargetLowering::combineGET_CCMASK(
6608 SDNode *N, DAGCombinerInfo &DCI) const {
6609
6610 // Optimize away GET_CCMASK (SELECT_CCMASK) if the CC masks are compatible
6611 auto *CCValid = dyn_cast<ConstantSDNode>(N->getOperand(1));
6612 auto *CCMask = dyn_cast<ConstantSDNode>(N->getOperand(2));
6613 if (!CCValid || !CCMask)
6614 return SDValue();
6615 int CCValidVal = CCValid->getZExtValue();
6616 int CCMaskVal = CCMask->getZExtValue();
6617
6618 SDValue Select = N->getOperand(0);
6619 if (Select->getOpcode() != SystemZISD::SELECT_CCMASK)
6620 return SDValue();
6621
6622 auto *SelectCCValid = dyn_cast<ConstantSDNode>(Select->getOperand(2));
6623 auto *SelectCCMask = dyn_cast<ConstantSDNode>(Select->getOperand(3));
6624 if (!SelectCCValid || !SelectCCMask)
6625 return SDValue();
6626 int SelectCCValidVal = SelectCCValid->getZExtValue();
6627 int SelectCCMaskVal = SelectCCMask->getZExtValue();
6628
6629 auto *TrueVal = dyn_cast<ConstantSDNode>(Select->getOperand(0));
6630 auto *FalseVal = dyn_cast<ConstantSDNode>(Select->getOperand(1));
6631 if (!TrueVal || !FalseVal)
6632 return SDValue();
6633 if (TrueVal->getZExtValue() != 0 && FalseVal->getZExtValue() == 0)
6634 ;
6635 else if (TrueVal->getZExtValue() == 0 && FalseVal->getZExtValue() != 0)
6636 SelectCCMaskVal ^= SelectCCValidVal;
6637 else
6638 return SDValue();
6639
6640 if (SelectCCValidVal & ~CCValidVal)
6641 return SDValue();
6642 if (SelectCCMaskVal != (CCMaskVal & SelectCCValidVal))
6643 return SDValue();
6644
6645 return Select->getOperand(4);
6646 }
6647
combineIntDIVREM(SDNode * N,DAGCombinerInfo & DCI) const6648 SDValue SystemZTargetLowering::combineIntDIVREM(
6649 SDNode *N, DAGCombinerInfo &DCI) const {
6650 SelectionDAG &DAG = DCI.DAG;
6651 EVT VT = N->getValueType(0);
6652 // In the case where the divisor is a vector of constants a cheaper
6653 // sequence of instructions can replace the divide. BuildSDIV is called to
6654 // do this during DAG combining, but it only succeeds when it can build a
6655 // multiplication node. The only option for SystemZ is ISD::SMUL_LOHI, and
6656 // since it is not Legal but Custom it can only happen before
6657 // legalization. Therefore we must scalarize this early before Combine
6658 // 1. For widened vectors, this is already the result of type legalization.
6659 if (DCI.Level == BeforeLegalizeTypes && VT.isVector() && isTypeLegal(VT) &&
6660 DAG.isConstantIntBuildVectorOrConstantInt(N->getOperand(1)))
6661 return DAG.UnrollVectorOp(N);
6662 return SDValue();
6663 }
6664
combineINTRINSIC(SDNode * N,DAGCombinerInfo & DCI) const6665 SDValue SystemZTargetLowering::combineINTRINSIC(
6666 SDNode *N, DAGCombinerInfo &DCI) const {
6667 SelectionDAG &DAG = DCI.DAG;
6668
6669 unsigned Id = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6670 switch (Id) {
6671 // VECTOR LOAD (RIGHTMOST) WITH LENGTH with a length operand of 15
6672 // or larger is simply a vector load.
6673 case Intrinsic::s390_vll:
6674 case Intrinsic::s390_vlrl:
6675 if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
6676 if (C->getZExtValue() >= 15)
6677 return DAG.getLoad(N->getValueType(0), SDLoc(N), N->getOperand(0),
6678 N->getOperand(3), MachinePointerInfo());
6679 break;
6680 // Likewise for VECTOR STORE (RIGHTMOST) WITH LENGTH.
6681 case Intrinsic::s390_vstl:
6682 case Intrinsic::s390_vstrl:
6683 if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
6684 if (C->getZExtValue() >= 15)
6685 return DAG.getStore(N->getOperand(0), SDLoc(N), N->getOperand(2),
6686 N->getOperand(4), MachinePointerInfo());
6687 break;
6688 }
6689
6690 return SDValue();
6691 }
6692
unwrapAddress(SDValue N) const6693 SDValue SystemZTargetLowering::unwrapAddress(SDValue N) const {
6694 if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)
6695 return N->getOperand(0);
6696 return N;
6697 }
6698
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const6699 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
6700 DAGCombinerInfo &DCI) const {
6701 switch(N->getOpcode()) {
6702 default: break;
6703 case ISD::ZERO_EXTEND: return combineZERO_EXTEND(N, DCI);
6704 case ISD::SIGN_EXTEND: return combineSIGN_EXTEND(N, DCI);
6705 case ISD::SIGN_EXTEND_INREG: return combineSIGN_EXTEND_INREG(N, DCI);
6706 case SystemZISD::MERGE_HIGH:
6707 case SystemZISD::MERGE_LOW: return combineMERGE(N, DCI);
6708 case ISD::LOAD: return combineLOAD(N, DCI);
6709 case ISD::STORE: return combineSTORE(N, DCI);
6710 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI);
6711 case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
6712 case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);
6713 case ISD::STRICT_FP_ROUND:
6714 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI);
6715 case ISD::STRICT_FP_EXTEND:
6716 case ISD::FP_EXTEND: return combineFP_EXTEND(N, DCI);
6717 case ISD::SINT_TO_FP:
6718 case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI);
6719 case ISD::BSWAP: return combineBSWAP(N, DCI);
6720 case SystemZISD::BR_CCMASK: return combineBR_CCMASK(N, DCI);
6721 case SystemZISD::SELECT_CCMASK: return combineSELECT_CCMASK(N, DCI);
6722 case SystemZISD::GET_CCMASK: return combineGET_CCMASK(N, DCI);
6723 case ISD::SDIV:
6724 case ISD::UDIV:
6725 case ISD::SREM:
6726 case ISD::UREM: return combineIntDIVREM(N, DCI);
6727 case ISD::INTRINSIC_W_CHAIN:
6728 case ISD::INTRINSIC_VOID: return combineINTRINSIC(N, DCI);
6729 }
6730
6731 return SDValue();
6732 }
6733
6734 // Return the demanded elements for the OpNo source operand of Op. DemandedElts
6735 // are for Op.
getDemandedSrcElements(SDValue Op,const APInt & DemandedElts,unsigned OpNo)6736 static APInt getDemandedSrcElements(SDValue Op, const APInt &DemandedElts,
6737 unsigned OpNo) {
6738 EVT VT = Op.getValueType();
6739 unsigned NumElts = (VT.isVector() ? VT.getVectorNumElements() : 1);
6740 APInt SrcDemE;
6741 unsigned Opcode = Op.getOpcode();
6742 if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
6743 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6744 switch (Id) {
6745 case Intrinsic::s390_vpksh: // PACKS
6746 case Intrinsic::s390_vpksf:
6747 case Intrinsic::s390_vpksg:
6748 case Intrinsic::s390_vpkshs: // PACKS_CC
6749 case Intrinsic::s390_vpksfs:
6750 case Intrinsic::s390_vpksgs:
6751 case Intrinsic::s390_vpklsh: // PACKLS
6752 case Intrinsic::s390_vpklsf:
6753 case Intrinsic::s390_vpklsg:
6754 case Intrinsic::s390_vpklshs: // PACKLS_CC
6755 case Intrinsic::s390_vpklsfs:
6756 case Intrinsic::s390_vpklsgs:
6757 // VECTOR PACK truncates the elements of two source vectors into one.
6758 SrcDemE = DemandedElts;
6759 if (OpNo == 2)
6760 SrcDemE.lshrInPlace(NumElts / 2);
6761 SrcDemE = SrcDemE.trunc(NumElts / 2);
6762 break;
6763 // VECTOR UNPACK extends half the elements of the source vector.
6764 case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
6765 case Intrinsic::s390_vuphh:
6766 case Intrinsic::s390_vuphf:
6767 case Intrinsic::s390_vuplhb: // VECTOR UNPACK LOGICAL HIGH
6768 case Intrinsic::s390_vuplhh:
6769 case Intrinsic::s390_vuplhf:
6770 SrcDemE = APInt(NumElts * 2, 0);
6771 SrcDemE.insertBits(DemandedElts, 0);
6772 break;
6773 case Intrinsic::s390_vuplb: // VECTOR UNPACK LOW
6774 case Intrinsic::s390_vuplhw:
6775 case Intrinsic::s390_vuplf:
6776 case Intrinsic::s390_vupllb: // VECTOR UNPACK LOGICAL LOW
6777 case Intrinsic::s390_vupllh:
6778 case Intrinsic::s390_vupllf:
6779 SrcDemE = APInt(NumElts * 2, 0);
6780 SrcDemE.insertBits(DemandedElts, NumElts);
6781 break;
6782 case Intrinsic::s390_vpdi: {
6783 // VECTOR PERMUTE DWORD IMMEDIATE selects one element from each source.
6784 SrcDemE = APInt(NumElts, 0);
6785 if (!DemandedElts[OpNo - 1])
6786 break;
6787 unsigned Mask = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
6788 unsigned MaskBit = ((OpNo - 1) ? 1 : 4);
6789 // Demand input element 0 or 1, given by the mask bit value.
6790 SrcDemE.setBit((Mask & MaskBit)? 1 : 0);
6791 break;
6792 }
6793 case Intrinsic::s390_vsldb: {
6794 // VECTOR SHIFT LEFT DOUBLE BY BYTE
6795 assert(VT == MVT::v16i8 && "Unexpected type.");
6796 unsigned FirstIdx = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
6797 assert (FirstIdx > 0 && FirstIdx < 16 && "Unused operand.");
6798 unsigned NumSrc0Els = 16 - FirstIdx;
6799 SrcDemE = APInt(NumElts, 0);
6800 if (OpNo == 1) {
6801 APInt DemEls = DemandedElts.trunc(NumSrc0Els);
6802 SrcDemE.insertBits(DemEls, FirstIdx);
6803 } else {
6804 APInt DemEls = DemandedElts.lshr(NumSrc0Els);
6805 SrcDemE.insertBits(DemEls, 0);
6806 }
6807 break;
6808 }
6809 case Intrinsic::s390_vperm:
6810 SrcDemE = APInt(NumElts, 1);
6811 break;
6812 default:
6813 llvm_unreachable("Unhandled intrinsic.");
6814 break;
6815 }
6816 } else {
6817 switch (Opcode) {
6818 case SystemZISD::JOIN_DWORDS:
6819 // Scalar operand.
6820 SrcDemE = APInt(1, 1);
6821 break;
6822 case SystemZISD::SELECT_CCMASK:
6823 SrcDemE = DemandedElts;
6824 break;
6825 default:
6826 llvm_unreachable("Unhandled opcode.");
6827 break;
6828 }
6829 }
6830 return SrcDemE;
6831 }
6832
computeKnownBitsBinOp(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth,unsigned OpNo)6833 static void computeKnownBitsBinOp(const SDValue Op, KnownBits &Known,
6834 const APInt &DemandedElts,
6835 const SelectionDAG &DAG, unsigned Depth,
6836 unsigned OpNo) {
6837 APInt Src0DemE = getDemandedSrcElements(Op, DemandedElts, OpNo);
6838 APInt Src1DemE = getDemandedSrcElements(Op, DemandedElts, OpNo + 1);
6839 KnownBits LHSKnown =
6840 DAG.computeKnownBits(Op.getOperand(OpNo), Src0DemE, Depth + 1);
6841 KnownBits RHSKnown =
6842 DAG.computeKnownBits(Op.getOperand(OpNo + 1), Src1DemE, Depth + 1);
6843 Known = KnownBits::commonBits(LHSKnown, RHSKnown);
6844 }
6845
6846 void
computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const6847 SystemZTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
6848 KnownBits &Known,
6849 const APInt &DemandedElts,
6850 const SelectionDAG &DAG,
6851 unsigned Depth) const {
6852 Known.resetAll();
6853
6854 // Intrinsic CC result is returned in the two low bits.
6855 unsigned tmp0, tmp1; // not used
6856 if (Op.getResNo() == 1 && isIntrinsicWithCC(Op, tmp0, tmp1)) {
6857 Known.Zero.setBitsFrom(2);
6858 return;
6859 }
6860 EVT VT = Op.getValueType();
6861 if (Op.getResNo() != 0 || VT == MVT::Untyped)
6862 return;
6863 assert (Known.getBitWidth() == VT.getScalarSizeInBits() &&
6864 "KnownBits does not match VT in bitwidth");
6865 assert ((!VT.isVector() ||
6866 (DemandedElts.getBitWidth() == VT.getVectorNumElements())) &&
6867 "DemandedElts does not match VT number of elements");
6868 unsigned BitWidth = Known.getBitWidth();
6869 unsigned Opcode = Op.getOpcode();
6870 if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
6871 bool IsLogical = false;
6872 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6873 switch (Id) {
6874 case Intrinsic::s390_vpksh: // PACKS
6875 case Intrinsic::s390_vpksf:
6876 case Intrinsic::s390_vpksg:
6877 case Intrinsic::s390_vpkshs: // PACKS_CC
6878 case Intrinsic::s390_vpksfs:
6879 case Intrinsic::s390_vpksgs:
6880 case Intrinsic::s390_vpklsh: // PACKLS
6881 case Intrinsic::s390_vpklsf:
6882 case Intrinsic::s390_vpklsg:
6883 case Intrinsic::s390_vpklshs: // PACKLS_CC
6884 case Intrinsic::s390_vpklsfs:
6885 case Intrinsic::s390_vpklsgs:
6886 case Intrinsic::s390_vpdi:
6887 case Intrinsic::s390_vsldb:
6888 case Intrinsic::s390_vperm:
6889 computeKnownBitsBinOp(Op, Known, DemandedElts, DAG, Depth, 1);
6890 break;
6891 case Intrinsic::s390_vuplhb: // VECTOR UNPACK LOGICAL HIGH
6892 case Intrinsic::s390_vuplhh:
6893 case Intrinsic::s390_vuplhf:
6894 case Intrinsic::s390_vupllb: // VECTOR UNPACK LOGICAL LOW
6895 case Intrinsic::s390_vupllh:
6896 case Intrinsic::s390_vupllf:
6897 IsLogical = true;
6898 LLVM_FALLTHROUGH;
6899 case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
6900 case Intrinsic::s390_vuphh:
6901 case Intrinsic::s390_vuphf:
6902 case Intrinsic::s390_vuplb: // VECTOR UNPACK LOW
6903 case Intrinsic::s390_vuplhw:
6904 case Intrinsic::s390_vuplf: {
6905 SDValue SrcOp = Op.getOperand(1);
6906 APInt SrcDemE = getDemandedSrcElements(Op, DemandedElts, 0);
6907 Known = DAG.computeKnownBits(SrcOp, SrcDemE, Depth + 1);
6908 if (IsLogical) {
6909 Known = Known.zext(BitWidth);
6910 } else
6911 Known = Known.sext(BitWidth);
6912 break;
6913 }
6914 default:
6915 break;
6916 }
6917 } else {
6918 switch (Opcode) {
6919 case SystemZISD::JOIN_DWORDS:
6920 case SystemZISD::SELECT_CCMASK:
6921 computeKnownBitsBinOp(Op, Known, DemandedElts, DAG, Depth, 0);
6922 break;
6923 case SystemZISD::REPLICATE: {
6924 SDValue SrcOp = Op.getOperand(0);
6925 Known = DAG.computeKnownBits(SrcOp, Depth + 1);
6926 if (Known.getBitWidth() < BitWidth && isa<ConstantSDNode>(SrcOp))
6927 Known = Known.sext(BitWidth); // VREPI sign extends the immedate.
6928 break;
6929 }
6930 default:
6931 break;
6932 }
6933 }
6934
6935 // Known has the width of the source operand(s). Adjust if needed to match
6936 // the passed bitwidth.
6937 if (Known.getBitWidth() != BitWidth)
6938 Known = Known.anyextOrTrunc(BitWidth);
6939 }
6940
computeNumSignBitsBinOp(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth,unsigned OpNo)6941 static unsigned computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts,
6942 const SelectionDAG &DAG, unsigned Depth,
6943 unsigned OpNo) {
6944 APInt Src0DemE = getDemandedSrcElements(Op, DemandedElts, OpNo);
6945 unsigned LHS = DAG.ComputeNumSignBits(Op.getOperand(OpNo), Src0DemE, Depth + 1);
6946 if (LHS == 1) return 1; // Early out.
6947 APInt Src1DemE = getDemandedSrcElements(Op, DemandedElts, OpNo + 1);
6948 unsigned RHS = DAG.ComputeNumSignBits(Op.getOperand(OpNo + 1), Src1DemE, Depth + 1);
6949 if (RHS == 1) return 1; // Early out.
6950 unsigned Common = std::min(LHS, RHS);
6951 unsigned SrcBitWidth = Op.getOperand(OpNo).getScalarValueSizeInBits();
6952 EVT VT = Op.getValueType();
6953 unsigned VTBits = VT.getScalarSizeInBits();
6954 if (SrcBitWidth > VTBits) { // PACK
6955 unsigned SrcExtraBits = SrcBitWidth - VTBits;
6956 if (Common > SrcExtraBits)
6957 return (Common - SrcExtraBits);
6958 return 1;
6959 }
6960 assert (SrcBitWidth == VTBits && "Expected operands of same bitwidth.");
6961 return Common;
6962 }
6963
6964 unsigned
ComputeNumSignBitsForTargetNode(SDValue Op,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const6965 SystemZTargetLowering::ComputeNumSignBitsForTargetNode(
6966 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
6967 unsigned Depth) const {
6968 if (Op.getResNo() != 0)
6969 return 1;
6970 unsigned Opcode = Op.getOpcode();
6971 if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
6972 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6973 switch (Id) {
6974 case Intrinsic::s390_vpksh: // PACKS
6975 case Intrinsic::s390_vpksf:
6976 case Intrinsic::s390_vpksg:
6977 case Intrinsic::s390_vpkshs: // PACKS_CC
6978 case Intrinsic::s390_vpksfs:
6979 case Intrinsic::s390_vpksgs:
6980 case Intrinsic::s390_vpklsh: // PACKLS
6981 case Intrinsic::s390_vpklsf:
6982 case Intrinsic::s390_vpklsg:
6983 case Intrinsic::s390_vpklshs: // PACKLS_CC
6984 case Intrinsic::s390_vpklsfs:
6985 case Intrinsic::s390_vpklsgs:
6986 case Intrinsic::s390_vpdi:
6987 case Intrinsic::s390_vsldb:
6988 case Intrinsic::s390_vperm:
6989 return computeNumSignBitsBinOp(Op, DemandedElts, DAG, Depth, 1);
6990 case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
6991 case Intrinsic::s390_vuphh:
6992 case Intrinsic::s390_vuphf:
6993 case Intrinsic::s390_vuplb: // VECTOR UNPACK LOW
6994 case Intrinsic::s390_vuplhw:
6995 case Intrinsic::s390_vuplf: {
6996 SDValue PackedOp = Op.getOperand(1);
6997 APInt SrcDemE = getDemandedSrcElements(Op, DemandedElts, 1);
6998 unsigned Tmp = DAG.ComputeNumSignBits(PackedOp, SrcDemE, Depth + 1);
6999 EVT VT = Op.getValueType();
7000 unsigned VTBits = VT.getScalarSizeInBits();
7001 Tmp += VTBits - PackedOp.getScalarValueSizeInBits();
7002 return Tmp;
7003 }
7004 default:
7005 break;
7006 }
7007 } else {
7008 switch (Opcode) {
7009 case SystemZISD::SELECT_CCMASK:
7010 return computeNumSignBitsBinOp(Op, DemandedElts, DAG, Depth, 0);
7011 default:
7012 break;
7013 }
7014 }
7015
7016 return 1;
7017 }
7018
7019 unsigned
getStackProbeSize(MachineFunction & MF) const7020 SystemZTargetLowering::getStackProbeSize(MachineFunction &MF) const {
7021 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
7022 unsigned StackAlign = TFI->getStackAlignment();
7023 assert(StackAlign >=1 && isPowerOf2_32(StackAlign) &&
7024 "Unexpected stack alignment");
7025 // The default stack probe size is 4096 if the function has no
7026 // stack-probe-size attribute.
7027 unsigned StackProbeSize = 4096;
7028 const Function &Fn = MF.getFunction();
7029 if (Fn.hasFnAttribute("stack-probe-size"))
7030 Fn.getFnAttribute("stack-probe-size")
7031 .getValueAsString()
7032 .getAsInteger(0, StackProbeSize);
7033 // Round down to the stack alignment.
7034 StackProbeSize &= ~(StackAlign - 1);
7035 return StackProbeSize ? StackProbeSize : StackAlign;
7036 }
7037
7038 //===----------------------------------------------------------------------===//
7039 // Custom insertion
7040 //===----------------------------------------------------------------------===//
7041
7042 // Force base value Base into a register before MI. Return the register.
forceReg(MachineInstr & MI,MachineOperand & Base,const SystemZInstrInfo * TII)7043 static Register forceReg(MachineInstr &MI, MachineOperand &Base,
7044 const SystemZInstrInfo *TII) {
7045 if (Base.isReg())
7046 return Base.getReg();
7047
7048 MachineBasicBlock *MBB = MI.getParent();
7049 MachineFunction &MF = *MBB->getParent();
7050 MachineRegisterInfo &MRI = MF.getRegInfo();
7051
7052 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7053 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
7054 .add(Base)
7055 .addImm(0)
7056 .addReg(0);
7057 return Reg;
7058 }
7059
7060 // The CC operand of MI might be missing a kill marker because there
7061 // were multiple uses of CC, and ISel didn't know which to mark.
7062 // Figure out whether MI should have had a kill marker.
checkCCKill(MachineInstr & MI,MachineBasicBlock * MBB)7063 static bool checkCCKill(MachineInstr &MI, MachineBasicBlock *MBB) {
7064 // Scan forward through BB for a use/def of CC.
7065 MachineBasicBlock::iterator miI(std::next(MachineBasicBlock::iterator(MI)));
7066 for (MachineBasicBlock::iterator miE = MBB->end(); miI != miE; ++miI) {
7067 const MachineInstr& mi = *miI;
7068 if (mi.readsRegister(SystemZ::CC))
7069 return false;
7070 if (mi.definesRegister(SystemZ::CC))
7071 break; // Should have kill-flag - update below.
7072 }
7073
7074 // If we hit the end of the block, check whether CC is live into a
7075 // successor.
7076 if (miI == MBB->end()) {
7077 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI)
7078 if ((*SI)->isLiveIn(SystemZ::CC))
7079 return false;
7080 }
7081
7082 return true;
7083 }
7084
7085 // Return true if it is OK for this Select pseudo-opcode to be cascaded
7086 // together with other Select pseudo-opcodes into a single basic-block with
7087 // a conditional jump around it.
isSelectPseudo(MachineInstr & MI)7088 static bool isSelectPseudo(MachineInstr &MI) {
7089 switch (MI.getOpcode()) {
7090 case SystemZ::Select32:
7091 case SystemZ::Select64:
7092 case SystemZ::SelectF32:
7093 case SystemZ::SelectF64:
7094 case SystemZ::SelectF128:
7095 case SystemZ::SelectVR32:
7096 case SystemZ::SelectVR64:
7097 case SystemZ::SelectVR128:
7098 return true;
7099
7100 default:
7101 return false;
7102 }
7103 }
7104
7105 // Helper function, which inserts PHI functions into SinkMBB:
7106 // %Result(i) = phi [ %FalseValue(i), FalseMBB ], [ %TrueValue(i), TrueMBB ],
7107 // where %FalseValue(i) and %TrueValue(i) are taken from Selects.
createPHIsForSelects(SmallVector<MachineInstr *,8> & Selects,MachineBasicBlock * TrueMBB,MachineBasicBlock * FalseMBB,MachineBasicBlock * SinkMBB)7108 static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
7109 MachineBasicBlock *TrueMBB,
7110 MachineBasicBlock *FalseMBB,
7111 MachineBasicBlock *SinkMBB) {
7112 MachineFunction *MF = TrueMBB->getParent();
7113 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
7114
7115 MachineInstr *FirstMI = Selects.front();
7116 unsigned CCValid = FirstMI->getOperand(3).getImm();
7117 unsigned CCMask = FirstMI->getOperand(4).getImm();
7118
7119 MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
7120
7121 // As we are creating the PHIs, we have to be careful if there is more than
7122 // one. Later Selects may reference the results of earlier Selects, but later
7123 // PHIs have to reference the individual true/false inputs from earlier PHIs.
7124 // That also means that PHI construction must work forward from earlier to
7125 // later, and that the code must maintain a mapping from earlier PHI's
7126 // destination registers, and the registers that went into the PHI.
7127 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
7128
7129 for (auto MI : Selects) {
7130 Register DestReg = MI->getOperand(0).getReg();
7131 Register TrueReg = MI->getOperand(1).getReg();
7132 Register FalseReg = MI->getOperand(2).getReg();
7133
7134 // If this Select we are generating is the opposite condition from
7135 // the jump we generated, then we have to swap the operands for the
7136 // PHI that is going to be generated.
7137 if (MI->getOperand(4).getImm() == (CCValid ^ CCMask))
7138 std::swap(TrueReg, FalseReg);
7139
7140 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end())
7141 TrueReg = RegRewriteTable[TrueReg].first;
7142
7143 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end())
7144 FalseReg = RegRewriteTable[FalseReg].second;
7145
7146 DebugLoc DL = MI->getDebugLoc();
7147 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(SystemZ::PHI), DestReg)
7148 .addReg(TrueReg).addMBB(TrueMBB)
7149 .addReg(FalseReg).addMBB(FalseMBB);
7150
7151 // Add this PHI to the rewrite table.
7152 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
7153 }
7154
7155 MF->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
7156 }
7157
7158 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
7159 MachineBasicBlock *
emitSelect(MachineInstr & MI,MachineBasicBlock * MBB) const7160 SystemZTargetLowering::emitSelect(MachineInstr &MI,
7161 MachineBasicBlock *MBB) const {
7162 assert(isSelectPseudo(MI) && "Bad call to emitSelect()");
7163 const SystemZInstrInfo *TII =
7164 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7165
7166 unsigned CCValid = MI.getOperand(3).getImm();
7167 unsigned CCMask = MI.getOperand(4).getImm();
7168
7169 // If we have a sequence of Select* pseudo instructions using the
7170 // same condition code value, we want to expand all of them into
7171 // a single pair of basic blocks using the same condition.
7172 SmallVector<MachineInstr*, 8> Selects;
7173 SmallVector<MachineInstr*, 8> DbgValues;
7174 Selects.push_back(&MI);
7175 unsigned Count = 0;
7176 for (MachineBasicBlock::iterator NextMIIt =
7177 std::next(MachineBasicBlock::iterator(MI));
7178 NextMIIt != MBB->end(); ++NextMIIt) {
7179 if (isSelectPseudo(*NextMIIt)) {
7180 assert(NextMIIt->getOperand(3).getImm() == CCValid &&
7181 "Bad CCValid operands since CC was not redefined.");
7182 if (NextMIIt->getOperand(4).getImm() == CCMask ||
7183 NextMIIt->getOperand(4).getImm() == (CCValid ^ CCMask)) {
7184 Selects.push_back(&*NextMIIt);
7185 continue;
7186 }
7187 break;
7188 }
7189 if (NextMIIt->definesRegister(SystemZ::CC) ||
7190 NextMIIt->usesCustomInsertionHook())
7191 break;
7192 bool User = false;
7193 for (auto SelMI : Selects)
7194 if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
7195 User = true;
7196 break;
7197 }
7198 if (NextMIIt->isDebugInstr()) {
7199 if (User) {
7200 assert(NextMIIt->isDebugValue() && "Unhandled debug opcode.");
7201 DbgValues.push_back(&*NextMIIt);
7202 }
7203 }
7204 else if (User || ++Count > 20)
7205 break;
7206 }
7207
7208 MachineInstr *LastMI = Selects.back();
7209 bool CCKilled =
7210 (LastMI->killsRegister(SystemZ::CC) || checkCCKill(*LastMI, MBB));
7211 MachineBasicBlock *StartMBB = MBB;
7212 MachineBasicBlock *JoinMBB = SystemZ::splitBlockAfter(LastMI, MBB);
7213 MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(StartMBB);
7214
7215 // Unless CC was killed in the last Select instruction, mark it as
7216 // live-in to both FalseMBB and JoinMBB.
7217 if (!CCKilled) {
7218 FalseMBB->addLiveIn(SystemZ::CC);
7219 JoinMBB->addLiveIn(SystemZ::CC);
7220 }
7221
7222 // StartMBB:
7223 // BRC CCMask, JoinMBB
7224 // # fallthrough to FalseMBB
7225 MBB = StartMBB;
7226 BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC))
7227 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
7228 MBB->addSuccessor(JoinMBB);
7229 MBB->addSuccessor(FalseMBB);
7230
7231 // FalseMBB:
7232 // # fallthrough to JoinMBB
7233 MBB = FalseMBB;
7234 MBB->addSuccessor(JoinMBB);
7235
7236 // JoinMBB:
7237 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
7238 // ...
7239 MBB = JoinMBB;
7240 createPHIsForSelects(Selects, StartMBB, FalseMBB, MBB);
7241 for (auto SelMI : Selects)
7242 SelMI->eraseFromParent();
7243
7244 MachineBasicBlock::iterator InsertPos = MBB->getFirstNonPHI();
7245 for (auto DbgMI : DbgValues)
7246 MBB->splice(InsertPos, StartMBB, DbgMI);
7247
7248 return JoinMBB;
7249 }
7250
7251 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
7252 // StoreOpcode is the store to use and Invert says whether the store should
7253 // happen when the condition is false rather than true. If a STORE ON
7254 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
emitCondStore(MachineInstr & MI,MachineBasicBlock * MBB,unsigned StoreOpcode,unsigned STOCOpcode,bool Invert) const7255 MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
7256 MachineBasicBlock *MBB,
7257 unsigned StoreOpcode,
7258 unsigned STOCOpcode,
7259 bool Invert) const {
7260 const SystemZInstrInfo *TII =
7261 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7262
7263 Register SrcReg = MI.getOperand(0).getReg();
7264 MachineOperand Base = MI.getOperand(1);
7265 int64_t Disp = MI.getOperand(2).getImm();
7266 Register IndexReg = MI.getOperand(3).getReg();
7267 unsigned CCValid = MI.getOperand(4).getImm();
7268 unsigned CCMask = MI.getOperand(5).getImm();
7269 DebugLoc DL = MI.getDebugLoc();
7270
7271 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
7272
7273 // ISel pattern matching also adds a load memory operand of the same
7274 // address, so take special care to find the storing memory operand.
7275 MachineMemOperand *MMO = nullptr;
7276 for (auto *I : MI.memoperands())
7277 if (I->isStore()) {
7278 MMO = I;
7279 break;
7280 }
7281
7282 // Use STOCOpcode if possible. We could use different store patterns in
7283 // order to avoid matching the index register, but the performance trade-offs
7284 // might be more complicated in that case.
7285 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
7286 if (Invert)
7287 CCMask ^= CCValid;
7288
7289 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
7290 .addReg(SrcReg)
7291 .add(Base)
7292 .addImm(Disp)
7293 .addImm(CCValid)
7294 .addImm(CCMask)
7295 .addMemOperand(MMO);
7296
7297 MI.eraseFromParent();
7298 return MBB;
7299 }
7300
7301 // Get the condition needed to branch around the store.
7302 if (!Invert)
7303 CCMask ^= CCValid;
7304
7305 MachineBasicBlock *StartMBB = MBB;
7306 MachineBasicBlock *JoinMBB = SystemZ::splitBlockBefore(MI, MBB);
7307 MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(StartMBB);
7308
7309 // Unless CC was killed in the CondStore instruction, mark it as
7310 // live-in to both FalseMBB and JoinMBB.
7311 if (!MI.killsRegister(SystemZ::CC) && !checkCCKill(MI, JoinMBB)) {
7312 FalseMBB->addLiveIn(SystemZ::CC);
7313 JoinMBB->addLiveIn(SystemZ::CC);
7314 }
7315
7316 // StartMBB:
7317 // BRC CCMask, JoinMBB
7318 // # fallthrough to FalseMBB
7319 MBB = StartMBB;
7320 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7321 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
7322 MBB->addSuccessor(JoinMBB);
7323 MBB->addSuccessor(FalseMBB);
7324
7325 // FalseMBB:
7326 // store %SrcReg, %Disp(%Index,%Base)
7327 // # fallthrough to JoinMBB
7328 MBB = FalseMBB;
7329 BuildMI(MBB, DL, TII->get(StoreOpcode))
7330 .addReg(SrcReg)
7331 .add(Base)
7332 .addImm(Disp)
7333 .addReg(IndexReg)
7334 .addMemOperand(MMO);
7335 MBB->addSuccessor(JoinMBB);
7336
7337 MI.eraseFromParent();
7338 return JoinMBB;
7339 }
7340
7341 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
7342 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
7343 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
7344 // BitSize is the width of the field in bits, or 0 if this is a partword
7345 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
7346 // is one of the operands. Invert says whether the field should be
7347 // inverted after performing BinOpcode (e.g. for NAND).
emitAtomicLoadBinary(MachineInstr & MI,MachineBasicBlock * MBB,unsigned BinOpcode,unsigned BitSize,bool Invert) const7348 MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
7349 MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode,
7350 unsigned BitSize, bool Invert) const {
7351 MachineFunction &MF = *MBB->getParent();
7352 const SystemZInstrInfo *TII =
7353 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7354 MachineRegisterInfo &MRI = MF.getRegInfo();
7355 bool IsSubWord = (BitSize < 32);
7356
7357 // Extract the operands. Base can be a register or a frame index.
7358 // Src2 can be a register or immediate.
7359 Register Dest = MI.getOperand(0).getReg();
7360 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
7361 int64_t Disp = MI.getOperand(2).getImm();
7362 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
7363 Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register();
7364 Register NegBitShift = IsSubWord ? MI.getOperand(5).getReg() : Register();
7365 DebugLoc DL = MI.getDebugLoc();
7366 if (IsSubWord)
7367 BitSize = MI.getOperand(6).getImm();
7368
7369 // Subword operations use 32-bit registers.
7370 const TargetRegisterClass *RC = (BitSize <= 32 ?
7371 &SystemZ::GR32BitRegClass :
7372 &SystemZ::GR64BitRegClass);
7373 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
7374 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
7375
7376 // Get the right opcodes for the displacement.
7377 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
7378 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
7379 assert(LOpcode && CSOpcode && "Displacement out of range");
7380
7381 // Create virtual registers for temporary results.
7382 Register OrigVal = MRI.createVirtualRegister(RC);
7383 Register OldVal = MRI.createVirtualRegister(RC);
7384 Register NewVal = (BinOpcode || IsSubWord ?
7385 MRI.createVirtualRegister(RC) : Src2.getReg());
7386 Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
7387 Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
7388
7389 // Insert a basic block for the main loop.
7390 MachineBasicBlock *StartMBB = MBB;
7391 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
7392 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(StartMBB);
7393
7394 // StartMBB:
7395 // ...
7396 // %OrigVal = L Disp(%Base)
7397 // # fall through to LoopMMB
7398 MBB = StartMBB;
7399 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
7400 MBB->addSuccessor(LoopMBB);
7401
7402 // LoopMBB:
7403 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
7404 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
7405 // %RotatedNewVal = OP %RotatedOldVal, %Src2
7406 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
7407 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
7408 // JNE LoopMBB
7409 // # fall through to DoneMMB
7410 MBB = LoopMBB;
7411 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
7412 .addReg(OrigVal).addMBB(StartMBB)
7413 .addReg(Dest).addMBB(LoopMBB);
7414 if (IsSubWord)
7415 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
7416 .addReg(OldVal).addReg(BitShift).addImm(0);
7417 if (Invert) {
7418 // Perform the operation normally and then invert every bit of the field.
7419 Register Tmp = MRI.createVirtualRegister(RC);
7420 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
7421 if (BitSize <= 32)
7422 // XILF with the upper BitSize bits set.
7423 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
7424 .addReg(Tmp).addImm(-1U << (32 - BitSize));
7425 else {
7426 // Use LCGR and add -1 to the result, which is more compact than
7427 // an XILF, XILH pair.
7428 Register Tmp2 = MRI.createVirtualRegister(RC);
7429 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
7430 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
7431 .addReg(Tmp2).addImm(-1);
7432 }
7433 } else if (BinOpcode)
7434 // A simply binary operation.
7435 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
7436 .addReg(RotatedOldVal)
7437 .add(Src2);
7438 else if (IsSubWord)
7439 // Use RISBG to rotate Src2 into position and use it to replace the
7440 // field in RotatedOldVal.
7441 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
7442 .addReg(RotatedOldVal).addReg(Src2.getReg())
7443 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
7444 if (IsSubWord)
7445 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
7446 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
7447 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
7448 .addReg(OldVal)
7449 .addReg(NewVal)
7450 .add(Base)
7451 .addImm(Disp);
7452 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7453 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7454 MBB->addSuccessor(LoopMBB);
7455 MBB->addSuccessor(DoneMBB);
7456
7457 MI.eraseFromParent();
7458 return DoneMBB;
7459 }
7460
7461 // Implement EmitInstrWithCustomInserter for pseudo
7462 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
7463 // instruction that should be used to compare the current field with the
7464 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
7465 // for when the current field should be kept. BitSize is the width of
7466 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
emitAtomicLoadMinMax(MachineInstr & MI,MachineBasicBlock * MBB,unsigned CompareOpcode,unsigned KeepOldMask,unsigned BitSize) const7467 MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
7468 MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode,
7469 unsigned KeepOldMask, unsigned BitSize) const {
7470 MachineFunction &MF = *MBB->getParent();
7471 const SystemZInstrInfo *TII =
7472 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7473 MachineRegisterInfo &MRI = MF.getRegInfo();
7474 bool IsSubWord = (BitSize < 32);
7475
7476 // Extract the operands. Base can be a register or a frame index.
7477 Register Dest = MI.getOperand(0).getReg();
7478 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
7479 int64_t Disp = MI.getOperand(2).getImm();
7480 Register Src2 = MI.getOperand(3).getReg();
7481 Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register());
7482 Register NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : Register());
7483 DebugLoc DL = MI.getDebugLoc();
7484 if (IsSubWord)
7485 BitSize = MI.getOperand(6).getImm();
7486
7487 // Subword operations use 32-bit registers.
7488 const TargetRegisterClass *RC = (BitSize <= 32 ?
7489 &SystemZ::GR32BitRegClass :
7490 &SystemZ::GR64BitRegClass);
7491 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
7492 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
7493
7494 // Get the right opcodes for the displacement.
7495 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
7496 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
7497 assert(LOpcode && CSOpcode && "Displacement out of range");
7498
7499 // Create virtual registers for temporary results.
7500 Register OrigVal = MRI.createVirtualRegister(RC);
7501 Register OldVal = MRI.createVirtualRegister(RC);
7502 Register NewVal = MRI.createVirtualRegister(RC);
7503 Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
7504 Register RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
7505 Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
7506
7507 // Insert 3 basic blocks for the loop.
7508 MachineBasicBlock *StartMBB = MBB;
7509 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
7510 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(StartMBB);
7511 MachineBasicBlock *UseAltMBB = SystemZ::emitBlockAfter(LoopMBB);
7512 MachineBasicBlock *UpdateMBB = SystemZ::emitBlockAfter(UseAltMBB);
7513
7514 // StartMBB:
7515 // ...
7516 // %OrigVal = L Disp(%Base)
7517 // # fall through to LoopMMB
7518 MBB = StartMBB;
7519 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
7520 MBB->addSuccessor(LoopMBB);
7521
7522 // LoopMBB:
7523 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
7524 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
7525 // CompareOpcode %RotatedOldVal, %Src2
7526 // BRC KeepOldMask, UpdateMBB
7527 MBB = LoopMBB;
7528 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
7529 .addReg(OrigVal).addMBB(StartMBB)
7530 .addReg(Dest).addMBB(UpdateMBB);
7531 if (IsSubWord)
7532 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
7533 .addReg(OldVal).addReg(BitShift).addImm(0);
7534 BuildMI(MBB, DL, TII->get(CompareOpcode))
7535 .addReg(RotatedOldVal).addReg(Src2);
7536 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7537 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
7538 MBB->addSuccessor(UpdateMBB);
7539 MBB->addSuccessor(UseAltMBB);
7540
7541 // UseAltMBB:
7542 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
7543 // # fall through to UpdateMMB
7544 MBB = UseAltMBB;
7545 if (IsSubWord)
7546 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
7547 .addReg(RotatedOldVal).addReg(Src2)
7548 .addImm(32).addImm(31 + BitSize).addImm(0);
7549 MBB->addSuccessor(UpdateMBB);
7550
7551 // UpdateMBB:
7552 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
7553 // [ %RotatedAltVal, UseAltMBB ]
7554 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
7555 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
7556 // JNE LoopMBB
7557 // # fall through to DoneMMB
7558 MBB = UpdateMBB;
7559 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
7560 .addReg(RotatedOldVal).addMBB(LoopMBB)
7561 .addReg(RotatedAltVal).addMBB(UseAltMBB);
7562 if (IsSubWord)
7563 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
7564 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
7565 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
7566 .addReg(OldVal)
7567 .addReg(NewVal)
7568 .add(Base)
7569 .addImm(Disp);
7570 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7571 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7572 MBB->addSuccessor(LoopMBB);
7573 MBB->addSuccessor(DoneMBB);
7574
7575 MI.eraseFromParent();
7576 return DoneMBB;
7577 }
7578
7579 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
7580 // instruction MI.
7581 MachineBasicBlock *
emitAtomicCmpSwapW(MachineInstr & MI,MachineBasicBlock * MBB) const7582 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
7583 MachineBasicBlock *MBB) const {
7584
7585 MachineFunction &MF = *MBB->getParent();
7586 const SystemZInstrInfo *TII =
7587 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7588 MachineRegisterInfo &MRI = MF.getRegInfo();
7589
7590 // Extract the operands. Base can be a register or a frame index.
7591 Register Dest = MI.getOperand(0).getReg();
7592 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
7593 int64_t Disp = MI.getOperand(2).getImm();
7594 Register OrigCmpVal = MI.getOperand(3).getReg();
7595 Register OrigSwapVal = MI.getOperand(4).getReg();
7596 Register BitShift = MI.getOperand(5).getReg();
7597 Register NegBitShift = MI.getOperand(6).getReg();
7598 int64_t BitSize = MI.getOperand(7).getImm();
7599 DebugLoc DL = MI.getDebugLoc();
7600
7601 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
7602
7603 // Get the right opcodes for the displacement.
7604 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
7605 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
7606 assert(LOpcode && CSOpcode && "Displacement out of range");
7607
7608 // Create virtual registers for temporary results.
7609 Register OrigOldVal = MRI.createVirtualRegister(RC);
7610 Register OldVal = MRI.createVirtualRegister(RC);
7611 Register CmpVal = MRI.createVirtualRegister(RC);
7612 Register SwapVal = MRI.createVirtualRegister(RC);
7613 Register StoreVal = MRI.createVirtualRegister(RC);
7614 Register RetryOldVal = MRI.createVirtualRegister(RC);
7615 Register RetryCmpVal = MRI.createVirtualRegister(RC);
7616 Register RetrySwapVal = MRI.createVirtualRegister(RC);
7617
7618 // Insert 2 basic blocks for the loop.
7619 MachineBasicBlock *StartMBB = MBB;
7620 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
7621 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(StartMBB);
7622 MachineBasicBlock *SetMBB = SystemZ::emitBlockAfter(LoopMBB);
7623
7624 // StartMBB:
7625 // ...
7626 // %OrigOldVal = L Disp(%Base)
7627 // # fall through to LoopMMB
7628 MBB = StartMBB;
7629 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
7630 .add(Base)
7631 .addImm(Disp)
7632 .addReg(0);
7633 MBB->addSuccessor(LoopMBB);
7634
7635 // LoopMBB:
7636 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
7637 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
7638 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
7639 // %Dest = RLL %OldVal, BitSize(%BitShift)
7640 // ^^ The low BitSize bits contain the field
7641 // of interest.
7642 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
7643 // ^^ Replace the upper 32-BitSize bits of the
7644 // comparison value with those that we loaded,
7645 // so that we can use a full word comparison.
7646 // CR %Dest, %RetryCmpVal
7647 // JNE DoneMBB
7648 // # Fall through to SetMBB
7649 MBB = LoopMBB;
7650 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
7651 .addReg(OrigOldVal).addMBB(StartMBB)
7652 .addReg(RetryOldVal).addMBB(SetMBB);
7653 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
7654 .addReg(OrigCmpVal).addMBB(StartMBB)
7655 .addReg(RetryCmpVal).addMBB(SetMBB);
7656 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
7657 .addReg(OrigSwapVal).addMBB(StartMBB)
7658 .addReg(RetrySwapVal).addMBB(SetMBB);
7659 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
7660 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
7661 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
7662 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7663 BuildMI(MBB, DL, TII->get(SystemZ::CR))
7664 .addReg(Dest).addReg(RetryCmpVal);
7665 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7666 .addImm(SystemZ::CCMASK_ICMP)
7667 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
7668 MBB->addSuccessor(DoneMBB);
7669 MBB->addSuccessor(SetMBB);
7670
7671 // SetMBB:
7672 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
7673 // ^^ Replace the upper 32-BitSize bits of the new
7674 // value with those that we loaded.
7675 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
7676 // ^^ Rotate the new field to its proper position.
7677 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
7678 // JNE LoopMBB
7679 // # fall through to ExitMMB
7680 MBB = SetMBB;
7681 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
7682 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7683 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
7684 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
7685 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
7686 .addReg(OldVal)
7687 .addReg(StoreVal)
7688 .add(Base)
7689 .addImm(Disp);
7690 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7691 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7692 MBB->addSuccessor(LoopMBB);
7693 MBB->addSuccessor(DoneMBB);
7694
7695 // If the CC def wasn't dead in the ATOMIC_CMP_SWAPW, mark CC as live-in
7696 // to the block after the loop. At this point, CC may have been defined
7697 // either by the CR in LoopMBB or by the CS in SetMBB.
7698 if (!MI.registerDefIsDead(SystemZ::CC))
7699 DoneMBB->addLiveIn(SystemZ::CC);
7700
7701 MI.eraseFromParent();
7702 return DoneMBB;
7703 }
7704
7705 // Emit a move from two GR64s to a GR128.
7706 MachineBasicBlock *
emitPair128(MachineInstr & MI,MachineBasicBlock * MBB) const7707 SystemZTargetLowering::emitPair128(MachineInstr &MI,
7708 MachineBasicBlock *MBB) const {
7709 MachineFunction &MF = *MBB->getParent();
7710 const SystemZInstrInfo *TII =
7711 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7712 MachineRegisterInfo &MRI = MF.getRegInfo();
7713 DebugLoc DL = MI.getDebugLoc();
7714
7715 Register Dest = MI.getOperand(0).getReg();
7716 Register Hi = MI.getOperand(1).getReg();
7717 Register Lo = MI.getOperand(2).getReg();
7718 Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7719 Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7720
7721 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1);
7722 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2)
7723 .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
7724 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
7725 .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);
7726
7727 MI.eraseFromParent();
7728 return MBB;
7729 }
7730
7731 // Emit an extension from a GR64 to a GR128. ClearEven is true
7732 // if the high register of the GR128 value must be cleared or false if
7733 // it's "don't care".
emitExt128(MachineInstr & MI,MachineBasicBlock * MBB,bool ClearEven) const7734 MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
7735 MachineBasicBlock *MBB,
7736 bool ClearEven) const {
7737 MachineFunction &MF = *MBB->getParent();
7738 const SystemZInstrInfo *TII =
7739 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7740 MachineRegisterInfo &MRI = MF.getRegInfo();
7741 DebugLoc DL = MI.getDebugLoc();
7742
7743 Register Dest = MI.getOperand(0).getReg();
7744 Register Src = MI.getOperand(1).getReg();
7745 Register In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7746
7747 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
7748 if (ClearEven) {
7749 Register NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7750 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
7751
7752 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
7753 .addImm(0);
7754 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
7755 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
7756 In128 = NewIn128;
7757 }
7758 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
7759 .addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);
7760
7761 MI.eraseFromParent();
7762 return MBB;
7763 }
7764
emitMemMemWrapper(MachineInstr & MI,MachineBasicBlock * MBB,unsigned Opcode) const7765 MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
7766 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
7767 MachineFunction &MF = *MBB->getParent();
7768 const SystemZInstrInfo *TII =
7769 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7770 MachineRegisterInfo &MRI = MF.getRegInfo();
7771 DebugLoc DL = MI.getDebugLoc();
7772
7773 MachineOperand DestBase = earlyUseOperand(MI.getOperand(0));
7774 uint64_t DestDisp = MI.getOperand(1).getImm();
7775 MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2));
7776 uint64_t SrcDisp = MI.getOperand(3).getImm();
7777 uint64_t Length = MI.getOperand(4).getImm();
7778
7779 // When generating more than one CLC, all but the last will need to
7780 // branch to the end when a difference is found.
7781 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
7782 SystemZ::splitBlockAfter(MI, MBB) : nullptr);
7783
7784 // Check for the loop form, in which operand 5 is the trip count.
7785 if (MI.getNumExplicitOperands() > 5) {
7786 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
7787
7788 Register StartCountReg = MI.getOperand(5).getReg();
7789 Register StartSrcReg = forceReg(MI, SrcBase, TII);
7790 Register StartDestReg = (HaveSingleBase ? StartSrcReg :
7791 forceReg(MI, DestBase, TII));
7792
7793 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
7794 Register ThisSrcReg = MRI.createVirtualRegister(RC);
7795 Register ThisDestReg = (HaveSingleBase ? ThisSrcReg :
7796 MRI.createVirtualRegister(RC));
7797 Register NextSrcReg = MRI.createVirtualRegister(RC);
7798 Register NextDestReg = (HaveSingleBase ? NextSrcReg :
7799 MRI.createVirtualRegister(RC));
7800
7801 RC = &SystemZ::GR64BitRegClass;
7802 Register ThisCountReg = MRI.createVirtualRegister(RC);
7803 Register NextCountReg = MRI.createVirtualRegister(RC);
7804
7805 MachineBasicBlock *StartMBB = MBB;
7806 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
7807 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(StartMBB);
7808 MachineBasicBlock *NextMBB =
7809 (EndMBB ? SystemZ::emitBlockAfter(LoopMBB) : LoopMBB);
7810
7811 // StartMBB:
7812 // # fall through to LoopMMB
7813 MBB->addSuccessor(LoopMBB);
7814
7815 // LoopMBB:
7816 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
7817 // [ %NextDestReg, NextMBB ]
7818 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
7819 // [ %NextSrcReg, NextMBB ]
7820 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
7821 // [ %NextCountReg, NextMBB ]
7822 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
7823 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
7824 // ( JLH EndMBB )
7825 //
7826 // The prefetch is used only for MVC. The JLH is used only for CLC.
7827 MBB = LoopMBB;
7828
7829 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
7830 .addReg(StartDestReg).addMBB(StartMBB)
7831 .addReg(NextDestReg).addMBB(NextMBB);
7832 if (!HaveSingleBase)
7833 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
7834 .addReg(StartSrcReg).addMBB(StartMBB)
7835 .addReg(NextSrcReg).addMBB(NextMBB);
7836 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
7837 .addReg(StartCountReg).addMBB(StartMBB)
7838 .addReg(NextCountReg).addMBB(NextMBB);
7839 if (Opcode == SystemZ::MVC)
7840 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
7841 .addImm(SystemZ::PFD_WRITE)
7842 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
7843 BuildMI(MBB, DL, TII->get(Opcode))
7844 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
7845 .addReg(ThisSrcReg).addImm(SrcDisp);
7846 if (EndMBB) {
7847 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7848 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7849 .addMBB(EndMBB);
7850 MBB->addSuccessor(EndMBB);
7851 MBB->addSuccessor(NextMBB);
7852 }
7853
7854 // NextMBB:
7855 // %NextDestReg = LA 256(%ThisDestReg)
7856 // %NextSrcReg = LA 256(%ThisSrcReg)
7857 // %NextCountReg = AGHI %ThisCountReg, -1
7858 // CGHI %NextCountReg, 0
7859 // JLH LoopMBB
7860 // # fall through to DoneMMB
7861 //
7862 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
7863 MBB = NextMBB;
7864
7865 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
7866 .addReg(ThisDestReg).addImm(256).addReg(0);
7867 if (!HaveSingleBase)
7868 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
7869 .addReg(ThisSrcReg).addImm(256).addReg(0);
7870 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
7871 .addReg(ThisCountReg).addImm(-1);
7872 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
7873 .addReg(NextCountReg).addImm(0);
7874 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7875 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7876 .addMBB(LoopMBB);
7877 MBB->addSuccessor(LoopMBB);
7878 MBB->addSuccessor(DoneMBB);
7879
7880 DestBase = MachineOperand::CreateReg(NextDestReg, false);
7881 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
7882 Length &= 255;
7883 if (EndMBB && !Length)
7884 // If the loop handled the whole CLC range, DoneMBB will be empty with
7885 // CC live-through into EndMBB, so add it as live-in.
7886 DoneMBB->addLiveIn(SystemZ::CC);
7887 MBB = DoneMBB;
7888 }
7889 // Handle any remaining bytes with straight-line code.
7890 while (Length > 0) {
7891 uint64_t ThisLength = std::min(Length, uint64_t(256));
7892 // The previous iteration might have created out-of-range displacements.
7893 // Apply them using LAY if so.
7894 if (!isUInt<12>(DestDisp)) {
7895 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7896 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
7897 .add(DestBase)
7898 .addImm(DestDisp)
7899 .addReg(0);
7900 DestBase = MachineOperand::CreateReg(Reg, false);
7901 DestDisp = 0;
7902 }
7903 if (!isUInt<12>(SrcDisp)) {
7904 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7905 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
7906 .add(SrcBase)
7907 .addImm(SrcDisp)
7908 .addReg(0);
7909 SrcBase = MachineOperand::CreateReg(Reg, false);
7910 SrcDisp = 0;
7911 }
7912 BuildMI(*MBB, MI, DL, TII->get(Opcode))
7913 .add(DestBase)
7914 .addImm(DestDisp)
7915 .addImm(ThisLength)
7916 .add(SrcBase)
7917 .addImm(SrcDisp)
7918 .setMemRefs(MI.memoperands());
7919 DestDisp += ThisLength;
7920 SrcDisp += ThisLength;
7921 Length -= ThisLength;
7922 // If there's another CLC to go, branch to the end if a difference
7923 // was found.
7924 if (EndMBB && Length > 0) {
7925 MachineBasicBlock *NextMBB = SystemZ::splitBlockBefore(MI, MBB);
7926 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7927 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7928 .addMBB(EndMBB);
7929 MBB->addSuccessor(EndMBB);
7930 MBB->addSuccessor(NextMBB);
7931 MBB = NextMBB;
7932 }
7933 }
7934 if (EndMBB) {
7935 MBB->addSuccessor(EndMBB);
7936 MBB = EndMBB;
7937 MBB->addLiveIn(SystemZ::CC);
7938 }
7939
7940 MI.eraseFromParent();
7941 return MBB;
7942 }
7943
7944 // Decompose string pseudo-instruction MI into a loop that continually performs
7945 // Opcode until CC != 3.
emitStringWrapper(MachineInstr & MI,MachineBasicBlock * MBB,unsigned Opcode) const7946 MachineBasicBlock *SystemZTargetLowering::emitStringWrapper(
7947 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
7948 MachineFunction &MF = *MBB->getParent();
7949 const SystemZInstrInfo *TII =
7950 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
7951 MachineRegisterInfo &MRI = MF.getRegInfo();
7952 DebugLoc DL = MI.getDebugLoc();
7953
7954 uint64_t End1Reg = MI.getOperand(0).getReg();
7955 uint64_t Start1Reg = MI.getOperand(1).getReg();
7956 uint64_t Start2Reg = MI.getOperand(2).getReg();
7957 uint64_t CharReg = MI.getOperand(3).getReg();
7958
7959 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
7960 uint64_t This1Reg = MRI.createVirtualRegister(RC);
7961 uint64_t This2Reg = MRI.createVirtualRegister(RC);
7962 uint64_t End2Reg = MRI.createVirtualRegister(RC);
7963
7964 MachineBasicBlock *StartMBB = MBB;
7965 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
7966 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(StartMBB);
7967
7968 // StartMBB:
7969 // # fall through to LoopMMB
7970 MBB->addSuccessor(LoopMBB);
7971
7972 // LoopMBB:
7973 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
7974 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
7975 // R0L = %CharReg
7976 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
7977 // JO LoopMBB
7978 // # fall through to DoneMMB
7979 //
7980 // The load of R0L can be hoisted by post-RA LICM.
7981 MBB = LoopMBB;
7982
7983 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
7984 .addReg(Start1Reg).addMBB(StartMBB)
7985 .addReg(End1Reg).addMBB(LoopMBB);
7986 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
7987 .addReg(Start2Reg).addMBB(StartMBB)
7988 .addReg(End2Reg).addMBB(LoopMBB);
7989 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
7990 BuildMI(MBB, DL, TII->get(Opcode))
7991 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
7992 .addReg(This1Reg).addReg(This2Reg);
7993 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7994 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
7995 MBB->addSuccessor(LoopMBB);
7996 MBB->addSuccessor(DoneMBB);
7997
7998 DoneMBB->addLiveIn(SystemZ::CC);
7999
8000 MI.eraseFromParent();
8001 return DoneMBB;
8002 }
8003
8004 // Update TBEGIN instruction with final opcode and register clobbers.
emitTransactionBegin(MachineInstr & MI,MachineBasicBlock * MBB,unsigned Opcode,bool NoFloat) const8005 MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin(
8006 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode,
8007 bool NoFloat) const {
8008 MachineFunction &MF = *MBB->getParent();
8009 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
8010 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
8011
8012 // Update opcode.
8013 MI.setDesc(TII->get(Opcode));
8014
8015 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
8016 // Make sure to add the corresponding GRSM bits if they are missing.
8017 uint64_t Control = MI.getOperand(2).getImm();
8018 static const unsigned GPRControlBit[16] = {
8019 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
8020 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
8021 };
8022 Control |= GPRControlBit[15];
8023 if (TFI->hasFP(MF))
8024 Control |= GPRControlBit[11];
8025 MI.getOperand(2).setImm(Control);
8026
8027 // Add GPR clobbers.
8028 for (int I = 0; I < 16; I++) {
8029 if ((Control & GPRControlBit[I]) == 0) {
8030 unsigned Reg = SystemZMC::GR64Regs[I];
8031 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
8032 }
8033 }
8034
8035 // Add FPR/VR clobbers.
8036 if (!NoFloat && (Control & 4) != 0) {
8037 if (Subtarget.hasVector()) {
8038 for (int I = 0; I < 32; I++) {
8039 unsigned Reg = SystemZMC::VR128Regs[I];
8040 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
8041 }
8042 } else {
8043 for (int I = 0; I < 16; I++) {
8044 unsigned Reg = SystemZMC::FP64Regs[I];
8045 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
8046 }
8047 }
8048 }
8049
8050 return MBB;
8051 }
8052
emitLoadAndTestCmp0(MachineInstr & MI,MachineBasicBlock * MBB,unsigned Opcode) const8053 MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
8054 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
8055 MachineFunction &MF = *MBB->getParent();
8056 MachineRegisterInfo *MRI = &MF.getRegInfo();
8057 const SystemZInstrInfo *TII =
8058 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
8059 DebugLoc DL = MI.getDebugLoc();
8060
8061 Register SrcReg = MI.getOperand(0).getReg();
8062
8063 // Create new virtual register of the same class as source.
8064 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
8065 Register DstReg = MRI->createVirtualRegister(RC);
8066
8067 // Replace pseudo with a normal load-and-test that models the def as
8068 // well.
8069 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
8070 .addReg(SrcReg)
8071 .setMIFlags(MI.getFlags());
8072 MI.eraseFromParent();
8073
8074 return MBB;
8075 }
8076
emitProbedAlloca(MachineInstr & MI,MachineBasicBlock * MBB) const8077 MachineBasicBlock *SystemZTargetLowering::emitProbedAlloca(
8078 MachineInstr &MI, MachineBasicBlock *MBB) const {
8079 MachineFunction &MF = *MBB->getParent();
8080 MachineRegisterInfo *MRI = &MF.getRegInfo();
8081 const SystemZInstrInfo *TII =
8082 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
8083 DebugLoc DL = MI.getDebugLoc();
8084 const unsigned ProbeSize = getStackProbeSize(MF);
8085 Register DstReg = MI.getOperand(0).getReg();
8086 Register SizeReg = MI.getOperand(2).getReg();
8087
8088 MachineBasicBlock *StartMBB = MBB;
8089 MachineBasicBlock *DoneMBB = SystemZ::splitBlockAfter(MI, MBB);
8090 MachineBasicBlock *LoopTestMBB = SystemZ::emitBlockAfter(StartMBB);
8091 MachineBasicBlock *LoopBodyMBB = SystemZ::emitBlockAfter(LoopTestMBB);
8092 MachineBasicBlock *TailTestMBB = SystemZ::emitBlockAfter(LoopBodyMBB);
8093 MachineBasicBlock *TailMBB = SystemZ::emitBlockAfter(TailTestMBB);
8094
8095 MachineMemOperand *VolLdMMO = MF.getMachineMemOperand(MachinePointerInfo(),
8096 MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad, 8, Align(1));
8097
8098 Register PHIReg = MRI->createVirtualRegister(&SystemZ::ADDR64BitRegClass);
8099 Register IncReg = MRI->createVirtualRegister(&SystemZ::ADDR64BitRegClass);
8100
8101 // LoopTestMBB
8102 // BRC TailTestMBB
8103 // # fallthrough to LoopBodyMBB
8104 StartMBB->addSuccessor(LoopTestMBB);
8105 MBB = LoopTestMBB;
8106 BuildMI(MBB, DL, TII->get(SystemZ::PHI), PHIReg)
8107 .addReg(SizeReg)
8108 .addMBB(StartMBB)
8109 .addReg(IncReg)
8110 .addMBB(LoopBodyMBB);
8111 BuildMI(MBB, DL, TII->get(SystemZ::CLGFI))
8112 .addReg(PHIReg)
8113 .addImm(ProbeSize);
8114 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
8115 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_LT)
8116 .addMBB(TailTestMBB);
8117 MBB->addSuccessor(LoopBodyMBB);
8118 MBB->addSuccessor(TailTestMBB);
8119
8120 // LoopBodyMBB: Allocate and probe by means of a volatile compare.
8121 // J LoopTestMBB
8122 MBB = LoopBodyMBB;
8123 BuildMI(MBB, DL, TII->get(SystemZ::SLGFI), IncReg)
8124 .addReg(PHIReg)
8125 .addImm(ProbeSize);
8126 BuildMI(MBB, DL, TII->get(SystemZ::SLGFI), SystemZ::R15D)
8127 .addReg(SystemZ::R15D)
8128 .addImm(ProbeSize);
8129 BuildMI(MBB, DL, TII->get(SystemZ::CG)).addReg(SystemZ::R15D)
8130 .addReg(SystemZ::R15D).addImm(ProbeSize - 8).addReg(0)
8131 .setMemRefs(VolLdMMO);
8132 BuildMI(MBB, DL, TII->get(SystemZ::J)).addMBB(LoopTestMBB);
8133 MBB->addSuccessor(LoopTestMBB);
8134
8135 // TailTestMBB
8136 // BRC DoneMBB
8137 // # fallthrough to TailMBB
8138 MBB = TailTestMBB;
8139 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
8140 .addReg(PHIReg)
8141 .addImm(0);
8142 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
8143 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_EQ)
8144 .addMBB(DoneMBB);
8145 MBB->addSuccessor(TailMBB);
8146 MBB->addSuccessor(DoneMBB);
8147
8148 // TailMBB
8149 // # fallthrough to DoneMBB
8150 MBB = TailMBB;
8151 BuildMI(MBB, DL, TII->get(SystemZ::SLGR), SystemZ::R15D)
8152 .addReg(SystemZ::R15D)
8153 .addReg(PHIReg);
8154 BuildMI(MBB, DL, TII->get(SystemZ::CG)).addReg(SystemZ::R15D)
8155 .addReg(SystemZ::R15D).addImm(-8).addReg(PHIReg)
8156 .setMemRefs(VolLdMMO);
8157 MBB->addSuccessor(DoneMBB);
8158
8159 // DoneMBB
8160 MBB = DoneMBB;
8161 BuildMI(*MBB, MBB->begin(), DL, TII->get(TargetOpcode::COPY), DstReg)
8162 .addReg(SystemZ::R15D);
8163
8164 MI.eraseFromParent();
8165 return DoneMBB;
8166 }
8167
8168 SDValue SystemZTargetLowering::
getBackchainAddress(SDValue SP,SelectionDAG & DAG) const8169 getBackchainAddress(SDValue SP, SelectionDAG &DAG) const {
8170 MachineFunction &MF = DAG.getMachineFunction();
8171 auto *TFL =
8172 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
8173 SDLoc DL(SP);
8174 return DAG.getNode(ISD::ADD, DL, MVT::i64, SP,
8175 DAG.getIntPtrConstant(TFL->getBackchainOffset(MF), DL));
8176 }
8177
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * MBB) const8178 MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
8179 MachineInstr &MI, MachineBasicBlock *MBB) const {
8180 switch (MI.getOpcode()) {
8181 case SystemZ::Select32:
8182 case SystemZ::Select64:
8183 case SystemZ::SelectF32:
8184 case SystemZ::SelectF64:
8185 case SystemZ::SelectF128:
8186 case SystemZ::SelectVR32:
8187 case SystemZ::SelectVR64:
8188 case SystemZ::SelectVR128:
8189 return emitSelect(MI, MBB);
8190
8191 case SystemZ::CondStore8Mux:
8192 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
8193 case SystemZ::CondStore8MuxInv:
8194 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
8195 case SystemZ::CondStore16Mux:
8196 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
8197 case SystemZ::CondStore16MuxInv:
8198 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
8199 case SystemZ::CondStore32Mux:
8200 return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, false);
8201 case SystemZ::CondStore32MuxInv:
8202 return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, true);
8203 case SystemZ::CondStore8:
8204 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
8205 case SystemZ::CondStore8Inv:
8206 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
8207 case SystemZ::CondStore16:
8208 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
8209 case SystemZ::CondStore16Inv:
8210 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
8211 case SystemZ::CondStore32:
8212 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
8213 case SystemZ::CondStore32Inv:
8214 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
8215 case SystemZ::CondStore64:
8216 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
8217 case SystemZ::CondStore64Inv:
8218 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
8219 case SystemZ::CondStoreF32:
8220 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
8221 case SystemZ::CondStoreF32Inv:
8222 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
8223 case SystemZ::CondStoreF64:
8224 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
8225 case SystemZ::CondStoreF64Inv:
8226 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
8227
8228 case SystemZ::PAIR128:
8229 return emitPair128(MI, MBB);
8230 case SystemZ::AEXT128:
8231 return emitExt128(MI, MBB, false);
8232 case SystemZ::ZEXT128:
8233 return emitExt128(MI, MBB, true);
8234
8235 case SystemZ::ATOMIC_SWAPW:
8236 return emitAtomicLoadBinary(MI, MBB, 0, 0);
8237 case SystemZ::ATOMIC_SWAP_32:
8238 return emitAtomicLoadBinary(MI, MBB, 0, 32);
8239 case SystemZ::ATOMIC_SWAP_64:
8240 return emitAtomicLoadBinary(MI, MBB, 0, 64);
8241
8242 case SystemZ::ATOMIC_LOADW_AR:
8243 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
8244 case SystemZ::ATOMIC_LOADW_AFI:
8245 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
8246 case SystemZ::ATOMIC_LOAD_AR:
8247 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
8248 case SystemZ::ATOMIC_LOAD_AHI:
8249 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
8250 case SystemZ::ATOMIC_LOAD_AFI:
8251 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
8252 case SystemZ::ATOMIC_LOAD_AGR:
8253 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
8254 case SystemZ::ATOMIC_LOAD_AGHI:
8255 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
8256 case SystemZ::ATOMIC_LOAD_AGFI:
8257 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
8258
8259 case SystemZ::ATOMIC_LOADW_SR:
8260 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
8261 case SystemZ::ATOMIC_LOAD_SR:
8262 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
8263 case SystemZ::ATOMIC_LOAD_SGR:
8264 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
8265
8266 case SystemZ::ATOMIC_LOADW_NR:
8267 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
8268 case SystemZ::ATOMIC_LOADW_NILH:
8269 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
8270 case SystemZ::ATOMIC_LOAD_NR:
8271 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
8272 case SystemZ::ATOMIC_LOAD_NILL:
8273 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
8274 case SystemZ::ATOMIC_LOAD_NILH:
8275 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
8276 case SystemZ::ATOMIC_LOAD_NILF:
8277 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
8278 case SystemZ::ATOMIC_LOAD_NGR:
8279 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
8280 case SystemZ::ATOMIC_LOAD_NILL64:
8281 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
8282 case SystemZ::ATOMIC_LOAD_NILH64:
8283 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
8284 case SystemZ::ATOMIC_LOAD_NIHL64:
8285 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
8286 case SystemZ::ATOMIC_LOAD_NIHH64:
8287 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
8288 case SystemZ::ATOMIC_LOAD_NILF64:
8289 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
8290 case SystemZ::ATOMIC_LOAD_NIHF64:
8291 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
8292
8293 case SystemZ::ATOMIC_LOADW_OR:
8294 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
8295 case SystemZ::ATOMIC_LOADW_OILH:
8296 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
8297 case SystemZ::ATOMIC_LOAD_OR:
8298 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
8299 case SystemZ::ATOMIC_LOAD_OILL:
8300 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
8301 case SystemZ::ATOMIC_LOAD_OILH:
8302 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
8303 case SystemZ::ATOMIC_LOAD_OILF:
8304 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
8305 case SystemZ::ATOMIC_LOAD_OGR:
8306 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
8307 case SystemZ::ATOMIC_LOAD_OILL64:
8308 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
8309 case SystemZ::ATOMIC_LOAD_OILH64:
8310 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
8311 case SystemZ::ATOMIC_LOAD_OIHL64:
8312 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
8313 case SystemZ::ATOMIC_LOAD_OIHH64:
8314 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
8315 case SystemZ::ATOMIC_LOAD_OILF64:
8316 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
8317 case SystemZ::ATOMIC_LOAD_OIHF64:
8318 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
8319
8320 case SystemZ::ATOMIC_LOADW_XR:
8321 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
8322 case SystemZ::ATOMIC_LOADW_XILF:
8323 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
8324 case SystemZ::ATOMIC_LOAD_XR:
8325 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
8326 case SystemZ::ATOMIC_LOAD_XILF:
8327 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
8328 case SystemZ::ATOMIC_LOAD_XGR:
8329 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
8330 case SystemZ::ATOMIC_LOAD_XILF64:
8331 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
8332 case SystemZ::ATOMIC_LOAD_XIHF64:
8333 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
8334
8335 case SystemZ::ATOMIC_LOADW_NRi:
8336 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
8337 case SystemZ::ATOMIC_LOADW_NILHi:
8338 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
8339 case SystemZ::ATOMIC_LOAD_NRi:
8340 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
8341 case SystemZ::ATOMIC_LOAD_NILLi:
8342 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
8343 case SystemZ::ATOMIC_LOAD_NILHi:
8344 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
8345 case SystemZ::ATOMIC_LOAD_NILFi:
8346 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
8347 case SystemZ::ATOMIC_LOAD_NGRi:
8348 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
8349 case SystemZ::ATOMIC_LOAD_NILL64i:
8350 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
8351 case SystemZ::ATOMIC_LOAD_NILH64i:
8352 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
8353 case SystemZ::ATOMIC_LOAD_NIHL64i:
8354 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
8355 case SystemZ::ATOMIC_LOAD_NIHH64i:
8356 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
8357 case SystemZ::ATOMIC_LOAD_NILF64i:
8358 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
8359 case SystemZ::ATOMIC_LOAD_NIHF64i:
8360 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
8361
8362 case SystemZ::ATOMIC_LOADW_MIN:
8363 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
8364 SystemZ::CCMASK_CMP_LE, 0);
8365 case SystemZ::ATOMIC_LOAD_MIN_32:
8366 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
8367 SystemZ::CCMASK_CMP_LE, 32);
8368 case SystemZ::ATOMIC_LOAD_MIN_64:
8369 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
8370 SystemZ::CCMASK_CMP_LE, 64);
8371
8372 case SystemZ::ATOMIC_LOADW_MAX:
8373 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
8374 SystemZ::CCMASK_CMP_GE, 0);
8375 case SystemZ::ATOMIC_LOAD_MAX_32:
8376 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
8377 SystemZ::CCMASK_CMP_GE, 32);
8378 case SystemZ::ATOMIC_LOAD_MAX_64:
8379 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
8380 SystemZ::CCMASK_CMP_GE, 64);
8381
8382 case SystemZ::ATOMIC_LOADW_UMIN:
8383 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
8384 SystemZ::CCMASK_CMP_LE, 0);
8385 case SystemZ::ATOMIC_LOAD_UMIN_32:
8386 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
8387 SystemZ::CCMASK_CMP_LE, 32);
8388 case SystemZ::ATOMIC_LOAD_UMIN_64:
8389 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
8390 SystemZ::CCMASK_CMP_LE, 64);
8391
8392 case SystemZ::ATOMIC_LOADW_UMAX:
8393 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
8394 SystemZ::CCMASK_CMP_GE, 0);
8395 case SystemZ::ATOMIC_LOAD_UMAX_32:
8396 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
8397 SystemZ::CCMASK_CMP_GE, 32);
8398 case SystemZ::ATOMIC_LOAD_UMAX_64:
8399 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
8400 SystemZ::CCMASK_CMP_GE, 64);
8401
8402 case SystemZ::ATOMIC_CMP_SWAPW:
8403 return emitAtomicCmpSwapW(MI, MBB);
8404 case SystemZ::MVCSequence:
8405 case SystemZ::MVCLoop:
8406 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
8407 case SystemZ::NCSequence:
8408 case SystemZ::NCLoop:
8409 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
8410 case SystemZ::OCSequence:
8411 case SystemZ::OCLoop:
8412 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
8413 case SystemZ::XCSequence:
8414 case SystemZ::XCLoop:
8415 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
8416 case SystemZ::CLCSequence:
8417 case SystemZ::CLCLoop:
8418 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
8419 case SystemZ::CLSTLoop:
8420 return emitStringWrapper(MI, MBB, SystemZ::CLST);
8421 case SystemZ::MVSTLoop:
8422 return emitStringWrapper(MI, MBB, SystemZ::MVST);
8423 case SystemZ::SRSTLoop:
8424 return emitStringWrapper(MI, MBB, SystemZ::SRST);
8425 case SystemZ::TBEGIN:
8426 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
8427 case SystemZ::TBEGIN_nofloat:
8428 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
8429 case SystemZ::TBEGINC:
8430 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
8431 case SystemZ::LTEBRCompare_VecPseudo:
8432 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTEBR);
8433 case SystemZ::LTDBRCompare_VecPseudo:
8434 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTDBR);
8435 case SystemZ::LTXBRCompare_VecPseudo:
8436 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTXBR);
8437
8438 case SystemZ::PROBED_ALLOCA:
8439 return emitProbedAlloca(MI, MBB);
8440
8441 case TargetOpcode::STACKMAP:
8442 case TargetOpcode::PATCHPOINT:
8443 return emitPatchPoint(MI, MBB);
8444
8445 default:
8446 llvm_unreachable("Unexpected instr type to insert");
8447 }
8448 }
8449
8450 // This is only used by the isel schedulers, and is needed only to prevent
8451 // compiler from crashing when list-ilp is used.
8452 const TargetRegisterClass *
getRepRegClassFor(MVT VT) const8453 SystemZTargetLowering::getRepRegClassFor(MVT VT) const {
8454 if (VT == MVT::Untyped)
8455 return &SystemZ::ADDR128BitRegClass;
8456 return TargetLowering::getRepRegClassFor(VT);
8457 }
8458