1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# WARNING: update_mir_test_checks.py does not include the constant pools output,
3# so this test requires manual fixing up after running the script.
4
5# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
6--- |
7  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
8  target triple = "aarch64"
9
10  define <2 x float> @shuffle_v2f32(<2 x float> %a, <2 x float> %b) {
11    %shuf = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 0>
12    ret <2 x float> %shuf
13  }
14
15  define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
16    %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0>
17    ret <4 x i32> %shuf
18  }
19
20  define <4 x i32> @shuffle_tbl_v4i32(<4 x i32> %a, <4 x i32> %b) {
21    %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 7, i32 1, i32 0>
22    ret <4 x i32> %shuf
23  }
24
25  define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) {
26    %shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer
27    ret <2 x i64> %shuf
28  }
29
30...
31---
32name:            shuffle_v2f32
33alignment:       4
34legalized:       true
35regBankSelected: true
36tracksRegLiveness: true
37body:             |
38  bb.1 (%ir-block.0):
39    liveins: $d0, $d1
40
41    ; CHECK-LABEL: name: shuffle_v2f32
42    ; CHECK: constants:
43    ; CHECK:  - id:              0
44    ; CHECK:    value:           '<8 x i8> <i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
45    ; CHECK:    alignment:       8
46    ; CHECK: liveins: $d0, $d1
47    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
48    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
49    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
50    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
51    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
52    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
53    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
54    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
55    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
56    ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
57    ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub
58    ; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]]
59    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
60    ; CHECK: $d0 = COPY [[COPY2]]
61    ; CHECK: RET_ReallyLR implicit $d0
62    %0:fpr(<2 x s32>) = COPY $d0
63    %1:fpr(<2 x s32>) = COPY $d1
64    %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0)
65    $d0 = COPY %2(<2 x s32>)
66    RET_ReallyLR implicit $d0
67
68...
69---
70name:            shuffle_v4i32
71alignment:       4
72legalized:       true
73regBankSelected: true
74tracksRegLiveness: true
75body:             |
76  bb.1 (%ir-block.0):
77    liveins: $q0, $q1
78
79    ; CHECK-LABEL: name: shuffle_v4i32
80    ; CHECK: constants:
81    ; CHECK: value:           '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'
82    ; CHECK: alignment:       16
83    ; CHECK: isTargetSpecific: false
84    ; CHECK: liveins: $q0, $q1
85    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
86    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
87    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
88    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
89    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
90    ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
91    ; CHECK: $q0 = COPY [[TBLv16i8Two]]
92    ; CHECK: RET_ReallyLR implicit $q0
93    %0:fpr(<4 x s32>) = COPY $q0
94    %1:fpr(<4 x s32>) = COPY $q1
95    %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0)
96    $q0 = COPY %2(<4 x s32>)
97    RET_ReallyLR implicit $q0
98
99...
100---
101name:            shuffle_tbl_v4i32
102alignment:       4
103legalized:       true
104regBankSelected: true
105tracksRegLiveness: true
106body:             |
107  bb.1 (%ir-block.0):
108    liveins: $q0, $q1
109
110    ; CHECK-LABEL: name: shuffle_tbl_v4i32
111    ; CHECK: constants:
112    ; CHECK: value:           '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
113    ; CHECK: alignment:       16
114    ; CHECK: isTargetSpecific: false
115    ; CHECK: liveins: $q0, $q1
116    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
117    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
118    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
119    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
120    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
121    ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
122    ; CHECK: $q0 = COPY [[TBLv16i8Two]]
123    ; CHECK: RET_ReallyLR implicit $q0
124    %0:fpr(<4 x s32>) = COPY $q0
125    %1:fpr(<4 x s32>) = COPY $q1
126    %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0)
127    $q0 = COPY %2(<4 x s32>)
128    RET_ReallyLR implicit $q0
129
130...
131---
132name:            shuffle_v2i64
133alignment:       4
134legalized:       true
135regBankSelected: true
136tracksRegLiveness: true
137body:             |
138  bb.1 (%ir-block.0):
139    liveins: $q0, $q1
140
141    ; CHECK-LABEL: name: shuffle_v2i64
142    ; CHECK: constants:
143    ; CHECK: value:           '<16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'
144    ; CHECK: alignment:       16
145    ; CHECK: isTargetSpecific: false
146    ; CHECK: liveins: $q0, $q1
147    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
148    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
149    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
150    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
151    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
152    ; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
153    ; CHECK: $q0 = COPY [[TBLv16i8Two]]
154    ; CHECK: RET_ReallyLR implicit $q0
155    %0:fpr(<2 x s64>) = COPY $q0
156    %1:fpr(<2 x s64>) = COPY $q1
157    %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 0)
158    $q0 = COPY %2(<2 x s64>)
159    RET_ReallyLR implicit $q0
160
161...
162