1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
4define <4 x i32> @test_signext_vector_inreg(<4 x i16> %n) {
5; CHECK-P9-LABEL: test_signext_vector_inreg:
6; CHECK-P9:       # %bb.0: # %entry
7; CHECK-P9-NEXT:    vmrglh 2, 2, 2
8; CHECK-P9-NEXT:    vextsh2w 2, 2
9; CHECK-P9-NEXT:    blr
10;
11; CHECK-P8-LABEL: test_signext_vector_inreg:
12; CHECK-P8:       # %bb.0: # %entry
13; CHECK-P8-NEXT:    vmrglh 2, 2, 2
14; CHECK-P8-NEXT:    vspltisw 3, 8
15; CHECK-P8-NEXT:    vadduwm 3, 3, 3
16; CHECK-P8-NEXT:    vslw 2, 2, 3
17; CHECK-P8-NEXT:    vsraw 2, 2, 3
18; CHECK-P8-NEXT:    blr
19entry:
20  %0 = sext <4 x i16> %n to <4 x i32>
21  ret <4 x i32> %0
22}
23