1; Test vector intrinsics added with z15. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s 4 5declare <16 x i8> @llvm.s390.vsld(<16 x i8>, <16 x i8>, i32) 6declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32) 7 8declare {<16 x i8>, i32} @llvm.s390.vstrsb(<16 x i8>, <16 x i8>, <16 x i8>) 9declare {<16 x i8>, i32} @llvm.s390.vstrsh(<8 x i16>, <8 x i16>, <16 x i8>) 10declare {<16 x i8>, i32} @llvm.s390.vstrsf(<4 x i32>, <4 x i32>, <16 x i8>) 11declare {<16 x i8>, i32} @llvm.s390.vstrszb(<16 x i8>, <16 x i8>, <16 x i8>) 12declare {<16 x i8>, i32} @llvm.s390.vstrszh(<8 x i16>, <8 x i16>, <16 x i8>) 13declare {<16 x i8>, i32} @llvm.s390.vstrszf(<4 x i32>, <4 x i32>, <16 x i8>) 14 15 16; VSLD with the minimum useful value. 17define <16 x i8> @test_vsld_1(<16 x i8> %a, <16 x i8> %b) { 18; CHECK-LABEL: test_vsld_1: 19; CHECK: vsld %v24, %v24, %v26, 1 20; CHECK: br %r14 21 %res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 1) 22 ret <16 x i8> %res 23} 24 25; VSLD with the maximum value. 26define <16 x i8> @test_vsld_7(<16 x i8> %a, <16 x i8> %b) { 27; CHECK-LABEL: test_vsld_7: 28; CHECK: vsld %v24, %v24, %v26, 7 29; CHECK: br %r14 30 %res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 7) 31 ret <16 x i8> %res 32} 33 34; VSRD with the minimum useful value. 35define <16 x i8> @test_vsrd_1(<16 x i8> %a, <16 x i8> %b) { 36; CHECK-LABEL: test_vsrd_1: 37; CHECK: vsrd %v24, %v24, %v26, 1 38; CHECK: br %r14 39 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 1) 40 ret <16 x i8> %res 41} 42 43; VSRD with the maximum value. 44define <16 x i8> @test_vsrd_7(<16 x i8> %a, <16 x i8> %b) { 45; CHECK-LABEL: test_vsrd_7: 46; CHECK: vsrd %v24, %v24, %v26, 7 47; CHECK: br %r14 48 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 7) 49 ret <16 x i8> %res 50} 51 52 53; VSTRSB. 54define <16 x i8> @test_vstrsb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, 55 i32 *%ccptr) { 56; CHECK-LABEL: test_vstrsb: 57; CHECK: vstrsb %v24, %v24, %v26, %v28, 0 58; CHECK: ipm [[REG:%r[0-5]]] 59; CHECK: srl [[REG]], 28 60; CHECK: st [[REG]], 0(%r2) 61; CHECK: br %r14 62 %call = call {<16 x i8>, i32} @llvm.s390.vstrsb(<16 x i8> %a, <16 x i8> %b, 63 <16 x i8> %c) 64 %res = extractvalue {<16 x i8>, i32} %call, 0 65 %cc = extractvalue {<16 x i8>, i32} %call, 1 66 store i32 %cc, i32 *%ccptr 67 ret <16 x i8> %res 68} 69 70; VSTRSH. 71define <16 x i8> @test_vstrsh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c, 72 i32 *%ccptr) { 73; CHECK-LABEL: test_vstrsh: 74; CHECK: vstrsh %v24, %v24, %v26, %v28, 0 75; CHECK: ipm [[REG:%r[0-5]]] 76; CHECK: srl [[REG]], 28 77; CHECK: st [[REG]], 0(%r2) 78; CHECK: br %r14 79 %call = call {<16 x i8>, i32} @llvm.s390.vstrsh(<8 x i16> %a, <8 x i16> %b, 80 <16 x i8> %c) 81 %res = extractvalue {<16 x i8>, i32} %call, 0 82 %cc = extractvalue {<16 x i8>, i32} %call, 1 83 store i32 %cc, i32 *%ccptr 84 ret <16 x i8> %res 85} 86 87; VSTRSFS. 88define <16 x i8> @test_vstrsf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c, 89 i32 *%ccptr) { 90; CHECK-LABEL: test_vstrsf: 91; CHECK: vstrsf %v24, %v24, %v26, %v28, 0 92; CHECK: ipm [[REG:%r[0-5]]] 93; CHECK: srl [[REG]], 28 94; CHECK: st [[REG]], 0(%r2) 95; CHECK: br %r14 96 %call = call {<16 x i8>, i32} @llvm.s390.vstrsf(<4 x i32> %a, <4 x i32> %b, 97 <16 x i8> %c) 98 %res = extractvalue {<16 x i8>, i32} %call, 0 99 %cc = extractvalue {<16 x i8>, i32} %call, 1 100 store i32 %cc, i32 *%ccptr 101 ret <16 x i8> %res 102} 103 104; VSTRSZB. 105define <16 x i8> @test_vstrszb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, 106 i32 *%ccptr) { 107; CHECK-LABEL: test_vstrszb: 108; CHECK: vstrszb %v24, %v24, %v26, %v28 109; CHECK: ipm [[REG:%r[0-5]]] 110; CHECK: srl [[REG]], 28 111; CHECK: st [[REG]], 0(%r2) 112; CHECK: br %r14 113 %call = call {<16 x i8>, i32} @llvm.s390.vstrszb(<16 x i8> %a, <16 x i8> %b, 114 <16 x i8> %c) 115 %res = extractvalue {<16 x i8>, i32} %call, 0 116 %cc = extractvalue {<16 x i8>, i32} %call, 1 117 store i32 %cc, i32 *%ccptr 118 ret <16 x i8> %res 119} 120 121; VSTRSZH. 122define <16 x i8> @test_vstrszh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c, 123 i32 *%ccptr) { 124; CHECK-LABEL: test_vstrszh: 125; CHECK: vstrszh %v24, %v24, %v26, %v28 126; CHECK: ipm [[REG:%r[0-5]]] 127; CHECK: srl [[REG]], 28 128; CHECK: st [[REG]], 0(%r2) 129; CHECK: br %r14 130 %call = call {<16 x i8>, i32} @llvm.s390.vstrszh(<8 x i16> %a, <8 x i16> %b, 131 <16 x i8> %c) 132 %res = extractvalue {<16 x i8>, i32} %call, 0 133 %cc = extractvalue {<16 x i8>, i32} %call, 1 134 store i32 %cc, i32 *%ccptr 135 ret <16 x i8> %res 136} 137 138; VSTRSZF. 139define <16 x i8> @test_vstrszf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c, 140 i32 *%ccptr) { 141; CHECK-LABEL: test_vstrszf: 142; CHECK: vstrszf %v24, %v24, %v26, %v28 143; CHECK: ipm [[REG:%r[0-5]]] 144; CHECK: srl [[REG]], 28 145; CHECK: st [[REG]], 0(%r2) 146; CHECK: br %r14 147 %call = call {<16 x i8>, i32} @llvm.s390.vstrszf(<4 x i32> %a, <4 x i32> %b, 148 <16 x i8> %c) 149 %res = extractvalue {<16 x i8>, i32} %call, 0 150 %cc = extractvalue {<16 x i8>, i32} %call, 1 151 store i32 %cc, i32 *%ccptr 152 ret <16 x i8> %res 153} 154 155