1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
4 // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
5
6 #include <riscv_vector.h>
7
8 //
9 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1(
10 // CHECK-RV64-NEXT: entry:
11 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
12 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
13 //
test_vfwredsum_vs_f32mf2_f64m1(vfloat64m1_t dst,vfloat32mf2_t vector,vfloat64m1_t scalar,size_t vl)14 vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1(vfloat64m1_t dst,
15 vfloat32mf2_t vector,
16 vfloat64m1_t scalar, size_t vl) {
17 return vfwredsum_vs_f32mf2_f64m1(dst, vector, scalar, vl);
18 }
19
20 //
21 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1(
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
24 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
25 //
test_vfwredsum_vs_f32m1_f64m1(vfloat64m1_t dst,vfloat32m1_t vector,vfloat64m1_t scalar,size_t vl)26 vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1(vfloat64m1_t dst,
27 vfloat32m1_t vector,
28 vfloat64m1_t scalar, size_t vl) {
29 return vfwredsum_vs_f32m1_f64m1(dst, vector, scalar, vl);
30 }
31
32 //
33 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1(
34 // CHECK-RV64-NEXT: entry:
35 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
36 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
37 //
test_vfwredsum_vs_f32m2_f64m1(vfloat64m1_t dst,vfloat32m2_t vector,vfloat64m1_t scalar,size_t vl)38 vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1(vfloat64m1_t dst,
39 vfloat32m2_t vector,
40 vfloat64m1_t scalar, size_t vl) {
41 return vfwredsum_vs_f32m2_f64m1(dst, vector, scalar, vl);
42 }
43
44 //
45 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1(
46 // CHECK-RV64-NEXT: entry:
47 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
48 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
49 //
test_vfwredsum_vs_f32m4_f64m1(vfloat64m1_t dst,vfloat32m4_t vector,vfloat64m1_t scalar,size_t vl)50 vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1(vfloat64m1_t dst,
51 vfloat32m4_t vector,
52 vfloat64m1_t scalar, size_t vl) {
53 return vfwredsum_vs_f32m4_f64m1(dst, vector, scalar, vl);
54 }
55
56 //
57 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1(
58 // CHECK-RV64-NEXT: entry:
59 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
60 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
61 //
test_vfwredsum_vs_f32m8_f64m1(vfloat64m1_t dst,vfloat32m8_t vector,vfloat64m1_t scalar,size_t vl)62 vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1(vfloat64m1_t dst,
63 vfloat32m8_t vector,
64 vfloat64m1_t scalar, size_t vl) {
65 return vfwredsum_vs_f32m8_f64m1(dst, vector, scalar, vl);
66 }
67
68 //
69 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1_m(
70 // CHECK-RV64-NEXT: entry:
71 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
72 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
73 //
test_vfwredsum_vs_f32mf2_f64m1_m(vbool64_t mask,vfloat64m1_t dst,vfloat32mf2_t vector,vfloat64m1_t scalar,size_t vl)74 vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
75 vfloat32mf2_t vector,
76 vfloat64m1_t scalar, size_t vl) {
77 return vfwredsum_vs_f32mf2_f64m1_m(mask, dst, vector, scalar, vl);
78 }
79
80 //
81 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1_m(
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
84 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
85 //
test_vfwredsum_vs_f32m1_f64m1_m(vbool32_t mask,vfloat64m1_t dst,vfloat32m1_t vector,vfloat64m1_t scalar,size_t vl)86 vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst,
87 vfloat32m1_t vector,
88 vfloat64m1_t scalar, size_t vl) {
89 return vfwredsum_vs_f32m1_f64m1_m(mask, dst, vector, scalar, vl);
90 }
91
92 //
93 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1_m(
94 // CHECK-RV64-NEXT: entry:
95 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
96 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
97 //
test_vfwredsum_vs_f32m2_f64m1_m(vbool16_t mask,vfloat64m1_t dst,vfloat32m2_t vector,vfloat64m1_t scalar,size_t vl)98 vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst,
99 vfloat32m2_t vector,
100 vfloat64m1_t scalar, size_t vl) {
101 return vfwredsum_vs_f32m2_f64m1_m(mask, dst, vector, scalar, vl);
102 }
103
104 //
105 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1_m(
106 // CHECK-RV64-NEXT: entry:
107 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
108 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
109 //
test_vfwredsum_vs_f32m4_f64m1_m(vbool8_t mask,vfloat64m1_t dst,vfloat32m4_t vector,vfloat64m1_t scalar,size_t vl)110 vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
111 vfloat32m4_t vector,
112 vfloat64m1_t scalar, size_t vl) {
113 return vfwredsum_vs_f32m4_f64m1_m(mask, dst, vector, scalar, vl);
114 }
115
116 //
117 // CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1_m(
118 // CHECK-RV64-NEXT: entry:
119 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
120 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
121 //
test_vfwredsum_vs_f32m8_f64m1_m(vbool4_t mask,vfloat64m1_t dst,vfloat32m8_t vector,vfloat64m1_t scalar,size_t vl)122 vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst,
123 vfloat32m8_t vector,
124 vfloat64m1_t scalar, size_t vl) {
125 return vfwredsum_vs_f32m8_f64m1_m(mask, dst, vector, scalar, vl);
126 }
127