1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
9
10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
16
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
26
27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
35
36 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
37 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
38 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18
39 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
41 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20
42
43 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
44 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
46 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
47 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
49
50 // Test target codegen - host bc file has to be created first.
51 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25
53 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
54 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26
55 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27
57 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
58 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28
59
60 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
64 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
66 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
68
69 // expected-no-diagnostics
70 #ifndef HEADER
71 #define HEADER
72
73
74
75
76 // We have 8 target regions, but only 6 that actually will generate offloading
77 // code and have mapped arguments, and only 4 have all-constant map sizes.
78
79
80
81 // Check target registration is registered as a Ctor.
82
83
84 template<typename tx, typename ty>
85 struct TT{
86 tx X;
87 ty Y;
88 };
89
90 int global;
91
foo(int n)92 int foo(int n) {
93 int a = 0;
94 short aa = 0;
95 float b[10];
96 float bn[n];
97 double c[5][10];
98 double cn[5][n];
99 TT<long long, char> d;
100
101 #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait
102 {
103 }
104
105 #pragma omp target teams if(target: 0)
106 {
107 a += 1;
108 }
109
110
111 #pragma omp target teams if(target: 1)
112 {
113 aa += 1;
114 }
115
116
117
118 #pragma omp target teams if(target: n>10)
119 {
120 a += 1;
121 aa += 1;
122 }
123
124 // We capture 3 VLA sizes in this target region
125
126
127
128
129
130 // The names below are not necessarily consistent with the names used for the
131 // addresses above as some are repeated.
132
133
134
135
136
137
138
139
140
141
142 #pragma omp target teams if(target: n>20)
143 {
144 a += 1;
145 b[2] += 1.0;
146 bn[3] += 1.0;
147 c[1][2] += 1.0;
148 cn[1][3] += 1.0;
149 d.X += 1;
150 d.Y += 1;
151 }
152
153 const int nn = 0;
154 #pragma omp target teams shared(nn)
155 #pragma omp parallel firstprivate(nn)
156 (void)nn;
157 #pragma omp target teams firstprivate(nn)
158 #pragma omp parallel shared(nn)
159 (void)nn;
160 return a;
161 }
162
163 // Check that the offloading functions are emitted and that the arguments are
164 // correct and loaded correctly for the target regions in foo().
165
166
167
168 // Create stack storage and store argument in there.
169
170 // Create stack storage and store argument in there.
171
172 // Create stack storage and store argument in there.
173
174 // Create local storage for each capture.
175
176
177
178 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
179
180
bazzzz(int n,int f[n])181 void bazzzz(int n, int f[n]) {
182 #pragma omp target teams private(f)
183 ;
184 }
185
186 template<typename tx>
ftemplate(int n)187 tx ftemplate(int n) {
188 tx a = 0;
189 short aa = 0;
190 tx b[10];
191
192 #pragma omp target teams if(target: n>40)
193 {
194 a += 1;
195 aa += 1;
196 b[2] += 1;
197 }
198
199 return a;
200 }
201
202 static
fstatic(int n)203 int fstatic(int n) {
204 int a = 0;
205 short aa = 0;
206 char aaa = 0;
207 int b[10];
208
209 #pragma omp target teams if(target: n>50)
210 {
211 a += 1;
212 aa += 1;
213 aaa += 1;
214 b[2] += 1;
215 }
216
217 return a;
218 }
219
220 struct S1 {
221 double a;
222
r1S1223 int r1(int n){
224 int b = n+1;
225 short int c[2][n];
226
227 #pragma omp target teams if(target: n>60)
228 {
229 this->a = (double)b + 1.5;
230 c[1][1] = ++a;
231 }
232
233 return c[1][1] + (int)b;
234 }
235 };
236
bar(int n)237 int bar(int n){
238 int a = 0;
239
240 a += foo(n);
241
242 S1 S;
243 a += S.r1(n);
244
245 a += fstatic(n);
246
247 a += ftemplate<int>(n);
248
249 return a;
250 }
251
252
253
254 // We capture 2 VLA sizes in this target region
255
256
257 // The names below are not necessarily consistent with the names used for the
258 // addresses above as some are repeated.
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279 // Check that the offloading functions are emitted and that the arguments are
280 // correct and loaded correctly for the target regions of the callees of bar().
281
282 // Create local storage for each capture.
283 // Store captures in the context.
284
285
286 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
287
288
289 // Create local storage for each capture.
290 // Store captures in the context.
291
292
293
294
295 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
296
297 // Create local storage for each capture.
298 // Store captures in the context.
299
300
301
302 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
303
304 #endif
305 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
306 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
307 // CHECK1-NEXT: entry:
308 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
309 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
311 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
312 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
313 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
314 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
315 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
316 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
320 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
321 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
325 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
326 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
327 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8
328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
331 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8
332 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8
333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
336 // CHECK1-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8
337 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8
338 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8
339 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8
340 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
341 // CHECK1-NEXT: [[NN:%.*]] = alloca i32, align 4
342 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8
344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8
345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8
346 // CHECK1-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8
347 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8
348 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8
349 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8
350 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
351 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
352 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
353 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
354 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
355 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
356 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
357 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
358 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
360 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
361 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
362 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
363 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
364 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
365 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
366 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
367 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
368 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
369 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
370 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
371 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
372 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
373 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
374 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
375 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
376 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
377 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
378 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
379 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4
380 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
381 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
382 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
383 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8
384 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
385 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
386 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8
387 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
388 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
389 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
390 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
391 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8
392 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
393 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
394 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8
395 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
396 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8
397 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
398 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
399 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8
400 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
401 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
402 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8
403 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
404 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8
405 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
406 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
407 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
408 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
409 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
410 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
411 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
412 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
413 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
414 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
415 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
416 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
417 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
418 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
419 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
420 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
421 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
422 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
423 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
424 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
425 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
426 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
427 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
428 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
429 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
430 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
431 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
432 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
433 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
434 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
435 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
436 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
437 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
438 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8
439 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]])
440 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
441 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
442 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4
443 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
444 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
445 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
446 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
447 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2
448 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
449 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
450 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
451 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8
452 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
453 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
454 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8
455 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
456 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8
457 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
458 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
459 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
460 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
461 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
462 // CHECK1: omp_offload.failed:
463 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]]
464 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
465 // CHECK1: omp_offload.cont:
466 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4
467 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
468 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4
469 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
470 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
471 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
472 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2
473 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
474 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
475 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
476 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
477 // CHECK1: omp_if.then:
478 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
479 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
480 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8
481 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
482 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
483 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8
484 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
485 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8
486 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
487 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
488 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8
489 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
490 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
491 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8
492 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
493 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8
494 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
495 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
496 // CHECK1-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
497 // CHECK1-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
498 // CHECK1-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
499 // CHECK1: omp_offload.failed19:
500 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
501 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]]
502 // CHECK1: omp_offload.cont20:
503 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
504 // CHECK1: omp_if.else:
505 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
506 // CHECK1-NEXT: br label [[OMP_IF_END]]
507 // CHECK1: omp_if.end:
508 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4
509 // CHECK1-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32*
510 // CHECK1-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4
511 // CHECK1-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8
512 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
513 // CHECK1-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20
514 // CHECK1-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]]
515 // CHECK1: omp_if.then24:
516 // CHECK1-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
517 // CHECK1-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
518 // CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
519 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
520 // CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64*
521 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8
522 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
523 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64*
524 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8
525 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
526 // CHECK1-NEXT: store i64 4, i64* [[TMP99]], align 8
527 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0
528 // CHECK1-NEXT: store i8* null, i8** [[TMP100]], align 8
529 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1
530 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
531 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
532 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1
533 // CHECK1-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
534 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
535 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
536 // CHECK1-NEXT: store i64 40, i64* [[TMP105]], align 8
537 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1
538 // CHECK1-NEXT: store i8* null, i8** [[TMP106]], align 8
539 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2
540 // CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64*
541 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8
542 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2
543 // CHECK1-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64*
544 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8
545 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
546 // CHECK1-NEXT: store i64 8, i64* [[TMP111]], align 8
547 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2
548 // CHECK1-NEXT: store i8* null, i8** [[TMP112]], align 8
549 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3
550 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
551 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP114]], align 8
552 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3
553 // CHECK1-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
554 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP116]], align 8
555 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
556 // CHECK1-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8
557 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3
558 // CHECK1-NEXT: store i8* null, i8** [[TMP118]], align 8
559 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4
560 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
561 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
562 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4
563 // CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
564 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8
565 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
566 // CHECK1-NEXT: store i64 400, i64* [[TMP123]], align 8
567 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4
568 // CHECK1-NEXT: store i8* null, i8** [[TMP124]], align 8
569 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5
570 // CHECK1-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
571 // CHECK1-NEXT: store i64 5, i64* [[TMP126]], align 8
572 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5
573 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
574 // CHECK1-NEXT: store i64 5, i64* [[TMP128]], align 8
575 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
576 // CHECK1-NEXT: store i64 8, i64* [[TMP129]], align 8
577 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5
578 // CHECK1-NEXT: store i8* null, i8** [[TMP130]], align 8
579 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6
580 // CHECK1-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64*
581 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8
582 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6
583 // CHECK1-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64*
584 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8
585 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
586 // CHECK1-NEXT: store i64 8, i64* [[TMP135]], align 8
587 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6
588 // CHECK1-NEXT: store i8* null, i8** [[TMP136]], align 8
589 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7
590 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
591 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8
592 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7
593 // CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
594 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8
595 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
596 // CHECK1-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8
597 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7
598 // CHECK1-NEXT: store i8* null, i8** [[TMP142]], align 8
599 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8
600 // CHECK1-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
601 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8
602 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8
603 // CHECK1-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
604 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8
605 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
606 // CHECK1-NEXT: store i64 16, i64* [[TMP147]], align 8
607 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8
608 // CHECK1-NEXT: store i8* null, i8** [[TMP148]], align 8
609 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
610 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
611 // CHECK1-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
612 // CHECK1-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
613 // CHECK1-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
614 // CHECK1-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]]
615 // CHECK1: omp_offload.failed28:
616 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
617 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT29]]
618 // CHECK1: omp_offload.cont29:
619 // CHECK1-NEXT: br label [[OMP_IF_END31:%.*]]
620 // CHECK1: omp_if.else30:
621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
622 // CHECK1-NEXT: br label [[OMP_IF_END31]]
623 // CHECK1: omp_if.end31:
624 // CHECK1-NEXT: store i32 0, i32* [[NN]], align 4
625 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
626 // CHECK1-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
627 // CHECK1-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4
628 // CHECK1-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8
629 // CHECK1-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
630 // CHECK1-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64*
631 // CHECK1-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8
632 // CHECK1-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
633 // CHECK1-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64*
634 // CHECK1-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8
635 // CHECK1-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0
636 // CHECK1-NEXT: store i8* null, i8** [[TMP160]], align 8
637 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
638 // CHECK1-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
639 // CHECK1-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
640 // CHECK1-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
641 // CHECK1-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
642 // CHECK1: omp_offload.failed36:
643 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]]
644 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT37]]
645 // CHECK1: omp_offload.cont37:
646 // CHECK1-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
647 // CHECK1-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32*
648 // CHECK1-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4
649 // CHECK1-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8
650 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
651 // CHECK1-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64*
652 // CHECK1-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8
653 // CHECK1-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
654 // CHECK1-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64*
655 // CHECK1-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8
656 // CHECK1-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0
657 // CHECK1-NEXT: store i8* null, i8** [[TMP171]], align 8
658 // CHECK1-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
659 // CHECK1-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
660 // CHECK1-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
661 // CHECK1-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
662 // CHECK1-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]]
663 // CHECK1: omp_offload.failed43:
664 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]]
665 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT44]]
666 // CHECK1: omp_offload.cont44:
667 // CHECK1-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
668 // CHECK1-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
669 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
670 // CHECK1-NEXT: ret i32 [[TMP176]]
671 //
672 //
673 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
674 // CHECK1-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
675 // CHECK1-NEXT: entry:
676 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
677 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
678 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
679 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
680 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
681 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
682 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
683 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
684 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
685 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
686 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
687 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
688 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
689 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
690 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
691 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
692 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
693 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
694 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
695 // CHECK1-NEXT: ret void
696 //
697 //
698 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
699 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
700 // CHECK1-NEXT: entry:
701 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
702 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
703 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
704 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
705 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
706 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
707 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
708 // CHECK1-NEXT: ret void
709 //
710 //
711 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
712 // CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
713 // CHECK1-NEXT: entry:
714 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
715 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
716 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
717 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
718 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
719 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
720 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
721 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
722 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
723 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
724 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
725 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
726 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
727 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
728 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
729 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
730 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
731 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
732 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
733 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
734 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
735 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
736 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
737 // CHECK1-NEXT: ret void
738 //
739 //
740 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
741 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
742 // CHECK1-NEXT: entry:
743 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
744 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
745 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
746 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
747 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
748 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
749 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
750 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
751 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
752 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
753 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
754 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
755 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
756 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
757 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
758 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
759 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
760 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
761 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
762 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
763 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
764 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
765 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
766 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
767 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
768 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
769 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
770 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
771 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
772 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
773 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
774 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
775 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
776 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
777 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
778 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
779 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
780 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
781 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
782 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
783 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
784 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
785 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
786 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
787 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
788 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
789 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
790 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
791 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
792 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
793 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
794 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
795 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
796 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
797 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
798 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
799 // CHECK1: omp_offload.failed.i:
800 // CHECK1-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
801 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
802 // CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
803 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
804 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
805 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
806 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
807 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
808 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
809 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
810 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
811 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
812 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
813 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
814 // CHECK1: .omp_outlined..1.exit:
815 // CHECK1-NEXT: ret i32 0
816 //
817 //
818 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
819 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
820 // CHECK1-NEXT: entry:
821 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
822 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
823 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
824 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
825 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
826 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
827 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
828 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
829 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
830 // CHECK1-NEXT: ret void
831 //
832 //
833 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
834 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
835 // CHECK1-NEXT: entry:
836 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
837 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
838 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
839 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
840 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
841 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
842 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
843 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
844 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
845 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
846 // CHECK1-NEXT: ret void
847 //
848 //
849 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
850 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
851 // CHECK1-NEXT: entry:
852 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
853 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
854 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
855 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
856 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
857 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
858 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
859 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
860 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
861 // CHECK1-NEXT: ret void
862 //
863 //
864 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
865 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
866 // CHECK1-NEXT: entry:
867 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
868 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
869 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
870 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
871 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
872 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
873 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
874 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
875 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
876 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
877 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
878 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
879 // CHECK1-NEXT: ret void
880 //
881 //
882 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
883 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
884 // CHECK1-NEXT: entry:
885 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
886 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
887 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
888 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
889 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
890 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
891 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
892 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
893 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
894 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
895 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
896 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
897 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
898 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
899 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
900 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
901 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
902 // CHECK1-NEXT: ret void
903 //
904 //
905 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
906 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
907 // CHECK1-NEXT: entry:
908 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
909 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
910 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
911 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
912 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
913 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
914 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
915 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
916 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
917 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
918 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
919 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
920 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
921 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
922 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
923 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
924 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
925 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
926 // CHECK1-NEXT: ret void
927 //
928 //
929 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
930 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
931 // CHECK1-NEXT: entry:
932 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
933 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
934 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
935 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
936 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
937 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
938 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
939 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
940 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
941 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
942 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
943 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
944 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
945 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
946 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
947 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
948 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
949 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
950 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
951 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
952 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
953 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
954 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
955 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
956 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
957 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
958 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
959 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
960 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
961 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
962 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
963 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
964 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
965 // CHECK1-NEXT: ret void
966 //
967 //
968 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
969 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
970 // CHECK1-NEXT: entry:
971 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
972 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
973 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
974 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
975 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
976 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
977 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
978 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
979 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
980 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
981 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
982 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
983 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
984 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
985 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
986 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
987 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
988 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
989 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
990 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
991 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
992 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
993 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
994 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
995 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
996 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
997 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
998 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
999 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1000 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1001 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1002 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1003 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
1004 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
1005 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1006 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
1007 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
1008 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
1009 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
1010 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
1011 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1012 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
1013 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
1014 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
1015 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
1016 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
1017 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1018 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
1019 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
1020 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
1021 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
1022 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
1023 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
1024 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
1025 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
1026 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
1027 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
1028 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1029 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
1030 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
1031 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
1032 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1033 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
1034 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
1035 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
1036 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
1037 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
1038 // CHECK1-NEXT: ret void
1039 //
1040 //
1041 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
1042 // CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
1043 // CHECK1-NEXT: entry:
1044 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
1045 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
1046 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
1047 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
1048 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1049 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
1050 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
1051 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
1052 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1053 // CHECK1-NEXT: ret void
1054 //
1055 //
1056 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1057 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
1058 // CHECK1-NEXT: entry:
1059 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1060 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1061 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
1063 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1064 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1065 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
1066 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
1067 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1068 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
1069 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
1070 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
1071 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1072 // CHECK1-NEXT: ret void
1073 //
1074 //
1075 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12
1076 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
1077 // CHECK1-NEXT: entry:
1078 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1079 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1080 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
1081 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1082 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1083 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
1084 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
1085 // CHECK1-NEXT: ret void
1086 //
1087 //
1088 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
1089 // CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
1090 // CHECK1-NEXT: entry:
1091 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
1092 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
1093 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
1094 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
1095 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1096 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
1097 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
1098 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
1099 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1100 // CHECK1-NEXT: ret void
1101 //
1102 //
1103 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15
1104 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
1105 // CHECK1-NEXT: entry:
1106 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1107 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1108 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
1109 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1110 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1111 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
1112 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
1113 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]])
1114 // CHECK1-NEXT: ret void
1115 //
1116 //
1117 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
1118 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
1119 // CHECK1-NEXT: entry:
1120 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1121 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1122 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
1123 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1124 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1125 // CHECK1-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
1126 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
1127 // CHECK1-NEXT: ret void
1128 //
1129 //
1130 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi
1131 // CHECK1-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
1132 // CHECK1-NEXT: entry:
1133 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1134 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8
1135 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1136 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1137 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1138 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1139 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8
1140 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1141 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1142 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1143 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
1144 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
1145 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1146 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
1147 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
1148 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1149 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8
1150 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1151 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1152 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1153 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1154 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1155 // CHECK1: omp_offload.failed:
1156 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]]
1157 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1158 // CHECK1: omp_offload.cont:
1159 // CHECK1-NEXT: ret void
1160 //
1161 //
1162 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
1163 // CHECK1-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] {
1164 // CHECK1-NEXT: entry:
1165 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1166 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1167 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1168 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]])
1169 // CHECK1-NEXT: ret void
1170 //
1171 //
1172 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19
1173 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] {
1174 // CHECK1-NEXT: entry:
1175 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1176 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1177 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1178 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8
1179 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1180 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1181 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1182 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1183 // CHECK1-NEXT: ret void
1184 //
1185 //
1186 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1187 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1188 // CHECK1-NEXT: entry:
1189 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1190 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1191 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1192 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1193 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
1194 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1195 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
1196 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1197 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1198 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
1199 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1200 // CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
1201 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1202 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1203 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
1204 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1205 // CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
1206 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1207 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1208 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
1209 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1210 // CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
1211 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1212 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1213 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
1214 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1215 // CHECK1-NEXT: ret i32 [[TMP8]]
1216 //
1217 //
1218 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1219 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1220 // CHECK1-NEXT: entry:
1221 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1222 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1223 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
1224 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
1225 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1226 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1227 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1228 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1229 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1230 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1231 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1232 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1233 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1234 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1235 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1236 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
1237 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1238 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1239 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
1240 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1241 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1242 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1243 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1244 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1245 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1246 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
1247 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1248 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1249 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1250 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1251 // CHECK1: omp_if.then:
1252 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1253 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1254 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1255 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1256 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
1257 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
1258 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1259 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
1260 // CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8
1261 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1262 // CHECK1-NEXT: store i64 8, i64* [[TMP14]], align 8
1263 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1264 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8
1265 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1266 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1267 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
1268 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1269 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1270 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
1271 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1272 // CHECK1-NEXT: store i64 4, i64* [[TMP20]], align 8
1273 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1274 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
1275 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1276 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1277 // CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8
1278 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1279 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1280 // CHECK1-NEXT: store i64 2, i64* [[TMP25]], align 8
1281 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1282 // CHECK1-NEXT: store i64 8, i64* [[TMP26]], align 8
1283 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1284 // CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8
1285 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1286 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1287 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
1288 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1289 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1290 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8
1291 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1292 // CHECK1-NEXT: store i64 8, i64* [[TMP32]], align 8
1293 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1294 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8
1295 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1296 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
1297 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8
1298 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1299 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
1300 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8
1301 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1302 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
1303 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1304 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8
1305 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1306 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1307 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1308 // CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1309 // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
1310 // CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1311 // CHECK1: omp_offload.failed:
1312 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1313 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1314 // CHECK1: omp_offload.cont:
1315 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1316 // CHECK1: omp_if.else:
1317 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1318 // CHECK1-NEXT: br label [[OMP_IF_END]]
1319 // CHECK1: omp_if.end:
1320 // CHECK1-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
1321 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
1322 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1323 // CHECK1-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1324 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
1325 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
1326 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
1327 // CHECK1-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1328 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
1329 // CHECK1-NEXT: ret i32 [[ADD4]]
1330 //
1331 //
1332 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1333 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1334 // CHECK1-NEXT: entry:
1335 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1336 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1337 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
1338 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
1339 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
1340 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1341 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1342 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
1343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1346 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1347 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
1348 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
1349 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1
1350 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1351 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1352 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1353 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1354 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1355 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1356 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
1357 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1358 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
1359 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1360 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
1361 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1362 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1363 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1364 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1365 // CHECK1: omp_if.then:
1366 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1367 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1368 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
1369 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1370 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1371 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
1372 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1373 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
1374 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1375 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1376 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1377 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1378 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1379 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
1380 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1381 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
1382 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1383 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1384 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
1385 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1386 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1387 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
1388 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1389 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
1390 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1391 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
1392 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
1393 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1394 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
1395 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
1396 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1397 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
1398 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1399 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1400 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1401 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1402 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1403 // CHECK1: omp_offload.failed:
1404 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
1405 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1406 // CHECK1: omp_offload.cont:
1407 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1408 // CHECK1: omp_if.else:
1409 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
1410 // CHECK1-NEXT: br label [[OMP_IF_END]]
1411 // CHECK1: omp_if.end:
1412 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
1413 // CHECK1-NEXT: ret i32 [[TMP31]]
1414 //
1415 //
1416 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1417 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
1418 // CHECK1-NEXT: entry:
1419 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1420 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1421 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
1422 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
1423 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1424 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1425 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1426 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1427 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1428 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1429 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
1430 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
1431 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1432 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1433 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1434 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1435 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1436 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1437 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
1438 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1439 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1440 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1441 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1442 // CHECK1: omp_if.then:
1443 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1444 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1445 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
1446 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1447 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1448 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
1449 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1450 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8
1451 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1452 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1453 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
1454 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1455 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1456 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1457 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1458 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8
1459 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1460 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1461 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1462 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1463 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1464 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1465 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1466 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
1467 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1468 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1469 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1470 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1471 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1472 // CHECK1: omp_offload.failed:
1473 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1474 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1475 // CHECK1: omp_offload.cont:
1476 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1477 // CHECK1: omp_if.else:
1478 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1479 // CHECK1-NEXT: br label [[OMP_IF_END]]
1480 // CHECK1: omp_if.end:
1481 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1482 // CHECK1-NEXT: ret i32 [[TMP24]]
1483 //
1484 //
1485 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
1486 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1487 // CHECK1-NEXT: entry:
1488 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1489 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1490 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1491 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1492 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
1493 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1494 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1495 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1496 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1497 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1498 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
1499 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1500 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1501 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1502 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1503 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1504 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1505 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1506 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
1507 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1508 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1509 // CHECK1-NEXT: ret void
1510 //
1511 //
1512 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22
1513 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1514 // CHECK1-NEXT: entry:
1515 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1516 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1517 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1518 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1519 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1520 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1521 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
1522 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1523 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1524 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1525 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1526 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1527 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1528 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
1529 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1530 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1531 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1532 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1533 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1534 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1535 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
1536 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
1537 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1538 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
1539 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1540 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
1541 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
1542 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8
1543 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
1544 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
1545 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
1546 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1547 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
1548 // CHECK1-NEXT: ret void
1549 //
1550 //
1551 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
1552 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1553 // CHECK1-NEXT: entry:
1554 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1555 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1556 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
1557 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1558 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1559 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1560 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
1561 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1562 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1563 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1564 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1565 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1566 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1567 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1568 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1569 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1570 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1571 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
1572 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1573 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1574 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1575 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
1576 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1577 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
1578 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1579 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
1580 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1581 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
1582 // CHECK1-NEXT: ret void
1583 //
1584 //
1585 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24
1586 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1587 // CHECK1-NEXT: entry:
1588 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1589 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1590 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1591 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1592 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
1593 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1594 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1595 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1596 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1597 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1598 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1599 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1600 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1601 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1602 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1603 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1604 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1605 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1606 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
1607 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1608 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
1609 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
1610 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
1611 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
1612 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
1613 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
1614 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
1615 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
1616 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
1617 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1618 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1619 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
1620 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
1621 // CHECK1-NEXT: ret void
1622 //
1623 //
1624 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
1625 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1626 // CHECK1-NEXT: entry:
1627 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1628 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1629 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1630 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1631 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1632 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1633 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1634 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1635 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1636 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1637 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1638 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1639 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1640 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
1641 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1642 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1643 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1644 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
1645 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1646 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1647 // CHECK1-NEXT: ret void
1648 //
1649 //
1650 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..27
1651 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1652 // CHECK1-NEXT: entry:
1653 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1654 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1655 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1656 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1657 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1658 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1659 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1660 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1661 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1662 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1663 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1664 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1665 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1666 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1667 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1668 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
1669 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1670 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1671 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
1672 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1673 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
1674 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1675 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1676 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
1677 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
1678 // CHECK1-NEXT: ret void
1679 //
1680 //
1681 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1682 // CHECK1-SAME: () #[[ATTR4]] {
1683 // CHECK1-NEXT: entry:
1684 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1685 // CHECK1-NEXT: ret void
1686 //
1687 //
1688 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
1689 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
1690 // CHECK2-NEXT: entry:
1691 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1692 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
1693 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
1694 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4
1695 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
1696 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1697 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
1698 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1699 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
1700 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1701 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1702 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1703 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1704 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
1705 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1706 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1707 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1708 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
1709 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1710 // CHECK2-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8
1711 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
1712 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
1713 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
1714 // CHECK2-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8
1715 // CHECK2-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8
1716 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
1717 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
1718 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
1719 // CHECK2-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8
1720 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8
1721 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8
1722 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8
1723 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
1724 // CHECK2-NEXT: [[NN:%.*]] = alloca i32, align 4
1725 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
1726 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8
1727 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8
1728 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8
1729 // CHECK2-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8
1730 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8
1731 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8
1732 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8
1733 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
1734 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1735 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
1736 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
1737 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1738 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1739 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
1740 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1741 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
1742 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1743 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1744 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
1745 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
1746 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
1747 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
1748 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1749 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
1750 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1751 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1752 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
1753 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1754 // CHECK2-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
1755 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1756 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1757 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
1758 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
1759 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1760 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1761 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
1762 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4
1763 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
1764 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1765 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
1766 // CHECK2-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8
1767 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1768 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1769 // CHECK2-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8
1770 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1771 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8
1772 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1773 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
1774 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8
1775 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1776 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1777 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8
1778 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1779 // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8
1780 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1781 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
1782 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8
1783 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1784 // CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
1785 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8
1786 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1787 // CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 8
1788 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1789 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1790 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
1791 // CHECK2-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
1792 // CHECK2-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
1793 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
1794 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1795 // CHECK2-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
1796 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
1797 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1798 // CHECK2-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
1799 // CHECK2-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
1800 // CHECK2-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
1801 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
1802 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
1803 // CHECK2-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
1804 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
1805 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
1806 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
1807 // CHECK2-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
1808 // CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
1809 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
1810 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
1811 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
1812 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
1813 // CHECK2-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
1814 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
1815 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
1816 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
1817 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
1818 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
1819 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
1820 // CHECK2-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
1821 // CHECK2-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8
1822 // CHECK2-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]])
1823 // CHECK2-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
1824 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1825 // CHECK2-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4
1826 // CHECK2-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
1827 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
1828 // CHECK2-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
1829 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
1830 // CHECK2-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2
1831 // CHECK2-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
1832 // CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
1833 // CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
1834 // CHECK2-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8
1835 // CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
1836 // CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
1837 // CHECK2-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8
1838 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
1839 // CHECK2-NEXT: store i8* null, i8** [[TMP65]], align 8
1840 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
1841 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
1842 // CHECK2-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1843 // CHECK2-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
1844 // CHECK2-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1845 // CHECK2: omp_offload.failed:
1846 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]]
1847 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1848 // CHECK2: omp_offload.cont:
1849 // CHECK2-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4
1850 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
1851 // CHECK2-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4
1852 // CHECK2-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
1853 // CHECK2-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
1854 // CHECK2-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
1855 // CHECK2-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2
1856 // CHECK2-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
1857 // CHECK2-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
1858 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
1859 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1860 // CHECK2: omp_if.then:
1861 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
1862 // CHECK2-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
1863 // CHECK2-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8
1864 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
1865 // CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
1866 // CHECK2-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8
1867 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
1868 // CHECK2-NEXT: store i8* null, i8** [[TMP79]], align 8
1869 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
1870 // CHECK2-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
1871 // CHECK2-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8
1872 // CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
1873 // CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
1874 // CHECK2-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8
1875 // CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
1876 // CHECK2-NEXT: store i8* null, i8** [[TMP84]], align 8
1877 // CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
1878 // CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
1879 // CHECK2-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1880 // CHECK2-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
1881 // CHECK2-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
1882 // CHECK2: omp_offload.failed19:
1883 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
1884 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]]
1885 // CHECK2: omp_offload.cont20:
1886 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
1887 // CHECK2: omp_if.else:
1888 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
1889 // CHECK2-NEXT: br label [[OMP_IF_END]]
1890 // CHECK2: omp_if.end:
1891 // CHECK2-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4
1892 // CHECK2-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32*
1893 // CHECK2-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4
1894 // CHECK2-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8
1895 // CHECK2-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
1896 // CHECK2-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20
1897 // CHECK2-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]]
1898 // CHECK2: omp_if.then24:
1899 // CHECK2-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
1900 // CHECK2-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
1901 // CHECK2-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
1902 // CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
1903 // CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64*
1904 // CHECK2-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8
1905 // CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
1906 // CHECK2-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64*
1907 // CHECK2-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8
1908 // CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1909 // CHECK2-NEXT: store i64 4, i64* [[TMP99]], align 8
1910 // CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0
1911 // CHECK2-NEXT: store i8* null, i8** [[TMP100]], align 8
1912 // CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1
1913 // CHECK2-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
1914 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
1915 // CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1
1916 // CHECK2-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
1917 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
1918 // CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1919 // CHECK2-NEXT: store i64 40, i64* [[TMP105]], align 8
1920 // CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1
1921 // CHECK2-NEXT: store i8* null, i8** [[TMP106]], align 8
1922 // CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2
1923 // CHECK2-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64*
1924 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8
1925 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2
1926 // CHECK2-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64*
1927 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8
1928 // CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1929 // CHECK2-NEXT: store i64 8, i64* [[TMP111]], align 8
1930 // CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2
1931 // CHECK2-NEXT: store i8* null, i8** [[TMP112]], align 8
1932 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3
1933 // CHECK2-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
1934 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP114]], align 8
1935 // CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3
1936 // CHECK2-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
1937 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP116]], align 8
1938 // CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1939 // CHECK2-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8
1940 // CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3
1941 // CHECK2-NEXT: store i8* null, i8** [[TMP118]], align 8
1942 // CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4
1943 // CHECK2-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
1944 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
1945 // CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4
1946 // CHECK2-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
1947 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8
1948 // CHECK2-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1949 // CHECK2-NEXT: store i64 400, i64* [[TMP123]], align 8
1950 // CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4
1951 // CHECK2-NEXT: store i8* null, i8** [[TMP124]], align 8
1952 // CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5
1953 // CHECK2-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
1954 // CHECK2-NEXT: store i64 5, i64* [[TMP126]], align 8
1955 // CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5
1956 // CHECK2-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
1957 // CHECK2-NEXT: store i64 5, i64* [[TMP128]], align 8
1958 // CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
1959 // CHECK2-NEXT: store i64 8, i64* [[TMP129]], align 8
1960 // CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5
1961 // CHECK2-NEXT: store i8* null, i8** [[TMP130]], align 8
1962 // CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6
1963 // CHECK2-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64*
1964 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8
1965 // CHECK2-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6
1966 // CHECK2-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64*
1967 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8
1968 // CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
1969 // CHECK2-NEXT: store i64 8, i64* [[TMP135]], align 8
1970 // CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6
1971 // CHECK2-NEXT: store i8* null, i8** [[TMP136]], align 8
1972 // CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7
1973 // CHECK2-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
1974 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8
1975 // CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7
1976 // CHECK2-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
1977 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8
1978 // CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
1979 // CHECK2-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8
1980 // CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7
1981 // CHECK2-NEXT: store i8* null, i8** [[TMP142]], align 8
1982 // CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8
1983 // CHECK2-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
1984 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8
1985 // CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8
1986 // CHECK2-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
1987 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8
1988 // CHECK2-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
1989 // CHECK2-NEXT: store i64 16, i64* [[TMP147]], align 8
1990 // CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8
1991 // CHECK2-NEXT: store i8* null, i8** [[TMP148]], align 8
1992 // CHECK2-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
1993 // CHECK2-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
1994 // CHECK2-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1995 // CHECK2-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1996 // CHECK2-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
1997 // CHECK2-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]]
1998 // CHECK2: omp_offload.failed28:
1999 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
2000 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT29]]
2001 // CHECK2: omp_offload.cont29:
2002 // CHECK2-NEXT: br label [[OMP_IF_END31:%.*]]
2003 // CHECK2: omp_if.else30:
2004 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
2005 // CHECK2-NEXT: br label [[OMP_IF_END31]]
2006 // CHECK2: omp_if.end31:
2007 // CHECK2-NEXT: store i32 0, i32* [[NN]], align 4
2008 // CHECK2-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
2009 // CHECK2-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
2010 // CHECK2-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4
2011 // CHECK2-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8
2012 // CHECK2-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
2013 // CHECK2-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64*
2014 // CHECK2-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8
2015 // CHECK2-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
2016 // CHECK2-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64*
2017 // CHECK2-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8
2018 // CHECK2-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0
2019 // CHECK2-NEXT: store i8* null, i8** [[TMP160]], align 8
2020 // CHECK2-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
2021 // CHECK2-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
2022 // CHECK2-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2023 // CHECK2-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
2024 // CHECK2-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
2025 // CHECK2: omp_offload.failed36:
2026 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]]
2027 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT37]]
2028 // CHECK2: omp_offload.cont37:
2029 // CHECK2-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
2030 // CHECK2-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32*
2031 // CHECK2-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4
2032 // CHECK2-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8
2033 // CHECK2-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
2034 // CHECK2-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64*
2035 // CHECK2-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8
2036 // CHECK2-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
2037 // CHECK2-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64*
2038 // CHECK2-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8
2039 // CHECK2-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0
2040 // CHECK2-NEXT: store i8* null, i8** [[TMP171]], align 8
2041 // CHECK2-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
2042 // CHECK2-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
2043 // CHECK2-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2044 // CHECK2-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
2045 // CHECK2-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]]
2046 // CHECK2: omp_offload.failed43:
2047 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]]
2048 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT44]]
2049 // CHECK2: omp_offload.cont44:
2050 // CHECK2-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
2051 // CHECK2-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2052 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
2053 // CHECK2-NEXT: ret i32 [[TMP176]]
2054 //
2055 //
2056 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
2057 // CHECK2-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2058 // CHECK2-NEXT: entry:
2059 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2060 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2061 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
2062 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2063 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2064 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2065 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2066 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
2067 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2068 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2069 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
2070 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
2071 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
2072 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2073 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
2074 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2075 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
2076 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2077 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
2078 // CHECK2-NEXT: ret void
2079 //
2080 //
2081 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
2082 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2083 // CHECK2-NEXT: entry:
2084 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2085 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2086 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2087 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2088 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2089 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2090 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2091 // CHECK2-NEXT: ret void
2092 //
2093 //
2094 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2095 // CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
2096 // CHECK2-NEXT: entry:
2097 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
2098 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
2099 // CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
2100 // CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
2101 // CHECK2-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
2102 // CHECK2-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
2103 // CHECK2-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
2104 // CHECK2-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
2105 // CHECK2-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
2106 // CHECK2-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
2107 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
2108 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
2109 // CHECK2-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
2110 // CHECK2-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
2111 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
2112 // CHECK2-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
2113 // CHECK2-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
2114 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
2115 // CHECK2-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
2116 // CHECK2-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
2117 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
2118 // CHECK2-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
2119 // CHECK2-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
2120 // CHECK2-NEXT: ret void
2121 //
2122 //
2123 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
2124 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
2125 // CHECK2-NEXT: entry:
2126 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2127 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
2128 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
2129 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
2130 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
2131 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
2132 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
2133 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
2134 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
2135 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
2136 // CHECK2-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
2137 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
2138 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
2139 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
2140 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
2141 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2142 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2143 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2144 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2145 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2146 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2147 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2148 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
2149 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2150 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
2151 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
2152 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2153 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
2154 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
2155 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
2156 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
2157 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
2158 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
2159 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
2160 // CHECK2-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
2161 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
2162 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
2163 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
2164 // CHECK2-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
2165 // CHECK2-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
2166 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
2167 // CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2168 // CHECK2-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
2169 // CHECK2-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
2170 // CHECK2-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
2171 // CHECK2-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
2172 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
2173 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
2174 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
2175 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
2176 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
2177 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
2178 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
2179 // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
2180 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2181 // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
2182 // CHECK2: omp_offload.failed.i:
2183 // CHECK2-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
2184 // CHECK2-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
2185 // CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
2186 // CHECK2-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
2187 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
2188 // CHECK2-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
2189 // CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
2190 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
2191 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
2192 // CHECK2-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
2193 // CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
2194 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
2195 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
2196 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
2197 // CHECK2: .omp_outlined..1.exit:
2198 // CHECK2-NEXT: ret i32 0
2199 //
2200 //
2201 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
2202 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
2203 // CHECK2-NEXT: entry:
2204 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2205 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2206 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2207 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2208 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2209 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2210 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
2211 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2212 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2213 // CHECK2-NEXT: ret void
2214 //
2215 //
2216 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
2217 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
2218 // CHECK2-NEXT: entry:
2219 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2220 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2221 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2222 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2223 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2224 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2225 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2226 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2227 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2228 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
2229 // CHECK2-NEXT: ret void
2230 //
2231 //
2232 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
2233 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
2234 // CHECK2-NEXT: entry:
2235 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2236 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2237 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2238 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2239 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
2240 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2241 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
2242 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2243 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2244 // CHECK2-NEXT: ret void
2245 //
2246 //
2247 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
2248 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2249 // CHECK2-NEXT: entry:
2250 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2251 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2252 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2253 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2254 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2255 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2256 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2257 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
2258 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
2259 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
2260 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
2261 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
2262 // CHECK2-NEXT: ret void
2263 //
2264 //
2265 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
2266 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2267 // CHECK2-NEXT: entry:
2268 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2269 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2270 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2271 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2272 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2273 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2274 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2275 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2276 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2277 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2278 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
2279 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2280 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2281 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2282 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
2283 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2284 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2285 // CHECK2-NEXT: ret void
2286 //
2287 //
2288 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
2289 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2290 // CHECK2-NEXT: entry:
2291 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2292 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2293 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2294 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2295 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2296 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2297 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2298 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2299 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2300 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2301 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2302 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2303 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
2304 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
2305 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
2306 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
2307 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2308 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
2309 // CHECK2-NEXT: ret void
2310 //
2311 //
2312 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
2313 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
2314 // CHECK2-NEXT: entry:
2315 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2316 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2317 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2318 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
2319 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2320 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2321 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
2322 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
2323 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2324 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2325 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2326 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2327 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2328 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
2329 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2330 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2331 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2332 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
2333 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2334 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2335 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2336 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2337 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2338 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2339 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2340 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2341 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2342 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2343 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2344 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2345 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
2346 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
2347 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
2348 // CHECK2-NEXT: ret void
2349 //
2350 //
2351 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
2352 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
2353 // CHECK2-NEXT: entry:
2354 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2355 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2356 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2357 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2358 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2359 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
2360 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2361 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2362 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
2363 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
2364 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2365 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2366 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2367 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2368 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2369 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2370 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
2371 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2372 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2373 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2374 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
2375 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2376 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2377 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2378 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2379 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2380 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2381 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2382 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2383 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2384 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2385 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2386 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
2387 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
2388 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
2389 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
2390 // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
2391 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
2392 // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
2393 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
2394 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
2395 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
2396 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
2397 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
2398 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
2399 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
2400 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
2401 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
2402 // CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
2403 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
2404 // CHECK2-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
2405 // CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
2406 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
2407 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
2408 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
2409 // CHECK2-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
2410 // CHECK2-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
2411 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
2412 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
2413 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
2414 // CHECK2-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
2415 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
2416 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
2417 // CHECK2-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
2418 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
2419 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
2420 // CHECK2-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
2421 // CHECK2-NEXT: ret void
2422 //
2423 //
2424 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
2425 // CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
2426 // CHECK2-NEXT: entry:
2427 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
2428 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
2429 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
2430 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
2431 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2432 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
2433 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
2434 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
2435 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2436 // CHECK2-NEXT: ret void
2437 //
2438 //
2439 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
2440 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
2441 // CHECK2-NEXT: entry:
2442 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2443 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2444 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
2445 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
2446 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2447 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2448 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
2449 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
2450 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2451 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
2452 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
2453 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
2454 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2455 // CHECK2-NEXT: ret void
2456 //
2457 //
2458 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12
2459 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
2460 // CHECK2-NEXT: entry:
2461 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2462 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2463 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
2464 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2465 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2466 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
2467 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
2468 // CHECK2-NEXT: ret void
2469 //
2470 //
2471 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
2472 // CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
2473 // CHECK2-NEXT: entry:
2474 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
2475 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
2476 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
2477 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
2478 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2479 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
2480 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
2481 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
2482 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2483 // CHECK2-NEXT: ret void
2484 //
2485 //
2486 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15
2487 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
2488 // CHECK2-NEXT: entry:
2489 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2490 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2491 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
2492 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2493 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2494 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
2495 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
2496 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]])
2497 // CHECK2-NEXT: ret void
2498 //
2499 //
2500 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16
2501 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
2502 // CHECK2-NEXT: entry:
2503 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2504 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2505 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
2506 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2507 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2508 // CHECK2-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
2509 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
2510 // CHECK2-NEXT: ret void
2511 //
2512 //
2513 // CHECK2-LABEL: define {{[^@]+}}@_Z6bazzzziPi
2514 // CHECK2-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
2515 // CHECK2-NEXT: entry:
2516 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2517 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8
2518 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
2519 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
2520 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
2521 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2522 // CHECK2-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8
2523 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2524 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2525 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2526 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
2527 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
2528 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2529 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
2530 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
2531 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2532 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8
2533 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2534 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2535 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2536 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2537 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2538 // CHECK2: omp_offload.failed:
2539 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]]
2540 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
2541 // CHECK2: omp_offload.cont:
2542 // CHECK2-NEXT: ret void
2543 //
2544 //
2545 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
2546 // CHECK2-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] {
2547 // CHECK2-NEXT: entry:
2548 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2549 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2550 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2551 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]])
2552 // CHECK2-NEXT: ret void
2553 //
2554 //
2555 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19
2556 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] {
2557 // CHECK2-NEXT: entry:
2558 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2559 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2560 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2561 // CHECK2-NEXT: [[F:%.*]] = alloca i32*, align 8
2562 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2563 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2564 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2565 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2566 // CHECK2-NEXT: ret void
2567 //
2568 //
2569 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
2570 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
2571 // CHECK2-NEXT: entry:
2572 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2573 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
2574 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
2575 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2576 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
2577 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2578 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
2579 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2580 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2581 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4
2582 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2583 // CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
2584 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2585 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2586 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
2587 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2588 // CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
2589 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2590 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2591 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
2592 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
2593 // CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
2594 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
2595 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
2596 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
2597 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
2598 // CHECK2-NEXT: ret i32 [[TMP8]]
2599 //
2600 //
2601 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2602 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2603 // CHECK2-NEXT: entry:
2604 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2605 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2606 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
2607 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
2608 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2609 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
2610 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
2611 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
2612 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
2613 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
2614 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2615 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2616 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2617 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2618 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2619 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4
2620 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2621 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2622 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
2623 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
2624 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
2625 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
2626 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
2627 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
2628 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2629 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
2630 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
2631 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
2632 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
2633 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2634 // CHECK2: omp_if.then:
2635 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2636 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
2637 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
2638 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2639 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
2640 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
2641 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2642 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
2643 // CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 8
2644 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2645 // CHECK2-NEXT: store i64 8, i64* [[TMP14]], align 8
2646 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2647 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8
2648 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2649 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
2650 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
2651 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2652 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
2653 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
2654 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2655 // CHECK2-NEXT: store i64 4, i64* [[TMP20]], align 8
2656 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2657 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
2658 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2659 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
2660 // CHECK2-NEXT: store i64 2, i64* [[TMP23]], align 8
2661 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2662 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
2663 // CHECK2-NEXT: store i64 2, i64* [[TMP25]], align 8
2664 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2665 // CHECK2-NEXT: store i64 8, i64* [[TMP26]], align 8
2666 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2667 // CHECK2-NEXT: store i8* null, i8** [[TMP27]], align 8
2668 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2669 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
2670 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
2671 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2672 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
2673 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8
2674 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2675 // CHECK2-NEXT: store i64 8, i64* [[TMP32]], align 8
2676 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2677 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8
2678 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2679 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
2680 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8
2681 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2682 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
2683 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8
2684 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2685 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
2686 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
2687 // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8
2688 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2689 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2690 // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2691 // CHECK2-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2692 // CHECK2-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
2693 // CHECK2-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2694 // CHECK2: omp_offload.failed:
2695 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
2696 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
2697 // CHECK2: omp_offload.cont:
2698 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
2699 // CHECK2: omp_if.else:
2700 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
2701 // CHECK2-NEXT: br label [[OMP_IF_END]]
2702 // CHECK2: omp_if.end:
2703 // CHECK2-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
2704 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
2705 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
2706 // CHECK2-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
2707 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
2708 // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
2709 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
2710 // CHECK2-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2711 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
2712 // CHECK2-NEXT: ret i32 [[ADD4]]
2713 //
2714 //
2715 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
2716 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
2717 // CHECK2-NEXT: entry:
2718 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2719 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
2720 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
2721 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1
2722 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
2723 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2724 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2725 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
2726 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
2727 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
2728 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
2729 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2730 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
2731 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
2732 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1
2733 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2734 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2735 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
2736 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2737 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
2738 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2739 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
2740 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2741 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
2742 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
2743 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
2744 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
2745 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
2746 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
2747 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2748 // CHECK2: omp_if.then:
2749 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2750 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
2751 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
2752 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2753 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
2754 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
2755 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2756 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8
2757 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2758 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2759 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
2760 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2761 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
2762 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
2763 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2764 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8
2765 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2766 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
2767 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
2768 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2769 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
2770 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
2771 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2772 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
2773 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2774 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
2775 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
2776 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2777 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
2778 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
2779 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2780 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8
2781 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2782 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2783 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2784 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2785 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2786 // CHECK2: omp_offload.failed:
2787 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
2788 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
2789 // CHECK2: omp_offload.cont:
2790 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
2791 // CHECK2: omp_if.else:
2792 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
2793 // CHECK2-NEXT: br label [[OMP_IF_END]]
2794 // CHECK2: omp_if.end:
2795 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
2796 // CHECK2-NEXT: ret i32 [[TMP31]]
2797 //
2798 //
2799 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2800 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
2801 // CHECK2-NEXT: entry:
2802 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2803 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
2804 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
2805 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
2806 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2807 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2808 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
2809 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
2810 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
2811 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2812 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
2813 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
2814 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2815 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2816 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
2817 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2818 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
2819 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2820 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
2821 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2822 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2823 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
2824 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2825 // CHECK2: omp_if.then:
2826 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2827 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
2828 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
2829 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2830 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
2831 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
2832 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2833 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8
2834 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2835 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
2836 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
2837 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2838 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2839 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
2840 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2841 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8
2842 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2843 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
2844 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
2845 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2846 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
2847 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
2848 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2849 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8
2850 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2851 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2852 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2853 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2854 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2855 // CHECK2: omp_offload.failed:
2856 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
2857 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
2858 // CHECK2: omp_offload.cont:
2859 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
2860 // CHECK2: omp_if.else:
2861 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
2862 // CHECK2-NEXT: br label [[OMP_IF_END]]
2863 // CHECK2: omp_if.end:
2864 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
2865 // CHECK2-NEXT: ret i32 [[TMP24]]
2866 //
2867 //
2868 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
2869 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
2870 // CHECK2-NEXT: entry:
2871 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2872 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
2873 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2874 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2875 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
2876 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
2877 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2878 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
2879 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2880 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2881 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
2882 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2883 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2884 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2885 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2886 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
2887 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
2888 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2889 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
2890 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
2891 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
2892 // CHECK2-NEXT: ret void
2893 //
2894 //
2895 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22
2896 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
2897 // CHECK2-NEXT: entry:
2898 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2899 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2900 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2901 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
2902 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2903 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2904 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
2905 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2906 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2907 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2908 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
2909 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2910 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2911 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
2912 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2913 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2914 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2915 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2916 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
2917 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
2918 // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
2919 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
2920 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
2921 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
2922 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
2923 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
2924 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
2925 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8
2926 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
2927 // CHECK2-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
2928 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
2929 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
2930 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
2931 // CHECK2-NEXT: ret void
2932 //
2933 //
2934 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
2935 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2936 // CHECK2-NEXT: entry:
2937 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2938 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2939 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
2940 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2941 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
2942 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
2943 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
2944 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2945 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2946 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
2947 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2948 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2949 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2950 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
2951 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2952 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2953 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2954 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
2955 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
2956 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
2957 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2958 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
2959 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2960 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
2961 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
2962 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
2963 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
2964 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
2965 // CHECK2-NEXT: ret void
2966 //
2967 //
2968 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24
2969 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2970 // CHECK2-NEXT: entry:
2971 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2972 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2973 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
2974 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
2975 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
2976 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2977 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2978 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2979 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
2980 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
2981 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
2982 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2983 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2984 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2985 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
2986 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2987 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2988 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2989 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
2990 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2991 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
2992 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
2993 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
2994 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
2995 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
2996 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
2997 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
2998 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
2999 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
3000 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3001 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3002 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
3003 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
3004 // CHECK2-NEXT: ret void
3005 //
3006 //
3007 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
3008 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3009 // CHECK2-NEXT: entry:
3010 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3011 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3012 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3013 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
3014 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
3015 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
3016 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
3017 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3018 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3019 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3020 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3021 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3022 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3023 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
3024 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3025 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
3026 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3027 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
3028 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3029 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
3030 // CHECK2-NEXT: ret void
3031 //
3032 //
3033 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..27
3034 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3035 // CHECK2-NEXT: entry:
3036 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3037 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3038 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3039 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3040 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3041 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3042 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3043 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
3044 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
3045 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3046 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3047 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3048 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3049 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3050 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3051 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
3052 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
3053 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
3054 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
3055 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
3056 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
3057 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3058 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3059 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
3060 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
3061 // CHECK2-NEXT: ret void
3062 //
3063 //
3064 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3065 // CHECK2-SAME: () #[[ATTR4]] {
3066 // CHECK2-NEXT: entry:
3067 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
3068 // CHECK2-NEXT: ret void
3069 //
3070 //
3071 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
3072 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3073 // CHECK3-NEXT: entry:
3074 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3075 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3076 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
3077 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
3078 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
3079 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3080 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
3081 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3082 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
3083 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3084 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3085 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3086 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
3087 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
3088 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3089 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3090 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3091 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
3092 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3093 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
3094 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
3095 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
3096 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
3097 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4
3098 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4
3099 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
3100 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
3101 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
3102 // CHECK3-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4
3103 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4
3104 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4
3105 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4
3106 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
3107 // CHECK3-NEXT: [[NN:%.*]] = alloca i32, align 4
3108 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
3109 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4
3110 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4
3111 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4
3112 // CHECK3-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4
3113 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4
3114 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4
3115 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4
3116 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
3117 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3118 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
3119 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
3120 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3121 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
3122 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3123 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
3124 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3125 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3126 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
3127 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
3128 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
3129 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3130 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
3131 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3132 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3133 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
3134 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3135 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2
3136 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3137 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3138 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3139 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3140 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3141 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
3142 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
3143 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3144 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
3145 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4
3146 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3147 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
3148 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4
3149 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3150 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4
3151 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3152 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
3153 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4
3154 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3155 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
3156 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4
3157 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3158 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4
3159 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3160 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
3161 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4
3162 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3163 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
3164 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4
3165 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3166 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4
3167 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3168 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3169 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
3170 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
3171 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4
3172 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
3173 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3174 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4
3175 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
3176 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3177 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
3178 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
3179 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
3180 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
3181 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
3182 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
3183 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
3184 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
3185 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
3186 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
3187 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
3188 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
3189 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
3190 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
3191 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
3192 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
3193 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
3194 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
3195 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
3196 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
3197 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
3198 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
3199 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
3200 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4
3201 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]])
3202 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
3203 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4
3204 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
3205 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
3206 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
3207 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
3208 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2
3209 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
3210 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3211 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
3212 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4
3213 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3214 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
3215 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4
3216 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
3217 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4
3218 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3219 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3220 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3221 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
3222 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3223 // CHECK3: omp_offload.failed:
3224 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]]
3225 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3226 // CHECK3: omp_offload.cont:
3227 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4
3228 // CHECK3-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
3229 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
3230 // CHECK3-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
3231 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
3232 // CHECK3-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2
3233 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
3234 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
3235 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
3236 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3237 // CHECK3: omp_if.then:
3238 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
3239 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
3240 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4
3241 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
3242 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
3243 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4
3244 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
3245 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4
3246 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
3247 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
3248 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4
3249 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
3250 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
3251 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4
3252 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
3253 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4
3254 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
3255 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
3256 // CHECK3-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3257 // CHECK3-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
3258 // CHECK3-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
3259 // CHECK3: omp_offload.failed15:
3260 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
3261 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]]
3262 // CHECK3: omp_offload.cont16:
3263 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3264 // CHECK3: omp_if.else:
3265 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
3266 // CHECK3-NEXT: br label [[OMP_IF_END]]
3267 // CHECK3: omp_if.end:
3268 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4
3269 // CHECK3-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4
3270 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4
3271 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
3272 // CHECK3-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20
3273 // CHECK3-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
3274 // CHECK3: omp_if.then19:
3275 // CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
3276 // CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
3277 // CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
3278 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
3279 // CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
3280 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
3281 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32*
3282 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4
3283 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
3284 // CHECK3-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32*
3285 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4
3286 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3287 // CHECK3-NEXT: store i64 4, i64* [[TMP99]], align 4
3288 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
3289 // CHECK3-NEXT: store i8* null, i8** [[TMP100]], align 4
3290 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
3291 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
3292 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
3293 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
3294 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
3295 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
3296 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3297 // CHECK3-NEXT: store i64 40, i64* [[TMP105]], align 4
3298 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1
3299 // CHECK3-NEXT: store i8* null, i8** [[TMP106]], align 4
3300 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
3301 // CHECK3-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32*
3302 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4
3303 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
3304 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32*
3305 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4
3306 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3307 // CHECK3-NEXT: store i64 4, i64* [[TMP111]], align 4
3308 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2
3309 // CHECK3-NEXT: store i8* null, i8** [[TMP112]], align 4
3310 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
3311 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
3312 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP114]], align 4
3313 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
3314 // CHECK3-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
3315 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP116]], align 4
3316 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3317 // CHECK3-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4
3318 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3
3319 // CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4
3320 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
3321 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
3322 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
3323 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
3324 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
3325 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4
3326 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3327 // CHECK3-NEXT: store i64 400, i64* [[TMP123]], align 4
3328 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4
3329 // CHECK3-NEXT: store i8* null, i8** [[TMP124]], align 4
3330 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
3331 // CHECK3-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
3332 // CHECK3-NEXT: store i32 5, i32* [[TMP126]], align 4
3333 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
3334 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
3335 // CHECK3-NEXT: store i32 5, i32* [[TMP128]], align 4
3336 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
3337 // CHECK3-NEXT: store i64 4, i64* [[TMP129]], align 4
3338 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5
3339 // CHECK3-NEXT: store i8* null, i8** [[TMP130]], align 4
3340 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
3341 // CHECK3-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32*
3342 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4
3343 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
3344 // CHECK3-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32*
3345 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4
3346 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
3347 // CHECK3-NEXT: store i64 4, i64* [[TMP135]], align 4
3348 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6
3349 // CHECK3-NEXT: store i8* null, i8** [[TMP136]], align 4
3350 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
3351 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
3352 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4
3353 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
3354 // CHECK3-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
3355 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4
3356 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
3357 // CHECK3-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4
3358 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7
3359 // CHECK3-NEXT: store i8* null, i8** [[TMP142]], align 4
3360 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
3361 // CHECK3-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
3362 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4
3363 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
3364 // CHECK3-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
3365 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4
3366 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
3367 // CHECK3-NEXT: store i64 12, i64* [[TMP147]], align 4
3368 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8
3369 // CHECK3-NEXT: store i8* null, i8** [[TMP148]], align 4
3370 // CHECK3-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
3371 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
3372 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3373 // CHECK3-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3374 // CHECK3-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
3375 // CHECK3-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
3376 // CHECK3: omp_offload.failed23:
3377 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
3378 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT24]]
3379 // CHECK3: omp_offload.cont24:
3380 // CHECK3-NEXT: br label [[OMP_IF_END26:%.*]]
3381 // CHECK3: omp_if.else25:
3382 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
3383 // CHECK3-NEXT: br label [[OMP_IF_END26]]
3384 // CHECK3: omp_if.end26:
3385 // CHECK3-NEXT: store i32 0, i32* [[NN]], align 4
3386 // CHECK3-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
3387 // CHECK3-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4
3388 // CHECK3-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4
3389 // CHECK3-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
3390 // CHECK3-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32*
3391 // CHECK3-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4
3392 // CHECK3-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
3393 // CHECK3-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32*
3394 // CHECK3-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4
3395 // CHECK3-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
3396 // CHECK3-NEXT: store i8* null, i8** [[TMP160]], align 4
3397 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
3398 // CHECK3-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
3399 // CHECK3-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3400 // CHECK3-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
3401 // CHECK3-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
3402 // CHECK3: omp_offload.failed30:
3403 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]]
3404 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT31]]
3405 // CHECK3: omp_offload.cont31:
3406 // CHECK3-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
3407 // CHECK3-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4
3408 // CHECK3-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4
3409 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
3410 // CHECK3-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32*
3411 // CHECK3-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4
3412 // CHECK3-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
3413 // CHECK3-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32*
3414 // CHECK3-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4
3415 // CHECK3-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0
3416 // CHECK3-NEXT: store i8* null, i8** [[TMP171]], align 4
3417 // CHECK3-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
3418 // CHECK3-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
3419 // CHECK3-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3420 // CHECK3-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
3421 // CHECK3-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
3422 // CHECK3: omp_offload.failed36:
3423 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]]
3424 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT37]]
3425 // CHECK3: omp_offload.cont37:
3426 // CHECK3-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
3427 // CHECK3-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3428 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
3429 // CHECK3-NEXT: ret i32 [[TMP176]]
3430 //
3431 //
3432 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
3433 // CHECK3-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
3434 // CHECK3-NEXT: entry:
3435 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3436 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3437 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
3438 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3439 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3440 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3441 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3442 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
3443 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3444 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3445 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
3446 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
3447 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
3448 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3449 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
3450 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3451 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
3452 // CHECK3-NEXT: ret void
3453 //
3454 //
3455 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
3456 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3457 // CHECK3-NEXT: entry:
3458 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3459 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3460 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3461 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3462 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3463 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3464 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3465 // CHECK3-NEXT: ret void
3466 //
3467 //
3468 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
3469 // CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
3470 // CHECK3-NEXT: entry:
3471 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
3472 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
3473 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
3474 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
3475 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
3476 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
3477 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
3478 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
3479 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
3480 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
3481 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
3482 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
3483 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
3484 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
3485 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
3486 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
3487 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
3488 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
3489 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
3490 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
3491 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
3492 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
3493 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
3494 // CHECK3-NEXT: ret void
3495 //
3496 //
3497 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
3498 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
3499 // CHECK3-NEXT: entry:
3500 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
3501 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
3502 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
3503 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
3504 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
3505 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
3506 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
3507 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
3508 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
3509 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
3510 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
3511 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
3512 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
3513 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
3514 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
3515 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
3516 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
3517 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
3518 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
3519 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
3520 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
3521 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
3522 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
3523 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
3524 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
3525 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
3526 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
3527 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
3528 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
3529 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
3530 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
3531 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
3532 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
3533 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
3534 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
3535 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
3536 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
3537 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
3538 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
3539 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
3540 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
3541 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
3542 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
3543 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
3544 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
3545 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
3546 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
3547 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
3548 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
3549 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
3550 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
3551 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
3552 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
3553 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
3554 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3555 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
3556 // CHECK3: omp_offload.failed.i:
3557 // CHECK3-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
3558 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
3559 // CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
3560 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
3561 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
3562 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
3563 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
3564 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
3565 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
3566 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
3567 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
3568 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
3569 // CHECK3: .omp_outlined..1.exit:
3570 // CHECK3-NEXT: ret i32 0
3571 //
3572 //
3573 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
3574 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
3575 // CHECK3-NEXT: entry:
3576 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3577 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3578 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3579 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3580 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3581 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3582 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3583 // CHECK3-NEXT: ret void
3584 //
3585 //
3586 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
3587 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
3588 // CHECK3-NEXT: entry:
3589 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3590 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3591 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3592 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3593 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3594 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3595 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3596 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3597 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
3598 // CHECK3-NEXT: ret void
3599 //
3600 //
3601 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
3602 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
3603 // CHECK3-NEXT: entry:
3604 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3605 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3606 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3607 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3608 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3609 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3610 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
3611 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3612 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3613 // CHECK3-NEXT: ret void
3614 //
3615 //
3616 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
3617 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3618 // CHECK3-NEXT: entry:
3619 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3620 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3621 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3622 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3623 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3624 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3625 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3626 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3627 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
3628 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
3629 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
3630 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
3631 // CHECK3-NEXT: ret void
3632 //
3633 //
3634 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
3635 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3636 // CHECK3-NEXT: entry:
3637 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3638 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3639 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3640 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3641 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3642 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3643 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3644 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3645 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3646 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3647 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
3648 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3649 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
3650 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3651 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
3652 // CHECK3-NEXT: ret void
3653 //
3654 //
3655 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
3656 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3657 // CHECK3-NEXT: entry:
3658 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3659 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3660 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3661 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3662 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3663 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3664 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3665 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3666 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3667 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3668 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3669 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
3670 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
3671 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
3672 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
3673 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
3674 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
3675 // CHECK3-NEXT: ret void
3676 //
3677 //
3678 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
3679 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
3680 // CHECK3-NEXT: entry:
3681 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3682 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
3683 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3684 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
3685 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3686 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3687 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
3688 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
3689 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3690 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3691 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3692 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3693 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3694 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
3695 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3696 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3697 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3698 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
3699 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3700 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3701 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3702 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3703 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3704 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3705 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3706 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3707 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3708 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
3709 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
3710 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
3711 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
3712 // CHECK3-NEXT: ret void
3713 //
3714 //
3715 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
3716 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
3717 // CHECK3-NEXT: entry:
3718 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3719 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3720 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3721 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
3722 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3723 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
3724 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3725 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3726 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
3727 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
3728 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3729 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3730 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3731 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3732 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3733 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3734 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
3735 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3736 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3737 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3738 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
3739 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3740 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3741 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3742 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3743 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3744 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3745 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3746 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3747 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3748 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
3749 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
3750 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
3751 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
3752 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
3753 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
3754 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
3755 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
3756 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
3757 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
3758 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
3759 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
3760 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
3761 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
3762 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
3763 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
3764 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
3765 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
3766 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
3767 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
3768 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
3769 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
3770 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
3771 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
3772 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
3773 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
3774 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
3775 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
3776 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
3777 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
3778 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
3779 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
3780 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
3781 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
3782 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
3783 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
3784 // CHECK3-NEXT: ret void
3785 //
3786 //
3787 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
3788 // CHECK3-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
3789 // CHECK3-NEXT: entry:
3790 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
3791 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
3792 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
3793 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
3794 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
3795 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
3796 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3797 // CHECK3-NEXT: ret void
3798 //
3799 //
3800 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
3801 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
3802 // CHECK3-NEXT: entry:
3803 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3804 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3805 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
3806 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
3807 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3808 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3809 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
3810 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
3811 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
3812 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
3813 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3814 // CHECK3-NEXT: ret void
3815 //
3816 //
3817 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12
3818 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
3819 // CHECK3-NEXT: entry:
3820 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3821 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3822 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
3823 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3824 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3825 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
3826 // CHECK3-NEXT: ret void
3827 //
3828 //
3829 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
3830 // CHECK3-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
3831 // CHECK3-NEXT: entry:
3832 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
3833 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
3834 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
3835 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
3836 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
3837 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
3838 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3839 // CHECK3-NEXT: ret void
3840 //
3841 //
3842 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15
3843 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
3844 // CHECK3-NEXT: entry:
3845 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3846 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3847 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
3848 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3849 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3850 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
3851 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
3852 // CHECK3-NEXT: ret void
3853 //
3854 //
3855 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
3856 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
3857 // CHECK3-NEXT: entry:
3858 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3859 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3860 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
3861 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3862 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3863 // CHECK3-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
3864 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
3865 // CHECK3-NEXT: ret void
3866 //
3867 //
3868 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi
3869 // CHECK3-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
3870 // CHECK3-NEXT: entry:
3871 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3872 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4
3873 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
3874 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
3875 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
3876 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3877 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4
3878 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3879 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3880 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32*
3881 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4
3882 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3883 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
3884 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4
3885 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3886 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4
3887 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3888 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3889 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3890 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
3891 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3892 // CHECK3: omp_offload.failed:
3893 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]]
3894 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3895 // CHECK3: omp_offload.cont:
3896 // CHECK3-NEXT: ret void
3897 //
3898 //
3899 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
3900 // CHECK3-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] {
3901 // CHECK3-NEXT: entry:
3902 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3903 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3904 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3905 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]])
3906 // CHECK3-NEXT: ret void
3907 //
3908 //
3909 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..19
3910 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] {
3911 // CHECK3-NEXT: entry:
3912 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3913 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3914 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3915 // CHECK3-NEXT: [[F:%.*]] = alloca i32*, align 4
3916 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3917 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3918 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3919 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3920 // CHECK3-NEXT: ret void
3921 //
3922 //
3923 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
3924 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
3925 // CHECK3-NEXT: entry:
3926 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3927 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3928 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3929 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3930 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
3931 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3932 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
3933 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3934 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3935 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4
3936 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3937 // CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
3938 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3939 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3940 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
3941 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3942 // CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
3943 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3944 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3945 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
3946 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3947 // CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
3948 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3949 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3950 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
3951 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3952 // CHECK3-NEXT: ret i32 [[TMP8]]
3953 //
3954 //
3955 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3956 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3957 // CHECK3-NEXT: entry:
3958 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3959 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3960 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
3961 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
3962 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3963 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3964 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3965 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3966 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3967 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3968 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3969 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3970 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3971 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3972 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3973 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4
3974 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3975 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
3976 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3977 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3978 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3979 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3980 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
3981 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3982 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3983 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3984 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3985 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3986 // CHECK3: omp_if.then:
3987 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3988 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3989 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3990 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3991 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3992 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
3993 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
3994 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3995 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
3996 // CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4
3997 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3998 // CHECK3-NEXT: store i64 8, i64* [[TMP14]], align 4
3999 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4000 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4
4001 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4002 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4003 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
4004 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4005 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
4006 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
4007 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
4008 // CHECK3-NEXT: store i64 4, i64* [[TMP20]], align 4
4009 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4010 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
4011 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4012 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
4013 // CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4
4014 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4015 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
4016 // CHECK3-NEXT: store i32 2, i32* [[TMP25]], align 4
4017 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
4018 // CHECK3-NEXT: store i64 4, i64* [[TMP26]], align 4
4019 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4020 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4
4021 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4022 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
4023 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
4024 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4025 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
4026 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4
4027 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4028 // CHECK3-NEXT: store i64 4, i64* [[TMP32]], align 4
4029 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4030 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
4031 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4032 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
4033 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4
4034 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4035 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
4036 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4
4037 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4038 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4
4039 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4040 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4
4041 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4042 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4043 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4044 // CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4045 // CHECK3-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
4046 // CHECK3-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4047 // CHECK3: omp_offload.failed:
4048 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4049 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
4050 // CHECK3: omp_offload.cont:
4051 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
4052 // CHECK3: omp_if.else:
4053 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4054 // CHECK3-NEXT: br label [[OMP_IF_END]]
4055 // CHECK3: omp_if.end:
4056 // CHECK3-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
4057 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
4058 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4059 // CHECK3-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
4060 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32
4061 // CHECK3-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
4062 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
4063 // CHECK3-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4064 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
4065 // CHECK3-NEXT: ret i32 [[ADD3]]
4066 //
4067 //
4068 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
4069 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4070 // CHECK3-NEXT: entry:
4071 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
4072 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
4073 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
4074 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
4075 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
4076 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4077 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4078 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
4079 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
4080 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
4081 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
4082 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
4083 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
4084 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
4085 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1
4086 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4087 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4088 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4089 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4090 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4091 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
4092 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4093 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
4094 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4095 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
4096 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4097 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4098 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
4099 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4100 // CHECK3: omp_if.then:
4101 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4102 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4103 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
4104 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4105 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
4106 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
4107 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4108 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
4109 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4110 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4111 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
4112 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4113 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4114 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
4115 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4116 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
4117 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4118 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
4119 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
4120 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4121 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
4122 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
4123 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4124 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
4125 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4126 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
4127 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
4128 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4129 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
4130 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
4131 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4132 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
4133 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4134 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4135 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4136 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
4137 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4138 // CHECK3: omp_offload.failed:
4139 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
4140 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
4141 // CHECK3: omp_offload.cont:
4142 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
4143 // CHECK3: omp_if.else:
4144 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
4145 // CHECK3-NEXT: br label [[OMP_IF_END]]
4146 // CHECK3: omp_if.end:
4147 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
4148 // CHECK3-NEXT: ret i32 [[TMP31]]
4149 //
4150 //
4151 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4152 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
4153 // CHECK3-NEXT: entry:
4154 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
4155 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
4156 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
4157 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
4158 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4159 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4160 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4161 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4162 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4163 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
4164 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
4165 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
4166 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4167 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4168 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4169 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4170 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4171 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
4172 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4173 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4174 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
4175 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4176 // CHECK3: omp_if.then:
4177 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4178 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
4179 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
4180 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4181 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4182 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
4183 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4184 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4
4185 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4186 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
4187 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
4188 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4189 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4190 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
4191 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4192 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4
4193 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4194 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
4195 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
4196 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4197 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
4198 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
4199 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4200 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
4201 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4202 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4203 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4204 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
4205 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4206 // CHECK3: omp_offload.failed:
4207 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
4208 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
4209 // CHECK3: omp_offload.cont:
4210 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
4211 // CHECK3: omp_if.else:
4212 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
4213 // CHECK3-NEXT: br label [[OMP_IF_END]]
4214 // CHECK3: omp_if.end:
4215 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
4216 // CHECK3-NEXT: ret i32 [[TMP24]]
4217 //
4218 //
4219 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
4220 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4221 // CHECK3-NEXT: entry:
4222 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4223 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
4224 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
4225 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
4226 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
4227 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
4228 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4229 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
4230 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4231 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4232 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
4233 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4234 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4235 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4236 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4237 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
4238 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4239 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4240 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
4241 // CHECK3-NEXT: ret void
4242 //
4243 //
4244 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..22
4245 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4246 // CHECK3-NEXT: entry:
4247 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4248 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4249 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4250 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
4251 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
4252 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
4253 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
4254 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4255 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4256 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4257 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
4258 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4259 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4260 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
4261 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4262 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4263 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4264 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4265 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
4266 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
4267 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
4268 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4269 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4
4270 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
4271 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
4272 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
4273 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4
4274 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
4275 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
4276 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
4277 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4278 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
4279 // CHECK3-NEXT: ret void
4280 //
4281 //
4282 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
4283 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4284 // CHECK3-NEXT: entry:
4285 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4286 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4287 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
4288 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4289 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4290 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4291 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
4292 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4293 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4294 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
4295 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4296 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4297 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
4298 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4299 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4300 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4301 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4302 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4303 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4304 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
4305 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4306 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
4307 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4308 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
4309 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4310 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
4311 // CHECK3-NEXT: ret void
4312 //
4313 //
4314 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..24
4315 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4316 // CHECK3-NEXT: entry:
4317 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4318 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4319 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4320 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4321 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
4322 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4323 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4324 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4325 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4326 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4327 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
4328 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4329 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4330 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
4331 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4332 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4333 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4334 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
4335 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4336 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
4337 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
4338 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4339 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
4340 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
4341 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
4342 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
4343 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
4344 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
4345 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
4346 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4347 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
4348 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
4349 // CHECK3-NEXT: ret void
4350 //
4351 //
4352 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
4353 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4354 // CHECK3-NEXT: entry:
4355 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4356 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4357 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4358 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4359 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4360 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4361 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4362 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4363 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4364 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4365 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4366 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4367 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4368 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4369 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4370 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
4371 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4372 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
4373 // CHECK3-NEXT: ret void
4374 //
4375 //
4376 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..27
4377 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4378 // CHECK3-NEXT: entry:
4379 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4380 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4381 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4382 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4383 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4384 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4385 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4386 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4387 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4388 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4389 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4390 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4391 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4392 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4393 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
4394 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4395 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
4396 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
4397 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4398 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
4399 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
4400 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4401 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
4402 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
4403 // CHECK3-NEXT: ret void
4404 //
4405 //
4406 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4407 // CHECK3-SAME: () #[[ATTR4]] {
4408 // CHECK3-NEXT: entry:
4409 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
4410 // CHECK3-NEXT: ret void
4411 //
4412 //
4413 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
4414 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
4415 // CHECK4-NEXT: entry:
4416 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
4417 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
4418 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
4419 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4
4420 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
4421 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4422 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
4423 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
4424 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
4425 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4426 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4427 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4428 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4429 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
4430 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4431 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4432 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4433 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
4434 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4435 // CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
4436 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
4437 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
4438 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
4439 // CHECK4-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4
4440 // CHECK4-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4
4441 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
4442 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
4443 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
4444 // CHECK4-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4
4445 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4
4446 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4
4447 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4
4448 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
4449 // CHECK4-NEXT: [[NN:%.*]] = alloca i32, align 4
4450 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
4451 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4
4452 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4
4453 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4
4454 // CHECK4-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4
4455 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4
4456 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4
4457 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4
4458 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
4459 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
4460 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
4461 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
4462 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4463 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
4464 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4465 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
4466 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
4467 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
4468 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
4469 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
4470 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
4471 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4472 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
4473 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
4474 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4475 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
4476 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4477 // CHECK4-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2
4478 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4479 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4480 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4481 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4482 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4483 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
4484 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
4485 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4486 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
4487 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4
4488 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4489 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
4490 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4
4491 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4492 // CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4
4493 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4494 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
4495 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4
4496 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4497 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
4498 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4
4499 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4500 // CHECK4-NEXT: store i8* null, i8** [[TMP22]], align 4
4501 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4502 // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
4503 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4
4504 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4505 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
4506 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4
4507 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4508 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4
4509 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4510 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4511 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
4512 // CHECK4-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
4513 // CHECK4-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4
4514 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
4515 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4516 // CHECK4-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4
4517 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
4518 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4519 // CHECK4-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
4520 // CHECK4-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
4521 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
4522 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
4523 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
4524 // CHECK4-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
4525 // CHECK4-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
4526 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
4527 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
4528 // CHECK4-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
4529 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
4530 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
4531 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
4532 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
4533 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
4534 // CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
4535 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
4536 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
4537 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
4538 // CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
4539 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
4540 // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
4541 // CHECK4-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
4542 // CHECK4-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4
4543 // CHECK4-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]])
4544 // CHECK4-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
4545 // CHECK4-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4
4546 // CHECK4-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
4547 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
4548 // CHECK4-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
4549 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
4550 // CHECK4-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2
4551 // CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
4552 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
4553 // CHECK4-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
4554 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4
4555 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
4556 // CHECK4-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
4557 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4
4558 // CHECK4-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
4559 // CHECK4-NEXT: store i8* null, i8** [[TMP63]], align 4
4560 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
4561 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
4562 // CHECK4-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4563 // CHECK4-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
4564 // CHECK4-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4565 // CHECK4: omp_offload.failed:
4566 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]]
4567 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
4568 // CHECK4: omp_offload.cont:
4569 // CHECK4-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4
4570 // CHECK4-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
4571 // CHECK4-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
4572 // CHECK4-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
4573 // CHECK4-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
4574 // CHECK4-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2
4575 // CHECK4-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
4576 // CHECK4-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
4577 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
4578 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4579 // CHECK4: omp_if.then:
4580 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
4581 // CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
4582 // CHECK4-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4
4583 // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
4584 // CHECK4-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
4585 // CHECK4-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4
4586 // CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
4587 // CHECK4-NEXT: store i8* null, i8** [[TMP77]], align 4
4588 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
4589 // CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
4590 // CHECK4-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4
4591 // CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
4592 // CHECK4-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
4593 // CHECK4-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4
4594 // CHECK4-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
4595 // CHECK4-NEXT: store i8* null, i8** [[TMP82]], align 4
4596 // CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
4597 // CHECK4-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
4598 // CHECK4-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4599 // CHECK4-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
4600 // CHECK4-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
4601 // CHECK4: omp_offload.failed15:
4602 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
4603 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT16]]
4604 // CHECK4: omp_offload.cont16:
4605 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
4606 // CHECK4: omp_if.else:
4607 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
4608 // CHECK4-NEXT: br label [[OMP_IF_END]]
4609 // CHECK4: omp_if.end:
4610 // CHECK4-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4
4611 // CHECK4-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4
4612 // CHECK4-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4
4613 // CHECK4-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
4614 // CHECK4-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20
4615 // CHECK4-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
4616 // CHECK4: omp_if.then19:
4617 // CHECK4-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
4618 // CHECK4-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
4619 // CHECK4-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
4620 // CHECK4-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
4621 // CHECK4-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
4622 // CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
4623 // CHECK4-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32*
4624 // CHECK4-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4
4625 // CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
4626 // CHECK4-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32*
4627 // CHECK4-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4
4628 // CHECK4-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4629 // CHECK4-NEXT: store i64 4, i64* [[TMP99]], align 4
4630 // CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
4631 // CHECK4-NEXT: store i8* null, i8** [[TMP100]], align 4
4632 // CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
4633 // CHECK4-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
4634 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
4635 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
4636 // CHECK4-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
4637 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
4638 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
4639 // CHECK4-NEXT: store i64 40, i64* [[TMP105]], align 4
4640 // CHECK4-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1
4641 // CHECK4-NEXT: store i8* null, i8** [[TMP106]], align 4
4642 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
4643 // CHECK4-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32*
4644 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4
4645 // CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
4646 // CHECK4-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32*
4647 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4
4648 // CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
4649 // CHECK4-NEXT: store i64 4, i64* [[TMP111]], align 4
4650 // CHECK4-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2
4651 // CHECK4-NEXT: store i8* null, i8** [[TMP112]], align 4
4652 // CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
4653 // CHECK4-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
4654 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP114]], align 4
4655 // CHECK4-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
4656 // CHECK4-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
4657 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP116]], align 4
4658 // CHECK4-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4659 // CHECK4-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4
4660 // CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3
4661 // CHECK4-NEXT: store i8* null, i8** [[TMP118]], align 4
4662 // CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
4663 // CHECK4-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
4664 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
4665 // CHECK4-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
4666 // CHECK4-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
4667 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4
4668 // CHECK4-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4669 // CHECK4-NEXT: store i64 400, i64* [[TMP123]], align 4
4670 // CHECK4-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4
4671 // CHECK4-NEXT: store i8* null, i8** [[TMP124]], align 4
4672 // CHECK4-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
4673 // CHECK4-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
4674 // CHECK4-NEXT: store i32 5, i32* [[TMP126]], align 4
4675 // CHECK4-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
4676 // CHECK4-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
4677 // CHECK4-NEXT: store i32 5, i32* [[TMP128]], align 4
4678 // CHECK4-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
4679 // CHECK4-NEXT: store i64 4, i64* [[TMP129]], align 4
4680 // CHECK4-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5
4681 // CHECK4-NEXT: store i8* null, i8** [[TMP130]], align 4
4682 // CHECK4-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
4683 // CHECK4-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32*
4684 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4
4685 // CHECK4-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
4686 // CHECK4-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32*
4687 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4
4688 // CHECK4-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
4689 // CHECK4-NEXT: store i64 4, i64* [[TMP135]], align 4
4690 // CHECK4-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6
4691 // CHECK4-NEXT: store i8* null, i8** [[TMP136]], align 4
4692 // CHECK4-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
4693 // CHECK4-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
4694 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4
4695 // CHECK4-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
4696 // CHECK4-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
4697 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4
4698 // CHECK4-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
4699 // CHECK4-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4
4700 // CHECK4-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7
4701 // CHECK4-NEXT: store i8* null, i8** [[TMP142]], align 4
4702 // CHECK4-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
4703 // CHECK4-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
4704 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4
4705 // CHECK4-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
4706 // CHECK4-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
4707 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4
4708 // CHECK4-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
4709 // CHECK4-NEXT: store i64 12, i64* [[TMP147]], align 4
4710 // CHECK4-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8
4711 // CHECK4-NEXT: store i8* null, i8** [[TMP148]], align 4
4712 // CHECK4-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
4713 // CHECK4-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
4714 // CHECK4-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4715 // CHECK4-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4716 // CHECK4-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
4717 // CHECK4-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
4718 // CHECK4: omp_offload.failed23:
4719 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
4720 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT24]]
4721 // CHECK4: omp_offload.cont24:
4722 // CHECK4-NEXT: br label [[OMP_IF_END26:%.*]]
4723 // CHECK4: omp_if.else25:
4724 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
4725 // CHECK4-NEXT: br label [[OMP_IF_END26]]
4726 // CHECK4: omp_if.end26:
4727 // CHECK4-NEXT: store i32 0, i32* [[NN]], align 4
4728 // CHECK4-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
4729 // CHECK4-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4
4730 // CHECK4-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4
4731 // CHECK4-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
4732 // CHECK4-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32*
4733 // CHECK4-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4
4734 // CHECK4-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
4735 // CHECK4-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32*
4736 // CHECK4-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4
4737 // CHECK4-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
4738 // CHECK4-NEXT: store i8* null, i8** [[TMP160]], align 4
4739 // CHECK4-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
4740 // CHECK4-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
4741 // CHECK4-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4742 // CHECK4-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
4743 // CHECK4-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
4744 // CHECK4: omp_offload.failed30:
4745 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]]
4746 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT31]]
4747 // CHECK4: omp_offload.cont31:
4748 // CHECK4-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
4749 // CHECK4-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4
4750 // CHECK4-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4
4751 // CHECK4-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
4752 // CHECK4-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32*
4753 // CHECK4-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4
4754 // CHECK4-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
4755 // CHECK4-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32*
4756 // CHECK4-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4
4757 // CHECK4-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0
4758 // CHECK4-NEXT: store i8* null, i8** [[TMP171]], align 4
4759 // CHECK4-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
4760 // CHECK4-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
4761 // CHECK4-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4762 // CHECK4-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
4763 // CHECK4-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
4764 // CHECK4: omp_offload.failed36:
4765 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]]
4766 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT37]]
4767 // CHECK4: omp_offload.cont37:
4768 // CHECK4-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
4769 // CHECK4-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4770 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
4771 // CHECK4-NEXT: ret i32 [[TMP176]]
4772 //
4773 //
4774 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
4775 // CHECK4-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
4776 // CHECK4-NEXT: entry:
4777 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4778 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4779 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
4780 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4781 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4782 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4783 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4784 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
4785 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4786 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4787 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
4788 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4789 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4790 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4791 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
4792 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4793 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
4794 // CHECK4-NEXT: ret void
4795 //
4796 //
4797 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
4798 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4799 // CHECK4-NEXT: entry:
4800 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4801 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4802 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4803 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4804 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4805 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4806 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4807 // CHECK4-NEXT: ret void
4808 //
4809 //
4810 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
4811 // CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
4812 // CHECK4-NEXT: entry:
4813 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
4814 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
4815 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
4816 // CHECK4-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
4817 // CHECK4-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
4818 // CHECK4-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
4819 // CHECK4-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
4820 // CHECK4-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
4821 // CHECK4-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
4822 // CHECK4-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
4823 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
4824 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
4825 // CHECK4-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
4826 // CHECK4-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
4827 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
4828 // CHECK4-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
4829 // CHECK4-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
4830 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
4831 // CHECK4-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
4832 // CHECK4-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
4833 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
4834 // CHECK4-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
4835 // CHECK4-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
4836 // CHECK4-NEXT: ret void
4837 //
4838 //
4839 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
4840 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
4841 // CHECK4-NEXT: entry:
4842 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
4843 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
4844 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
4845 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
4846 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
4847 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
4848 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
4849 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
4850 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
4851 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
4852 // CHECK4-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
4853 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
4854 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
4855 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
4856 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
4857 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
4858 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4859 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
4860 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4861 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
4862 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
4863 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
4864 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
4865 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
4866 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
4867 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
4868 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
4869 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
4870 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
4871 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
4872 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
4873 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
4874 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
4875 // CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
4876 // CHECK4-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
4877 // CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
4878 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
4879 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
4880 // CHECK4-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
4881 // CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
4882 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
4883 // CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
4884 // CHECK4-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
4885 // CHECK4-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
4886 // CHECK4-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
4887 // CHECK4-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
4888 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
4889 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
4890 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
4891 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
4892 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
4893 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
4894 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
4895 // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
4896 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4897 // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
4898 // CHECK4: omp_offload.failed.i:
4899 // CHECK4-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
4900 // CHECK4-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
4901 // CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
4902 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
4903 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
4904 // CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
4905 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
4906 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
4907 // CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
4908 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
4909 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
4910 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
4911 // CHECK4: .omp_outlined..1.exit:
4912 // CHECK4-NEXT: ret i32 0
4913 //
4914 //
4915 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
4916 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
4917 // CHECK4-NEXT: entry:
4918 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4919 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4920 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4921 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4922 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4923 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4924 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
4925 // CHECK4-NEXT: ret void
4926 //
4927 //
4928 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
4929 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
4930 // CHECK4-NEXT: entry:
4931 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4932 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4933 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4934 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4935 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4936 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4937 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4938 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4939 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
4940 // CHECK4-NEXT: ret void
4941 //
4942 //
4943 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
4944 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
4945 // CHECK4-NEXT: entry:
4946 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4947 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4948 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4949 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4950 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
4951 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4952 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
4953 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4954 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
4955 // CHECK4-NEXT: ret void
4956 //
4957 //
4958 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
4959 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4960 // CHECK4-NEXT: entry:
4961 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4962 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4963 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4964 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4965 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4966 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4967 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4968 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
4969 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
4970 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
4971 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
4972 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
4973 // CHECK4-NEXT: ret void
4974 //
4975 //
4976 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
4977 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4978 // CHECK4-NEXT: entry:
4979 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4980 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4981 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4982 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4983 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4984 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
4985 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4986 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4987 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4988 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4989 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4990 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4991 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
4992 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4993 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
4994 // CHECK4-NEXT: ret void
4995 //
4996 //
4997 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
4998 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4999 // CHECK4-NEXT: entry:
5000 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5001 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5002 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5003 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5004 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5005 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5006 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5007 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5008 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5009 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5010 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5011 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
5012 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
5013 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
5014 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
5015 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
5016 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
5017 // CHECK4-NEXT: ret void
5018 //
5019 //
5020 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
5021 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
5022 // CHECK4-NEXT: entry:
5023 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5024 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
5025 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5026 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
5027 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
5028 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5029 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
5030 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
5031 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
5032 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5033 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5034 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
5035 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5036 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
5037 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
5038 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5039 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
5040 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
5041 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
5042 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
5043 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5044 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
5045 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
5046 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5047 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
5048 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
5049 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
5050 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
5051 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
5052 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
5053 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
5054 // CHECK4-NEXT: ret void
5055 //
5056 //
5057 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
5058 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
5059 // CHECK4-NEXT: entry:
5060 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5061 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5062 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5063 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
5064 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5065 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
5066 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
5067 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5068 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
5069 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
5070 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
5071 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5072 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5073 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5074 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
5075 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5076 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
5077 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
5078 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5079 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
5080 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
5081 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
5082 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
5083 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5084 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
5085 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
5086 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5087 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
5088 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
5089 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
5090 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
5091 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
5092 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
5093 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
5094 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
5095 // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
5096 // CHECK4-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
5097 // CHECK4-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
5098 // CHECK4-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
5099 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
5100 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
5101 // CHECK4-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
5102 // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
5103 // CHECK4-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
5104 // CHECK4-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
5105 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
5106 // CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
5107 // CHECK4-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
5108 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
5109 // CHECK4-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
5110 // CHECK4-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
5111 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
5112 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
5113 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
5114 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
5115 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
5116 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
5117 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
5118 // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
5119 // CHECK4-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
5120 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
5121 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
5122 // CHECK4-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
5123 // CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
5124 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
5125 // CHECK4-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
5126 // CHECK4-NEXT: ret void
5127 //
5128 //
5129 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
5130 // CHECK4-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
5131 // CHECK4-NEXT: entry:
5132 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
5133 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
5134 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
5135 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
5136 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
5137 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
5138 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]])
5139 // CHECK4-NEXT: ret void
5140 //
5141 //
5142 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
5143 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
5144 // CHECK4-NEXT: entry:
5145 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5146 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5147 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
5148 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
5149 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5150 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5151 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
5152 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
5153 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
5154 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
5155 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]])
5156 // CHECK4-NEXT: ret void
5157 //
5158 //
5159 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12
5160 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
5161 // CHECK4-NEXT: entry:
5162 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5163 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5164 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
5165 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5166 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5167 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
5168 // CHECK4-NEXT: ret void
5169 //
5170 //
5171 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
5172 // CHECK4-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
5173 // CHECK4-NEXT: entry:
5174 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
5175 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
5176 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
5177 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
5178 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
5179 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
5180 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]])
5181 // CHECK4-NEXT: ret void
5182 //
5183 //
5184 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15
5185 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
5186 // CHECK4-NEXT: entry:
5187 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5188 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5189 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
5190 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5191 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5192 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
5193 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
5194 // CHECK4-NEXT: ret void
5195 //
5196 //
5197 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16
5198 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
5199 // CHECK4-NEXT: entry:
5200 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5201 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5202 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
5203 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5204 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5205 // CHECK4-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
5206 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
5207 // CHECK4-NEXT: ret void
5208 //
5209 //
5210 // CHECK4-LABEL: define {{[^@]+}}@_Z6bazzzziPi
5211 // CHECK4-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
5212 // CHECK4-NEXT: entry:
5213 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5214 // CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4
5215 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
5216 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
5217 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
5218 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
5219 // CHECK4-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4
5220 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5221 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5222 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32*
5223 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4
5224 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5225 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
5226 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4
5227 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5228 // CHECK4-NEXT: store i8* null, i8** [[TMP5]], align 4
5229 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5230 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5231 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5232 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
5233 // CHECK4-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5234 // CHECK4: omp_offload.failed:
5235 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]]
5236 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
5237 // CHECK4: omp_offload.cont:
5238 // CHECK4-NEXT: ret void
5239 //
5240 //
5241 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
5242 // CHECK4-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] {
5243 // CHECK4-NEXT: entry:
5244 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5245 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5246 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5247 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]])
5248 // CHECK4-NEXT: ret void
5249 //
5250 //
5251 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..19
5252 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] {
5253 // CHECK4-NEXT: entry:
5254 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5255 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5256 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5257 // CHECK4-NEXT: [[F:%.*]] = alloca i32*, align 4
5258 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5259 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5260 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5261 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5262 // CHECK4-NEXT: ret void
5263 //
5264 //
5265 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
5266 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5267 // CHECK4-NEXT: entry:
5268 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5269 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
5270 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
5271 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
5272 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
5273 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5274 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
5275 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
5276 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
5277 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4
5278 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5279 // CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
5280 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5281 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
5282 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
5283 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5284 // CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
5285 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5286 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
5287 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
5288 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
5289 // CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
5290 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
5291 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
5292 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
5293 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
5294 // CHECK4-NEXT: ret i32 [[TMP8]]
5295 //
5296 //
5297 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
5298 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
5299 // CHECK4-NEXT: entry:
5300 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5301 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5302 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4
5303 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
5304 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5305 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
5306 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
5307 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
5308 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
5309 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
5310 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5311 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
5312 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5313 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5314 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5315 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4
5316 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5317 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
5318 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5319 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
5320 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
5321 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5322 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
5323 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
5324 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
5325 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
5326 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
5327 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5328 // CHECK4: omp_if.then:
5329 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
5330 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
5331 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
5332 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
5333 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5334 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
5335 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
5336 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5337 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
5338 // CHECK4-NEXT: store double* [[A]], double** [[TMP13]], align 4
5339 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5340 // CHECK4-NEXT: store i64 8, i64* [[TMP14]], align 4
5341 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5342 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4
5343 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5344 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
5345 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
5346 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5347 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
5348 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
5349 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
5350 // CHECK4-NEXT: store i64 4, i64* [[TMP20]], align 4
5351 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5352 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
5353 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5354 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
5355 // CHECK4-NEXT: store i32 2, i32* [[TMP23]], align 4
5356 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5357 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
5358 // CHECK4-NEXT: store i32 2, i32* [[TMP25]], align 4
5359 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
5360 // CHECK4-NEXT: store i64 4, i64* [[TMP26]], align 4
5361 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5362 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4
5363 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5364 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
5365 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
5366 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5367 // CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
5368 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4
5369 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5370 // CHECK4-NEXT: store i64 4, i64* [[TMP32]], align 4
5371 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
5372 // CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4
5373 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
5374 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
5375 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4
5376 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
5377 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
5378 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4
5379 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
5380 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4
5381 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
5382 // CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4
5383 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5384 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5385 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5386 // CHECK4-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5387 // CHECK4-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
5388 // CHECK4-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5389 // CHECK4: omp_offload.failed:
5390 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
5391 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
5392 // CHECK4: omp_offload.cont:
5393 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
5394 // CHECK4: omp_if.else:
5395 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
5396 // CHECK4-NEXT: br label [[OMP_IF_END]]
5397 // CHECK4: omp_if.end:
5398 // CHECK4-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
5399 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
5400 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5401 // CHECK4-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
5402 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32
5403 // CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
5404 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
5405 // CHECK4-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5406 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
5407 // CHECK4-NEXT: ret i32 [[ADD3]]
5408 //
5409 //
5410 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
5411 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5412 // CHECK4-NEXT: entry:
5413 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5414 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
5415 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
5416 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1
5417 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
5418 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5419 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5420 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
5421 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
5422 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
5423 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
5424 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
5425 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
5426 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
5427 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1
5428 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5429 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5430 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5431 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
5432 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5433 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
5434 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5435 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
5436 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
5437 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
5438 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
5439 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
5440 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
5441 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5442 // CHECK4: omp_if.then:
5443 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5444 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
5445 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
5446 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5447 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
5448 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
5449 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5450 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4
5451 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5452 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
5453 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
5454 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5455 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
5456 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
5457 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5458 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4
5459 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5460 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5461 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
5462 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5463 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
5464 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
5465 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5466 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
5467 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5468 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
5469 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
5470 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5471 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
5472 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
5473 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
5474 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4
5475 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5476 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5477 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5478 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
5479 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5480 // CHECK4: omp_offload.failed:
5481 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
5482 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
5483 // CHECK4: omp_offload.cont:
5484 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
5485 // CHECK4: omp_if.else:
5486 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
5487 // CHECK4-NEXT: br label [[OMP_IF_END]]
5488 // CHECK4: omp_if.end:
5489 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
5490 // CHECK4-NEXT: ret i32 [[TMP31]]
5491 //
5492 //
5493 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5494 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
5495 // CHECK4-NEXT: entry:
5496 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5497 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
5498 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
5499 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
5500 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5501 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5502 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5503 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5504 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5505 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
5506 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
5507 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
5508 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5509 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5510 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5511 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
5512 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5513 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
5514 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5515 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5516 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
5517 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5518 // CHECK4: omp_if.then:
5519 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5520 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
5521 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
5522 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5523 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
5524 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
5525 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5526 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4
5527 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5528 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
5529 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
5530 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5531 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
5532 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
5533 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5534 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4
5535 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5536 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
5537 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
5538 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5539 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
5540 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
5541 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5542 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4
5543 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5544 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5545 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5546 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
5547 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5548 // CHECK4: omp_offload.failed:
5549 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
5550 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
5551 // CHECK4: omp_offload.cont:
5552 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
5553 // CHECK4: omp_if.else:
5554 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
5555 // CHECK4-NEXT: br label [[OMP_IF_END]]
5556 // CHECK4: omp_if.end:
5557 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
5558 // CHECK4-NEXT: ret i32 [[TMP24]]
5559 //
5560 //
5561 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
5562 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
5563 // CHECK4-NEXT: entry:
5564 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5565 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
5566 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5567 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5568 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
5569 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
5570 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5571 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
5572 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5573 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5574 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
5575 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5576 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5577 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5578 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5579 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
5580 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
5581 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
5582 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
5583 // CHECK4-NEXT: ret void
5584 //
5585 //
5586 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..22
5587 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
5588 // CHECK4-NEXT: entry:
5589 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5590 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5591 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5592 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
5593 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5594 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5595 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
5596 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5597 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5598 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5599 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
5600 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5601 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5602 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
5603 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5604 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5605 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5606 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5607 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
5608 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
5609 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
5610 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5611 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4
5612 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5613 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
5614 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
5615 // CHECK4-NEXT: store double [[INC]], double* [[A3]], align 4
5616 // CHECK4-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
5617 // CHECK4-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
5618 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
5619 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5620 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
5621 // CHECK4-NEXT: ret void
5622 //
5623 //
5624 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
5625 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5626 // CHECK4-NEXT: entry:
5627 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5628 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5629 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
5630 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5631 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5632 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5633 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
5634 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5635 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5636 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5637 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5638 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5639 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5640 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5641 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5642 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5643 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5644 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
5645 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5646 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
5647 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5648 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
5649 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
5650 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
5651 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
5652 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
5653 // CHECK4-NEXT: ret void
5654 //
5655 //
5656 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..24
5657 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5658 // CHECK4-NEXT: entry:
5659 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5660 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5661 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5662 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5663 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
5664 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5665 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5666 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5667 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5668 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5669 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5670 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5671 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5672 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5673 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5674 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5675 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
5676 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
5677 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
5678 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
5679 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
5680 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5681 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
5682 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
5683 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
5684 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
5685 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
5686 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
5687 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5688 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5689 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
5690 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
5691 // CHECK4-NEXT: ret void
5692 //
5693 //
5694 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
5695 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5696 // CHECK4-NEXT: entry:
5697 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5698 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5699 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5700 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5701 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5702 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5703 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5704 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5705 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5706 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5707 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5708 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5709 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5710 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
5711 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5712 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
5713 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5714 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
5715 // CHECK4-NEXT: ret void
5716 //
5717 //
5718 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..27
5719 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5720 // CHECK4-NEXT: entry:
5721 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5722 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5723 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5724 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5725 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5726 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5727 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5728 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5729 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
5730 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5731 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5732 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5733 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5734 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
5735 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
5736 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
5737 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
5738 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
5739 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
5740 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
5741 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5742 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5743 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
5744 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
5745 // CHECK4-NEXT: ret void
5746 //
5747 //
5748 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5749 // CHECK4-SAME: () #[[ATTR4]] {
5750 // CHECK4-NEXT: entry:
5751 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
5752 // CHECK4-NEXT: ret void
5753 //
5754 //
5755 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
5756 // CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
5757 // CHECK9-NEXT: entry:
5758 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5759 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
5760 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
5761 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
5762 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
5763 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5764 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
5765 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
5766 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5767 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
5768 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
5769 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
5770 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
5771 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
5772 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
5773 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5774 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
5775 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5776 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
5777 // CHECK9-NEXT: ret void
5778 //
5779 //
5780 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
5781 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5782 // CHECK9-NEXT: entry:
5783 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5784 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5785 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5786 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5787 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5788 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5789 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5790 // CHECK9-NEXT: ret void
5791 //
5792 //
5793 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
5794 // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
5795 // CHECK9-NEXT: entry:
5796 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5797 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
5798 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5799 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5800 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
5801 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5802 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
5803 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5804 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
5805 // CHECK9-NEXT: ret void
5806 //
5807 //
5808 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
5809 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5810 // CHECK9-NEXT: entry:
5811 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5812 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5813 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5814 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5815 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5816 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5817 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5818 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
5819 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
5820 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
5821 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
5822 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
5823 // CHECK9-NEXT: ret void
5824 //
5825 //
5826 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
5827 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5828 // CHECK9-NEXT: entry:
5829 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5830 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5831 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
5832 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
5833 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5834 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5835 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5836 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5837 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5838 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5839 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
5840 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5841 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5842 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5843 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
5844 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5845 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
5846 // CHECK9-NEXT: ret void
5847 //
5848 //
5849 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
5850 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5851 // CHECK9-NEXT: entry:
5852 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5853 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5854 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5855 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5856 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5857 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5858 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5859 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5860 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5861 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5862 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5863 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5864 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
5865 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
5866 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
5867 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
5868 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5869 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
5870 // CHECK9-NEXT: ret void
5871 //
5872 //
5873 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
5874 // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
5875 // CHECK9-NEXT: entry:
5876 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5877 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
5878 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
5879 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
5880 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
5881 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
5882 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
5883 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
5884 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
5885 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
5886 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5887 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
5888 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5889 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
5890 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
5891 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5892 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
5893 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
5894 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
5895 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5896 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
5897 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5898 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
5899 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
5900 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5901 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
5902 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
5903 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
5904 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
5905 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5906 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
5907 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
5908 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
5909 // CHECK9-NEXT: ret void
5910 //
5911 //
5912 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
5913 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
5914 // CHECK9-NEXT: entry:
5915 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5916 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5917 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5918 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
5919 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
5920 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
5921 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
5922 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
5923 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
5924 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
5925 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
5926 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5927 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5928 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5929 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
5930 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5931 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
5932 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
5933 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5934 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
5935 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
5936 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
5937 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5938 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
5939 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5940 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
5941 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
5942 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5943 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
5944 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
5945 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
5946 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
5947 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
5948 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
5949 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
5950 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
5951 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
5952 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
5953 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
5954 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
5955 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
5956 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
5957 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
5958 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
5959 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
5960 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
5961 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
5962 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
5963 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
5964 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
5965 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
5966 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
5967 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
5968 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
5969 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
5970 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
5971 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
5972 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
5973 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
5974 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
5975 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
5976 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
5977 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
5978 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
5979 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
5980 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
5981 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
5982 // CHECK9-NEXT: ret void
5983 //
5984 //
5985 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
5986 // CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
5987 // CHECK9-NEXT: entry:
5988 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
5989 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
5990 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
5991 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
5992 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5993 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
5994 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
5995 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
5996 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
5997 // CHECK9-NEXT: ret void
5998 //
5999 //
6000 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
6001 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
6002 // CHECK9-NEXT: entry:
6003 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6004 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6005 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6006 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
6007 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6008 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6009 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6010 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6011 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6012 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
6013 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
6014 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
6015 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
6016 // CHECK9-NEXT: ret void
6017 //
6018 //
6019 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
6020 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
6021 // CHECK9-NEXT: entry:
6022 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6023 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6024 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6025 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6026 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6027 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6028 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6029 // CHECK9-NEXT: ret void
6030 //
6031 //
6032 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
6033 // CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
6034 // CHECK9-NEXT: entry:
6035 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6036 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
6037 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6038 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6039 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6040 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
6041 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
6042 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
6043 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
6044 // CHECK9-NEXT: ret void
6045 //
6046 //
6047 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
6048 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
6049 // CHECK9-NEXT: entry:
6050 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6051 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6052 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6053 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6054 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6055 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6056 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6057 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]])
6058 // CHECK9-NEXT: ret void
6059 //
6060 //
6061 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7
6062 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
6063 // CHECK9-NEXT: entry:
6064 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6065 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6066 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
6067 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6068 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6069 // CHECK9-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
6070 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
6071 // CHECK9-NEXT: ret void
6072 //
6073 //
6074 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
6075 // CHECK9-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] {
6076 // CHECK9-NEXT: entry:
6077 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6078 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6079 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6080 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]])
6081 // CHECK9-NEXT: ret void
6082 //
6083 //
6084 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8
6085 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] {
6086 // CHECK9-NEXT: entry:
6087 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6088 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6089 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6090 // CHECK9-NEXT: [[F:%.*]] = alloca i32*, align 8
6091 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6092 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6093 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6094 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6095 // CHECK9-NEXT: ret void
6096 //
6097 //
6098 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
6099 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6100 // CHECK9-NEXT: entry:
6101 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6102 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6103 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
6104 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6105 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6106 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6107 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
6108 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6109 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6110 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
6111 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6112 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6113 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6114 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
6115 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6116 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6117 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6118 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
6119 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6120 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
6121 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6122 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
6123 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6124 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
6125 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
6126 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
6127 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
6128 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
6129 // CHECK9-NEXT: ret void
6130 //
6131 //
6132 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9
6133 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6134 // CHECK9-NEXT: entry:
6135 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6136 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6137 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6138 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6139 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
6140 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6141 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6142 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6143 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6144 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6145 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
6146 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6147 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6148 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6149 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
6150 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6151 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6152 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6153 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
6154 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6155 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
6156 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6157 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6158 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
6159 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
6160 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
6161 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
6162 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
6163 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
6164 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
6165 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6166 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
6167 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
6168 // CHECK9-NEXT: ret void
6169 //
6170 //
6171 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
6172 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6173 // CHECK9-NEXT: entry:
6174 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6175 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
6176 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6177 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6178 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
6179 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
6180 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6181 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
6182 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6183 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6184 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
6185 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6186 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6187 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6188 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6189 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
6190 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
6191 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
6192 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
6193 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
6194 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
6195 // CHECK9-NEXT: ret void
6196 //
6197 //
6198 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10
6199 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6200 // CHECK9-NEXT: entry:
6201 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6202 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6203 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6204 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
6205 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6206 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6207 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
6208 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6209 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6210 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6211 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
6212 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6213 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6214 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
6215 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6216 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6217 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6218 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6219 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
6220 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
6221 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
6222 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
6223 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6224 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
6225 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6226 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
6227 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
6228 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8
6229 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
6230 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
6231 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
6232 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
6233 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
6234 // CHECK9-NEXT: ret void
6235 //
6236 //
6237 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
6238 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6239 // CHECK9-NEXT: entry:
6240 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6241 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6242 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6243 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6244 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6245 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6246 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6247 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6248 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6249 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6250 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6251 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6252 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6253 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
6254 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6255 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
6256 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6257 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
6258 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6259 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
6260 // CHECK9-NEXT: ret void
6261 //
6262 //
6263 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11
6264 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6265 // CHECK9-NEXT: entry:
6266 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6267 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6268 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6269 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6270 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6271 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6272 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6273 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6274 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6275 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6276 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6277 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6278 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6279 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6280 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6281 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
6282 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6283 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
6284 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6285 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6286 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
6287 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
6288 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6289 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
6290 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
6291 // CHECK9-NEXT: ret void
6292 //
6293 //
6294 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
6295 // CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
6296 // CHECK10-NEXT: entry:
6297 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6298 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6299 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
6300 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6301 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
6302 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6303 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6304 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
6305 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6306 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
6307 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
6308 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
6309 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
6310 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
6311 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
6312 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6313 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
6314 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6315 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
6316 // CHECK10-NEXT: ret void
6317 //
6318 //
6319 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
6320 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
6321 // CHECK10-NEXT: entry:
6322 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6323 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6324 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6325 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6326 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6327 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6328 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6329 // CHECK10-NEXT: ret void
6330 //
6331 //
6332 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
6333 // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
6334 // CHECK10-NEXT: entry:
6335 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6336 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6337 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6338 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6339 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
6340 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6341 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
6342 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6343 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
6344 // CHECK10-NEXT: ret void
6345 //
6346 //
6347 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
6348 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
6349 // CHECK10-NEXT: entry:
6350 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6351 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6352 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6353 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6354 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6355 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6356 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6357 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
6358 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
6359 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
6360 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
6361 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
6362 // CHECK10-NEXT: ret void
6363 //
6364 //
6365 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
6366 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
6367 // CHECK10-NEXT: entry:
6368 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6369 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6370 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6371 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6372 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6373 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6374 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6375 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6376 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6377 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6378 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
6379 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
6380 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6381 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6382 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
6383 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6384 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
6385 // CHECK10-NEXT: ret void
6386 //
6387 //
6388 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
6389 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
6390 // CHECK10-NEXT: entry:
6391 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6392 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6393 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6394 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6395 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6396 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6397 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6398 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6399 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6400 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6401 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6402 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6403 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
6404 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
6405 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
6406 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6407 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6408 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
6409 // CHECK10-NEXT: ret void
6410 //
6411 //
6412 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
6413 // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
6414 // CHECK10-NEXT: entry:
6415 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6416 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
6417 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6418 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
6419 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
6420 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6421 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
6422 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
6423 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
6424 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6425 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6426 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
6427 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6428 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
6429 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
6430 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6431 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
6432 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
6433 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
6434 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6435 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
6436 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6437 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
6438 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
6439 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6440 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
6441 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
6442 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
6443 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
6444 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6445 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
6446 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
6447 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
6448 // CHECK10-NEXT: ret void
6449 //
6450 //
6451 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
6452 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
6453 // CHECK10-NEXT: entry:
6454 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6455 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6456 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6457 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
6458 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6459 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
6460 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
6461 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6462 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
6463 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
6464 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
6465 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6466 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6467 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6468 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
6469 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6470 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
6471 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
6472 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6473 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
6474 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
6475 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
6476 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6477 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
6478 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6479 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
6480 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
6481 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6482 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
6483 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
6484 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
6485 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
6486 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
6487 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
6488 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
6489 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
6490 // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
6491 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
6492 // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
6493 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
6494 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
6495 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
6496 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
6497 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
6498 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
6499 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
6500 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
6501 // CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
6502 // CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
6503 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
6504 // CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
6505 // CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
6506 // CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
6507 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
6508 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
6509 // CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
6510 // CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
6511 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6512 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
6513 // CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
6514 // CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
6515 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6516 // CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
6517 // CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
6518 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
6519 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
6520 // CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
6521 // CHECK10-NEXT: ret void
6522 //
6523 //
6524 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
6525 // CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
6526 // CHECK10-NEXT: entry:
6527 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6528 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
6529 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6530 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6531 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6532 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
6533 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
6534 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
6535 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
6536 // CHECK10-NEXT: ret void
6537 //
6538 //
6539 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
6540 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
6541 // CHECK10-NEXT: entry:
6542 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6543 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6544 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6545 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
6546 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6547 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6548 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6549 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6550 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6551 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
6552 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
6553 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
6554 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
6555 // CHECK10-NEXT: ret void
6556 //
6557 //
6558 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
6559 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
6560 // CHECK10-NEXT: entry:
6561 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6562 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6563 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6564 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6565 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6566 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6567 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6568 // CHECK10-NEXT: ret void
6569 //
6570 //
6571 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
6572 // CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
6573 // CHECK10-NEXT: entry:
6574 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6575 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
6576 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6577 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6578 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6579 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
6580 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
6581 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
6582 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
6583 // CHECK10-NEXT: ret void
6584 //
6585 //
6586 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
6587 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
6588 // CHECK10-NEXT: entry:
6589 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6590 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6591 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
6592 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6593 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6594 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
6595 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
6596 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]])
6597 // CHECK10-NEXT: ret void
6598 //
6599 //
6600 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7
6601 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
6602 // CHECK10-NEXT: entry:
6603 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6604 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6605 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
6606 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6607 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6608 // CHECK10-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
6609 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
6610 // CHECK10-NEXT: ret void
6611 //
6612 //
6613 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
6614 // CHECK10-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] {
6615 // CHECK10-NEXT: entry:
6616 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6617 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6618 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6619 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]])
6620 // CHECK10-NEXT: ret void
6621 //
6622 //
6623 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8
6624 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] {
6625 // CHECK10-NEXT: entry:
6626 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6627 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6628 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6629 // CHECK10-NEXT: [[F:%.*]] = alloca i32*, align 8
6630 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6631 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6632 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6633 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6634 // CHECK10-NEXT: ret void
6635 //
6636 //
6637 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
6638 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6639 // CHECK10-NEXT: entry:
6640 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6641 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6642 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
6643 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6644 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6645 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6646 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
6647 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6648 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6649 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
6650 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6651 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6652 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6653 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
6654 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6655 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6656 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6657 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
6658 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6659 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
6660 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6661 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
6662 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6663 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
6664 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
6665 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
6666 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
6667 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
6668 // CHECK10-NEXT: ret void
6669 //
6670 //
6671 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9
6672 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6673 // CHECK10-NEXT: entry:
6674 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6675 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6676 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6677 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6678 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
6679 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6680 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6681 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6682 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6683 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6684 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
6685 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6686 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6687 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6688 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
6689 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6690 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6691 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6692 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
6693 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6694 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
6695 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6696 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6697 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
6698 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
6699 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
6700 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
6701 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
6702 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
6703 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
6704 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6705 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
6706 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
6707 // CHECK10-NEXT: ret void
6708 //
6709 //
6710 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
6711 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6712 // CHECK10-NEXT: entry:
6713 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6714 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
6715 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6716 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6717 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
6718 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
6719 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6720 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
6721 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6722 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6723 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
6724 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6725 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6726 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6727 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6728 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
6729 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
6730 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
6731 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
6732 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
6733 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
6734 // CHECK10-NEXT: ret void
6735 //
6736 //
6737 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10
6738 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6739 // CHECK10-NEXT: entry:
6740 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6741 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6742 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6743 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
6744 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
6745 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
6746 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
6747 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6748 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6749 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6750 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
6751 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
6752 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
6753 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
6754 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6755 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6756 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
6757 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
6758 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
6759 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
6760 // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
6761 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
6762 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6763 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
6764 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6765 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
6766 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
6767 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8
6768 // CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
6769 // CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
6770 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
6771 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
6772 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
6773 // CHECK10-NEXT: ret void
6774 //
6775 //
6776 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
6777 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6778 // CHECK10-NEXT: entry:
6779 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6780 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6781 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6782 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
6783 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
6784 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6785 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6786 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6787 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6788 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6789 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6790 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6791 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6792 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
6793 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6794 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
6795 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6796 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
6797 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6798 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
6799 // CHECK10-NEXT: ret void
6800 //
6801 //
6802 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11
6803 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6804 // CHECK10-NEXT: entry:
6805 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6806 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6807 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6808 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
6809 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6810 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6811 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6812 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
6813 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
6814 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6815 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6816 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6817 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6818 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6819 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6820 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
6821 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6822 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
6823 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6824 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6825 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
6826 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
6827 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6828 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
6829 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
6830 // CHECK10-NEXT: ret void
6831 //
6832 //
6833 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
6834 // CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
6835 // CHECK11-NEXT: entry:
6836 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6837 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6838 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
6839 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
6840 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
6841 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6842 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6843 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
6844 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6845 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6846 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
6847 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
6848 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6849 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6850 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
6851 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6852 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
6853 // CHECK11-NEXT: ret void
6854 //
6855 //
6856 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
6857 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6858 // CHECK11-NEXT: entry:
6859 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6860 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6861 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6862 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6863 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6864 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6865 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6866 // CHECK11-NEXT: ret void
6867 //
6868 //
6869 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
6870 // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
6871 // CHECK11-NEXT: entry:
6872 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6873 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
6874 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6875 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6876 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6877 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6878 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
6879 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6880 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6881 // CHECK11-NEXT: ret void
6882 //
6883 //
6884 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
6885 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6886 // CHECK11-NEXT: entry:
6887 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6888 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6889 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6890 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6891 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6892 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6893 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6894 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6895 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
6896 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
6897 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
6898 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
6899 // CHECK11-NEXT: ret void
6900 //
6901 //
6902 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
6903 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6904 // CHECK11-NEXT: entry:
6905 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
6906 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6907 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
6908 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
6909 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
6910 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6911 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6912 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6913 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6914 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6915 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6916 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6917 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
6918 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6919 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6920 // CHECK11-NEXT: ret void
6921 //
6922 //
6923 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
6924 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6925 // CHECK11-NEXT: entry:
6926 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6927 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6928 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
6929 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6930 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6931 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6932 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
6933 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6934 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6935 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6936 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6937 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
6938 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
6939 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
6940 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
6941 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6942 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
6943 // CHECK11-NEXT: ret void
6944 //
6945 //
6946 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
6947 // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
6948 // CHECK11-NEXT: entry:
6949 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
6950 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6951 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
6952 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
6953 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6954 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
6955 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
6956 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
6957 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6958 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
6959 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
6960 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6961 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6962 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
6963 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6964 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6965 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6966 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
6967 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6968 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6969 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6970 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6971 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6972 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6973 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6974 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6975 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6976 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6977 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6978 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6979 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
6980 // CHECK11-NEXT: ret void
6981 //
6982 //
6983 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
6984 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
6985 // CHECK11-NEXT: entry:
6986 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6987 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6988 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
6989 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6990 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
6991 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
6992 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6993 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
6994 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
6995 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
6996 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6997 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6998 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6999 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7000 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
7001 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7002 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
7003 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
7004 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7005 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
7006 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
7007 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
7008 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
7009 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7010 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
7011 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
7012 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7013 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
7014 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
7015 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
7016 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
7017 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
7018 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7019 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
7020 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
7021 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
7022 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
7023 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
7024 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
7025 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
7026 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
7027 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
7028 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
7029 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
7030 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
7031 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
7032 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
7033 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
7034 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
7035 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
7036 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
7037 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
7038 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
7039 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
7040 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
7041 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
7042 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
7043 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
7044 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
7045 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
7046 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
7047 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
7048 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
7049 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
7050 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
7051 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
7052 // CHECK11-NEXT: ret void
7053 //
7054 //
7055 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
7056 // CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
7057 // CHECK11-NEXT: entry:
7058 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7059 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
7060 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7061 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
7062 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
7063 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
7064 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7065 // CHECK11-NEXT: ret void
7066 //
7067 //
7068 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
7069 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
7070 // CHECK11-NEXT: entry:
7071 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7072 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7073 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7074 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
7075 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7076 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7077 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7078 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
7079 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
7080 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
7081 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7082 // CHECK11-NEXT: ret void
7083 //
7084 //
7085 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
7086 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
7087 // CHECK11-NEXT: entry:
7088 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7089 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7090 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7091 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7092 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7093 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7094 // CHECK11-NEXT: ret void
7095 //
7096 //
7097 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
7098 // CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
7099 // CHECK11-NEXT: entry:
7100 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7101 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
7102 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7103 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
7104 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
7105 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
7106 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7107 // CHECK11-NEXT: ret void
7108 //
7109 //
7110 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
7111 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
7112 // CHECK11-NEXT: entry:
7113 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7114 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7115 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7116 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7117 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7118 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7119 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
7120 // CHECK11-NEXT: ret void
7121 //
7122 //
7123 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7
7124 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
7125 // CHECK11-NEXT: entry:
7126 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7127 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7128 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
7129 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7130 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7131 // CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
7132 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
7133 // CHECK11-NEXT: ret void
7134 //
7135 //
7136 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
7137 // CHECK11-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] {
7138 // CHECK11-NEXT: entry:
7139 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7140 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7141 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7142 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]])
7143 // CHECK11-NEXT: ret void
7144 //
7145 //
7146 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8
7147 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] {
7148 // CHECK11-NEXT: entry:
7149 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7150 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7151 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7152 // CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4
7153 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7154 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7155 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7156 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7157 // CHECK11-NEXT: ret void
7158 //
7159 //
7160 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
7161 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7162 // CHECK11-NEXT: entry:
7163 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7164 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7165 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
7166 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7167 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7168 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7169 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
7170 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7171 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7172 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
7173 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7174 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7175 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
7176 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7177 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7178 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7179 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7180 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
7181 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7182 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
7183 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7184 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
7185 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
7186 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
7187 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
7188 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
7189 // CHECK11-NEXT: ret void
7190 //
7191 //
7192 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9
7193 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7194 // CHECK11-NEXT: entry:
7195 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7196 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7197 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7198 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7199 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
7200 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7201 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7202 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7203 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7204 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7205 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
7206 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7207 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7208 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
7209 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7210 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7211 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7212 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7213 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7214 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
7215 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
7216 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
7217 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
7218 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
7219 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
7220 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
7221 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
7222 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
7223 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7224 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7225 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
7226 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
7227 // CHECK11-NEXT: ret void
7228 //
7229 //
7230 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
7231 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
7232 // CHECK11-NEXT: entry:
7233 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7234 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
7235 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7236 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
7237 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
7238 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
7239 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7240 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
7241 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7242 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7243 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
7244 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7245 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7246 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7247 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
7248 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
7249 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
7250 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
7251 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
7252 // CHECK11-NEXT: ret void
7253 //
7254 //
7255 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10
7256 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
7257 // CHECK11-NEXT: entry:
7258 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7259 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7260 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7261 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
7262 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7263 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
7264 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
7265 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7266 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7267 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7268 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
7269 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7270 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7271 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
7272 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7273 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7274 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7275 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
7276 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
7277 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
7278 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7279 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7280 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4
7281 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
7282 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
7283 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
7284 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4
7285 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
7286 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
7287 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
7288 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7289 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7290 // CHECK11-NEXT: ret void
7291 //
7292 //
7293 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
7294 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7295 // CHECK11-NEXT: entry:
7296 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7297 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7298 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7299 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7300 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7301 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7302 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7303 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7304 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7305 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7306 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7307 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7308 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7309 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
7310 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7311 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
7312 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7313 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
7314 // CHECK11-NEXT: ret void
7315 //
7316 //
7317 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11
7318 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7319 // CHECK11-NEXT: entry:
7320 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7321 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7322 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7323 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7324 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7325 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7326 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7327 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7328 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7329 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7330 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7331 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7332 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7333 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7334 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7335 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7336 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
7337 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
7338 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
7339 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
7340 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7341 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7342 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
7343 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
7344 // CHECK11-NEXT: ret void
7345 //
7346 //
7347 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
7348 // CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
7349 // CHECK12-NEXT: entry:
7350 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7351 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7352 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
7353 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7354 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
7355 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7356 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7357 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
7358 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7359 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7360 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
7361 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
7362 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
7363 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7364 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
7365 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7366 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
7367 // CHECK12-NEXT: ret void
7368 //
7369 //
7370 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
7371 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
7372 // CHECK12-NEXT: entry:
7373 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7374 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7375 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7376 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7377 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7378 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7379 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7380 // CHECK12-NEXT: ret void
7381 //
7382 //
7383 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
7384 // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
7385 // CHECK12-NEXT: entry:
7386 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7387 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7388 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7389 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7390 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
7391 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7392 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
7393 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7394 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7395 // CHECK12-NEXT: ret void
7396 //
7397 //
7398 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
7399 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
7400 // CHECK12-NEXT: entry:
7401 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7402 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7403 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7404 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7405 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7406 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7407 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7408 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
7409 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
7410 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
7411 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
7412 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
7413 // CHECK12-NEXT: ret void
7414 //
7415 //
7416 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
7417 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
7418 // CHECK12-NEXT: entry:
7419 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7420 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7421 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7422 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7423 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7424 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7425 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7426 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7427 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
7428 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
7429 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7430 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7431 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
7432 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7433 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
7434 // CHECK12-NEXT: ret void
7435 //
7436 //
7437 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
7438 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
7439 // CHECK12-NEXT: entry:
7440 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7441 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7442 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7443 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7444 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7445 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7446 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7447 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7448 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7449 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7450 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7451 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7452 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
7453 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
7454 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
7455 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
7456 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
7457 // CHECK12-NEXT: ret void
7458 //
7459 //
7460 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
7461 // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
7462 // CHECK12-NEXT: entry:
7463 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7464 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
7465 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7466 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
7467 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
7468 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
7469 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
7470 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
7471 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
7472 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7473 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7474 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
7475 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7476 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
7477 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
7478 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7479 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
7480 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
7481 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
7482 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
7483 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7484 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
7485 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
7486 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7487 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
7488 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
7489 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
7490 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
7491 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
7492 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
7493 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
7494 // CHECK12-NEXT: ret void
7495 //
7496 //
7497 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
7498 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
7499 // CHECK12-NEXT: entry:
7500 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7501 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7502 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7503 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
7504 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7505 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
7506 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
7507 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
7508 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
7509 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
7510 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
7511 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7512 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7513 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7514 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
7515 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7516 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
7517 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
7518 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7519 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
7520 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
7521 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
7522 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
7523 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7524 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
7525 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
7526 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7527 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
7528 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
7529 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
7530 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
7531 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
7532 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7533 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
7534 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
7535 // CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
7536 // CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
7537 // CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
7538 // CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
7539 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
7540 // CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
7541 // CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
7542 // CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
7543 // CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
7544 // CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
7545 // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
7546 // CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
7547 // CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
7548 // CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
7549 // CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
7550 // CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
7551 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
7552 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
7553 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
7554 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
7555 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
7556 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
7557 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
7558 // CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
7559 // CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
7560 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
7561 // CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
7562 // CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
7563 // CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
7564 // CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
7565 // CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
7566 // CHECK12-NEXT: ret void
7567 //
7568 //
7569 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
7570 // CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
7571 // CHECK12-NEXT: entry:
7572 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7573 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
7574 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7575 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
7576 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
7577 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
7578 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7579 // CHECK12-NEXT: ret void
7580 //
7581 //
7582 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
7583 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
7584 // CHECK12-NEXT: entry:
7585 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7586 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7587 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7588 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
7589 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7590 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7591 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7592 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
7593 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
7594 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
7595 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7596 // CHECK12-NEXT: ret void
7597 //
7598 //
7599 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
7600 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
7601 // CHECK12-NEXT: entry:
7602 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7603 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7604 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7605 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7606 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7607 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7608 // CHECK12-NEXT: ret void
7609 //
7610 //
7611 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
7612 // CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
7613 // CHECK12-NEXT: entry:
7614 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7615 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
7616 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7617 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
7618 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
7619 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
7620 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]])
7621 // CHECK12-NEXT: ret void
7622 //
7623 //
7624 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
7625 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
7626 // CHECK12-NEXT: entry:
7627 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7628 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7629 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
7630 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7631 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7632 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
7633 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
7634 // CHECK12-NEXT: ret void
7635 //
7636 //
7637 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7
7638 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
7639 // CHECK12-NEXT: entry:
7640 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7641 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7642 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
7643 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7644 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7645 // CHECK12-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
7646 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
7647 // CHECK12-NEXT: ret void
7648 //
7649 //
7650 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
7651 // CHECK12-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] {
7652 // CHECK12-NEXT: entry:
7653 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7654 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7655 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7656 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]])
7657 // CHECK12-NEXT: ret void
7658 //
7659 //
7660 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8
7661 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] {
7662 // CHECK12-NEXT: entry:
7663 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7664 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7665 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7666 // CHECK12-NEXT: [[F:%.*]] = alloca i32*, align 4
7667 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7668 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7669 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7670 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7671 // CHECK12-NEXT: ret void
7672 //
7673 //
7674 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
7675 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7676 // CHECK12-NEXT: entry:
7677 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7678 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7679 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
7680 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7681 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7682 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7683 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
7684 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7685 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7686 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
7687 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7688 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7689 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
7690 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7691 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7692 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7693 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7694 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
7695 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7696 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
7697 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7698 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
7699 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
7700 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
7701 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
7702 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
7703 // CHECK12-NEXT: ret void
7704 //
7705 //
7706 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9
7707 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7708 // CHECK12-NEXT: entry:
7709 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7710 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7711 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7712 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7713 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
7714 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7715 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7716 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7717 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7718 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7719 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
7720 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7721 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7722 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
7723 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7724 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7725 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7726 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7727 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7728 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
7729 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
7730 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
7731 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
7732 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
7733 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
7734 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
7735 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
7736 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
7737 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7738 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7739 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
7740 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
7741 // CHECK12-NEXT: ret void
7742 //
7743 //
7744 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
7745 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
7746 // CHECK12-NEXT: entry:
7747 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7748 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
7749 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7750 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
7751 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
7752 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
7753 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7754 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
7755 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7756 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7757 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
7758 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7759 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7760 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7761 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
7762 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
7763 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
7764 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
7765 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
7766 // CHECK12-NEXT: ret void
7767 //
7768 //
7769 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10
7770 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
7771 // CHECK12-NEXT: entry:
7772 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7773 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7774 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7775 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
7776 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
7777 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
7778 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
7779 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7780 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7781 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7782 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
7783 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7784 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7785 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
7786 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7787 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7788 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7789 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
7790 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
7791 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
7792 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7793 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7794 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4
7795 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
7796 // CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
7797 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
7798 // CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4
7799 // CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
7800 // CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
7801 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
7802 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7803 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7804 // CHECK12-NEXT: ret void
7805 //
7806 //
7807 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
7808 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7809 // CHECK12-NEXT: entry:
7810 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7811 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7812 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7813 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7814 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7815 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7816 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7817 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7818 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7819 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7820 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7821 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7822 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7823 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
7824 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7825 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
7826 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7827 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
7828 // CHECK12-NEXT: ret void
7829 //
7830 //
7831 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11
7832 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
7833 // CHECK12-NEXT: entry:
7834 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7835 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7836 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7837 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7838 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7839 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7840 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7841 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7842 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7843 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7844 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7845 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7846 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7847 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7848 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
7849 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7850 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
7851 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
7852 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
7853 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
7854 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7855 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7856 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
7857 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
7858 // CHECK12-NEXT: ret void
7859 //
7860 //
7861 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
7862 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7863 // CHECK17-NEXT: entry:
7864 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
7865 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
7866 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
7867 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4
7868 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
7869 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7870 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
7871 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7872 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7873 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7874 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7875 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
7876 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
7877 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
7878 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
7879 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
7880 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
7881 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
7882 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
7883 // CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8
7884 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
7885 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
7886 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
7887 // CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8
7888 // CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8
7889 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
7890 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
7891 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
7892 // CHECK17-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8
7893 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8
7894 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8
7895 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8
7896 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
7897 // CHECK17-NEXT: [[NN:%.*]] = alloca i32, align 4
7898 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
7899 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8
7900 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8
7901 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8
7902 // CHECK17-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8
7903 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8
7904 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8
7905 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8
7906 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
7907 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
7908 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
7909 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
7910 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7911 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7912 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
7913 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7914 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
7915 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7916 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7917 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
7918 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
7919 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
7920 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
7921 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7922 // CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
7923 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7924 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7925 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
7926 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7927 // CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
7928 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7929 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7930 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
7931 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
7932 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
7933 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7934 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
7935 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4
7936 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
7937 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7938 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
7939 // CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8
7940 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7941 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
7942 // CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8
7943 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
7944 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8
7945 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7946 // CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
7947 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8
7948 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7949 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
7950 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8
7951 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
7952 // CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8
7953 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7954 // CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
7955 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8
7956 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7957 // CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
7958 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8
7959 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
7960 // CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8
7961 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7962 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7963 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
7964 // CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
7965 // CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
7966 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
7967 // CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7968 // CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
7969 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
7970 // CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7971 // CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
7972 // CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
7973 // CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
7974 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
7975 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
7976 // CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
7977 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
7978 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
7979 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
7980 // CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
7981 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
7982 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
7983 // CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
7984 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
7985 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
7986 // CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
7987 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
7988 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
7989 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
7990 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
7991 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
7992 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
7993 // CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
7994 // CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8
7995 // CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]])
7996 // CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
7997 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7998 // CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4
7999 // CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
8000 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
8001 // CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
8002 // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
8003 // CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2
8004 // CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
8005 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
8006 // CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
8007 // CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8
8008 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
8009 // CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
8010 // CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8
8011 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
8012 // CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8
8013 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
8014 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
8015 // CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8016 // CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
8017 // CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8018 // CHECK17: omp_offload.failed:
8019 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]]
8020 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
8021 // CHECK17: omp_offload.cont:
8022 // CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4
8023 // CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
8024 // CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4
8025 // CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
8026 // CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
8027 // CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
8028 // CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2
8029 // CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
8030 // CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
8031 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
8032 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8033 // CHECK17: omp_if.then:
8034 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
8035 // CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
8036 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8
8037 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
8038 // CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
8039 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8
8040 // CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
8041 // CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8
8042 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
8043 // CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
8044 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8
8045 // CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
8046 // CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
8047 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8
8048 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
8049 // CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8
8050 // CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
8051 // CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
8052 // CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8053 // CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
8054 // CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
8055 // CHECK17: omp_offload.failed19:
8056 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
8057 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]]
8058 // CHECK17: omp_offload.cont20:
8059 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
8060 // CHECK17: omp_if.else:
8061 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
8062 // CHECK17-NEXT: br label [[OMP_IF_END]]
8063 // CHECK17: omp_if.end:
8064 // CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4
8065 // CHECK17-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32*
8066 // CHECK17-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4
8067 // CHECK17-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8
8068 // CHECK17-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
8069 // CHECK17-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20
8070 // CHECK17-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]]
8071 // CHECK17: omp_if.then24:
8072 // CHECK17-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
8073 // CHECK17-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
8074 // CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
8075 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
8076 // CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64*
8077 // CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8
8078 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
8079 // CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64*
8080 // CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8
8081 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8082 // CHECK17-NEXT: store i64 4, i64* [[TMP99]], align 8
8083 // CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0
8084 // CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8
8085 // CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1
8086 // CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
8087 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
8088 // CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1
8089 // CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
8090 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
8091 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
8092 // CHECK17-NEXT: store i64 40, i64* [[TMP105]], align 8
8093 // CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1
8094 // CHECK17-NEXT: store i8* null, i8** [[TMP106]], align 8
8095 // CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2
8096 // CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64*
8097 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8
8098 // CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2
8099 // CHECK17-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64*
8100 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8
8101 // CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
8102 // CHECK17-NEXT: store i64 8, i64* [[TMP111]], align 8
8103 // CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2
8104 // CHECK17-NEXT: store i8* null, i8** [[TMP112]], align 8
8105 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3
8106 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
8107 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP114]], align 8
8108 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3
8109 // CHECK17-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
8110 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP116]], align 8
8111 // CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
8112 // CHECK17-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8
8113 // CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3
8114 // CHECK17-NEXT: store i8* null, i8** [[TMP118]], align 8
8115 // CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4
8116 // CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
8117 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
8118 // CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4
8119 // CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
8120 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8
8121 // CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8122 // CHECK17-NEXT: store i64 400, i64* [[TMP123]], align 8
8123 // CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4
8124 // CHECK17-NEXT: store i8* null, i8** [[TMP124]], align 8
8125 // CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5
8126 // CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
8127 // CHECK17-NEXT: store i64 5, i64* [[TMP126]], align 8
8128 // CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5
8129 // CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
8130 // CHECK17-NEXT: store i64 5, i64* [[TMP128]], align 8
8131 // CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
8132 // CHECK17-NEXT: store i64 8, i64* [[TMP129]], align 8
8133 // CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5
8134 // CHECK17-NEXT: store i8* null, i8** [[TMP130]], align 8
8135 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6
8136 // CHECK17-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64*
8137 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8
8138 // CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6
8139 // CHECK17-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64*
8140 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8
8141 // CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
8142 // CHECK17-NEXT: store i64 8, i64* [[TMP135]], align 8
8143 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6
8144 // CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8
8145 // CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7
8146 // CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
8147 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8
8148 // CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7
8149 // CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
8150 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8
8151 // CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
8152 // CHECK17-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8
8153 // CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7
8154 // CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8
8155 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8
8156 // CHECK17-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
8157 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8
8158 // CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8
8159 // CHECK17-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
8160 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8
8161 // CHECK17-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
8162 // CHECK17-NEXT: store i64 16, i64* [[TMP147]], align 8
8163 // CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8
8164 // CHECK17-NEXT: store i8* null, i8** [[TMP148]], align 8
8165 // CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
8166 // CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
8167 // CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8168 // CHECK17-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8169 // CHECK17-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
8170 // CHECK17-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]]
8171 // CHECK17: omp_offload.failed28:
8172 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
8173 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT29]]
8174 // CHECK17: omp_offload.cont29:
8175 // CHECK17-NEXT: br label [[OMP_IF_END31:%.*]]
8176 // CHECK17: omp_if.else30:
8177 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
8178 // CHECK17-NEXT: br label [[OMP_IF_END31]]
8179 // CHECK17: omp_if.end31:
8180 // CHECK17-NEXT: store i32 0, i32* [[NN]], align 4
8181 // CHECK17-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
8182 // CHECK17-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
8183 // CHECK17-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4
8184 // CHECK17-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8
8185 // CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
8186 // CHECK17-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64*
8187 // CHECK17-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8
8188 // CHECK17-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
8189 // CHECK17-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64*
8190 // CHECK17-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8
8191 // CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0
8192 // CHECK17-NEXT: store i8* null, i8** [[TMP160]], align 8
8193 // CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
8194 // CHECK17-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
8195 // CHECK17-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8196 // CHECK17-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
8197 // CHECK17-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
8198 // CHECK17: omp_offload.failed36:
8199 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]]
8200 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT37]]
8201 // CHECK17: omp_offload.cont37:
8202 // CHECK17-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
8203 // CHECK17-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32*
8204 // CHECK17-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4
8205 // CHECK17-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8
8206 // CHECK17-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
8207 // CHECK17-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64*
8208 // CHECK17-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8
8209 // CHECK17-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
8210 // CHECK17-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64*
8211 // CHECK17-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8
8212 // CHECK17-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0
8213 // CHECK17-NEXT: store i8* null, i8** [[TMP171]], align 8
8214 // CHECK17-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
8215 // CHECK17-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
8216 // CHECK17-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8217 // CHECK17-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
8218 // CHECK17-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]]
8219 // CHECK17: omp_offload.failed43:
8220 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]]
8221 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT44]]
8222 // CHECK17: omp_offload.cont44:
8223 // CHECK17-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
8224 // CHECK17-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8225 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
8226 // CHECK17-NEXT: ret i32 [[TMP176]]
8227 //
8228 //
8229 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
8230 // CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
8231 // CHECK17-NEXT: entry:
8232 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
8233 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8234 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
8235 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
8236 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
8237 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
8238 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8239 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
8240 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8241 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
8242 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
8243 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
8244 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
8245 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
8246 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
8247 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8248 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
8249 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8250 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
8251 // CHECK17-NEXT: ret void
8252 //
8253 //
8254 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
8255 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8256 // CHECK17-NEXT: entry:
8257 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8258 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8259 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
8260 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8261 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8262 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
8263 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8264 // CHECK17-NEXT: ret void
8265 //
8266 //
8267 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
8268 // CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
8269 // CHECK17-NEXT: entry:
8270 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
8271 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
8272 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
8273 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
8274 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
8275 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
8276 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
8277 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
8278 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
8279 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
8280 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
8281 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
8282 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
8283 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
8284 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
8285 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
8286 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
8287 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
8288 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
8289 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
8290 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
8291 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
8292 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
8293 // CHECK17-NEXT: ret void
8294 //
8295 //
8296 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
8297 // CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
8298 // CHECK17-NEXT: entry:
8299 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
8300 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
8301 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
8302 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
8303 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
8304 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
8305 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
8306 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
8307 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
8308 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
8309 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
8310 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
8311 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
8312 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
8313 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
8314 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
8315 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
8316 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
8317 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
8318 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
8319 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
8320 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
8321 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
8322 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
8323 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
8324 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
8325 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
8326 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
8327 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
8328 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
8329 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
8330 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
8331 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
8332 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
8333 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
8334 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
8335 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
8336 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
8337 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
8338 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
8339 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
8340 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
8341 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
8342 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
8343 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
8344 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
8345 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
8346 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
8347 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
8348 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
8349 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
8350 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
8351 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
8352 // CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
8353 // CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
8354 // CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
8355 // CHECK17: omp_offload.failed.i:
8356 // CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
8357 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
8358 // CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
8359 // CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
8360 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
8361 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
8362 // CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
8363 // CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
8364 // CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
8365 // CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
8366 // CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
8367 // CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
8368 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
8369 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
8370 // CHECK17: .omp_outlined..1.exit:
8371 // CHECK17-NEXT: ret i32 0
8372 //
8373 //
8374 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
8375 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
8376 // CHECK17-NEXT: entry:
8377 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
8378 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
8379 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
8380 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8381 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8382 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8383 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
8384 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8385 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8386 // CHECK17-NEXT: ret void
8387 //
8388 //
8389 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
8390 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
8391 // CHECK17-NEXT: entry:
8392 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8393 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8394 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
8395 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8396 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8397 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
8398 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8399 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8400 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8401 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
8402 // CHECK17-NEXT: ret void
8403 //
8404 //
8405 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
8406 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
8407 // CHECK17-NEXT: entry:
8408 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
8409 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
8410 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
8411 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8412 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8413 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8414 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
8415 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8416 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8417 // CHECK17-NEXT: ret void
8418 //
8419 //
8420 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
8421 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8422 // CHECK17-NEXT: entry:
8423 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8424 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8425 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
8426 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8427 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8428 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
8429 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8430 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8431 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
8432 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
8433 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
8434 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
8435 // CHECK17-NEXT: ret void
8436 //
8437 //
8438 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
8439 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8440 // CHECK17-NEXT: entry:
8441 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
8442 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
8443 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
8444 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
8445 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
8446 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
8447 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8448 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8449 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8450 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8451 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
8452 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8453 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8454 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8455 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
8456 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8457 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
8458 // CHECK17-NEXT: ret void
8459 //
8460 //
8461 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
8462 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8463 // CHECK17-NEXT: entry:
8464 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8465 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8466 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
8467 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
8468 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8469 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8470 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
8471 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
8472 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8473 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8474 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8475 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8476 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
8477 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
8478 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
8479 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
8480 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
8481 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
8482 // CHECK17-NEXT: ret void
8483 //
8484 //
8485 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
8486 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
8487 // CHECK17-NEXT: entry:
8488 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
8489 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8490 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
8491 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
8492 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8493 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
8494 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
8495 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
8496 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8497 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
8498 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
8499 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8500 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8501 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
8502 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8503 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8504 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8505 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
8506 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8507 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8508 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8509 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8510 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8511 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8512 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8513 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8514 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8515 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8516 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8517 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8518 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
8519 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
8520 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
8521 // CHECK17-NEXT: ret void
8522 //
8523 //
8524 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
8525 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
8526 // CHECK17-NEXT: entry:
8527 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8528 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8529 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
8530 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8531 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
8532 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
8533 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8534 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
8535 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
8536 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
8537 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8538 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8539 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8540 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
8541 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8542 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8543 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
8544 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8545 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8546 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8547 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
8548 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8549 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8550 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8551 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8552 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8553 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8554 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8555 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8556 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8557 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8558 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8559 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
8560 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
8561 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
8562 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
8563 // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
8564 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
8565 // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
8566 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
8567 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
8568 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
8569 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
8570 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
8571 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
8572 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
8573 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
8574 // CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
8575 // CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
8576 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
8577 // CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
8578 // CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
8579 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
8580 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
8581 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
8582 // CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
8583 // CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
8584 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
8585 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
8586 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
8587 // CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
8588 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
8589 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
8590 // CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
8591 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
8592 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
8593 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
8594 // CHECK17-NEXT: ret void
8595 //
8596 //
8597 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
8598 // CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
8599 // CHECK17-NEXT: entry:
8600 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
8601 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
8602 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
8603 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
8604 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8605 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
8606 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
8607 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
8608 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8609 // CHECK17-NEXT: ret void
8610 //
8611 //
8612 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
8613 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
8614 // CHECK17-NEXT: entry:
8615 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8616 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8617 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
8618 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
8619 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8620 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8621 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
8622 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
8623 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8624 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
8625 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
8626 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
8627 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8628 // CHECK17-NEXT: ret void
8629 //
8630 //
8631 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12
8632 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
8633 // CHECK17-NEXT: entry:
8634 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8635 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8636 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
8637 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8638 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8639 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
8640 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
8641 // CHECK17-NEXT: ret void
8642 //
8643 //
8644 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
8645 // CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
8646 // CHECK17-NEXT: entry:
8647 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
8648 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
8649 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
8650 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
8651 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8652 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
8653 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
8654 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
8655 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8656 // CHECK17-NEXT: ret void
8657 //
8658 //
8659 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15
8660 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
8661 // CHECK17-NEXT: entry:
8662 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8663 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8664 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
8665 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8666 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8667 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
8668 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
8669 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]])
8670 // CHECK17-NEXT: ret void
8671 //
8672 //
8673 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16
8674 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
8675 // CHECK17-NEXT: entry:
8676 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8677 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8678 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
8679 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8680 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8681 // CHECK17-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
8682 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
8683 // CHECK17-NEXT: ret void
8684 //
8685 //
8686 // CHECK17-LABEL: define {{[^@]+}}@_Z6bazzzziPi
8687 // CHECK17-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
8688 // CHECK17-NEXT: entry:
8689 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8690 // CHECK17-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8
8691 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
8692 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
8693 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
8694 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8695 // CHECK17-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8
8696 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8697 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
8698 // CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8699 // CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
8700 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
8701 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8702 // CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
8703 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
8704 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8705 // CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8
8706 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8707 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8708 // CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8709 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
8710 // CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8711 // CHECK17: omp_offload.failed:
8712 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]]
8713 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
8714 // CHECK17: omp_offload.cont:
8715 // CHECK17-NEXT: ret void
8716 //
8717 //
8718 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
8719 // CHECK17-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] {
8720 // CHECK17-NEXT: entry:
8721 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
8722 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8723 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8724 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]])
8725 // CHECK17-NEXT: ret void
8726 //
8727 //
8728 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..19
8729 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] {
8730 // CHECK17-NEXT: entry:
8731 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8732 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8733 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
8734 // CHECK17-NEXT: [[F:%.*]] = alloca i32*, align 8
8735 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8736 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8737 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8738 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8739 // CHECK17-NEXT: ret void
8740 //
8741 //
8742 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
8743 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
8744 // CHECK17-NEXT: entry:
8745 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8746 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
8747 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
8748 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8749 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
8750 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8751 // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
8752 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8753 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8754 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4
8755 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8756 // CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
8757 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8758 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8759 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
8760 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8761 // CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
8762 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8763 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8764 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
8765 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8766 // CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
8767 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8768 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8769 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
8770 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8771 // CHECK17-NEXT: ret i32 [[TMP8]]
8772 //
8773 //
8774 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8775 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8776 // CHECK17-NEXT: entry:
8777 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8778 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8779 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4
8780 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
8781 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8782 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
8783 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
8784 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
8785 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
8786 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
8787 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8788 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8789 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8790 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8791 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8792 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4
8793 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8794 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8795 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
8796 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8797 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
8798 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
8799 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8800 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
8801 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
8802 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
8803 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
8804 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
8805 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
8806 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8807 // CHECK17: omp_if.then:
8808 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8809 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
8810 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
8811 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8812 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
8813 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
8814 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8815 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
8816 // CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8
8817 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8818 // CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8
8819 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8820 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8
8821 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8822 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
8823 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
8824 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8825 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
8826 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
8827 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
8828 // CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8
8829 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8830 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8
8831 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8832 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
8833 // CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8
8834 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8835 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
8836 // CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8
8837 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
8838 // CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8
8839 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8840 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8
8841 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8842 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
8843 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
8844 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8845 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
8846 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8
8847 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
8848 // CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8
8849 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
8850 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8
8851 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
8852 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
8853 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8
8854 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
8855 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
8856 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8
8857 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8858 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
8859 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
8860 // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8
8861 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8862 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8863 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8864 // CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8865 // CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
8866 // CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8867 // CHECK17: omp_offload.failed:
8868 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
8869 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
8870 // CHECK17: omp_offload.cont:
8871 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
8872 // CHECK17: omp_if.else:
8873 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
8874 // CHECK17-NEXT: br label [[OMP_IF_END]]
8875 // CHECK17: omp_if.end:
8876 // CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
8877 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
8878 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8879 // CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
8880 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
8881 // CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
8882 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
8883 // CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8884 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
8885 // CHECK17-NEXT: ret i32 [[ADD4]]
8886 //
8887 //
8888 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
8889 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
8890 // CHECK17-NEXT: entry:
8891 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8892 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
8893 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
8894 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1
8895 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
8896 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
8897 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
8898 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
8899 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
8900 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
8901 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
8902 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8903 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
8904 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
8905 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1
8906 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8907 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8908 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
8909 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8910 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8911 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8912 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
8913 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8914 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
8915 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8916 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
8917 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8918 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8919 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
8920 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8921 // CHECK17: omp_if.then:
8922 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8923 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
8924 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
8925 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8926 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
8927 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
8928 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8929 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8
8930 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8931 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
8932 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
8933 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8934 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
8935 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
8936 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8937 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8
8938 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8939 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
8940 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
8941 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8942 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
8943 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
8944 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8945 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8
8946 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8947 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
8948 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
8949 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8950 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
8951 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
8952 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
8953 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8
8954 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8955 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8956 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
8957 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
8958 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8959 // CHECK17: omp_offload.failed:
8960 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
8961 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
8962 // CHECK17: omp_offload.cont:
8963 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
8964 // CHECK17: omp_if.else:
8965 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
8966 // CHECK17-NEXT: br label [[OMP_IF_END]]
8967 // CHECK17: omp_if.end:
8968 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
8969 // CHECK17-NEXT: ret i32 [[TMP31]]
8970 //
8971 //
8972 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8973 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
8974 // CHECK17-NEXT: entry:
8975 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
8976 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
8977 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
8978 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
8979 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
8980 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
8981 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
8982 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
8983 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
8984 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
8985 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4
8986 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
8987 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8988 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8989 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
8990 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8991 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8992 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8993 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
8994 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8995 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8996 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
8997 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8998 // CHECK17: omp_if.then:
8999 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9000 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
9001 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
9002 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9003 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
9004 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
9005 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9006 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8
9007 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9008 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
9009 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
9010 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9011 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
9012 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
9013 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9014 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8
9015 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9016 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
9017 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
9018 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9019 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
9020 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
9021 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9022 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8
9023 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9024 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9025 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
9026 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
9027 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9028 // CHECK17: omp_offload.failed:
9029 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
9030 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
9031 // CHECK17: omp_offload.cont:
9032 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
9033 // CHECK17: omp_if.else:
9034 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
9035 // CHECK17-NEXT: br label [[OMP_IF_END]]
9036 // CHECK17: omp_if.end:
9037 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
9038 // CHECK17-NEXT: ret i32 [[TMP24]]
9039 //
9040 //
9041 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
9042 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
9043 // CHECK17-NEXT: entry:
9044 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9045 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
9046 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
9047 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
9048 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
9049 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
9050 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9051 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
9052 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9053 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9054 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
9055 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9056 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9057 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9058 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9059 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9060 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
9061 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9062 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
9063 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
9064 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
9065 // CHECK17-NEXT: ret void
9066 //
9067 //
9068 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22
9069 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
9070 // CHECK17-NEXT: entry:
9071 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9072 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9073 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9074 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
9075 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
9076 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
9077 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
9078 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9079 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9080 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9081 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
9082 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9083 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9084 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
9085 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9086 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9087 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9088 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9089 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9090 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
9091 // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
9092 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
9093 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
9094 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
9095 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9096 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
9097 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
9098 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8
9099 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
9100 // CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
9101 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
9102 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9103 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
9104 // CHECK17-NEXT: ret void
9105 //
9106 //
9107 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
9108 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9109 // CHECK17-NEXT: entry:
9110 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9111 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9112 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
9113 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9114 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
9115 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
9116 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
9117 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9118 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9119 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9120 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9121 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9122 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9123 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9124 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9125 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9126 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9127 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
9128 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9129 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9130 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9131 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
9132 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9133 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
9134 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9135 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
9136 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9137 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
9138 // CHECK17-NEXT: ret void
9139 //
9140 //
9141 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..24
9142 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9143 // CHECK17-NEXT: entry:
9144 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9145 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9146 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9147 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9148 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
9149 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9150 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9151 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9152 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9153 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9154 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9155 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9156 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9157 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9158 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9159 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9160 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9161 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
9162 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
9163 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9164 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
9165 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
9166 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
9167 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
9168 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
9169 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
9170 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
9171 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
9172 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
9173 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9174 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9175 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
9176 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
9177 // CHECK17-NEXT: ret void
9178 //
9179 //
9180 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
9181 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9182 // CHECK17-NEXT: entry:
9183 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9184 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9185 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9186 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
9187 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
9188 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9189 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9190 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9191 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9192 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9193 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9194 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9195 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9196 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
9197 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9198 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9199 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9200 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
9201 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9202 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
9203 // CHECK17-NEXT: ret void
9204 //
9205 //
9206 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..27
9207 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9208 // CHECK17-NEXT: entry:
9209 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9210 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9211 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9212 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9213 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9214 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9215 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9216 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9217 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9218 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9219 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9220 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9221 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9222 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9223 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
9224 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
9225 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9226 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
9227 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
9228 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9229 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
9230 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9231 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9232 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
9233 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
9234 // CHECK17-NEXT: ret void
9235 //
9236 //
9237 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
9238 // CHECK17-SAME: () #[[ATTR4]] {
9239 // CHECK17-NEXT: entry:
9240 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
9241 // CHECK17-NEXT: ret void
9242 //
9243 //
9244 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi
9245 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
9246 // CHECK18-NEXT: entry:
9247 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
9248 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
9249 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2
9250 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4
9251 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
9252 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
9253 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
9254 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
9255 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
9256 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9257 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
9258 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
9259 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9260 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
9261 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
9262 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
9263 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
9264 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
9265 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
9266 // CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8
9267 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
9268 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
9269 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
9270 // CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8
9271 // CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8
9272 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
9273 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
9274 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
9275 // CHECK18-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8
9276 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8
9277 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8
9278 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8
9279 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
9280 // CHECK18-NEXT: [[NN:%.*]] = alloca i32, align 4
9281 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
9282 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8
9283 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8
9284 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8
9285 // CHECK18-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8
9286 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8
9287 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8
9288 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8
9289 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
9290 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
9291 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4
9292 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2
9293 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9294 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
9295 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
9296 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
9297 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
9298 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
9299 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9300 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
9301 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
9302 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
9303 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
9304 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
9305 // CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
9306 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9307 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
9308 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
9309 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9310 // CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
9311 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9312 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9313 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
9314 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
9315 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9316 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
9317 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
9318 // CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4
9319 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
9320 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9321 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
9322 // CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8
9323 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9324 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
9325 // CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8
9326 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9327 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8
9328 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9329 // CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
9330 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8
9331 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9332 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
9333 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8
9334 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9335 // CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8
9336 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9337 // CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
9338 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8
9339 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9340 // CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
9341 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8
9342 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9343 // CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8
9344 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9345 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9346 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
9347 // CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
9348 // CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
9349 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
9350 // CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9351 // CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
9352 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
9353 // CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
9354 // CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
9355 // CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
9356 // CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
9357 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
9358 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
9359 // CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
9360 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
9361 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
9362 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
9363 // CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
9364 // CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
9365 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
9366 // CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
9367 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
9368 // CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
9369 // CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
9370 // CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
9371 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
9372 // CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
9373 // CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
9374 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
9375 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
9376 // CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
9377 // CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8
9378 // CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]])
9379 // CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
9380 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9381 // CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4
9382 // CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
9383 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
9384 // CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
9385 // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
9386 // CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2
9387 // CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
9388 // CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
9389 // CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
9390 // CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8
9391 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
9392 // CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
9393 // CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8
9394 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
9395 // CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8
9396 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
9397 // CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
9398 // CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
9399 // CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
9400 // CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9401 // CHECK18: omp_offload.failed:
9402 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]]
9403 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
9404 // CHECK18: omp_offload.cont:
9405 // CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4
9406 // CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
9407 // CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4
9408 // CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
9409 // CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
9410 // CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
9411 // CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2
9412 // CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
9413 // CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
9414 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
9415 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9416 // CHECK18: omp_if.then:
9417 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
9418 // CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
9419 // CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8
9420 // CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
9421 // CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
9422 // CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8
9423 // CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
9424 // CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8
9425 // CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
9426 // CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
9427 // CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8
9428 // CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
9429 // CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
9430 // CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8
9431 // CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
9432 // CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8
9433 // CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
9434 // CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
9435 // CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
9436 // CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
9437 // CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
9438 // CHECK18: omp_offload.failed19:
9439 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
9440 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]]
9441 // CHECK18: omp_offload.cont20:
9442 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
9443 // CHECK18: omp_if.else:
9444 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
9445 // CHECK18-NEXT: br label [[OMP_IF_END]]
9446 // CHECK18: omp_if.end:
9447 // CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4
9448 // CHECK18-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32*
9449 // CHECK18-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4
9450 // CHECK18-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8
9451 // CHECK18-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
9452 // CHECK18-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20
9453 // CHECK18-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]]
9454 // CHECK18: omp_if.then24:
9455 // CHECK18-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
9456 // CHECK18-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
9457 // CHECK18-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
9458 // CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
9459 // CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64*
9460 // CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8
9461 // CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
9462 // CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64*
9463 // CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8
9464 // CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9465 // CHECK18-NEXT: store i64 4, i64* [[TMP99]], align 8
9466 // CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0
9467 // CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8
9468 // CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1
9469 // CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
9470 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
9471 // CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1
9472 // CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
9473 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
9474 // CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
9475 // CHECK18-NEXT: store i64 40, i64* [[TMP105]], align 8
9476 // CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1
9477 // CHECK18-NEXT: store i8* null, i8** [[TMP106]], align 8
9478 // CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2
9479 // CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64*
9480 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8
9481 // CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2
9482 // CHECK18-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64*
9483 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8
9484 // CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
9485 // CHECK18-NEXT: store i64 8, i64* [[TMP111]], align 8
9486 // CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2
9487 // CHECK18-NEXT: store i8* null, i8** [[TMP112]], align 8
9488 // CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3
9489 // CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
9490 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP114]], align 8
9491 // CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3
9492 // CHECK18-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
9493 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP116]], align 8
9494 // CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
9495 // CHECK18-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8
9496 // CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3
9497 // CHECK18-NEXT: store i8* null, i8** [[TMP118]], align 8
9498 // CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4
9499 // CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
9500 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
9501 // CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4
9502 // CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
9503 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8
9504 // CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
9505 // CHECK18-NEXT: store i64 400, i64* [[TMP123]], align 8
9506 // CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4
9507 // CHECK18-NEXT: store i8* null, i8** [[TMP124]], align 8
9508 // CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5
9509 // CHECK18-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64*
9510 // CHECK18-NEXT: store i64 5, i64* [[TMP126]], align 8
9511 // CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5
9512 // CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
9513 // CHECK18-NEXT: store i64 5, i64* [[TMP128]], align 8
9514 // CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
9515 // CHECK18-NEXT: store i64 8, i64* [[TMP129]], align 8
9516 // CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5
9517 // CHECK18-NEXT: store i8* null, i8** [[TMP130]], align 8
9518 // CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6
9519 // CHECK18-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64*
9520 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8
9521 // CHECK18-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6
9522 // CHECK18-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64*
9523 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8
9524 // CHECK18-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
9525 // CHECK18-NEXT: store i64 8, i64* [[TMP135]], align 8
9526 // CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6
9527 // CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8
9528 // CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7
9529 // CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
9530 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8
9531 // CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7
9532 // CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
9533 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8
9534 // CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
9535 // CHECK18-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8
9536 // CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7
9537 // CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8
9538 // CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8
9539 // CHECK18-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
9540 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8
9541 // CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8
9542 // CHECK18-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
9543 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8
9544 // CHECK18-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
9545 // CHECK18-NEXT: store i64 16, i64* [[TMP147]], align 8
9546 // CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8
9547 // CHECK18-NEXT: store i8* null, i8** [[TMP148]], align 8
9548 // CHECK18-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0
9549 // CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0
9550 // CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9551 // CHECK18-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
9552 // CHECK18-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
9553 // CHECK18-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]]
9554 // CHECK18: omp_offload.failed28:
9555 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
9556 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT29]]
9557 // CHECK18: omp_offload.cont29:
9558 // CHECK18-NEXT: br label [[OMP_IF_END31:%.*]]
9559 // CHECK18: omp_if.else30:
9560 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
9561 // CHECK18-NEXT: br label [[OMP_IF_END31]]
9562 // CHECK18: omp_if.end31:
9563 // CHECK18-NEXT: store i32 0, i32* [[NN]], align 4
9564 // CHECK18-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
9565 // CHECK18-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
9566 // CHECK18-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4
9567 // CHECK18-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8
9568 // CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
9569 // CHECK18-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64*
9570 // CHECK18-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8
9571 // CHECK18-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
9572 // CHECK18-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64*
9573 // CHECK18-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8
9574 // CHECK18-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0
9575 // CHECK18-NEXT: store i8* null, i8** [[TMP160]], align 8
9576 // CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
9577 // CHECK18-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
9578 // CHECK18-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
9579 // CHECK18-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
9580 // CHECK18-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
9581 // CHECK18: omp_offload.failed36:
9582 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]]
9583 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT37]]
9584 // CHECK18: omp_offload.cont37:
9585 // CHECK18-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
9586 // CHECK18-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32*
9587 // CHECK18-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4
9588 // CHECK18-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8
9589 // CHECK18-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
9590 // CHECK18-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64*
9591 // CHECK18-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8
9592 // CHECK18-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
9593 // CHECK18-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64*
9594 // CHECK18-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8
9595 // CHECK18-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0
9596 // CHECK18-NEXT: store i8* null, i8** [[TMP171]], align 8
9597 // CHECK18-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
9598 // CHECK18-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
9599 // CHECK18-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
9600 // CHECK18-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
9601 // CHECK18-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]]
9602 // CHECK18: omp_offload.failed43:
9603 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]]
9604 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT44]]
9605 // CHECK18: omp_offload.cont44:
9606 // CHECK18-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
9607 // CHECK18-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9608 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
9609 // CHECK18-NEXT: ret i32 [[TMP176]]
9610 //
9611 //
9612 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
9613 // CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
9614 // CHECK18-NEXT: entry:
9615 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9616 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9617 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
9618 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
9619 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
9620 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9621 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9622 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
9623 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9624 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9625 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
9626 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
9627 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
9628 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
9629 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
9630 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9631 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
9632 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9633 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
9634 // CHECK18-NEXT: ret void
9635 //
9636 //
9637 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
9638 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9639 // CHECK18-NEXT: entry:
9640 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9641 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9642 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9643 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9644 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9645 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9646 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9647 // CHECK18-NEXT: ret void
9648 //
9649 //
9650 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map.
9651 // CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
9652 // CHECK18-NEXT: entry:
9653 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
9654 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
9655 // CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
9656 // CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
9657 // CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
9658 // CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
9659 // CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
9660 // CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
9661 // CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
9662 // CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
9663 // CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
9664 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
9665 // CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
9666 // CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
9667 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
9668 // CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
9669 // CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
9670 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
9671 // CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
9672 // CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
9673 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
9674 // CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
9675 // CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
9676 // CHECK18-NEXT: ret void
9677 //
9678 //
9679 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry.
9680 // CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
9681 // CHECK18-NEXT: entry:
9682 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
9683 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
9684 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
9685 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
9686 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
9687 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
9688 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
9689 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
9690 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
9691 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
9692 // CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
9693 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
9694 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
9695 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
9696 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
9697 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
9698 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
9699 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
9700 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
9701 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
9702 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
9703 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
9704 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
9705 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
9706 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
9707 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
9708 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
9709 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
9710 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
9711 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
9712 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
9713 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
9714 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
9715 // CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
9716 // CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
9717 // CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
9718 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
9719 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
9720 // CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
9721 // CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
9722 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
9723 // CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
9724 // CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
9725 // CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
9726 // CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
9727 // CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
9728 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
9729 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
9730 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
9731 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
9732 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
9733 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
9734 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
9735 // CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
9736 // CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
9737 // CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
9738 // CHECK18: omp_offload.failed.i:
9739 // CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
9740 // CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
9741 // CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
9742 // CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
9743 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
9744 // CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
9745 // CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
9746 // CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
9747 // CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
9748 // CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
9749 // CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
9750 // CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
9751 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
9752 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
9753 // CHECK18: .omp_outlined..1.exit:
9754 // CHECK18-NEXT: ret i32 0
9755 //
9756 //
9757 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
9758 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
9759 // CHECK18-NEXT: entry:
9760 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9761 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
9762 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9763 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9764 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9765 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9766 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
9767 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9768 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9769 // CHECK18-NEXT: ret void
9770 //
9771 //
9772 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
9773 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
9774 // CHECK18-NEXT: entry:
9775 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9776 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9777 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9778 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9779 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9780 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9781 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9782 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9783 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9784 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
9785 // CHECK18-NEXT: ret void
9786 //
9787 //
9788 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
9789 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
9790 // CHECK18-NEXT: entry:
9791 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9792 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
9793 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9794 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9795 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
9796 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9797 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
9798 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9799 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9800 // CHECK18-NEXT: ret void
9801 //
9802 //
9803 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
9804 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9805 // CHECK18-NEXT: entry:
9806 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9807 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9808 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9809 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9810 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9811 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9812 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9813 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
9814 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
9815 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
9816 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
9817 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
9818 // CHECK18-NEXT: ret void
9819 //
9820 //
9821 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
9822 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9823 // CHECK18-NEXT: entry:
9824 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9825 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9826 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
9827 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
9828 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9829 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9830 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9831 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9832 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9833 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9834 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
9835 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9836 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9837 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9838 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
9839 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9840 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
9841 // CHECK18-NEXT: ret void
9842 //
9843 //
9844 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
9845 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9846 // CHECK18-NEXT: entry:
9847 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9848 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9849 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9850 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
9851 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9852 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9853 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9854 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
9855 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9856 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9857 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9858 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9859 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
9860 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
9861 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
9862 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
9863 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9864 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
9865 // CHECK18-NEXT: ret void
9866 //
9867 //
9868 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
9869 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
9870 // CHECK18-NEXT: entry:
9871 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9872 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9873 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
9874 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
9875 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9876 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
9877 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
9878 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
9879 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9880 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
9881 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9882 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9883 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9884 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
9885 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9886 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9887 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9888 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
9889 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9890 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9891 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9892 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9893 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9894 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9895 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9896 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9897 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9898 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9899 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9900 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9901 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
9902 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
9903 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
9904 // CHECK18-NEXT: ret void
9905 //
9906 //
9907 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
9908 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
9909 // CHECK18-NEXT: entry:
9910 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9911 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9912 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
9913 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9914 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
9915 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
9916 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9917 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
9918 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
9919 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
9920 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9921 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9922 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9923 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
9924 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9925 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9926 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
9927 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9928 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9929 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9930 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
9931 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9932 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9933 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9934 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9935 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9936 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9937 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9938 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9939 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9940 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9941 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9942 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
9943 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
9944 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
9945 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
9946 // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
9947 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
9948 // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
9949 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
9950 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
9951 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
9952 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
9953 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
9954 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
9955 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
9956 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
9957 // CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
9958 // CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
9959 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
9960 // CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
9961 // CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
9962 // CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
9963 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
9964 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
9965 // CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
9966 // CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
9967 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
9968 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
9969 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
9970 // CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
9971 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
9972 // CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
9973 // CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
9974 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
9975 // CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
9976 // CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
9977 // CHECK18-NEXT: ret void
9978 //
9979 //
9980 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
9981 // CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
9982 // CHECK18-NEXT: entry:
9983 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
9984 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
9985 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
9986 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
9987 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9988 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
9989 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
9990 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
9991 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9992 // CHECK18-NEXT: ret void
9993 //
9994 //
9995 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
9996 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
9997 // CHECK18-NEXT: entry:
9998 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9999 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10000 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
10001 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
10002 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10003 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10004 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
10005 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
10006 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
10007 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
10008 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
10009 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
10010 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]])
10011 // CHECK18-NEXT: ret void
10012 //
10013 //
10014 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12
10015 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
10016 // CHECK18-NEXT: entry:
10017 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10018 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10019 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
10020 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10021 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10022 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
10023 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
10024 // CHECK18-NEXT: ret void
10025 //
10026 //
10027 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
10028 // CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] {
10029 // CHECK18-NEXT: entry:
10030 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
10031 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
10032 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
10033 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
10034 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
10035 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
10036 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
10037 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
10038 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]])
10039 // CHECK18-NEXT: ret void
10040 //
10041 //
10042 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15
10043 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] {
10044 // CHECK18-NEXT: entry:
10045 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10046 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10047 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
10048 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10049 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10050 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
10051 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
10052 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]])
10053 // CHECK18-NEXT: ret void
10054 //
10055 //
10056 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16
10057 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
10058 // CHECK18-NEXT: entry:
10059 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10060 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10061 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
10062 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10063 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10064 // CHECK18-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
10065 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
10066 // CHECK18-NEXT: ret void
10067 //
10068 //
10069 // CHECK18-LABEL: define {{[^@]+}}@_Z6bazzzziPi
10070 // CHECK18-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
10071 // CHECK18-NEXT: entry:
10072 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
10073 // CHECK18-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8
10074 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
10075 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
10076 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
10077 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
10078 // CHECK18-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8
10079 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10080 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
10081 // CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10082 // CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
10083 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
10084 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10085 // CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
10086 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
10087 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
10088 // CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8
10089 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10090 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10091 // CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10092 // CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
10093 // CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10094 // CHECK18: omp_offload.failed:
10095 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]]
10096 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
10097 // CHECK18: omp_offload.cont:
10098 // CHECK18-NEXT: ret void
10099 //
10100 //
10101 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
10102 // CHECK18-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] {
10103 // CHECK18-NEXT: entry:
10104 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
10105 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10106 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10107 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]])
10108 // CHECK18-NEXT: ret void
10109 //
10110 //
10111 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..19
10112 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] {
10113 // CHECK18-NEXT: entry:
10114 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10115 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10116 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
10117 // CHECK18-NEXT: [[F:%.*]] = alloca i32*, align 8
10118 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10119 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10120 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10121 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10122 // CHECK18-NEXT: ret void
10123 //
10124 //
10125 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari
10126 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
10127 // CHECK18-NEXT: entry:
10128 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
10129 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
10130 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
10131 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
10132 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4
10133 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10134 // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
10135 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
10136 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
10137 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4
10138 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
10139 // CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
10140 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
10141 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
10142 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
10143 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10144 // CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
10145 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
10146 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
10147 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
10148 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
10149 // CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
10150 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
10151 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
10152 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
10153 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
10154 // CHECK18-NEXT: ret i32 [[TMP8]]
10155 //
10156 //
10157 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
10158 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
10159 // CHECK18-NEXT: entry:
10160 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10161 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
10162 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4
10163 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
10164 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
10165 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
10166 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
10167 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
10168 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
10169 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
10170 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10171 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
10172 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10173 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10174 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
10175 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4
10176 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10177 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
10178 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
10179 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
10180 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
10181 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
10182 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
10183 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
10184 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
10185 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
10186 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
10187 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
10188 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
10189 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10190 // CHECK18: omp_if.then:
10191 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
10192 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
10193 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
10194 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10195 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
10196 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
10197 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10198 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
10199 // CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8
10200 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10201 // CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8
10202 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
10203 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8
10204 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10205 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
10206 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
10207 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10208 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
10209 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
10210 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
10211 // CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8
10212 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
10213 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8
10214 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10215 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
10216 // CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8
10217 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10218 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
10219 // CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8
10220 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
10221 // CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8
10222 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
10223 // CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8
10224 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
10225 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
10226 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
10227 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
10228 // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
10229 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8
10230 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
10231 // CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8
10232 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
10233 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8
10234 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
10235 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
10236 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8
10237 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
10238 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
10239 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8
10240 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
10241 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
10242 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
10243 // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8
10244 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10245 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10246 // CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10247 // CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10248 // CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
10249 // CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10250 // CHECK18: omp_offload.failed:
10251 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
10252 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
10253 // CHECK18: omp_offload.cont:
10254 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
10255 // CHECK18: omp_if.else:
10256 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
10257 // CHECK18-NEXT: br label [[OMP_IF_END]]
10258 // CHECK18: omp_if.end:
10259 // CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
10260 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
10261 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
10262 // CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
10263 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
10264 // CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
10265 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
10266 // CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
10267 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
10268 // CHECK18-NEXT: ret i32 [[ADD4]]
10269 //
10270 //
10271 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
10272 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
10273 // CHECK18-NEXT: entry:
10274 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
10275 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
10276 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2
10277 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1
10278 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
10279 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
10280 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
10281 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
10282 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
10283 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
10284 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
10285 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
10286 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4
10287 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2
10288 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1
10289 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
10290 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10291 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
10292 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
10293 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
10294 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10295 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
10296 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10297 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
10298 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
10299 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
10300 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
10301 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
10302 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
10303 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10304 // CHECK18: omp_if.then:
10305 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10306 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
10307 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
10308 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10309 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
10310 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
10311 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
10312 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8
10313 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10314 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
10315 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
10316 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10317 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
10318 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
10319 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
10320 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8
10321 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10322 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
10323 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
10324 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10325 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
10326 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
10327 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
10328 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8
10329 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
10330 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
10331 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
10332 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
10333 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
10334 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
10335 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
10336 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8
10337 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10338 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10339 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10340 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
10341 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10342 // CHECK18: omp_offload.failed:
10343 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
10344 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
10345 // CHECK18: omp_offload.cont:
10346 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
10347 // CHECK18: omp_if.else:
10348 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
10349 // CHECK18-NEXT: br label [[OMP_IF_END]]
10350 // CHECK18: omp_if.end:
10351 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
10352 // CHECK18-NEXT: ret i32 [[TMP31]]
10353 //
10354 //
10355 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
10356 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
10357 // CHECK18-NEXT: entry:
10358 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
10359 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
10360 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2
10361 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
10362 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
10363 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
10364 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
10365 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
10366 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
10367 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
10368 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4
10369 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2
10370 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
10371 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10372 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
10373 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
10374 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
10375 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10376 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
10377 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10378 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10379 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
10380 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10381 // CHECK18: omp_if.then:
10382 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10383 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
10384 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
10385 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10386 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
10387 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
10388 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
10389 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8
10390 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10391 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
10392 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
10393 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10394 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
10395 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
10396 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
10397 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8
10398 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10399 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
10400 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
10401 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10402 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
10403 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
10404 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
10405 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8
10406 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10407 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10408 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10409 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
10410 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10411 // CHECK18: omp_offload.failed:
10412 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
10413 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
10414 // CHECK18: omp_offload.cont:
10415 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
10416 // CHECK18: omp_if.else:
10417 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
10418 // CHECK18-NEXT: br label [[OMP_IF_END]]
10419 // CHECK18: omp_if.end:
10420 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
10421 // CHECK18-NEXT: ret i32 [[TMP24]]
10422 //
10423 //
10424 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
10425 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
10426 // CHECK18-NEXT: entry:
10427 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10428 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
10429 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
10430 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
10431 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
10432 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
10433 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10434 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
10435 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10436 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10437 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
10438 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10439 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10440 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10441 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10442 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10443 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
10444 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
10445 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
10446 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
10447 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
10448 // CHECK18-NEXT: ret void
10449 //
10450 //
10451 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22
10452 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
10453 // CHECK18-NEXT: entry:
10454 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10455 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10456 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10457 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
10458 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
10459 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
10460 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
10461 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10462 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10463 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10464 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
10465 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10466 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10467 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
10468 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10469 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10470 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10471 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10472 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10473 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
10474 // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
10475 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
10476 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10477 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
10478 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10479 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
10480 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
10481 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8
10482 // CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
10483 // CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
10484 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
10485 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
10486 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
10487 // CHECK18-NEXT: ret void
10488 //
10489 //
10490 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
10491 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10492 // CHECK18-NEXT: entry:
10493 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
10494 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
10495 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
10496 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10497 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
10498 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
10499 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
10500 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
10501 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
10502 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
10503 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10504 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10505 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10506 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
10507 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10508 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
10509 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10510 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
10511 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10512 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
10513 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10514 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
10515 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10516 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
10517 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
10518 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
10519 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
10520 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
10521 // CHECK18-NEXT: ret void
10522 //
10523 //
10524 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..24
10525 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10526 // CHECK18-NEXT: entry:
10527 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10528 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10529 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
10530 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
10531 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
10532 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10533 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10534 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10535 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
10536 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
10537 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
10538 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10539 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10540 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10541 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
10542 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10543 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
10544 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
10545 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
10546 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
10547 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
10548 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
10549 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
10550 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
10551 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
10552 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
10553 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
10554 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
10555 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
10556 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10557 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10558 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
10559 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
10560 // CHECK18-NEXT: ret void
10561 //
10562 //
10563 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
10564 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10565 // CHECK18-NEXT: entry:
10566 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
10567 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
10568 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10569 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
10570 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
10571 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
10572 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
10573 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10574 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10575 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10576 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10577 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
10578 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10579 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
10580 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10581 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
10582 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10583 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
10584 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10585 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
10586 // CHECK18-NEXT: ret void
10587 //
10588 //
10589 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..27
10590 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10591 // CHECK18-NEXT: entry:
10592 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10593 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10594 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
10595 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
10596 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10597 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10598 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10599 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
10600 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
10601 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10602 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10603 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10604 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10605 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
10606 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
10607 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
10608 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
10609 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
10610 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
10611 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10612 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
10613 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10614 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10615 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
10616 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
10617 // CHECK18-NEXT: ret void
10618 //
10619 //
10620 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
10621 // CHECK18-SAME: () #[[ATTR4]] {
10622 // CHECK18-NEXT: entry:
10623 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
10624 // CHECK18-NEXT: ret void
10625 //
10626 //
10627 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
10628 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
10629 // CHECK19-NEXT: entry:
10630 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
10631 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
10632 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
10633 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4
10634 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
10635 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
10636 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
10637 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
10638 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
10639 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10640 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
10641 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
10642 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10643 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
10644 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
10645 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
10646 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
10647 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
10648 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
10649 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
10650 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
10651 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
10652 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
10653 // CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4
10654 // CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4
10655 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
10656 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
10657 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
10658 // CHECK19-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4
10659 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4
10660 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4
10661 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4
10662 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
10663 // CHECK19-NEXT: [[NN:%.*]] = alloca i32, align 4
10664 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
10665 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4
10666 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4
10667 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4
10668 // CHECK19-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4
10669 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4
10670 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4
10671 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4
10672 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
10673 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
10674 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
10675 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
10676 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10677 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
10678 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
10679 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
10680 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
10681 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
10682 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
10683 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
10684 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
10685 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
10686 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
10687 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
10688 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
10689 // CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
10690 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10691 // CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2
10692 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10693 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10694 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10695 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10696 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
10697 // CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
10698 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
10699 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10700 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
10701 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4
10702 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10703 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
10704 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4
10705 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10706 // CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4
10707 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10708 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
10709 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4
10710 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10711 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
10712 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4
10713 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
10714 // CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4
10715 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10716 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
10717 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4
10718 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10719 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
10720 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4
10721 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
10722 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4
10723 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10724 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10725 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
10726 // CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
10727 // CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4
10728 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
10729 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10730 // CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4
10731 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
10732 // CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
10733 // CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
10734 // CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
10735 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
10736 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
10737 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
10738 // CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
10739 // CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
10740 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
10741 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
10742 // CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
10743 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
10744 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
10745 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
10746 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
10747 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
10748 // CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
10749 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
10750 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
10751 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
10752 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
10753 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
10754 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
10755 // CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
10756 // CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4
10757 // CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]])
10758 // CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
10759 // CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4
10760 // CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
10761 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
10762 // CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
10763 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
10764 // CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2
10765 // CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
10766 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
10767 // CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
10768 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4
10769 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
10770 // CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
10771 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4
10772 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
10773 // CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4
10774 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
10775 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
10776 // CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10777 // CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
10778 // CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10779 // CHECK19: omp_offload.failed:
10780 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]]
10781 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
10782 // CHECK19: omp_offload.cont:
10783 // CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4
10784 // CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
10785 // CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
10786 // CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
10787 // CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
10788 // CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2
10789 // CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
10790 // CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
10791 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
10792 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10793 // CHECK19: omp_if.then:
10794 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
10795 // CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
10796 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4
10797 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
10798 // CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
10799 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4
10800 // CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
10801 // CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4
10802 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
10803 // CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
10804 // CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4
10805 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
10806 // CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
10807 // CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4
10808 // CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
10809 // CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4
10810 // CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
10811 // CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
10812 // CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10813 // CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
10814 // CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
10815 // CHECK19: omp_offload.failed15:
10816 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
10817 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]]
10818 // CHECK19: omp_offload.cont16:
10819 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
10820 // CHECK19: omp_if.else:
10821 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
10822 // CHECK19-NEXT: br label [[OMP_IF_END]]
10823 // CHECK19: omp_if.end:
10824 // CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4
10825 // CHECK19-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4
10826 // CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4
10827 // CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
10828 // CHECK19-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20
10829 // CHECK19-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
10830 // CHECK19: omp_if.then19:
10831 // CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
10832 // CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
10833 // CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
10834 // CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
10835 // CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
10836 // CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
10837 // CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32*
10838 // CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4
10839 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
10840 // CHECK19-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32*
10841 // CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4
10842 // CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10843 // CHECK19-NEXT: store i64 4, i64* [[TMP99]], align 4
10844 // CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
10845 // CHECK19-NEXT: store i8* null, i8** [[TMP100]], align 4
10846 // CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
10847 // CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
10848 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
10849 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
10850 // CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
10851 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
10852 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
10853 // CHECK19-NEXT: store i64 40, i64* [[TMP105]], align 4
10854 // CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1
10855 // CHECK19-NEXT: store i8* null, i8** [[TMP106]], align 4
10856 // CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
10857 // CHECK19-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32*
10858 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4
10859 // CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
10860 // CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32*
10861 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4
10862 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
10863 // CHECK19-NEXT: store i64 4, i64* [[TMP111]], align 4
10864 // CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2
10865 // CHECK19-NEXT: store i8* null, i8** [[TMP112]], align 4
10866 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
10867 // CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
10868 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP114]], align 4
10869 // CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
10870 // CHECK19-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
10871 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP116]], align 4
10872 // CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
10873 // CHECK19-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4
10874 // CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3
10875 // CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4
10876 // CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
10877 // CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
10878 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
10879 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
10880 // CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
10881 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4
10882 // CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
10883 // CHECK19-NEXT: store i64 400, i64* [[TMP123]], align 4
10884 // CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4
10885 // CHECK19-NEXT: store i8* null, i8** [[TMP124]], align 4
10886 // CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
10887 // CHECK19-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
10888 // CHECK19-NEXT: store i32 5, i32* [[TMP126]], align 4
10889 // CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
10890 // CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
10891 // CHECK19-NEXT: store i32 5, i32* [[TMP128]], align 4
10892 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
10893 // CHECK19-NEXT: store i64 4, i64* [[TMP129]], align 4
10894 // CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5
10895 // CHECK19-NEXT: store i8* null, i8** [[TMP130]], align 4
10896 // CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
10897 // CHECK19-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32*
10898 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4
10899 // CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
10900 // CHECK19-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32*
10901 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4
10902 // CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
10903 // CHECK19-NEXT: store i64 4, i64* [[TMP135]], align 4
10904 // CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6
10905 // CHECK19-NEXT: store i8* null, i8** [[TMP136]], align 4
10906 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
10907 // CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
10908 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4
10909 // CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
10910 // CHECK19-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
10911 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4
10912 // CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
10913 // CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4
10914 // CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7
10915 // CHECK19-NEXT: store i8* null, i8** [[TMP142]], align 4
10916 // CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
10917 // CHECK19-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
10918 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4
10919 // CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
10920 // CHECK19-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
10921 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4
10922 // CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
10923 // CHECK19-NEXT: store i64 12, i64* [[TMP147]], align 4
10924 // CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8
10925 // CHECK19-NEXT: store i8* null, i8** [[TMP148]], align 4
10926 // CHECK19-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
10927 // CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
10928 // CHECK19-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10929 // CHECK19-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10930 // CHECK19-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
10931 // CHECK19-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
10932 // CHECK19: omp_offload.failed23:
10933 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
10934 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT24]]
10935 // CHECK19: omp_offload.cont24:
10936 // CHECK19-NEXT: br label [[OMP_IF_END26:%.*]]
10937 // CHECK19: omp_if.else25:
10938 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
10939 // CHECK19-NEXT: br label [[OMP_IF_END26]]
10940 // CHECK19: omp_if.end26:
10941 // CHECK19-NEXT: store i32 0, i32* [[NN]], align 4
10942 // CHECK19-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
10943 // CHECK19-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4
10944 // CHECK19-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4
10945 // CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
10946 // CHECK19-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32*
10947 // CHECK19-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4
10948 // CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
10949 // CHECK19-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32*
10950 // CHECK19-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4
10951 // CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
10952 // CHECK19-NEXT: store i8* null, i8** [[TMP160]], align 4
10953 // CHECK19-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
10954 // CHECK19-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
10955 // CHECK19-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10956 // CHECK19-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
10957 // CHECK19-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
10958 // CHECK19: omp_offload.failed30:
10959 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]]
10960 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT31]]
10961 // CHECK19: omp_offload.cont31:
10962 // CHECK19-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
10963 // CHECK19-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4
10964 // CHECK19-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4
10965 // CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
10966 // CHECK19-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32*
10967 // CHECK19-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4
10968 // CHECK19-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
10969 // CHECK19-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32*
10970 // CHECK19-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4
10971 // CHECK19-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0
10972 // CHECK19-NEXT: store i8* null, i8** [[TMP171]], align 4
10973 // CHECK19-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
10974 // CHECK19-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
10975 // CHECK19-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
10976 // CHECK19-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
10977 // CHECK19-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
10978 // CHECK19: omp_offload.failed36:
10979 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]]
10980 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT37]]
10981 // CHECK19: omp_offload.cont37:
10982 // CHECK19-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
10983 // CHECK19-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
10984 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
10985 // CHECK19-NEXT: ret i32 [[TMP176]]
10986 //
10987 //
10988 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
10989 // CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
10990 // CHECK19-NEXT: entry:
10991 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
10992 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10993 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
10994 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
10995 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
10996 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
10997 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10998 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
10999 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11000 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11001 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
11002 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
11003 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11004 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11005 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
11006 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11007 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
11008 // CHECK19-NEXT: ret void
11009 //
11010 //
11011 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
11012 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11013 // CHECK19-NEXT: entry:
11014 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11015 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11016 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11017 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11018 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11019 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11020 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11021 // CHECK19-NEXT: ret void
11022 //
11023 //
11024 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
11025 // CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
11026 // CHECK19-NEXT: entry:
11027 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
11028 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
11029 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
11030 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
11031 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
11032 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
11033 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
11034 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
11035 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
11036 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
11037 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
11038 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
11039 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
11040 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
11041 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
11042 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
11043 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
11044 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
11045 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
11046 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
11047 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
11048 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
11049 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
11050 // CHECK19-NEXT: ret void
11051 //
11052 //
11053 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
11054 // CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
11055 // CHECK19-NEXT: entry:
11056 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
11057 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
11058 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
11059 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
11060 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
11061 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
11062 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
11063 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
11064 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
11065 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
11066 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
11067 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
11068 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
11069 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
11070 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
11071 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
11072 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
11073 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
11074 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
11075 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
11076 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
11077 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
11078 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
11079 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
11080 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
11081 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
11082 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
11083 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
11084 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
11085 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
11086 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
11087 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
11088 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
11089 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
11090 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
11091 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
11092 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
11093 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
11094 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
11095 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
11096 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
11097 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
11098 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
11099 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
11100 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
11101 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
11102 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
11103 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
11104 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
11105 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
11106 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
11107 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
11108 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
11109 // CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
11110 // CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
11111 // CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
11112 // CHECK19: omp_offload.failed.i:
11113 // CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
11114 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
11115 // CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
11116 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
11117 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
11118 // CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
11119 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
11120 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
11121 // CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
11122 // CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
11123 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
11124 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
11125 // CHECK19: .omp_outlined..1.exit:
11126 // CHECK19-NEXT: ret i32 0
11127 //
11128 //
11129 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
11130 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
11131 // CHECK19-NEXT: entry:
11132 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11133 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11134 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11135 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11136 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11137 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11138 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11139 // CHECK19-NEXT: ret void
11140 //
11141 //
11142 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
11143 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
11144 // CHECK19-NEXT: entry:
11145 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11146 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11147 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11148 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11149 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11150 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11151 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11152 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11153 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
11154 // CHECK19-NEXT: ret void
11155 //
11156 //
11157 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
11158 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
11159 // CHECK19-NEXT: entry:
11160 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11161 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11162 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11163 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11164 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
11165 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11166 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
11167 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11168 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11169 // CHECK19-NEXT: ret void
11170 //
11171 //
11172 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
11173 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11174 // CHECK19-NEXT: entry:
11175 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11176 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11177 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11178 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11179 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11180 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11181 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11182 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
11183 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
11184 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
11185 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
11186 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
11187 // CHECK19-NEXT: ret void
11188 //
11189 //
11190 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
11191 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11192 // CHECK19-NEXT: entry:
11193 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11194 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11195 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11196 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11197 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11198 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11199 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11200 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11201 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11202 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11203 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11204 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11205 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
11206 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11207 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
11208 // CHECK19-NEXT: ret void
11209 //
11210 //
11211 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
11212 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11213 // CHECK19-NEXT: entry:
11214 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11215 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11216 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11217 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11218 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11219 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11220 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11221 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11222 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11223 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11224 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11225 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
11226 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
11227 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
11228 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
11229 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
11230 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
11231 // CHECK19-NEXT: ret void
11232 //
11233 //
11234 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
11235 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
11236 // CHECK19-NEXT: entry:
11237 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11238 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11239 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
11240 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
11241 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11242 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
11243 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
11244 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
11245 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11246 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11247 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11248 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11249 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11250 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
11251 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11252 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11253 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11254 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
11255 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11256 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11257 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11258 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11259 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11260 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11261 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11262 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11263 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11264 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11265 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
11266 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
11267 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
11268 // CHECK19-NEXT: ret void
11269 //
11270 //
11271 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9
11272 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
11273 // CHECK19-NEXT: entry:
11274 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11275 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11276 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11277 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11278 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
11279 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
11280 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11281 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
11282 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
11283 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
11284 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11285 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11286 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11287 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11288 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11289 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11290 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
11291 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11292 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11293 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11294 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
11295 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11296 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11297 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11298 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11299 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11300 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11301 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11302 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11303 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11304 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11305 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
11306 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
11307 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
11308 // CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
11309 // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
11310 // CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
11311 // CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
11312 // CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
11313 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
11314 // CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
11315 // CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
11316 // CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
11317 // CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
11318 // CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
11319 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
11320 // CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
11321 // CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
11322 // CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
11323 // CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
11324 // CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
11325 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
11326 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
11327 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
11328 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
11329 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
11330 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
11331 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
11332 // CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
11333 // CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
11334 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
11335 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
11336 // CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
11337 // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
11338 // CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
11339 // CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
11340 // CHECK19-NEXT: ret void
11341 //
11342 //
11343 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
11344 // CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
11345 // CHECK19-NEXT: entry:
11346 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
11347 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
11348 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
11349 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
11350 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
11351 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
11352 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11353 // CHECK19-NEXT: ret void
11354 //
11355 //
11356 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
11357 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
11358 // CHECK19-NEXT: entry:
11359 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11360 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11361 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
11362 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
11363 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11364 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11365 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
11366 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
11367 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
11368 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
11369 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11370 // CHECK19-NEXT: ret void
11371 //
11372 //
11373 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12
11374 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
11375 // CHECK19-NEXT: entry:
11376 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11377 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11378 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
11379 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11380 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11381 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
11382 // CHECK19-NEXT: ret void
11383 //
11384 //
11385 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
11386 // CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
11387 // CHECK19-NEXT: entry:
11388 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
11389 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
11390 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
11391 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
11392 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
11393 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
11394 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11395 // CHECK19-NEXT: ret void
11396 //
11397 //
11398 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15
11399 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
11400 // CHECK19-NEXT: entry:
11401 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11402 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11403 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
11404 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11405 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11406 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
11407 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
11408 // CHECK19-NEXT: ret void
11409 //
11410 //
11411 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16
11412 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
11413 // CHECK19-NEXT: entry:
11414 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11415 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11416 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
11417 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11418 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11419 // CHECK19-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
11420 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
11421 // CHECK19-NEXT: ret void
11422 //
11423 //
11424 // CHECK19-LABEL: define {{[^@]+}}@_Z6bazzzziPi
11425 // CHECK19-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
11426 // CHECK19-NEXT: entry:
11427 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
11428 // CHECK19-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4
11429 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
11430 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
11431 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
11432 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
11433 // CHECK19-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4
11434 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11435 // CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11436 // CHECK19-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32*
11437 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4
11438 // CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11439 // CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
11440 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4
11441 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11442 // CHECK19-NEXT: store i8* null, i8** [[TMP5]], align 4
11443 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11444 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11445 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
11446 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
11447 // CHECK19-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11448 // CHECK19: omp_offload.failed:
11449 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]]
11450 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
11451 // CHECK19: omp_offload.cont:
11452 // CHECK19-NEXT: ret void
11453 //
11454 //
11455 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
11456 // CHECK19-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] {
11457 // CHECK19-NEXT: entry:
11458 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
11459 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11460 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11461 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]])
11462 // CHECK19-NEXT: ret void
11463 //
11464 //
11465 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..19
11466 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] {
11467 // CHECK19-NEXT: entry:
11468 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11469 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11470 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
11471 // CHECK19-NEXT: [[F:%.*]] = alloca i32*, align 4
11472 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11473 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11474 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11475 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11476 // CHECK19-NEXT: ret void
11477 //
11478 //
11479 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
11480 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
11481 // CHECK19-NEXT: entry:
11482 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
11483 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
11484 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
11485 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
11486 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
11487 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11488 // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
11489 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11490 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
11491 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4
11492 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11493 // CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
11494 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
11495 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
11496 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
11497 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11498 // CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
11499 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
11500 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
11501 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
11502 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11503 // CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
11504 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
11505 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
11506 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
11507 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
11508 // CHECK19-NEXT: ret i32 [[TMP8]]
11509 //
11510 //
11511 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
11512 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
11513 // CHECK19-NEXT: entry:
11514 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11515 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
11516 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4
11517 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
11518 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
11519 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
11520 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
11521 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
11522 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
11523 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
11524 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11525 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
11526 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11527 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11528 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11529 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4
11530 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11531 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
11532 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
11533 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
11534 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
11535 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
11536 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
11537 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11538 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11539 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11540 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
11541 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11542 // CHECK19: omp_if.then:
11543 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
11544 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
11545 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
11546 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
11547 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11548 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
11549 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
11550 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11551 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
11552 // CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4
11553 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11554 // CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4
11555 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11556 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4
11557 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11558 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
11559 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
11560 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11561 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
11562 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
11563 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
11564 // CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4
11565 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11566 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4
11567 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11568 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
11569 // CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4
11570 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11571 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
11572 // CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4
11573 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
11574 // CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4
11575 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11576 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4
11577 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11578 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
11579 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
11580 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11581 // CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
11582 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4
11583 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
11584 // CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4
11585 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11586 // CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4
11587 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
11588 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
11589 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4
11590 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
11591 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
11592 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4
11593 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
11594 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4
11595 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
11596 // CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4
11597 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11598 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11599 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11600 // CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
11601 // CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
11602 // CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11603 // CHECK19: omp_offload.failed:
11604 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
11605 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
11606 // CHECK19: omp_offload.cont:
11607 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
11608 // CHECK19: omp_if.else:
11609 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
11610 // CHECK19-NEXT: br label [[OMP_IF_END]]
11611 // CHECK19: omp_if.end:
11612 // CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
11613 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
11614 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11615 // CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
11616 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32
11617 // CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
11618 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
11619 // CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11620 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
11621 // CHECK19-NEXT: ret i32 [[ADD3]]
11622 //
11623 //
11624 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
11625 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
11626 // CHECK19-NEXT: entry:
11627 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
11628 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
11629 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
11630 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1
11631 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
11632 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11633 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11634 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
11635 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
11636 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
11637 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
11638 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
11639 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
11640 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
11641 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1
11642 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11643 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11644 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11645 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11646 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11647 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
11648 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11649 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
11650 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11651 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
11652 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11653 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11654 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
11655 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11656 // CHECK19: omp_if.then:
11657 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11658 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11659 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
11660 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11661 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
11662 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
11663 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11664 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4
11665 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11666 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11667 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
11668 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11669 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
11670 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
11671 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11672 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4
11673 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11674 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
11675 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
11676 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11677 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11678 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
11679 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11680 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4
11681 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11682 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
11683 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
11684 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11685 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
11686 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
11687 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11688 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4
11689 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11690 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11691 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
11692 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
11693 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11694 // CHECK19: omp_offload.failed:
11695 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
11696 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
11697 // CHECK19: omp_offload.cont:
11698 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
11699 // CHECK19: omp_if.else:
11700 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
11701 // CHECK19-NEXT: br label [[OMP_IF_END]]
11702 // CHECK19: omp_if.end:
11703 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
11704 // CHECK19-NEXT: ret i32 [[TMP31]]
11705 //
11706 //
11707 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
11708 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
11709 // CHECK19-NEXT: entry:
11710 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
11711 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
11712 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
11713 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
11714 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11715 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11716 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
11717 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
11718 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
11719 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
11720 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4
11721 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
11722 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11723 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11724 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11725 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11726 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11727 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
11728 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11729 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11730 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
11731 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11732 // CHECK19: omp_if.then:
11733 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11734 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
11735 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
11736 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11737 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11738 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
11739 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11740 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4
11741 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11742 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
11743 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
11744 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11745 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11746 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
11747 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11748 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4
11749 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11750 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
11751 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
11752 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11753 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
11754 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
11755 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11756 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4
11757 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11758 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11759 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
11760 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
11761 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11762 // CHECK19: omp_offload.failed:
11763 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
11764 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
11765 // CHECK19: omp_offload.cont:
11766 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
11767 // CHECK19: omp_if.else:
11768 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
11769 // CHECK19-NEXT: br label [[OMP_IF_END]]
11770 // CHECK19: omp_if.end:
11771 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
11772 // CHECK19-NEXT: ret i32 [[TMP24]]
11773 //
11774 //
11775 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
11776 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
11777 // CHECK19-NEXT: entry:
11778 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11779 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
11780 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
11781 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
11782 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
11783 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
11784 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11785 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
11786 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11787 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11788 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
11789 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11790 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11791 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11792 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11793 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11794 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11795 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11796 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
11797 // CHECK19-NEXT: ret void
11798 //
11799 //
11800 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22
11801 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
11802 // CHECK19-NEXT: entry:
11803 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11804 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11805 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11806 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
11807 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
11808 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
11809 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
11810 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11811 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11812 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11813 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
11814 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11815 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11816 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
11817 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11818 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11819 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11820 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11821 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11822 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
11823 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
11824 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
11825 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4
11826 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11827 // CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
11828 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
11829 // CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4
11830 // CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
11831 // CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
11832 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
11833 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11834 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
11835 // CHECK19-NEXT: ret void
11836 //
11837 //
11838 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
11839 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11840 // CHECK19-NEXT: entry:
11841 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11842 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11843 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
11844 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11845 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11846 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11847 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
11848 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11849 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11850 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11851 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11852 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11853 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11854 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11855 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11856 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11857 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11858 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11859 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11860 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
11861 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11862 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
11863 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11864 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
11865 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11866 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
11867 // CHECK19-NEXT: ret void
11868 //
11869 //
11870 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..24
11871 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11872 // CHECK19-NEXT: entry:
11873 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11874 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11875 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11876 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11877 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
11878 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11879 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11880 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11881 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11882 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11883 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11884 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11885 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11886 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11887 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11888 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11889 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
11890 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
11891 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11892 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
11893 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
11894 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11895 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
11896 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
11897 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
11898 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
11899 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
11900 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
11901 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11902 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11903 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
11904 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
11905 // CHECK19-NEXT: ret void
11906 //
11907 //
11908 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
11909 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11910 // CHECK19-NEXT: entry:
11911 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11912 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11913 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11914 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11915 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11916 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11917 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11918 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11919 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11920 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11921 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11922 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11923 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11924 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11925 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11926 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
11927 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11928 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
11929 // CHECK19-NEXT: ret void
11930 //
11931 //
11932 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..27
11933 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11934 // CHECK19-NEXT: entry:
11935 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11936 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11937 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11938 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11939 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11940 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11941 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11942 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11943 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11944 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11945 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11946 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11947 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11948 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
11949 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
11950 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11951 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
11952 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
11953 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
11954 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
11955 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11956 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11957 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
11958 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
11959 // CHECK19-NEXT: ret void
11960 //
11961 //
11962 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
11963 // CHECK19-SAME: () #[[ATTR4]] {
11964 // CHECK19-NEXT: entry:
11965 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
11966 // CHECK19-NEXT: ret void
11967 //
11968 //
11969 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi
11970 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
11971 // CHECK20-NEXT: entry:
11972 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
11973 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
11974 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2
11975 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4
11976 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
11977 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
11978 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
11979 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
11980 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
11981 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11982 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11983 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
11984 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
11985 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
11986 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
11987 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
11988 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
11989 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
11990 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
11991 // CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
11992 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
11993 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
11994 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
11995 // CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4
11996 // CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4
11997 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
11998 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
11999 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
12000 // CHECK20-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4
12001 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4
12002 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4
12003 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4
12004 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
12005 // CHECK20-NEXT: [[NN:%.*]] = alloca i32, align 4
12006 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
12007 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4
12008 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4
12009 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4
12010 // CHECK20-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4
12011 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4
12012 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4
12013 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4
12014 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
12015 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
12016 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4
12017 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2
12018 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12019 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
12020 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12021 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
12022 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12023 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
12024 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
12025 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
12026 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
12027 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12028 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
12029 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12030 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
12031 // CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
12032 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12033 // CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2
12034 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12035 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12036 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12037 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12038 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12039 // CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
12040 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
12041 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12042 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
12043 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4
12044 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12045 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
12046 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4
12047 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12048 // CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4
12049 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
12050 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
12051 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4
12052 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
12053 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
12054 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4
12055 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
12056 // CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4
12057 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
12058 // CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
12059 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4
12060 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
12061 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
12062 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4
12063 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
12064 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4
12065 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12066 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12067 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
12068 // CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
12069 // CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4
12070 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
12071 // CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12072 // CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4
12073 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
12074 // CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12075 // CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
12076 // CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
12077 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
12078 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
12079 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
12080 // CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
12081 // CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
12082 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
12083 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
12084 // CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
12085 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
12086 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
12087 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
12088 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
12089 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
12090 // CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
12091 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
12092 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
12093 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
12094 // CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
12095 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
12096 // CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
12097 // CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
12098 // CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4
12099 // CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]])
12100 // CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
12101 // CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4
12102 // CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
12103 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
12104 // CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
12105 // CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
12106 // CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2
12107 // CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
12108 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
12109 // CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
12110 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4
12111 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
12112 // CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
12113 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4
12114 // CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
12115 // CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4
12116 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
12117 // CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
12118 // CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12119 // CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
12120 // CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12121 // CHECK20: omp_offload.failed:
12122 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]]
12123 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
12124 // CHECK20: omp_offload.cont:
12125 // CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4
12126 // CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
12127 // CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
12128 // CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
12129 // CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
12130 // CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2
12131 // CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
12132 // CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
12133 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
12134 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12135 // CHECK20: omp_if.then:
12136 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
12137 // CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
12138 // CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4
12139 // CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
12140 // CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
12141 // CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4
12142 // CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
12143 // CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4
12144 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
12145 // CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
12146 // CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4
12147 // CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
12148 // CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
12149 // CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4
12150 // CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
12151 // CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4
12152 // CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
12153 // CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
12154 // CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12155 // CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
12156 // CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
12157 // CHECK20: omp_offload.failed15:
12158 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
12159 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]]
12160 // CHECK20: omp_offload.cont16:
12161 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
12162 // CHECK20: omp_if.else:
12163 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
12164 // CHECK20-NEXT: br label [[OMP_IF_END]]
12165 // CHECK20: omp_if.end:
12166 // CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4
12167 // CHECK20-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4
12168 // CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4
12169 // CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
12170 // CHECK20-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20
12171 // CHECK20-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
12172 // CHECK20: omp_if.then19:
12173 // CHECK20-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
12174 // CHECK20-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
12175 // CHECK20-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
12176 // CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
12177 // CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
12178 // CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
12179 // CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32*
12180 // CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4
12181 // CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
12182 // CHECK20-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32*
12183 // CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4
12184 // CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12185 // CHECK20-NEXT: store i64 4, i64* [[TMP99]], align 4
12186 // CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
12187 // CHECK20-NEXT: store i8* null, i8** [[TMP100]], align 4
12188 // CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
12189 // CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
12190 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
12191 // CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
12192 // CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
12193 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
12194 // CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
12195 // CHECK20-NEXT: store i64 40, i64* [[TMP105]], align 4
12196 // CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1
12197 // CHECK20-NEXT: store i8* null, i8** [[TMP106]], align 4
12198 // CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
12199 // CHECK20-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32*
12200 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4
12201 // CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
12202 // CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32*
12203 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4
12204 // CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
12205 // CHECK20-NEXT: store i64 4, i64* [[TMP111]], align 4
12206 // CHECK20-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2
12207 // CHECK20-NEXT: store i8* null, i8** [[TMP112]], align 4
12208 // CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
12209 // CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
12210 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP114]], align 4
12211 // CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
12212 // CHECK20-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float**
12213 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP116]], align 4
12214 // CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
12215 // CHECK20-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4
12216 // CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3
12217 // CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4
12218 // CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
12219 // CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
12220 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
12221 // CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
12222 // CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]**
12223 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4
12224 // CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
12225 // CHECK20-NEXT: store i64 400, i64* [[TMP123]], align 4
12226 // CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4
12227 // CHECK20-NEXT: store i8* null, i8** [[TMP124]], align 4
12228 // CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
12229 // CHECK20-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32*
12230 // CHECK20-NEXT: store i32 5, i32* [[TMP126]], align 4
12231 // CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
12232 // CHECK20-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
12233 // CHECK20-NEXT: store i32 5, i32* [[TMP128]], align 4
12234 // CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
12235 // CHECK20-NEXT: store i64 4, i64* [[TMP129]], align 4
12236 // CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5
12237 // CHECK20-NEXT: store i8* null, i8** [[TMP130]], align 4
12238 // CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
12239 // CHECK20-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32*
12240 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4
12241 // CHECK20-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
12242 // CHECK20-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32*
12243 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4
12244 // CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
12245 // CHECK20-NEXT: store i64 4, i64* [[TMP135]], align 4
12246 // CHECK20-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6
12247 // CHECK20-NEXT: store i8* null, i8** [[TMP136]], align 4
12248 // CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
12249 // CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double**
12250 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4
12251 // CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
12252 // CHECK20-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double**
12253 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4
12254 // CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
12255 // CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4
12256 // CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7
12257 // CHECK20-NEXT: store i8* null, i8** [[TMP142]], align 4
12258 // CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
12259 // CHECK20-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT**
12260 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4
12261 // CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
12262 // CHECK20-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT**
12263 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4
12264 // CHECK20-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
12265 // CHECK20-NEXT: store i64 12, i64* [[TMP147]], align 4
12266 // CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8
12267 // CHECK20-NEXT: store i8* null, i8** [[TMP148]], align 4
12268 // CHECK20-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
12269 // CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
12270 // CHECK20-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12271 // CHECK20-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12272 // CHECK20-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
12273 // CHECK20-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
12274 // CHECK20: omp_offload.failed23:
12275 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
12276 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT24]]
12277 // CHECK20: omp_offload.cont24:
12278 // CHECK20-NEXT: br label [[OMP_IF_END26:%.*]]
12279 // CHECK20: omp_if.else25:
12280 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
12281 // CHECK20-NEXT: br label [[OMP_IF_END26]]
12282 // CHECK20: omp_if.end26:
12283 // CHECK20-NEXT: store i32 0, i32* [[NN]], align 4
12284 // CHECK20-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4
12285 // CHECK20-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4
12286 // CHECK20-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4
12287 // CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
12288 // CHECK20-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32*
12289 // CHECK20-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4
12290 // CHECK20-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
12291 // CHECK20-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32*
12292 // CHECK20-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4
12293 // CHECK20-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
12294 // CHECK20-NEXT: store i8* null, i8** [[TMP160]], align 4
12295 // CHECK20-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
12296 // CHECK20-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
12297 // CHECK20-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12298 // CHECK20-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0
12299 // CHECK20-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
12300 // CHECK20: omp_offload.failed30:
12301 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]]
12302 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT31]]
12303 // CHECK20: omp_offload.cont31:
12304 // CHECK20-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4
12305 // CHECK20-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4
12306 // CHECK20-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4
12307 // CHECK20-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
12308 // CHECK20-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32*
12309 // CHECK20-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4
12310 // CHECK20-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
12311 // CHECK20-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32*
12312 // CHECK20-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4
12313 // CHECK20-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0
12314 // CHECK20-NEXT: store i8* null, i8** [[TMP171]], align 4
12315 // CHECK20-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0
12316 // CHECK20-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0
12317 // CHECK20-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12318 // CHECK20-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0
12319 // CHECK20-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
12320 // CHECK20: omp_offload.failed36:
12321 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]]
12322 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT37]]
12323 // CHECK20: omp_offload.cont37:
12324 // CHECK20-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4
12325 // CHECK20-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12326 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP177]])
12327 // CHECK20-NEXT: ret i32 [[TMP176]]
12328 //
12329 //
12330 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
12331 // CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
12332 // CHECK20-NEXT: entry:
12333 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12334 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12335 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
12336 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
12337 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
12338 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12339 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12340 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
12341 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12342 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12343 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
12344 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
12345 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
12346 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12347 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
12348 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12349 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
12350 // CHECK20-NEXT: ret void
12351 //
12352 //
12353 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
12354 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
12355 // CHECK20-NEXT: entry:
12356 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12357 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12358 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12359 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12360 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12361 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12362 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12363 // CHECK20-NEXT: ret void
12364 //
12365 //
12366 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map.
12367 // CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
12368 // CHECK20-NEXT: entry:
12369 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
12370 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
12371 // CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
12372 // CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
12373 // CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
12374 // CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
12375 // CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
12376 // CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
12377 // CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
12378 // CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
12379 // CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
12380 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
12381 // CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
12382 // CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
12383 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
12384 // CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
12385 // CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
12386 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
12387 // CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
12388 // CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
12389 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
12390 // CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
12391 // CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
12392 // CHECK20-NEXT: ret void
12393 //
12394 //
12395 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry.
12396 // CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
12397 // CHECK20-NEXT: entry:
12398 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
12399 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
12400 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
12401 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
12402 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
12403 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
12404 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
12405 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
12406 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
12407 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
12408 // CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
12409 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
12410 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
12411 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
12412 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
12413 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
12414 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
12415 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
12416 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
12417 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
12418 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
12419 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
12420 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
12421 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
12422 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
12423 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
12424 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
12425 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
12426 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
12427 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
12428 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
12429 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
12430 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
12431 // CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
12432 // CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
12433 // CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
12434 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
12435 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
12436 // CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
12437 // CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
12438 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
12439 // CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
12440 // CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
12441 // CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
12442 // CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
12443 // CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
12444 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
12445 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
12446 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
12447 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
12448 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
12449 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
12450 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
12451 // CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]]
12452 // CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
12453 // CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
12454 // CHECK20: omp_offload.failed.i:
12455 // CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
12456 // CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
12457 // CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
12458 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
12459 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
12460 // CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
12461 // CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
12462 // CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
12463 // CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
12464 // CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
12465 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
12466 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
12467 // CHECK20: .omp_outlined..1.exit:
12468 // CHECK20-NEXT: ret i32 0
12469 //
12470 //
12471 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
12472 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
12473 // CHECK20-NEXT: entry:
12474 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12475 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
12476 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12477 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12478 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12479 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12480 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12481 // CHECK20-NEXT: ret void
12482 //
12483 //
12484 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
12485 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
12486 // CHECK20-NEXT: entry:
12487 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12488 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12489 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12490 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12491 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12492 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12493 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12494 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12495 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
12496 // CHECK20-NEXT: ret void
12497 //
12498 //
12499 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
12500 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
12501 // CHECK20-NEXT: entry:
12502 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12503 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
12504 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12505 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12506 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
12507 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12508 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
12509 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12510 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12511 // CHECK20-NEXT: ret void
12512 //
12513 //
12514 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
12515 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
12516 // CHECK20-NEXT: entry:
12517 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12518 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12519 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12520 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12521 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12522 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12523 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12524 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
12525 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
12526 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
12527 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
12528 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
12529 // CHECK20-NEXT: ret void
12530 //
12531 //
12532 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
12533 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
12534 // CHECK20-NEXT: entry:
12535 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12536 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12537 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
12538 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
12539 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12540 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12541 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12542 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12543 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12544 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12545 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
12546 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12547 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
12548 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12549 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
12550 // CHECK20-NEXT: ret void
12551 //
12552 //
12553 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
12554 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
12555 // CHECK20-NEXT: entry:
12556 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12557 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12558 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12559 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12560 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12561 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12562 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12563 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12564 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12565 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12566 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12567 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
12568 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
12569 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
12570 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
12571 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
12572 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
12573 // CHECK20-NEXT: ret void
12574 //
12575 //
12576 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
12577 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
12578 // CHECK20-NEXT: entry:
12579 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12580 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
12581 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
12582 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
12583 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
12584 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
12585 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
12586 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
12587 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
12588 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
12589 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12590 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
12591 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12592 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
12593 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
12594 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12595 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
12596 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
12597 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
12598 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
12599 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12600 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
12601 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
12602 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12603 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
12604 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
12605 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
12606 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
12607 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
12608 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
12609 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
12610 // CHECK20-NEXT: ret void
12611 //
12612 //
12613 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9
12614 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
12615 // CHECK20-NEXT: entry:
12616 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12617 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12618 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12619 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
12620 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
12621 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
12622 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
12623 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
12624 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
12625 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
12626 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
12627 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12628 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12629 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12630 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
12631 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12632 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
12633 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
12634 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12635 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
12636 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
12637 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
12638 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
12639 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12640 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
12641 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
12642 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12643 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
12644 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
12645 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
12646 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
12647 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
12648 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
12649 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
12650 // CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
12651 // CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
12652 // CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
12653 // CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
12654 // CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
12655 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
12656 // CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
12657 // CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
12658 // CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
12659 // CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
12660 // CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
12661 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
12662 // CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
12663 // CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
12664 // CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
12665 // CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
12666 // CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
12667 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
12668 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
12669 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
12670 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
12671 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
12672 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
12673 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
12674 // CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
12675 // CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
12676 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
12677 // CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
12678 // CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
12679 // CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
12680 // CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
12681 // CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
12682 // CHECK20-NEXT: ret void
12683 //
12684 //
12685 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
12686 // CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
12687 // CHECK20-NEXT: entry:
12688 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
12689 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
12690 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
12691 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
12692 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
12693 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
12694 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12695 // CHECK20-NEXT: ret void
12696 //
12697 //
12698 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
12699 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
12700 // CHECK20-NEXT: entry:
12701 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12702 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12703 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
12704 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
12705 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12706 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12707 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
12708 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
12709 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
12710 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
12711 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12712 // CHECK20-NEXT: ret void
12713 //
12714 //
12715 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12
12716 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
12717 // CHECK20-NEXT: entry:
12718 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12719 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12720 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
12721 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12722 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12723 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
12724 // CHECK20-NEXT: ret void
12725 //
12726 //
12727 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
12728 // CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] {
12729 // CHECK20-NEXT: entry:
12730 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
12731 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
12732 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
12733 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
12734 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
12735 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
12736 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12737 // CHECK20-NEXT: ret void
12738 //
12739 //
12740 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15
12741 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] {
12742 // CHECK20-NEXT: entry:
12743 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12744 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12745 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
12746 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12747 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12748 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
12749 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
12750 // CHECK20-NEXT: ret void
12751 //
12752 //
12753 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16
12754 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
12755 // CHECK20-NEXT: entry:
12756 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12757 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12758 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
12759 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12760 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12761 // CHECK20-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
12762 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
12763 // CHECK20-NEXT: ret void
12764 //
12765 //
12766 // CHECK20-LABEL: define {{[^@]+}}@_Z6bazzzziPi
12767 // CHECK20-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] {
12768 // CHECK20-NEXT: entry:
12769 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
12770 // CHECK20-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4
12771 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
12772 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
12773 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
12774 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
12775 // CHECK20-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4
12776 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12777 // CHECK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12778 // CHECK20-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32*
12779 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4
12780 // CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12781 // CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
12782 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4
12783 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12784 // CHECK20-NEXT: store i8* null, i8** [[TMP5]], align 4
12785 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12786 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12787 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12788 // CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
12789 // CHECK20-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12790 // CHECK20: omp_offload.failed:
12791 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]]
12792 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
12793 // CHECK20: omp_offload.cont:
12794 // CHECK20-NEXT: ret void
12795 //
12796 //
12797 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
12798 // CHECK20-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] {
12799 // CHECK20-NEXT: entry:
12800 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
12801 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12802 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12803 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]])
12804 // CHECK20-NEXT: ret void
12805 //
12806 //
12807 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..19
12808 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] {
12809 // CHECK20-NEXT: entry:
12810 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12811 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12812 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
12813 // CHECK20-NEXT: [[F:%.*]] = alloca i32*, align 4
12814 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12815 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12816 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12817 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12818 // CHECK20-NEXT: ret void
12819 //
12820 //
12821 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari
12822 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12823 // CHECK20-NEXT: entry:
12824 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
12825 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
12826 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12827 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
12828 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4
12829 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12830 // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12831 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12832 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12833 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4
12834 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12835 // CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12836 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12837 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12838 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
12839 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12840 // CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12841 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12842 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12843 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
12844 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12845 // CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12846 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12847 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12848 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
12849 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12850 // CHECK20-NEXT: ret i32 [[TMP8]]
12851 //
12852 //
12853 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12854 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12855 // CHECK20-NEXT: entry:
12856 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12857 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
12858 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4
12859 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
12860 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12861 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
12862 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
12863 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
12864 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
12865 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
12866 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12867 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
12868 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12869 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12870 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12871 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4
12872 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12873 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
12874 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12875 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12876 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12877 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12878 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
12879 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
12880 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
12881 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12882 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
12883 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12884 // CHECK20: omp_if.then:
12885 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12886 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
12887 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
12888 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
12889 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12890 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
12891 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
12892 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12893 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
12894 // CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4
12895 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12896 // CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4
12897 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12898 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4
12899 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
12900 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
12901 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
12902 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
12903 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
12904 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
12905 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
12906 // CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4
12907 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
12908 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4
12909 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
12910 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
12911 // CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4
12912 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
12913 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
12914 // CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4
12915 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
12916 // CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4
12917 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
12918 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4
12919 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
12920 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
12921 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
12922 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
12923 // CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
12924 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4
12925 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
12926 // CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4
12927 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
12928 // CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4
12929 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
12930 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
12931 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4
12932 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
12933 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
12934 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4
12935 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
12936 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4
12937 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
12938 // CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4
12939 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12940 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12941 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12942 // CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
12943 // CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
12944 // CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12945 // CHECK20: omp_offload.failed:
12946 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
12947 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
12948 // CHECK20: omp_offload.cont:
12949 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
12950 // CHECK20: omp_if.else:
12951 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
12952 // CHECK20-NEXT: br label [[OMP_IF_END]]
12953 // CHECK20: omp_if.end:
12954 // CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
12955 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
12956 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12957 // CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
12958 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32
12959 // CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
12960 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
12961 // CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12962 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
12963 // CHECK20-NEXT: ret i32 [[ADD3]]
12964 //
12965 //
12966 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
12967 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12968 // CHECK20-NEXT: entry:
12969 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
12970 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
12971 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2
12972 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1
12973 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
12974 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
12975 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
12976 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
12977 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
12978 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
12979 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
12980 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
12981 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4
12982 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2
12983 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1
12984 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12985 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12986 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12987 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12988 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12989 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
12990 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12991 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
12992 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
12993 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
12994 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
12995 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12996 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
12997 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12998 // CHECK20: omp_if.then:
12999 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13000 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
13001 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
13002 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13003 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
13004 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
13005 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
13006 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4
13007 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13008 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
13009 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
13010 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13011 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
13012 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
13013 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
13014 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4
13015 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13016 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
13017 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
13018 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13019 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
13020 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
13021 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
13022 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4
13023 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
13024 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
13025 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
13026 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
13027 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
13028 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
13029 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
13030 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4
13031 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13032 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13033 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
13034 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
13035 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
13036 // CHECK20: omp_offload.failed:
13037 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
13038 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
13039 // CHECK20: omp_offload.cont:
13040 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
13041 // CHECK20: omp_if.else:
13042 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
13043 // CHECK20-NEXT: br label [[OMP_IF_END]]
13044 // CHECK20: omp_if.end:
13045 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
13046 // CHECK20-NEXT: ret i32 [[TMP31]]
13047 //
13048 //
13049 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
13050 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
13051 // CHECK20-NEXT: entry:
13052 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
13053 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
13054 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2
13055 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
13056 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
13057 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
13058 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
13059 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
13060 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
13061 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
13062 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4
13063 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2
13064 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
13065 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
13066 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
13067 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
13068 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13069 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
13070 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13071 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13072 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
13073 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13074 // CHECK20: omp_if.then:
13075 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13076 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
13077 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
13078 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13079 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
13080 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
13081 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
13082 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4
13083 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13084 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
13085 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
13086 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13087 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
13088 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
13089 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
13090 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4
13091 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13092 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
13093 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
13094 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13095 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
13096 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
13097 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
13098 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4
13099 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13100 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13101 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
13102 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
13103 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
13104 // CHECK20: omp_offload.failed:
13105 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
13106 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
13107 // CHECK20: omp_offload.cont:
13108 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
13109 // CHECK20: omp_if.else:
13110 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
13111 // CHECK20-NEXT: br label [[OMP_IF_END]]
13112 // CHECK20: omp_if.end:
13113 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
13114 // CHECK20-NEXT: ret i32 [[TMP24]]
13115 //
13116 //
13117 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
13118 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
13119 // CHECK20-NEXT: entry:
13120 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13121 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
13122 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
13123 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
13124 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
13125 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
13126 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13127 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
13128 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13129 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13130 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
13131 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13132 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13133 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13134 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13135 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
13136 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
13137 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
13138 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
13139 // CHECK20-NEXT: ret void
13140 //
13141 //
13142 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22
13143 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
13144 // CHECK20-NEXT: entry:
13145 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13146 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13147 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13148 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
13149 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
13150 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
13151 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
13152 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13153 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13154 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13155 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
13156 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13157 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13158 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
13159 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13160 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13161 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13162 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13163 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
13164 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
13165 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
13166 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13167 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4
13168 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13169 // CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
13170 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
13171 // CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4
13172 // CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
13173 // CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
13174 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
13175 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13176 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
13177 // CHECK20-NEXT: ret void
13178 //
13179 //
13180 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
13181 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13182 // CHECK20-NEXT: entry:
13183 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
13184 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
13185 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
13186 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13187 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
13188 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
13189 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
13190 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
13191 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
13192 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13193 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13194 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13195 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13196 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13197 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13198 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13199 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13200 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
13201 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13202 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
13203 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13204 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
13205 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
13206 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
13207 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
13208 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
13209 // CHECK20-NEXT: ret void
13210 //
13211 //
13212 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..24
13213 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13214 // CHECK20-NEXT: entry:
13215 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13216 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13217 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
13218 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
13219 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
13220 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13221 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13222 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13223 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
13224 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
13225 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13226 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13227 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13228 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13229 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13230 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13231 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13232 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
13233 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
13234 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
13235 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13236 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13237 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
13238 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
13239 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
13240 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
13241 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
13242 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
13243 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13244 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13245 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
13246 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
13247 // CHECK20-NEXT: ret void
13248 //
13249 //
13250 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
13251 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13252 // CHECK20-NEXT: entry:
13253 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
13254 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
13255 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13256 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
13257 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
13258 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
13259 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
13260 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13261 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13262 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13263 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13264 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13265 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13266 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
13267 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13268 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
13269 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13270 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
13271 // CHECK20-NEXT: ret void
13272 //
13273 //
13274 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..27
13275 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13276 // CHECK20-NEXT: entry:
13277 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13278 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13279 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
13280 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
13281 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13282 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13283 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13284 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
13285 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
13286 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13287 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13288 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13289 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13290 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13291 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
13292 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
13293 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
13294 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
13295 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
13296 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
13297 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13298 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13299 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
13300 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
13301 // CHECK20-NEXT: ret void
13302 //
13303 //
13304 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
13305 // CHECK20-SAME: () #[[ATTR4]] {
13306 // CHECK20-NEXT: entry:
13307 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
13308 // CHECK20-NEXT: ret void
13309 //
13310 //
13311 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
13312 // CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
13313 // CHECK25-NEXT: entry:
13314 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13315 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
13316 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
13317 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13318 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
13319 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13320 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
13321 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
13322 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13323 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
13324 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
13325 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
13326 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
13327 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
13328 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
13329 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13330 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
13331 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13332 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
13333 // CHECK25-NEXT: ret void
13334 //
13335 //
13336 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
13337 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13338 // CHECK25-NEXT: entry:
13339 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13340 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13341 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13342 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13343 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13344 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13345 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13346 // CHECK25-NEXT: ret void
13347 //
13348 //
13349 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
13350 // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
13351 // CHECK25-NEXT: entry:
13352 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13353 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13354 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13355 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13356 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13357 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13358 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
13359 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13360 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13361 // CHECK25-NEXT: ret void
13362 //
13363 //
13364 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
13365 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13366 // CHECK25-NEXT: entry:
13367 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13368 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13369 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13370 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13371 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13372 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13373 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13374 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13375 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
13376 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
13377 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
13378 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
13379 // CHECK25-NEXT: ret void
13380 //
13381 //
13382 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
13383 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13384 // CHECK25-NEXT: entry:
13385 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13386 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13387 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
13388 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13389 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13390 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13391 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13392 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13393 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13394 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13395 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
13396 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13397 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13398 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13399 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
13400 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13401 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
13402 // CHECK25-NEXT: ret void
13403 //
13404 //
13405 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
13406 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13407 // CHECK25-NEXT: entry:
13408 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13409 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13410 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13411 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13412 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13413 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13414 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13415 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13416 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13417 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13418 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13419 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13420 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
13421 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
13422 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
13423 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13424 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13425 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
13426 // CHECK25-NEXT: ret void
13427 //
13428 //
13429 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
13430 // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
13431 // CHECK25-NEXT: entry:
13432 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13433 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13434 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13435 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
13436 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13437 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
13438 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
13439 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
13440 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13441 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
13442 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13443 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13444 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13445 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
13446 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13447 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13448 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13449 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
13450 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13451 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13452 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13453 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13454 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13455 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13456 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13457 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13458 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13459 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13460 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13461 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13462 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
13463 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
13464 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
13465 // CHECK25-NEXT: ret void
13466 //
13467 //
13468 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
13469 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
13470 // CHECK25-NEXT: entry:
13471 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13472 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13473 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13474 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13475 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13476 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
13477 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13478 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
13479 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
13480 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
13481 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13482 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13483 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13484 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13485 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13486 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13487 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
13488 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13489 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13490 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13491 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
13492 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13493 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13494 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13495 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13496 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13497 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13498 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13499 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13500 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13501 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13502 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13503 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
13504 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
13505 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
13506 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
13507 // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
13508 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
13509 // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
13510 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
13511 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
13512 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
13513 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
13514 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
13515 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
13516 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
13517 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
13518 // CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
13519 // CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
13520 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
13521 // CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
13522 // CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
13523 // CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
13524 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
13525 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
13526 // CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
13527 // CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
13528 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
13529 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
13530 // CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
13531 // CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
13532 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
13533 // CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
13534 // CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
13535 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
13536 // CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
13537 // CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
13538 // CHECK25-NEXT: ret void
13539 //
13540 //
13541 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
13542 // CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
13543 // CHECK25-NEXT: entry:
13544 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
13545 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
13546 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
13547 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
13548 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13549 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
13550 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
13551 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
13552 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13553 // CHECK25-NEXT: ret void
13554 //
13555 //
13556 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
13557 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
13558 // CHECK25-NEXT: entry:
13559 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13560 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13561 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
13562 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
13563 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13564 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13565 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
13566 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
13567 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13568 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
13569 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
13570 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
13571 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13572 // CHECK25-NEXT: ret void
13573 //
13574 //
13575 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
13576 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
13577 // CHECK25-NEXT: entry:
13578 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13579 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13580 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
13581 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13582 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13583 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
13584 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
13585 // CHECK25-NEXT: ret void
13586 //
13587 //
13588 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
13589 // CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
13590 // CHECK25-NEXT: entry:
13591 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
13592 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
13593 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
13594 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
13595 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13596 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
13597 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
13598 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
13599 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13600 // CHECK25-NEXT: ret void
13601 //
13602 //
13603 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
13604 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
13605 // CHECK25-NEXT: entry:
13606 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13607 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13608 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
13609 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13610 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13611 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
13612 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
13613 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]])
13614 // CHECK25-NEXT: ret void
13615 //
13616 //
13617 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..7
13618 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
13619 // CHECK25-NEXT: entry:
13620 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13621 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13622 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
13623 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13624 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13625 // CHECK25-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
13626 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
13627 // CHECK25-NEXT: ret void
13628 //
13629 //
13630 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
13631 // CHECK25-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] {
13632 // CHECK25-NEXT: entry:
13633 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13634 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13635 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13636 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]])
13637 // CHECK25-NEXT: ret void
13638 //
13639 //
13640 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..8
13641 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] {
13642 // CHECK25-NEXT: entry:
13643 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13644 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13645 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13646 // CHECK25-NEXT: [[F:%.*]] = alloca i32*, align 8
13647 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13648 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13649 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13650 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13651 // CHECK25-NEXT: ret void
13652 //
13653 //
13654 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
13655 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13656 // CHECK25-NEXT: entry:
13657 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13658 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13659 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
13660 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13661 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
13662 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13663 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
13664 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13665 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13666 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
13667 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13668 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13669 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13670 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
13671 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13672 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13673 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13674 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
13675 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
13676 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
13677 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13678 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
13679 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13680 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
13681 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
13682 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
13683 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
13684 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
13685 // CHECK25-NEXT: ret void
13686 //
13687 //
13688 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9
13689 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13690 // CHECK25-NEXT: entry:
13691 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13692 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13693 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13694 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13695 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
13696 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13697 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13698 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13699 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13700 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13701 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
13702 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13703 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13704 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13705 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
13706 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13707 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13708 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13709 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
13710 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13711 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
13712 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
13713 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
13714 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
13715 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
13716 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
13717 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
13718 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
13719 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
13720 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
13721 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13722 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
13723 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
13724 // CHECK25-NEXT: ret void
13725 //
13726 //
13727 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
13728 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13729 // CHECK25-NEXT: entry:
13730 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
13731 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
13732 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13733 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
13734 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
13735 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
13736 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
13737 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
13738 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13739 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13740 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
13741 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13742 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
13743 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13744 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13745 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
13746 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
13747 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
13748 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
13749 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
13750 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
13751 // CHECK25-NEXT: ret void
13752 //
13753 //
13754 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10
13755 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13756 // CHECK25-NEXT: entry:
13757 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13758 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13759 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
13760 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
13761 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13762 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
13763 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
13764 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13765 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13766 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
13767 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
13768 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13769 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13770 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
13771 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13772 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
13773 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13774 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13775 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
13776 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
13777 // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
13778 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
13779 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13780 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
13781 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13782 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
13783 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
13784 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8
13785 // CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
13786 // CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
13787 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
13788 // CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
13789 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
13790 // CHECK25-NEXT: ret void
13791 //
13792 //
13793 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
13794 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13795 // CHECK25-NEXT: entry:
13796 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13797 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13798 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13799 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
13800 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13801 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13802 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13803 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13804 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13805 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13806 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13807 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13808 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13809 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
13810 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
13811 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
13812 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13813 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
13814 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13815 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
13816 // CHECK25-NEXT: ret void
13817 //
13818 //
13819 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11
13820 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13821 // CHECK25-NEXT: entry:
13822 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13823 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13824 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13825 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13826 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13827 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13828 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13829 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13830 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13831 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13832 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13833 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13834 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13835 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13836 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13837 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
13838 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13839 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
13840 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13841 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13842 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
13843 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
13844 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13845 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
13846 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
13847 // CHECK25-NEXT: ret void
13848 //
13849 //
13850 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
13851 // CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
13852 // CHECK26-NEXT: entry:
13853 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13854 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
13855 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
13856 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13857 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
13858 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13859 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
13860 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
13861 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13862 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
13863 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
13864 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
13865 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
13866 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
13867 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
13868 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13869 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
13870 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13871 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
13872 // CHECK26-NEXT: ret void
13873 //
13874 //
13875 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
13876 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13877 // CHECK26-NEXT: entry:
13878 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13879 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13880 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13881 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13882 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13883 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13884 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13885 // CHECK26-NEXT: ret void
13886 //
13887 //
13888 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
13889 // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
13890 // CHECK26-NEXT: entry:
13891 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13892 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13893 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13894 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13895 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13896 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13897 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
13898 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13899 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13900 // CHECK26-NEXT: ret void
13901 //
13902 //
13903 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
13904 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13905 // CHECK26-NEXT: entry:
13906 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13907 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13908 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13909 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13910 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13911 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13912 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13913 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13914 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
13915 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
13916 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
13917 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
13918 // CHECK26-NEXT: ret void
13919 //
13920 //
13921 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
13922 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13923 // CHECK26-NEXT: entry:
13924 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13925 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13926 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
13927 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
13928 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13929 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13930 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13931 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13932 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13933 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13934 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
13935 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13936 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13937 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13938 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
13939 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13940 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
13941 // CHECK26-NEXT: ret void
13942 //
13943 //
13944 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
13945 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13946 // CHECK26-NEXT: entry:
13947 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13948 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13949 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13950 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13951 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13952 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13953 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13954 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13955 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13956 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13957 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13958 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13959 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
13960 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
13961 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
13962 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13963 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13964 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
13965 // CHECK26-NEXT: ret void
13966 //
13967 //
13968 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
13969 // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
13970 // CHECK26-NEXT: entry:
13971 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13972 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13973 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
13974 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
13975 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13976 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
13977 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
13978 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
13979 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13980 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
13981 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13982 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13983 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13984 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
13985 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13986 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13987 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13988 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
13989 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13990 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13991 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13992 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13993 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13994 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13995 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13996 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13997 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13998 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13999 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
14000 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14001 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
14002 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
14003 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
14004 // CHECK26-NEXT: ret void
14005 //
14006 //
14007 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
14008 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
14009 // CHECK26-NEXT: entry:
14010 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14011 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14012 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
14013 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
14014 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
14015 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
14016 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
14017 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
14018 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
14019 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
14020 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
14021 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14022 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14023 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
14024 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
14025 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14026 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
14027 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
14028 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14029 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
14030 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
14031 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
14032 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14033 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
14034 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14035 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
14036 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
14037 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14038 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
14039 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
14040 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
14041 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
14042 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
14043 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
14044 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
14045 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
14046 // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
14047 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
14048 // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
14049 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4
14050 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
14051 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
14052 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double
14053 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
14054 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
14055 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4
14056 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
14057 // CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
14058 // CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
14059 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
14060 // CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8
14061 // CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
14062 // CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
14063 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
14064 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
14065 // CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
14066 // CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8
14067 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
14068 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8
14069 // CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
14070 // CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8
14071 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
14072 // CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
14073 // CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
14074 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
14075 // CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
14076 // CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8
14077 // CHECK26-NEXT: ret void
14078 //
14079 //
14080 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
14081 // CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
14082 // CHECK26-NEXT: entry:
14083 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
14084 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
14085 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
14086 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
14087 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
14088 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
14089 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
14090 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
14091 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]])
14092 // CHECK26-NEXT: ret void
14093 //
14094 //
14095 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
14096 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
14097 // CHECK26-NEXT: entry:
14098 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14099 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14100 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
14101 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
14102 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14103 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14104 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
14105 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
14106 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
14107 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
14108 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
14109 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
14110 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]])
14111 // CHECK26-NEXT: ret void
14112 //
14113 //
14114 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
14115 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
14116 // CHECK26-NEXT: entry:
14117 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14118 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14119 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
14120 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14121 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14122 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
14123 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
14124 // CHECK26-NEXT: ret void
14125 //
14126 //
14127 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
14128 // CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] {
14129 // CHECK26-NEXT: entry:
14130 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
14131 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
14132 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
14133 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
14134 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
14135 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
14136 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
14137 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
14138 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]])
14139 // CHECK26-NEXT: ret void
14140 //
14141 //
14142 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
14143 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] {
14144 // CHECK26-NEXT: entry:
14145 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14146 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14147 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8
14148 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14149 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14150 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
14151 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
14152 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]])
14153 // CHECK26-NEXT: ret void
14154 //
14155 //
14156 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..7
14157 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
14158 // CHECK26-NEXT: entry:
14159 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14160 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14161 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8
14162 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14163 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14164 // CHECK26-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8
14165 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8
14166 // CHECK26-NEXT: ret void
14167 //
14168 //
14169 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
14170 // CHECK26-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] {
14171 // CHECK26-NEXT: entry:
14172 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
14173 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14174 // CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14175 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]])
14176 // CHECK26-NEXT: ret void
14177 //
14178 //
14179 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..8
14180 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] {
14181 // CHECK26-NEXT: entry:
14182 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14183 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14184 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
14185 // CHECK26-NEXT: [[F:%.*]] = alloca i32*, align 8
14186 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14187 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14188 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14189 // CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14190 // CHECK26-NEXT: ret void
14191 //
14192 //
14193 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
14194 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14195 // CHECK26-NEXT: entry:
14196 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
14197 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
14198 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
14199 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14200 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
14201 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
14202 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
14203 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
14204 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
14205 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
14206 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14207 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14208 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14209 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
14210 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14211 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14212 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14213 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
14214 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
14215 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
14216 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14217 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
14218 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14219 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
14220 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
14221 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
14222 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
14223 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
14224 // CHECK26-NEXT: ret void
14225 //
14226 //
14227 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9
14228 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14229 // CHECK26-NEXT: entry:
14230 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14231 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14232 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
14233 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
14234 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
14235 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14236 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14237 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14238 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
14239 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
14240 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
14241 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14242 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14243 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14244 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
14245 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14246 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14247 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
14248 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
14249 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
14250 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
14251 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
14252 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
14253 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
14254 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
14255 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
14256 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
14257 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
14258 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
14259 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
14260 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14261 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
14262 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
14263 // CHECK26-NEXT: ret void
14264 //
14265 //
14266 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
14267 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
14268 // CHECK26-NEXT: entry:
14269 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14270 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
14271 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
14272 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
14273 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
14274 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
14275 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14276 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
14277 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14278 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14279 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
14280 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14281 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
14282 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14283 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14284 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
14285 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
14286 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
14287 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
14288 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
14289 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
14290 // CHECK26-NEXT: ret void
14291 //
14292 //
14293 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10
14294 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
14295 // CHECK26-NEXT: entry:
14296 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14297 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14298 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14299 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
14300 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
14301 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
14302 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
14303 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14304 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14305 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14306 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
14307 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14308 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14309 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
14310 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14311 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
14312 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14313 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14314 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
14315 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
14316 // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
14317 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
14318 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
14319 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
14320 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
14321 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8
14322 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
14323 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8
14324 // CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
14325 // CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
14326 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
14327 // CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14328 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
14329 // CHECK26-NEXT: ret void
14330 //
14331 //
14332 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
14333 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14334 // CHECK26-NEXT: entry:
14335 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
14336 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
14337 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14338 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
14339 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
14340 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
14341 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
14342 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14343 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14344 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14345 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14346 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14347 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14348 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
14349 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
14350 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
14351 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14352 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
14353 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14354 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
14355 // CHECK26-NEXT: ret void
14356 //
14357 //
14358 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11
14359 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14360 // CHECK26-NEXT: entry:
14361 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14362 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14363 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
14364 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
14365 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14366 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14367 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14368 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
14369 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
14370 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14371 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14372 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14373 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14374 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14375 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
14376 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
14377 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
14378 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
14379 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
14380 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
14381 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
14382 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
14383 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14384 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
14385 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
14386 // CHECK26-NEXT: ret void
14387 //
14388 //
14389 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
14390 // CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
14391 // CHECK27-NEXT: entry:
14392 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14393 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
14394 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
14395 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14396 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
14397 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14398 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
14399 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
14400 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14401 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
14402 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
14403 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
14404 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
14405 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14406 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
14407 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14408 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
14409 // CHECK27-NEXT: ret void
14410 //
14411 //
14412 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
14413 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14414 // CHECK27-NEXT: entry:
14415 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14416 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14417 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14418 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14419 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14420 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14421 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14422 // CHECK27-NEXT: ret void
14423 //
14424 //
14425 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
14426 // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
14427 // CHECK27-NEXT: entry:
14428 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14429 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14430 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14431 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14432 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
14433 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14434 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
14435 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14436 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
14437 // CHECK27-NEXT: ret void
14438 //
14439 //
14440 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
14441 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14442 // CHECK27-NEXT: entry:
14443 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14444 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14445 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14446 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14447 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14448 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14449 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14450 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
14451 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
14452 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
14453 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
14454 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
14455 // CHECK27-NEXT: ret void
14456 //
14457 //
14458 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
14459 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14460 // CHECK27-NEXT: entry:
14461 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14462 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14463 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
14464 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14465 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14466 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14467 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14468 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
14469 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
14470 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
14471 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
14472 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14473 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
14474 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14475 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
14476 // CHECK27-NEXT: ret void
14477 //
14478 //
14479 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
14480 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14481 // CHECK27-NEXT: entry:
14482 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14483 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14484 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14485 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14486 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14487 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14488 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14489 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14490 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14491 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
14492 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14493 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
14494 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
14495 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
14496 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
14497 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14498 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
14499 // CHECK27-NEXT: ret void
14500 //
14501 //
14502 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
14503 // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
14504 // CHECK27-NEXT: entry:
14505 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14506 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
14507 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
14508 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
14509 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
14510 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
14511 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
14512 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
14513 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
14514 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
14515 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14516 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
14517 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14518 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
14519 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
14520 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14521 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
14522 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
14523 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
14524 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
14525 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14526 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
14527 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
14528 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14529 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
14530 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
14531 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
14532 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
14533 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
14534 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
14535 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
14536 // CHECK27-NEXT: ret void
14537 //
14538 //
14539 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
14540 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
14541 // CHECK27-NEXT: entry:
14542 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14543 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14544 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14545 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
14546 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
14547 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
14548 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
14549 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
14550 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
14551 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
14552 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
14553 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14554 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14555 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14556 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
14557 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14558 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
14559 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
14560 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14561 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
14562 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
14563 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
14564 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
14565 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14566 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
14567 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
14568 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14569 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
14570 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
14571 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
14572 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
14573 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
14574 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
14575 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
14576 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
14577 // CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
14578 // CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
14579 // CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
14580 // CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
14581 // CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
14582 // CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
14583 // CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
14584 // CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
14585 // CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
14586 // CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
14587 // CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
14588 // CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
14589 // CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
14590 // CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
14591 // CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
14592 // CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
14593 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
14594 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
14595 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
14596 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
14597 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
14598 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
14599 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
14600 // CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
14601 // CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
14602 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
14603 // CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
14604 // CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
14605 // CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
14606 // CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
14607 // CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
14608 // CHECK27-NEXT: ret void
14609 //
14610 //
14611 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
14612 // CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
14613 // CHECK27-NEXT: entry:
14614 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
14615 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
14616 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
14617 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
14618 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
14619 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
14620 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]])
14621 // CHECK27-NEXT: ret void
14622 //
14623 //
14624 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
14625 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
14626 // CHECK27-NEXT: entry:
14627 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14628 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14629 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
14630 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
14631 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14632 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14633 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
14634 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
14635 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
14636 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
14637 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]])
14638 // CHECK27-NEXT: ret void
14639 //
14640 //
14641 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
14642 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
14643 // CHECK27-NEXT: entry:
14644 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14645 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14646 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
14647 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14648 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14649 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
14650 // CHECK27-NEXT: ret void
14651 //
14652 //
14653 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
14654 // CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
14655 // CHECK27-NEXT: entry:
14656 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
14657 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
14658 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
14659 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
14660 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
14661 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
14662 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]])
14663 // CHECK27-NEXT: ret void
14664 //
14665 //
14666 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
14667 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
14668 // CHECK27-NEXT: entry:
14669 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14670 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14671 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
14672 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14673 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14674 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
14675 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
14676 // CHECK27-NEXT: ret void
14677 //
14678 //
14679 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..7
14680 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
14681 // CHECK27-NEXT: entry:
14682 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14683 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14684 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
14685 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14686 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14687 // CHECK27-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
14688 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
14689 // CHECK27-NEXT: ret void
14690 //
14691 //
14692 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
14693 // CHECK27-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] {
14694 // CHECK27-NEXT: entry:
14695 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
14696 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14697 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14698 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]])
14699 // CHECK27-NEXT: ret void
14700 //
14701 //
14702 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..8
14703 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] {
14704 // CHECK27-NEXT: entry:
14705 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14706 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14707 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
14708 // CHECK27-NEXT: [[F:%.*]] = alloca i32*, align 4
14709 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14710 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14711 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14712 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14713 // CHECK27-NEXT: ret void
14714 //
14715 //
14716 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
14717 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14718 // CHECK27-NEXT: entry:
14719 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14720 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14721 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
14722 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14723 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
14724 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14725 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
14726 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14727 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14728 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
14729 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14730 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14731 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
14732 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14733 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14734 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
14735 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
14736 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
14737 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14738 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
14739 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14740 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
14741 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
14742 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
14743 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
14744 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
14745 // CHECK27-NEXT: ret void
14746 //
14747 //
14748 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9
14749 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14750 // CHECK27-NEXT: entry:
14751 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14752 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14753 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14754 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14755 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
14756 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14757 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14758 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14759 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14760 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14761 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
14762 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14763 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14764 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
14765 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14766 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14767 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
14768 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
14769 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
14770 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
14771 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
14772 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
14773 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
14774 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
14775 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
14776 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
14777 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
14778 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
14779 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
14780 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14781 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
14782 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
14783 // CHECK27-NEXT: ret void
14784 //
14785 //
14786 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
14787 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
14788 // CHECK27-NEXT: entry:
14789 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
14790 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
14791 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
14792 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
14793 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
14794 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
14795 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
14796 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
14797 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14798 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14799 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
14800 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
14801 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14802 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14803 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
14804 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
14805 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
14806 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
14807 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
14808 // CHECK27-NEXT: ret void
14809 //
14810 //
14811 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..10
14812 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
14813 // CHECK27-NEXT: entry:
14814 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14815 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14816 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
14817 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
14818 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
14819 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
14820 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
14821 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14822 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14823 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
14824 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
14825 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14826 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14827 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
14828 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
14829 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14830 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14831 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
14832 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
14833 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
14834 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
14835 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
14836 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4
14837 // CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
14838 // CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
14839 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
14840 // CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4
14841 // CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
14842 // CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
14843 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
14844 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
14845 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
14846 // CHECK27-NEXT: ret void
14847 //
14848 //
14849 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
14850 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14851 // CHECK27-NEXT: entry:
14852 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14853 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14854 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14855 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
14856 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14857 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14858 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14859 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14860 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14861 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14862 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14863 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
14864 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
14865 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
14866 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14867 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
14868 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14869 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
14870 // CHECK27-NEXT: ret void
14871 //
14872 //
14873 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11
14874 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14875 // CHECK27-NEXT: entry:
14876 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14877 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14878 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14879 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14880 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14881 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14882 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14883 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14884 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14885 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14886 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14887 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14888 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14889 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
14890 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
14891 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
14892 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
14893 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
14894 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14895 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
14896 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
14897 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14898 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
14899 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
14900 // CHECK27-NEXT: ret void
14901 //
14902 //
14903 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
14904 // CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
14905 // CHECK28-NEXT: entry:
14906 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14907 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
14908 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
14909 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14910 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
14911 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14912 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
14913 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
14914 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14915 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
14916 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
14917 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
14918 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
14919 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14920 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
14921 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14922 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
14923 // CHECK28-NEXT: ret void
14924 //
14925 //
14926 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
14927 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14928 // CHECK28-NEXT: entry:
14929 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14930 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14931 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14932 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14933 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14934 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14935 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14936 // CHECK28-NEXT: ret void
14937 //
14938 //
14939 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
14940 // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
14941 // CHECK28-NEXT: entry:
14942 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14943 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14944 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14945 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14946 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
14947 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14948 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
14949 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14950 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
14951 // CHECK28-NEXT: ret void
14952 //
14953 //
14954 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
14955 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14956 // CHECK28-NEXT: entry:
14957 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14958 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14959 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14960 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14961 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14962 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14963 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14964 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
14965 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
14966 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
14967 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
14968 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
14969 // CHECK28-NEXT: ret void
14970 //
14971 //
14972 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
14973 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14974 // CHECK28-NEXT: entry:
14975 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14976 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14977 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
14978 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
14979 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14980 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14981 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14982 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
14983 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
14984 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
14985 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
14986 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14987 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
14988 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14989 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
14990 // CHECK28-NEXT: ret void
14991 //
14992 //
14993 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
14994 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14995 // CHECK28-NEXT: entry:
14996 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14997 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14998 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14999 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
15000 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15001 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15002 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15003 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
15004 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
15005 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
15006 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15007 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
15008 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
15009 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
15010 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
15011 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15012 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
15013 // CHECK28-NEXT: ret void
15014 //
15015 //
15016 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
15017 // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
15018 // CHECK28-NEXT: entry:
15019 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
15020 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
15021 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
15022 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
15023 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
15024 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
15025 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
15026 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
15027 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
15028 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
15029 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15030 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
15031 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
15032 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
15033 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
15034 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
15035 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
15036 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
15037 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
15038 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
15039 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
15040 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
15041 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
15042 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
15043 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
15044 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
15045 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
15046 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
15047 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
15048 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
15049 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
15050 // CHECK28-NEXT: ret void
15051 //
15052 //
15053 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
15054 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
15055 // CHECK28-NEXT: entry:
15056 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15057 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15058 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
15059 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
15060 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
15061 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
15062 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
15063 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
15064 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
15065 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
15066 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
15067 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15068 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15069 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15070 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
15071 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
15072 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
15073 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
15074 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
15075 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
15076 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
15077 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
15078 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
15079 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
15080 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
15081 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
15082 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
15083 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
15084 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
15085 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
15086 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
15087 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
15088 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
15089 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
15090 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
15091 // CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double
15092 // CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
15093 // CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
15094 // CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4
15095 // CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
15096 // CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
15097 // CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double
15098 // CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
15099 // CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
15100 // CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4
15101 // CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
15102 // CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
15103 // CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
15104 // CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
15105 // CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8
15106 // CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
15107 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
15108 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
15109 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
15110 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
15111 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
15112 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
15113 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4
15114 // CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
15115 // CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4
15116 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
15117 // CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
15118 // CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
15119 // CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
15120 // CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
15121 // CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4
15122 // CHECK28-NEXT: ret void
15123 //
15124 //
15125 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154
15126 // CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
15127 // CHECK28-NEXT: entry:
15128 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
15129 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
15130 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
15131 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
15132 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
15133 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
15134 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]])
15135 // CHECK28-NEXT: ret void
15136 //
15137 //
15138 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
15139 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
15140 // CHECK28-NEXT: entry:
15141 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15142 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15143 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
15144 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
15145 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15146 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15147 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
15148 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
15149 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
15150 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
15151 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]])
15152 // CHECK28-NEXT: ret void
15153 //
15154 //
15155 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
15156 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
15157 // CHECK28-NEXT: entry:
15158 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15159 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15160 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
15161 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15162 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15163 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
15164 // CHECK28-NEXT: ret void
15165 //
15166 //
15167 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157
15168 // CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] {
15169 // CHECK28-NEXT: entry:
15170 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
15171 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
15172 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
15173 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4
15174 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4
15175 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4
15176 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]])
15177 // CHECK28-NEXT: ret void
15178 //
15179 //
15180 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
15181 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] {
15182 // CHECK28-NEXT: entry:
15183 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15184 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15185 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4
15186 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15187 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15188 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4
15189 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]])
15190 // CHECK28-NEXT: ret void
15191 //
15192 //
15193 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..7
15194 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
15195 // CHECK28-NEXT: entry:
15196 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15197 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15198 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4
15199 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15200 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15201 // CHECK28-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4
15202 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4
15203 // CHECK28-NEXT: ret void
15204 //
15205 //
15206 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182
15207 // CHECK28-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] {
15208 // CHECK28-NEXT: entry:
15209 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
15210 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
15211 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
15212 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]])
15213 // CHECK28-NEXT: ret void
15214 //
15215 //
15216 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..8
15217 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] {
15218 // CHECK28-NEXT: entry:
15219 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15220 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15221 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
15222 // CHECK28-NEXT: [[F:%.*]] = alloca i32*, align 4
15223 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15224 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15225 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
15226 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
15227 // CHECK28-NEXT: ret void
15228 //
15229 //
15230 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209
15231 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
15232 // CHECK28-NEXT: entry:
15233 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
15234 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
15235 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
15236 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
15237 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
15238 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
15239 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
15240 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15241 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
15242 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
15243 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
15244 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
15245 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
15246 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
15247 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
15248 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
15249 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
15250 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
15251 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
15252 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
15253 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
15254 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
15255 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
15256 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
15257 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
15258 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
15259 // CHECK28-NEXT: ret void
15260 //
15261 //
15262 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9
15263 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
15264 // CHECK28-NEXT: entry:
15265 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15266 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15267 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
15268 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
15269 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
15270 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
15271 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15272 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15273 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15274 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
15275 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
15276 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
15277 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
15278 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
15279 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
15280 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
15281 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
15282 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
15283 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
15284 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
15285 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
15286 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
15287 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
15288 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
15289 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
15290 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
15291 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
15292 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
15293 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
15294 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
15295 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
15296 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
15297 // CHECK28-NEXT: ret void
15298 //
15299 //
15300 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227
15301 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
15302 // CHECK28-NEXT: entry:
15303 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
15304 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
15305 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
15306 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
15307 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
15308 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
15309 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
15310 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
15311 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
15312 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
15313 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
15314 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
15315 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
15316 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
15317 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
15318 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
15319 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
15320 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
15321 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
15322 // CHECK28-NEXT: ret void
15323 //
15324 //
15325 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..10
15326 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
15327 // CHECK28-NEXT: entry:
15328 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15329 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15330 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
15331 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
15332 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
15333 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
15334 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
15335 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15336 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15337 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
15338 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
15339 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
15340 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
15341 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
15342 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
15343 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
15344 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
15345 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
15346 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
15347 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
15348 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
15349 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
15350 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4
15351 // CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
15352 // CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
15353 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
15354 // CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4
15355 // CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
15356 // CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
15357 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
15358 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
15359 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
15360 // CHECK28-NEXT: ret void
15361 //
15362 //
15363 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192
15364 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
15365 // CHECK28-NEXT: entry:
15366 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
15367 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
15368 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
15369 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
15370 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
15371 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15372 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
15373 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
15374 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
15375 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
15376 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
15377 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
15378 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
15379 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
15380 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
15381 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
15382 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
15383 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
15384 // CHECK28-NEXT: ret void
15385 //
15386 //
15387 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11
15388 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
15389 // CHECK28-NEXT: entry:
15390 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
15391 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
15392 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
15393 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
15394 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
15395 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
15396 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
15397 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
15398 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
15399 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
15400 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
15401 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
15402 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
15403 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
15404 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
15405 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
15406 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
15407 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
15408 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15409 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
15410 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
15411 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
15412 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
15413 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
15414 // CHECK28-NEXT: ret void
15415 //
15416