1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target 33 #pragma omp teams distribute simd reduction(+: t_var) 34 for (int i = 0; i < 2; ++i) { 35 t_var += (T) i; 36 } 37 return T(); 38 } 39 40 int main() { 41 static int sivar; 42 #ifdef LAMBDA 43 44 [&]() { 45 #pragma omp target 46 #pragma omp teams distribute simd reduction(+: sivar) 47 for (int i = 0; i < 2; ++i) { 48 49 // Skip global and bound tid vars 50 51 52 sivar += i; 53 54 [&]() { 55 56 sivar += 4; 57 58 }(); 59 } 60 }(); 61 return 0; 62 #else 63 #pragma omp target 64 #pragma omp teams distribute simd reduction(+: sivar) 65 for (int i = 0; i < 2; ++i) { 66 sivar += i; 67 } 68 return tmain<int>(); 69 #endif 70 } 71 72 73 74 75 // Skip global and bound tid vars 76 77 78 79 80 81 // Skip global and bound tid vars 82 83 84 #endif 85 // CHECK1-LABEL: define {{[^@]+}}@main 86 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 87 // CHECK1-NEXT: entry: 88 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 89 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 90 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 91 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 92 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 93 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 94 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 95 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 96 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 97 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 98 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 99 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 100 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 101 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 102 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 103 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 104 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 105 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 106 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 107 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 108 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 109 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 110 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 111 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 112 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 113 // CHECK1: omp_offload.failed: 114 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 115 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 116 // CHECK1: omp_offload.cont: 117 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 118 // CHECK1-NEXT: ret i32 [[CALL]] 119 // 120 // 121 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 122 // CHECK1-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 123 // CHECK1-NEXT: entry: 124 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 125 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 126 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 127 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 128 // CHECK1-NEXT: ret void 129 // 130 // 131 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 132 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 133 // CHECK1-NEXT: entry: 134 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 135 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 136 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 137 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 138 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 139 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 140 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 141 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 142 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 143 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 144 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 145 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 146 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 147 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 148 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 149 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 150 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4 151 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 152 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 153 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 154 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 155 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 156 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 157 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 158 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 159 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 160 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 161 // CHECK1: cond.true: 162 // CHECK1-NEXT: br label [[COND_END:%.*]] 163 // CHECK1: cond.false: 164 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 165 // CHECK1-NEXT: br label [[COND_END]] 166 // CHECK1: cond.end: 167 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 168 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 169 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 170 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 171 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 172 // CHECK1: omp.inner.for.cond: 173 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 174 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 175 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 176 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 177 // CHECK1: omp.inner.for.body: 178 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 179 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 180 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 181 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 182 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 183 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 184 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 185 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 186 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 187 // CHECK1: omp.body.continue: 188 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 189 // CHECK1: omp.inner.for.inc: 190 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 191 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 192 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 193 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 194 // CHECK1: omp.inner.for.end: 195 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 196 // CHECK1: omp.loop.exit: 197 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 198 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 199 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 200 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 201 // CHECK1: .omp.final.then: 202 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 203 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 204 // CHECK1: .omp.final.done: 205 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 206 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 207 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 208 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 209 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 210 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 211 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 212 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 213 // CHECK1-NEXT: ] 214 // CHECK1: .omp.reduction.case1: 215 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 216 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 217 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 218 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 219 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 220 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 221 // CHECK1: .omp.reduction.case2: 222 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 223 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 224 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 225 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 226 // CHECK1: .omp.reduction.default: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 231 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 234 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 235 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 236 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 237 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 238 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 239 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 240 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 241 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 242 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 243 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 244 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 245 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 246 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 247 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 248 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 249 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 250 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 251 // CHECK1-NEXT: ret void 252 // 253 // 254 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 255 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat { 256 // CHECK1-NEXT: entry: 257 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 258 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 263 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 264 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 265 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 266 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 267 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 268 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 269 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 271 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 272 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 273 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 274 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 276 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 277 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 278 // CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8 279 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 280 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 281 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 282 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 283 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 284 // CHECK1-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 285 // CHECK1: omp_offload.failed: 286 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP2]]) #[[ATTR2]] 287 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 288 // CHECK1: omp_offload.cont: 289 // CHECK1-NEXT: ret i32 0 290 // 291 // 292 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 293 // CHECK1-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { 294 // CHECK1-NEXT: entry: 295 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 296 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 297 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 298 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 299 // CHECK1-NEXT: ret void 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 303 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 306 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 307 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 308 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 311 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 312 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 313 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 315 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 316 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 317 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 318 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 319 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 320 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 321 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4 322 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 323 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 324 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 325 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 327 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 328 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 329 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 330 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 331 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 332 // CHECK1: cond.true: 333 // CHECK1-NEXT: br label [[COND_END:%.*]] 334 // CHECK1: cond.false: 335 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 336 // CHECK1-NEXT: br label [[COND_END]] 337 // CHECK1: cond.end: 338 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 339 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 340 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 341 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 342 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 343 // CHECK1: omp.inner.for.cond: 344 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 345 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 346 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 347 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 348 // CHECK1: omp.inner.for.body: 349 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 350 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 352 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 353 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 354 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 355 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 356 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 357 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 358 // CHECK1: omp.body.continue: 359 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 360 // CHECK1: omp.inner.for.inc: 361 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 362 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 363 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 364 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 365 // CHECK1: omp.inner.for.end: 366 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 367 // CHECK1: omp.loop.exit: 368 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 369 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 370 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 371 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 372 // CHECK1: .omp.final.then: 373 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 374 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 375 // CHECK1: .omp.final.done: 376 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 377 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 378 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 379 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 380 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 381 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 382 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 383 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 384 // CHECK1-NEXT: ] 385 // CHECK1: .omp.reduction.case1: 386 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 387 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 388 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 389 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 390 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 391 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 392 // CHECK1: .omp.reduction.case2: 393 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 394 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 395 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 396 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 397 // CHECK1: .omp.reduction.default: 398 // CHECK1-NEXT: ret void 399 // 400 // 401 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 402 // CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 403 // CHECK1-NEXT: entry: 404 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 405 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 406 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 407 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 408 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 409 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 410 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 411 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 412 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 413 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 414 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 415 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 416 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 417 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 418 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 419 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 420 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 421 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 422 // CHECK1-NEXT: ret void 423 // 424 // 425 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 426 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] { 427 // CHECK1-NEXT: entry: 428 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 429 // CHECK1-NEXT: ret void 430 // 431 // 432 // CHECK2-LABEL: define {{[^@]+}}@main 433 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 434 // CHECK2-NEXT: entry: 435 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 436 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 437 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 438 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 439 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 440 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 441 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 442 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 443 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 444 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 445 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 446 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 447 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 448 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 449 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 450 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 451 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 452 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 453 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 454 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 455 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 456 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 457 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 458 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 459 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 460 // CHECK2: omp_offload.failed: 461 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 462 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 463 // CHECK2: omp_offload.cont: 464 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 465 // CHECK2-NEXT: ret i32 [[CALL]] 466 // 467 // 468 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 469 // CHECK2-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 470 // CHECK2-NEXT: entry: 471 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 472 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 473 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 474 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 475 // CHECK2-NEXT: ret void 476 // 477 // 478 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 479 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 480 // CHECK2-NEXT: entry: 481 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 482 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 483 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 484 // CHECK2-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 485 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 486 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 487 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 488 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 489 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 490 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 491 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 492 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 493 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 494 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 495 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 496 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 497 // CHECK2-NEXT: store i32 0, i32* [[SIVAR1]], align 4 498 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 499 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 500 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 501 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 502 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 503 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 504 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 505 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 506 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 507 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 508 // CHECK2: cond.true: 509 // CHECK2-NEXT: br label [[COND_END:%.*]] 510 // CHECK2: cond.false: 511 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 512 // CHECK2-NEXT: br label [[COND_END]] 513 // CHECK2: cond.end: 514 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 515 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 516 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 517 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 518 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 519 // CHECK2: omp.inner.for.cond: 520 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 521 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 522 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 523 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 524 // CHECK2: omp.inner.for.body: 525 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 526 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 527 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 528 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 529 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 530 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 531 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 532 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 533 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 534 // CHECK2: omp.body.continue: 535 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 536 // CHECK2: omp.inner.for.inc: 537 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 538 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 539 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 540 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 541 // CHECK2: omp.inner.for.end: 542 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 543 // CHECK2: omp.loop.exit: 544 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 545 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 546 // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 547 // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 548 // CHECK2: .omp.final.then: 549 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 550 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 551 // CHECK2: .omp.final.done: 552 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 553 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 554 // CHECK2-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 555 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 556 // CHECK2-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 557 // CHECK2-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 558 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 559 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 560 // CHECK2-NEXT: ] 561 // CHECK2: .omp.reduction.case1: 562 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 563 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 564 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 565 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 566 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 567 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 568 // CHECK2: .omp.reduction.case2: 569 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 570 // CHECK2-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 571 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 572 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 573 // CHECK2: .omp.reduction.default: 574 // CHECK2-NEXT: ret void 575 // 576 // 577 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 578 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 579 // CHECK2-NEXT: entry: 580 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 581 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 582 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 583 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 584 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 585 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 586 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 587 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 588 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 589 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 590 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 591 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 592 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 593 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 594 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 595 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 596 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 597 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 598 // CHECK2-NEXT: ret void 599 // 600 // 601 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 602 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] comdat { 603 // CHECK2-NEXT: entry: 604 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 605 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 606 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 607 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 608 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 609 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 610 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 611 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 612 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 613 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 614 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 615 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 616 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 617 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 618 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 619 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 620 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 621 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 622 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 623 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 624 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 625 // CHECK2-NEXT: store i8* null, i8** [[TMP7]], align 8 626 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 627 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 628 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 629 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 630 // CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 631 // CHECK2-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 632 // CHECK2: omp_offload.failed: 633 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP2]]) #[[ATTR2]] 634 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 635 // CHECK2: omp_offload.cont: 636 // CHECK2-NEXT: ret i32 0 637 // 638 // 639 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 640 // CHECK2-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { 641 // CHECK2-NEXT: entry: 642 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 643 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 644 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 645 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 646 // CHECK2-NEXT: ret void 647 // 648 // 649 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 650 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 651 // CHECK2-NEXT: entry: 652 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 653 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 654 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 655 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 656 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 657 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 658 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 659 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 660 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 661 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 662 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 663 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 664 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 665 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 666 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 667 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 668 // CHECK2-NEXT: store i32 0, i32* [[T_VAR1]], align 4 669 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 670 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 671 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 672 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 673 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 674 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 675 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 676 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 677 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 678 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 679 // CHECK2: cond.true: 680 // CHECK2-NEXT: br label [[COND_END:%.*]] 681 // CHECK2: cond.false: 682 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 683 // CHECK2-NEXT: br label [[COND_END]] 684 // CHECK2: cond.end: 685 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 686 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 687 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 688 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 689 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 690 // CHECK2: omp.inner.for.cond: 691 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 692 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 693 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 694 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 695 // CHECK2: omp.inner.for.body: 696 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 697 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 698 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 699 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 700 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 701 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 702 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 703 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 704 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 705 // CHECK2: omp.body.continue: 706 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 707 // CHECK2: omp.inner.for.inc: 708 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 709 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 710 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 711 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 712 // CHECK2: omp.inner.for.end: 713 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 714 // CHECK2: omp.loop.exit: 715 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 716 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 717 // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 718 // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 719 // CHECK2: .omp.final.then: 720 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 721 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 722 // CHECK2: .omp.final.done: 723 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 724 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 725 // CHECK2-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 726 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 727 // CHECK2-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 728 // CHECK2-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 729 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 730 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 731 // CHECK2-NEXT: ] 732 // CHECK2: .omp.reduction.case1: 733 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 734 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 735 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 736 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 737 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 738 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 739 // CHECK2: .omp.reduction.case2: 740 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 741 // CHECK2-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 742 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 743 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 744 // CHECK2: .omp.reduction.default: 745 // CHECK2-NEXT: ret void 746 // 747 // 748 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 749 // CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 750 // CHECK2-NEXT: entry: 751 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 752 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 753 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 754 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 755 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 756 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 757 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 758 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 759 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 760 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 761 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 762 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 763 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 764 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 765 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 766 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 767 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 768 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 769 // CHECK2-NEXT: ret void 770 // 771 // 772 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 773 // CHECK2-SAME: () #[[ATTR7:[0-9]+]] { 774 // CHECK2-NEXT: entry: 775 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 776 // CHECK2-NEXT: ret void 777 // 778 // 779 // CHECK3-LABEL: define {{[^@]+}}@main 780 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 781 // CHECK3-NEXT: entry: 782 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 783 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 784 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 785 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 786 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 787 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 788 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 789 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 790 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4 791 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 792 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 793 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 794 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 795 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 796 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 797 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 798 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 799 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 800 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 801 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 802 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 803 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 804 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 805 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 806 // CHECK3: omp_offload.failed: 807 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 808 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 809 // CHECK3: omp_offload.cont: 810 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 811 // CHECK3-NEXT: ret i32 [[CALL]] 812 // 813 // 814 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 815 // CHECK3-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 816 // CHECK3-NEXT: entry: 817 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 818 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 819 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[SIVAR_ADDR]]) 820 // CHECK3-NEXT: ret void 821 // 822 // 823 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 824 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 825 // CHECK3-NEXT: entry: 826 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 827 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 828 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 829 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 830 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 831 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 832 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 833 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 834 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 835 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 836 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 837 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 838 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 839 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 840 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 841 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 842 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4 843 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 844 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 845 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 846 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 847 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 848 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 849 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 850 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 851 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 852 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 853 // CHECK3: cond.true: 854 // CHECK3-NEXT: br label [[COND_END:%.*]] 855 // CHECK3: cond.false: 856 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 857 // CHECK3-NEXT: br label [[COND_END]] 858 // CHECK3: cond.end: 859 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 860 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 861 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 862 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 863 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 864 // CHECK3: omp.inner.for.cond: 865 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 866 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 867 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 868 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 869 // CHECK3: omp.inner.for.body: 870 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 871 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 872 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 873 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 874 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 875 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 876 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 877 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 878 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 879 // CHECK3: omp.body.continue: 880 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 881 // CHECK3: omp.inner.for.inc: 882 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 883 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 884 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 885 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 886 // CHECK3: omp.inner.for.end: 887 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 888 // CHECK3: omp.loop.exit: 889 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 890 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 891 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 892 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 893 // CHECK3: .omp.final.then: 894 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 895 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 896 // CHECK3: .omp.final.done: 897 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 898 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 899 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 900 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 901 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 902 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 903 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 904 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 905 // CHECK3-NEXT: ] 906 // CHECK3: .omp.reduction.case1: 907 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 908 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 909 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 910 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 911 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 912 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 913 // CHECK3: .omp.reduction.case2: 914 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 915 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 916 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 917 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 918 // CHECK3: .omp.reduction.default: 919 // CHECK3-NEXT: ret void 920 // 921 // 922 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 923 // CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 924 // CHECK3-NEXT: entry: 925 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 926 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 927 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 928 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 929 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 930 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 931 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 932 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 933 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 934 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 935 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 936 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 937 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 938 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 939 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 940 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 941 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 942 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 943 // CHECK3-NEXT: ret void 944 // 945 // 946 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 947 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] comdat { 948 // CHECK3-NEXT: entry: 949 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 950 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 951 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 952 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 953 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 954 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 955 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 956 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 957 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 958 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 959 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 960 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 961 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 962 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 963 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 964 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 965 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 966 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 967 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 968 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 969 // CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4 970 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 971 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 972 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 973 // CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 974 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 975 // CHECK3-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 976 // CHECK3: omp_offload.failed: 977 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP2]]) #[[ATTR2]] 978 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 979 // CHECK3: omp_offload.cont: 980 // CHECK3-NEXT: ret i32 0 981 // 982 // 983 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 984 // CHECK3-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { 985 // CHECK3-NEXT: entry: 986 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 987 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 988 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]]) 989 // CHECK3-NEXT: ret void 990 // 991 // 992 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 993 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 994 // CHECK3-NEXT: entry: 995 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 996 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 997 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 998 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 999 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1000 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1001 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1002 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1003 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1004 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1005 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1006 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 1007 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1008 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1009 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1010 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1011 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1012 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1013 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1014 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1015 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1016 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1017 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1018 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1019 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1020 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1021 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1022 // CHECK3: cond.true: 1023 // CHECK3-NEXT: br label [[COND_END:%.*]] 1024 // CHECK3: cond.false: 1025 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1026 // CHECK3-NEXT: br label [[COND_END]] 1027 // CHECK3: cond.end: 1028 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1029 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1030 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1031 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1032 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1033 // CHECK3: omp.inner.for.cond: 1034 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1035 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1036 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1037 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1038 // CHECK3: omp.inner.for.body: 1039 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1040 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1041 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1042 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1043 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1044 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 1045 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1046 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 1047 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1048 // CHECK3: omp.body.continue: 1049 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1050 // CHECK3: omp.inner.for.inc: 1051 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1052 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1053 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1054 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 1055 // CHECK3: omp.inner.for.end: 1056 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1057 // CHECK3: omp.loop.exit: 1058 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1059 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1060 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1061 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1062 // CHECK3: .omp.final.then: 1063 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1064 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1065 // CHECK3: .omp.final.done: 1066 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1067 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 1068 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 1069 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1070 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 1071 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1072 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1073 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1074 // CHECK3-NEXT: ] 1075 // CHECK3: .omp.reduction.case1: 1076 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 1077 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 1078 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1079 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1080 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1081 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1082 // CHECK3: .omp.reduction.case2: 1083 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 1084 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 1085 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1086 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1087 // CHECK3: .omp.reduction.default: 1088 // CHECK3-NEXT: ret void 1089 // 1090 // 1091 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 1092 // CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 1093 // CHECK3-NEXT: entry: 1094 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1095 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 1096 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1097 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 1098 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 1099 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1100 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 1101 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1102 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 1103 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1104 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1105 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 1106 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 1107 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1108 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1109 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1110 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1111 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1112 // CHECK3-NEXT: ret void 1113 // 1114 // 1115 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1116 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] { 1117 // CHECK3-NEXT: entry: 1118 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1119 // CHECK3-NEXT: ret void 1120 // 1121 // 1122 // CHECK4-LABEL: define {{[^@]+}}@main 1123 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 1124 // CHECK4-NEXT: entry: 1125 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1126 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1127 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1128 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1129 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1130 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1131 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1132 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1133 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4 1134 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1135 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1136 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1137 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1138 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1139 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1140 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1141 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1142 // CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4 1143 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1144 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1145 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 1146 // CHECK4-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1147 // CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1148 // CHECK4-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1149 // CHECK4: omp_offload.failed: 1150 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 1151 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1152 // CHECK4: omp_offload.cont: 1153 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1154 // CHECK4-NEXT: ret i32 [[CALL]] 1155 // 1156 // 1157 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 1158 // CHECK4-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 1159 // CHECK4-NEXT: entry: 1160 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1161 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1162 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[SIVAR_ADDR]]) 1163 // CHECK4-NEXT: ret void 1164 // 1165 // 1166 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1167 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { 1168 // CHECK4-NEXT: entry: 1169 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1170 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1171 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 1172 // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1173 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1174 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1175 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1176 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1177 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1178 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1179 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1180 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 1181 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1182 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1183 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 1184 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 1185 // CHECK4-NEXT: store i32 0, i32* [[SIVAR1]], align 4 1186 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1187 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1188 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1189 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1190 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1191 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1192 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1193 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1194 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1195 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1196 // CHECK4: cond.true: 1197 // CHECK4-NEXT: br label [[COND_END:%.*]] 1198 // CHECK4: cond.false: 1199 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1200 // CHECK4-NEXT: br label [[COND_END]] 1201 // CHECK4: cond.end: 1202 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1203 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1204 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1205 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1206 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1207 // CHECK4: omp.inner.for.cond: 1208 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1209 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1210 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1211 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1212 // CHECK4: omp.inner.for.body: 1213 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1214 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1215 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1216 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1217 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1218 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 1219 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1220 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 1221 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1222 // CHECK4: omp.body.continue: 1223 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1224 // CHECK4: omp.inner.for.inc: 1225 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1226 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1227 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1228 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1229 // CHECK4: omp.inner.for.end: 1230 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1231 // CHECK4: omp.loop.exit: 1232 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1233 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1234 // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1235 // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1236 // CHECK4: .omp.final.then: 1237 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 1238 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 1239 // CHECK4: .omp.final.done: 1240 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1241 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 1242 // CHECK4-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 1243 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1244 // CHECK4-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1245 // CHECK4-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1246 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1247 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1248 // CHECK4-NEXT: ] 1249 // CHECK4: .omp.reduction.case1: 1250 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 1251 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 1252 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1253 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1254 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1255 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1256 // CHECK4: .omp.reduction.case2: 1257 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 1258 // CHECK4-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 1259 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1260 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1261 // CHECK4: .omp.reduction.default: 1262 // CHECK4-NEXT: ret void 1263 // 1264 // 1265 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1266 // CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { 1267 // CHECK4-NEXT: entry: 1268 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1269 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 1270 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1271 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 1272 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 1273 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1274 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 1275 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1276 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 1277 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1278 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1279 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 1280 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 1281 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1282 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1283 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1284 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1285 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1286 // CHECK4-NEXT: ret void 1287 // 1288 // 1289 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1290 // CHECK4-SAME: () #[[ATTR5:[0-9]+]] comdat { 1291 // CHECK4-NEXT: entry: 1292 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1293 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1294 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1295 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1296 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1297 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1298 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1299 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 1300 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1301 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1302 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1303 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 1304 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1305 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1306 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 1307 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 1308 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1309 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1310 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1311 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1312 // CHECK4-NEXT: store i8* null, i8** [[TMP7]], align 4 1313 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1314 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1315 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 1316 // CHECK4-NEXT: [[TMP10:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1317 // CHECK4-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 1318 // CHECK4-NEXT: br i1 [[TMP11]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1319 // CHECK4: omp_offload.failed: 1320 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP2]]) #[[ATTR2]] 1321 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1322 // CHECK4: omp_offload.cont: 1323 // CHECK4-NEXT: ret i32 0 1324 // 1325 // 1326 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 1327 // CHECK4-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { 1328 // CHECK4-NEXT: entry: 1329 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1330 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1331 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]]) 1332 // CHECK4-NEXT: ret void 1333 // 1334 // 1335 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 1336 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1337 // CHECK4-NEXT: entry: 1338 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1339 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1340 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1341 // CHECK4-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1342 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1343 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1344 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1345 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1346 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1347 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1348 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1349 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 1350 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1351 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1352 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1353 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1354 // CHECK4-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1355 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1356 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1357 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1358 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1359 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1360 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1361 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1362 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1363 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1364 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1365 // CHECK4: cond.true: 1366 // CHECK4-NEXT: br label [[COND_END:%.*]] 1367 // CHECK4: cond.false: 1368 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1369 // CHECK4-NEXT: br label [[COND_END]] 1370 // CHECK4: cond.end: 1371 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1372 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1373 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1374 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1375 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1376 // CHECK4: omp.inner.for.cond: 1377 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1378 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1379 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1380 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1381 // CHECK4: omp.inner.for.body: 1382 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1383 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1384 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1385 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1386 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1387 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 1388 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1389 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 1390 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1391 // CHECK4: omp.body.continue: 1392 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1393 // CHECK4: omp.inner.for.inc: 1394 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1395 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1396 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1397 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 1398 // CHECK4: omp.inner.for.end: 1399 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1400 // CHECK4: omp.loop.exit: 1401 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1402 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1403 // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1404 // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1405 // CHECK4: .omp.final.then: 1406 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 1407 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 1408 // CHECK4: .omp.final.done: 1409 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1410 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 1411 // CHECK4-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 1412 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1413 // CHECK4-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 1414 // CHECK4-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1415 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1416 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1417 // CHECK4-NEXT: ] 1418 // CHECK4: .omp.reduction.case1: 1419 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 1420 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 1421 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1422 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1423 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1424 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1425 // CHECK4: .omp.reduction.case2: 1426 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 1427 // CHECK4-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 1428 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1429 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1430 // CHECK4: .omp.reduction.default: 1431 // CHECK4-NEXT: ret void 1432 // 1433 // 1434 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 1435 // CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { 1436 // CHECK4-NEXT: entry: 1437 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1438 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 1439 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1440 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 1441 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 1442 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1443 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 1444 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1445 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 1446 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1447 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1448 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 1449 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 1450 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1451 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1452 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1453 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1454 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1455 // CHECK4-NEXT: ret void 1456 // 1457 // 1458 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1459 // CHECK4-SAME: () #[[ATTR7:[0-9]+]] { 1460 // CHECK4-NEXT: entry: 1461 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 1462 // CHECK4-NEXT: ret void 1463 // 1464 // 1465 // CHECK5-LABEL: define {{[^@]+}}@main 1466 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1467 // CHECK5-NEXT: entry: 1468 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1469 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1470 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1471 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1472 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1473 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1474 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1475 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1476 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1477 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1478 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1479 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1480 // CHECK5-NEXT: store i32 0, i32* [[SIVAR]], align 4 1481 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1482 // CHECK5: omp.inner.for.cond: 1483 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1484 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1485 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1486 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1487 // CHECK5: omp.inner.for.body: 1488 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1489 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1490 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1491 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1492 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1493 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 1494 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1495 // CHECK5-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 1496 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1497 // CHECK5: omp.body.continue: 1498 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1499 // CHECK5: omp.inner.for.inc: 1500 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1501 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1502 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1503 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1504 // CHECK5: omp.inner.for.end: 1505 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1506 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1507 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1508 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1509 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1510 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1511 // CHECK5-NEXT: ret i32 [[CALL]] 1512 // 1513 // 1514 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1515 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 1516 // CHECK5-NEXT: entry: 1517 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1518 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1519 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1520 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1521 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1522 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1523 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1524 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1525 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1526 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1527 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1528 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1529 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1530 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1531 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1532 // CHECK5-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1533 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1534 // CHECK5: omp.inner.for.cond: 1535 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1536 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1537 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1538 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1539 // CHECK5: omp.inner.for.body: 1540 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1541 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1542 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1543 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1544 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1545 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 1546 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1547 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 1548 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1549 // CHECK5: omp.body.continue: 1550 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1551 // CHECK5: omp.inner.for.inc: 1552 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1553 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1554 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1555 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1556 // CHECK5: omp.inner.for.end: 1557 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1558 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1559 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1560 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1561 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1562 // CHECK5-NEXT: ret i32 0 1563 // 1564 // 1565 // CHECK6-LABEL: define {{[^@]+}}@main 1566 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 1567 // CHECK6-NEXT: entry: 1568 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1569 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 1570 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1571 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1572 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1573 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 1574 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1575 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 1576 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1577 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1578 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1579 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1580 // CHECK6-NEXT: store i32 0, i32* [[SIVAR]], align 4 1581 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1582 // CHECK6: omp.inner.for.cond: 1583 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1584 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1585 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1586 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1587 // CHECK6: omp.inner.for.body: 1588 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1589 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1590 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1591 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1592 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1593 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 1594 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1595 // CHECK6-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 1596 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1597 // CHECK6: omp.body.continue: 1598 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1599 // CHECK6: omp.inner.for.inc: 1600 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1601 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1602 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1603 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1604 // CHECK6: omp.inner.for.end: 1605 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 1606 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1607 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1608 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1609 // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1610 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1611 // CHECK6-NEXT: ret i32 [[CALL]] 1612 // 1613 // 1614 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1615 // CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { 1616 // CHECK6-NEXT: entry: 1617 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1618 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1619 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 1620 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1621 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1622 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1623 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 1624 // CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1625 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 1626 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1627 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1628 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1629 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1630 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1631 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1632 // CHECK6-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1633 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1634 // CHECK6: omp.inner.for.cond: 1635 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1636 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1637 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1638 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1639 // CHECK6: omp.inner.for.body: 1640 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1641 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1642 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1643 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1644 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1645 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 1646 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1647 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 1648 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1649 // CHECK6: omp.body.continue: 1650 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1651 // CHECK6: omp.inner.for.inc: 1652 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1653 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1654 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1655 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1656 // CHECK6: omp.inner.for.end: 1657 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 1658 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1659 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1660 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1661 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1662 // CHECK6-NEXT: ret i32 0 1663 // 1664 // 1665 // CHECK7-LABEL: define {{[^@]+}}@main 1666 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1667 // CHECK7-NEXT: entry: 1668 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1669 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1670 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1671 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1672 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1673 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1674 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1675 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 1676 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1677 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1678 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1679 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1680 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4 1681 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1682 // CHECK7: omp.inner.for.cond: 1683 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1684 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 1685 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1686 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1687 // CHECK7: omp.inner.for.body: 1688 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1689 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1690 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1691 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 1692 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1693 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 1694 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1695 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 1696 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1697 // CHECK7: omp.body.continue: 1698 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1699 // CHECK7: omp.inner.for.inc: 1700 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1701 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1702 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1703 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1704 // CHECK7: omp.inner.for.end: 1705 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1706 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1707 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1708 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1709 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1710 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1711 // CHECK7-NEXT: ret i32 [[CALL]] 1712 // 1713 // 1714 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1715 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 1716 // CHECK7-NEXT: entry: 1717 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1718 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1719 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1720 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1721 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1722 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1723 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1724 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1725 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 1726 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1727 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1728 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1729 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1730 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1731 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1732 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1733 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1734 // CHECK7: omp.inner.for.cond: 1735 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1736 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1737 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1738 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1739 // CHECK7: omp.inner.for.body: 1740 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1741 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1742 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1743 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1744 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1745 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 1746 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1747 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 1748 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1749 // CHECK7: omp.body.continue: 1750 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1751 // CHECK7: omp.inner.for.inc: 1752 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1753 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1754 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1755 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1756 // CHECK7: omp.inner.for.end: 1757 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1758 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1759 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1760 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1761 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1762 // CHECK7-NEXT: ret i32 0 1763 // 1764 // 1765 // CHECK8-LABEL: define {{[^@]+}}@main 1766 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 1767 // CHECK8-NEXT: entry: 1768 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1769 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 1770 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1771 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1772 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1773 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1774 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1775 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 1776 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1777 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1778 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1779 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1780 // CHECK8-NEXT: store i32 0, i32* [[SIVAR]], align 4 1781 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1782 // CHECK8: omp.inner.for.cond: 1783 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1784 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 1785 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1786 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1787 // CHECK8: omp.inner.for.body: 1788 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1789 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1790 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1791 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 1792 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1793 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 1794 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1795 // CHECK8-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 1796 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1797 // CHECK8: omp.body.continue: 1798 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1799 // CHECK8: omp.inner.for.inc: 1800 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1801 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1802 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1803 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1804 // CHECK8: omp.inner.for.end: 1805 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 1806 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1807 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1808 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1809 // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1810 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1811 // CHECK8-NEXT: ret i32 [[CALL]] 1812 // 1813 // 1814 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1815 // CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { 1816 // CHECK8-NEXT: entry: 1817 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1818 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1819 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 1820 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1821 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1822 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1823 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1824 // CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1825 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 1826 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1827 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1828 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1829 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1830 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1831 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1832 // CHECK8-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1833 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1834 // CHECK8: omp.inner.for.cond: 1835 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1836 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1837 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1838 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1839 // CHECK8: omp.inner.for.body: 1840 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1841 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1842 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1843 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1844 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1845 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 1846 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1847 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 1848 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1849 // CHECK8: omp.body.continue: 1850 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1851 // CHECK8: omp.inner.for.inc: 1852 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1853 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1854 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1855 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1856 // CHECK8: omp.inner.for.end: 1857 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 1858 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1859 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1860 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1861 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1862 // CHECK8-NEXT: ret i32 0 1863 // 1864 // 1865 // CHECK9-LABEL: define {{[^@]+}}@main 1866 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1867 // CHECK9-NEXT: entry: 1868 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1869 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1870 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1871 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1872 // CHECK9-NEXT: ret i32 0 1873 // 1874 // 1875 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 1876 // CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1877 // CHECK9-NEXT: entry: 1878 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1879 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1880 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1881 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 1882 // CHECK9-NEXT: ret void 1883 // 1884 // 1885 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1886 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 1887 // CHECK9-NEXT: entry: 1888 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1889 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1890 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1891 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1892 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1893 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1894 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1895 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1896 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1897 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1898 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1899 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1900 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 1901 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1902 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1903 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1904 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1905 // CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 1906 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1907 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1908 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1909 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1910 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1911 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1912 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1913 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1914 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1915 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1916 // CHECK9: cond.true: 1917 // CHECK9-NEXT: br label [[COND_END:%.*]] 1918 // CHECK9: cond.false: 1919 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1920 // CHECK9-NEXT: br label [[COND_END]] 1921 // CHECK9: cond.end: 1922 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1923 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1924 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1925 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1926 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1927 // CHECK9: omp.inner.for.cond: 1928 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1929 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1930 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1931 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1932 // CHECK9: omp.inner.for.body: 1933 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1934 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1935 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1936 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1937 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1938 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 1939 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1940 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 1941 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1942 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 1943 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) 1944 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1945 // CHECK9: omp.body.continue: 1946 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1947 // CHECK9: omp.inner.for.inc: 1948 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1949 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 1950 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1951 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1952 // CHECK9: omp.inner.for.end: 1953 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1954 // CHECK9: omp.loop.exit: 1955 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1956 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1957 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1958 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1959 // CHECK9: .omp.final.then: 1960 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 1961 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1962 // CHECK9: .omp.final.done: 1963 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1964 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8* 1965 // CHECK9-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 1966 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1967 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1968 // CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1969 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1970 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1971 // CHECK9-NEXT: ] 1972 // CHECK9: .omp.reduction.case1: 1973 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 1974 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 1975 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1976 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1977 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1978 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1979 // CHECK9: .omp.reduction.case2: 1980 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4 1981 // CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 1982 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1983 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1984 // CHECK9: .omp.reduction.default: 1985 // CHECK9-NEXT: ret void 1986 // 1987 // 1988 // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1989 // CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 1990 // CHECK9-NEXT: entry: 1991 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1992 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1993 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1994 // CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1995 // CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1996 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1997 // CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1998 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1999 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 2000 // CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2001 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 2002 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 2003 // CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2004 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 2005 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2006 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 2007 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 2008 // CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 2009 // CHECK9-NEXT: ret void 2010 // 2011 // 2012 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2013 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 2014 // CHECK9-NEXT: entry: 2015 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2016 // CHECK9-NEXT: ret void 2017 // 2018 // 2019 // CHECK10-LABEL: define {{[^@]+}}@main 2020 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 2021 // CHECK10-NEXT: entry: 2022 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2023 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2024 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 2025 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2026 // CHECK10-NEXT: ret i32 0 2027 // 2028 // 2029 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 2030 // CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 2031 // CHECK10-NEXT: entry: 2032 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2033 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2034 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2035 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 2036 // CHECK10-NEXT: ret void 2037 // 2038 // 2039 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2040 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { 2041 // CHECK10-NEXT: entry: 2042 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2043 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2044 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 2045 // CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 2046 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2047 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 2048 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2049 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2050 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2051 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2052 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 2053 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2054 // CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 2055 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2056 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2057 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 2058 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 2059 // CHECK10-NEXT: store i32 0, i32* [[SIVAR1]], align 4 2060 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2061 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2062 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2063 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2064 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2065 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2066 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2067 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2068 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 2069 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2070 // CHECK10: cond.true: 2071 // CHECK10-NEXT: br label [[COND_END:%.*]] 2072 // CHECK10: cond.false: 2073 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2074 // CHECK10-NEXT: br label [[COND_END]] 2075 // CHECK10: cond.end: 2076 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2077 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2078 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2079 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2080 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2081 // CHECK10: omp.inner.for.cond: 2082 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2083 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2084 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2085 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2086 // CHECK10: omp.inner.for.body: 2087 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2088 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2089 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2090 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2091 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 2092 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 2093 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 2094 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 2095 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2096 // CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 2097 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) 2098 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2099 // CHECK10: omp.body.continue: 2100 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2101 // CHECK10: omp.inner.for.inc: 2102 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2103 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2104 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2105 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2106 // CHECK10: omp.inner.for.end: 2107 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2108 // CHECK10: omp.loop.exit: 2109 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2110 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2111 // CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2112 // CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2113 // CHECK10: .omp.final.then: 2114 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 2115 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 2116 // CHECK10: .omp.final.done: 2117 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2118 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8* 2119 // CHECK10-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 2120 // CHECK10-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 2121 // CHECK10-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 2122 // CHECK10-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2123 // CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2124 // CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2125 // CHECK10-NEXT: ] 2126 // CHECK10: .omp.reduction.case1: 2127 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 2128 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 2129 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 2130 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 2131 // CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2132 // CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2133 // CHECK10: .omp.reduction.case2: 2134 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4 2135 // CHECK10-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 2136 // CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2137 // CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2138 // CHECK10: .omp.reduction.default: 2139 // CHECK10-NEXT: ret void 2140 // 2141 // 2142 // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 2143 // CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 2144 // CHECK10-NEXT: entry: 2145 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2146 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 2147 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2148 // CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 2149 // CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 2150 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 2151 // CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 2152 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 2153 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 2154 // CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2155 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 2156 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 2157 // CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2158 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 2159 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2160 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 2161 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 2162 // CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 2163 // CHECK10-NEXT: ret void 2164 // 2165 // 2166 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2167 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { 2168 // CHECK10-NEXT: entry: 2169 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 2170 // CHECK10-NEXT: ret void 2171 // 2172 // 2173 // CHECK11-LABEL: define {{[^@]+}}@main 2174 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2175 // CHECK11-NEXT: entry: 2176 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2177 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2178 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2179 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2180 // CHECK11-NEXT: ret i32 0 2181 // 2182 // 2183 // CHECK12-LABEL: define {{[^@]+}}@main 2184 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 2185 // CHECK12-NEXT: entry: 2186 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2187 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2188 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2189 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2190 // CHECK12-NEXT: ret i32 0 2191 // 2192