1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCRegisterInfo.h"
15 #include "PPCFrameLowering.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 #include "llvm/CodeGen/TargetInstrInfo.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include <cstdlib>
43
44 using namespace llvm;
45
46 #define DEBUG_TYPE "reginfo"
47
48 #define GET_REGINFO_TARGET_DESC
49 #include "PPCGenRegisterInfo.inc"
50
51 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
52 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
53
54 static cl::opt<bool>
55 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
56 cl::desc("Enable use of a base pointer for complex stack frames"));
57
58 static cl::opt<bool>
59 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
60 cl::desc("Force the use of a base pointer in every function"));
61
62 static cl::opt<bool>
63 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
64 cl::desc("Enable spills from gpr to vsr rather than stack"));
65
66 static cl::opt<bool>
67 StackPtrConst("ppc-stack-ptr-caller-preserved",
68 cl::desc("Consider R1 caller preserved so stack saves of "
69 "caller preserved registers can be LICM candidates"),
70 cl::init(true), cl::Hidden);
71
72 static cl::opt<unsigned>
73 MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
74 cl::desc("Maximum search distance for definition of CR bit "
75 "spill on ppc"),
76 cl::Hidden, cl::init(100));
77
78 // Copies/moves of physical accumulators are expensive operations
79 // that should be avoided whenever possible. MMA instructions are
80 // meant to be used in performance-sensitive computational kernels.
81 // This option is provided, at least for the time being, to give the
82 // user a tool to detect this expensive operation and either rework
83 // their code or report a compiler bug if that turns out to be the
84 // cause.
85 #ifndef NDEBUG
86 static cl::opt<bool>
87 ReportAccMoves("ppc-report-acc-moves",
88 cl::desc("Emit information about accumulator register spills "
89 "and copies"),
90 cl::Hidden, cl::init(false));
91 #endif
92
93 static unsigned offsetMinAlignForOpcode(unsigned OpC);
94
PPCRegisterInfo(const PPCTargetMachine & TM)95 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
97 TM.isPPC64() ? 0 : 1,
98 TM.isPPC64() ? 0 : 1),
99 TM(TM) {
100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
101 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
102 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
103 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
104 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
105 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
108 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
109
110 // 64-bit
111 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
112 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
113 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
114 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
115 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
116
117 // VSX
118 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
119 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
120 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
121 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
122 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
123 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
124 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
125 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
126 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
127 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
128 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
129 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
130
131 // SPE
132 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
133 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
134 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
135 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
136
137 // Power10
138 ImmToIdxMap[PPC::LXVP] = PPC::LXVPX;
139 ImmToIdxMap[PPC::STXVP] = PPC::STXVPX;
140 ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX;
141 ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX;
142 }
143
144 /// getPointerRegClass - Return the register class to use to hold pointers.
145 /// This is used for addressing modes.
146 const TargetRegisterClass *
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const147 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
148 const {
149 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
150 // when it checks for ZERO folding.
151 if (Kind == 1) {
152 if (TM.isPPC64())
153 return &PPC::G8RC_NOX0RegClass;
154 return &PPC::GPRC_NOR0RegClass;
155 }
156
157 if (TM.isPPC64())
158 return &PPC::G8RCRegClass;
159 return &PPC::GPRCRegClass;
160 }
161
162 const MCPhysReg*
getCalleeSavedRegs(const MachineFunction * MF) const163 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
164 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
165 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
166 if (!TM.isPPC64() && Subtarget.isAIXABI())
167 report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
168 if (Subtarget.hasVSX()) {
169 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
170 return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
171 return CSR_64_AllRegs_VSX_SaveList;
172 }
173 if (Subtarget.hasAltivec()) {
174 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
175 return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList;
176 return CSR_64_AllRegs_Altivec_SaveList;
177 }
178 return CSR_64_AllRegs_SaveList;
179 }
180
181 // On PPC64, we might need to save r2 (but only if it is not reserved).
182 // We do not need to treat R2 as callee-saved when using PC-Relative calls
183 // because any direct uses of R2 will cause it to be reserved. If the function
184 // is a leaf or the only uses of R2 are implicit uses for calls, the calls
185 // will use the @notoc relocation which will cause this function to set the
186 // st_other bit to 1, thereby communicating to its caller that it arbitrarily
187 // clobbers the TOC.
188 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) &&
189 !Subtarget.isUsingPCRelativeCalls();
190
191 // Cold calling convention CSRs.
192 if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
193 if (Subtarget.isAIXABI())
194 report_fatal_error("Cold calling unimplemented on AIX.");
195 if (TM.isPPC64()) {
196 if (Subtarget.hasAltivec())
197 return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
198 : CSR_SVR64_ColdCC_Altivec_SaveList;
199 return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
200 : CSR_SVR64_ColdCC_SaveList;
201 }
202 // 32-bit targets.
203 if (Subtarget.hasAltivec())
204 return CSR_SVR32_ColdCC_Altivec_SaveList;
205 else if (Subtarget.hasSPE())
206 return CSR_SVR32_ColdCC_SPE_SaveList;
207 return CSR_SVR32_ColdCC_SaveList;
208 }
209 // Standard calling convention CSRs.
210 if (TM.isPPC64()) {
211 if (Subtarget.hasAltivec() &&
212 (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
213 return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
214 : CSR_PPC64_Altivec_SaveList;
215 }
216 return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
217 }
218 // 32-bit targets.
219 if (Subtarget.isAIXABI()) {
220 if (Subtarget.hasAltivec())
221 return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
222 : CSR_AIX32_SaveList;
223 return CSR_AIX32_SaveList;
224 }
225 if (Subtarget.hasAltivec())
226 return CSR_SVR432_Altivec_SaveList;
227 else if (Subtarget.hasSPE())
228 return CSR_SVR432_SPE_SaveList;
229 return CSR_SVR432_SaveList;
230 }
231
232 const uint32_t *
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID CC) const233 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
234 CallingConv::ID CC) const {
235 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
236 if (CC == CallingConv::AnyReg) {
237 if (Subtarget.hasVSX()) {
238 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
239 return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
240 return CSR_64_AllRegs_VSX_RegMask;
241 }
242 if (Subtarget.hasAltivec()) {
243 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
244 return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
245 return CSR_64_AllRegs_Altivec_RegMask;
246 }
247 return CSR_64_AllRegs_RegMask;
248 }
249
250 if (Subtarget.isAIXABI()) {
251 return TM.isPPC64()
252 ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
253 ? CSR_PPC64_Altivec_RegMask
254 : CSR_PPC64_RegMask)
255 : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
256 ? CSR_AIX32_Altivec_RegMask
257 : CSR_AIX32_RegMask);
258 }
259
260 if (CC == CallingConv::Cold) {
261 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
262 : CSR_SVR64_ColdCC_RegMask)
263 : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
264 : (Subtarget.hasSPE()
265 ? CSR_SVR32_ColdCC_SPE_RegMask
266 : CSR_SVR32_ColdCC_RegMask));
267 }
268
269 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
270 : CSR_PPC64_RegMask)
271 : (Subtarget.hasAltivec()
272 ? CSR_SVR432_Altivec_RegMask
273 : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
274 : CSR_SVR432_RegMask));
275 }
276
277 const uint32_t*
getNoPreservedMask() const278 PPCRegisterInfo::getNoPreservedMask() const {
279 return CSR_NoRegs_RegMask;
280 }
281
adjustStackMapLiveOutMask(uint32_t * Mask) const282 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
283 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
284 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
285 }
286
getReservedRegs(const MachineFunction & MF) const287 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
288 BitVector Reserved(getNumRegs());
289 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
290 const PPCFrameLowering *TFI = getFrameLowering(MF);
291
292 // The ZERO register is not really a register, but the representation of r0
293 // when used in instructions that treat r0 as the constant 0.
294 markSuperRegs(Reserved, PPC::ZERO);
295
296 // The FP register is also not really a register, but is the representation
297 // of the frame pointer register used by ISD::FRAMEADDR.
298 markSuperRegs(Reserved, PPC::FP);
299
300 // The BP register is also not really a register, but is the representation
301 // of the base pointer register used by setjmp.
302 markSuperRegs(Reserved, PPC::BP);
303
304 // The counter registers must be reserved so that counter-based loops can
305 // be correctly formed (and the mtctr instructions are not DCE'd).
306 markSuperRegs(Reserved, PPC::CTR);
307 markSuperRegs(Reserved, PPC::CTR8);
308
309 markSuperRegs(Reserved, PPC::R1);
310 markSuperRegs(Reserved, PPC::LR);
311 markSuperRegs(Reserved, PPC::LR8);
312 markSuperRegs(Reserved, PPC::RM);
313
314 markSuperRegs(Reserved, PPC::VRSAVE);
315
316 // The SVR4 ABI reserves r2 and r13
317 if (Subtarget.isSVR4ABI()) {
318 // We only reserve r2 if we need to use the TOC pointer. If we have no
319 // explicit uses of the TOC pointer (meaning we're a leaf function with
320 // no constant-pool loads, etc.) and we have no potential uses inside an
321 // inline asm block, then we can treat r2 has an ordinary callee-saved
322 // register.
323 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
324 if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
325 markSuperRegs(Reserved, PPC::R2); // System-reserved register
326 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
327 }
328
329 // Always reserve r2 on AIX for now.
330 // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
331 if (Subtarget.isAIXABI())
332 markSuperRegs(Reserved, PPC::R2); // System-reserved register
333
334 // On PPC64, r13 is the thread pointer. Never allocate this register.
335 if (TM.isPPC64())
336 markSuperRegs(Reserved, PPC::R13);
337
338 if (TFI->needsFP(MF))
339 markSuperRegs(Reserved, PPC::R31);
340
341 bool IsPositionIndependent = TM.isPositionIndependent();
342 if (hasBasePointer(MF)) {
343 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
344 markSuperRegs(Reserved, PPC::R29);
345 else
346 markSuperRegs(Reserved, PPC::R30);
347 }
348
349 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
350 markSuperRegs(Reserved, PPC::R30);
351
352 // Reserve Altivec registers when Altivec is unavailable.
353 if (!Subtarget.hasAltivec())
354 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
355 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
356 markSuperRegs(Reserved, *I);
357
358 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
359 !TM.getAIXExtendedAltivecABI()) {
360 // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved
361 // and cannot be used.
362 for (auto Reg : CSR_Altivec_SaveList) {
363 if (Reg == 0)
364 break;
365 markSuperRegs(Reserved, Reg);
366 for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) {
367 Reserved.set(*AS);
368 }
369 }
370 }
371
372 assert(checkAllSuperRegsMarked(Reserved));
373 return Reserved;
374 }
375
requiresFrameIndexScavenging(const MachineFunction & MF) const376 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
377 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
378 const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo();
379 const MachineFrameInfo &MFI = MF.getFrameInfo();
380 const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
381
382 LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
383 << ".\n");
384 // If the callee saved info is invalid we have to default to true for safety.
385 if (!MFI.isCalleeSavedInfoValid()) {
386 LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n");
387 return true;
388 }
389
390 // We will require the use of X-Forms because the frame is larger than what
391 // can be represented in signed 16 bits that fit in the immediate of a D-Form.
392 // If we need an X-Form then we need a register to store the address offset.
393 unsigned FrameSize = MFI.getStackSize();
394 // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
395 if (FrameSize & ~0x7FFF) {
396 LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n");
397 return true;
398 }
399
400 // The callee saved info is valid so it can be traversed.
401 // Checking for registers that need saving that do not have load or store
402 // forms where the address offset is an immediate.
403 for (unsigned i = 0; i < Info.size(); i++) {
404 // If the spill is to a register no scavenging is required.
405 if (Info[i].isSpilledToReg())
406 continue;
407
408 int FrIdx = Info[i].getFrameIdx();
409 unsigned Reg = Info[i].getReg();
410
411 const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
412 unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);
413 if (!MFI.isFixedObjectIndex(FrIdx)) {
414 // This is not a fixed object. If it requires alignment then we may still
415 // need to use the XForm.
416 if (offsetMinAlignForOpcode(Opcode) > 1) {
417 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
418 << " for register " << printReg(Reg, this) << ".\n");
419 LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires "
420 << "alignment.\n");
421 return true;
422 }
423 }
424
425 // This is eiher:
426 // 1) A fixed frame index object which we know are aligned so
427 // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
428 // need to consider the alignment here.
429 // 2) A not fixed object but in that case we now know that the min required
430 // alignment is no more than 1 based on the previous check.
431 if (InstrInfo->isXFormMemOp(Opcode)) {
432 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
433 << " for register " << printReg(Reg, this) << ".\n");
434 LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n");
435 return true;
436 }
437 }
438 LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n");
439 return false;
440 }
441
requiresVirtualBaseRegisters(const MachineFunction & MF) const442 bool PPCRegisterInfo::requiresVirtualBaseRegisters(
443 const MachineFunction &MF) const {
444 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
445 // Do not use virtual base registers when ROP protection is turned on.
446 // Virtual base registers break the layout of the local variable space and may
447 // push the ROP Hash location past the 512 byte range of the ROP store
448 // instruction.
449 return !Subtarget.hasROPProtect();
450 }
451
isCallerPreservedPhysReg(MCRegister PhysReg,const MachineFunction & MF) const452 bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
453 const MachineFunction &MF) const {
454 assert(Register::isPhysicalRegister(PhysReg));
455 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
456 const MachineFrameInfo &MFI = MF.getFrameInfo();
457
458 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
459 return false;
460 if (PhysReg == Subtarget.getTOCPointerRegister())
461 // X2/R2 is guaranteed to be preserved within a function if it is reserved.
462 // The reason it's reserved is that it's the TOC pointer (and the function
463 // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
464 // with no TOC access), we can't claim that it is preserved.
465 return (getReservedRegs(MF).test(PhysReg));
466 if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
467 !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
468 // The value of the stack pointer does not change within a function after
469 // the prologue and before the epilogue if there are no dynamic allocations
470 // and no inline asm which clobbers X1/R1.
471 return true;
472 return false;
473 }
474
getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const475 bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
476 ArrayRef<MCPhysReg> Order,
477 SmallVectorImpl<MCPhysReg> &Hints,
478 const MachineFunction &MF,
479 const VirtRegMap *VRM,
480 const LiveRegMatrix *Matrix) const {
481 const MachineRegisterInfo *MRI = &MF.getRegInfo();
482
483 // Call the base implementation first to set any hints based on the usual
484 // heuristics and decide what the return value should be. We want to return
485 // the same value returned by the base implementation. If the base
486 // implementation decides to return true and force the allocation then we
487 // will leave it as such. On the other hand if the base implementation
488 // decides to return false the following code will not force the allocation
489 // as we are just looking to provide a hint.
490 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
491 VirtReg, Order, Hints, MF, VRM, Matrix);
492 // We are interested in instructions that copy values to ACC/UACC.
493 // The copy into UACC will be simply a COPY to a subreg so we
494 // want to allocate the corresponding physical subreg for the source.
495 // The copy into ACC will be a BUILD_UACC so we want to allocate
496 // the same number UACC for the source.
497 for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
498 const MachineOperand *ResultOp = nullptr;
499 Register ResultReg;
500 switch (Use.getOpcode()) {
501 case TargetOpcode::COPY: {
502 ResultOp = &Use.getOperand(0);
503 ResultReg = ResultOp->getReg();
504 if (Register::isVirtualRegister(ResultReg) &&
505 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) &&
506 VRM->hasPhys(ResultReg)) {
507 Register UACCPhys = VRM->getPhys(ResultReg);
508 Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
509 Hints.push_back(HintReg);
510 }
511 break;
512 }
513 case PPC::BUILD_UACC: {
514 ResultOp = &Use.getOperand(0);
515 ResultReg = ResultOp->getReg();
516 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) &&
517 VRM->hasPhys(ResultReg)) {
518 Register ACCPhys = VRM->getPhys(ResultReg);
519 assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
520 "Expecting an ACC register for BUILD_UACC.");
521 Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
522 Hints.push_back(HintReg);
523 }
524 break;
525 }
526 }
527 }
528 return BaseImplRetVal;
529 }
530
getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF) const531 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
532 MachineFunction &MF) const {
533 const PPCFrameLowering *TFI = getFrameLowering(MF);
534 const unsigned DefaultSafety = 1;
535
536 switch (RC->getID()) {
537 default:
538 return 0;
539 case PPC::G8RC_NOX0RegClassID:
540 case PPC::GPRC_NOR0RegClassID:
541 case PPC::SPERCRegClassID:
542 case PPC::G8RCRegClassID:
543 case PPC::GPRCRegClassID: {
544 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
545 return 32 - FP - DefaultSafety;
546 }
547 case PPC::F4RCRegClassID:
548 case PPC::F8RCRegClassID:
549 case PPC::VSLRCRegClassID:
550 return 32 - DefaultSafety;
551 case PPC::VFRCRegClassID:
552 case PPC::VRRCRegClassID: {
553 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
554 // Vector registers VR20-VR31 are reserved and cannot be used in the default
555 // Altivec ABI on AIX.
556 if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
557 return 20 - DefaultSafety;
558 }
559 return 32 - DefaultSafety;
560 case PPC::VSFRCRegClassID:
561 case PPC::VSSRCRegClassID:
562 case PPC::VSRCRegClassID: {
563 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
564 if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
565 // Vector registers VR20-VR31 are reserved and cannot be used in the
566 // default Altivec ABI on AIX.
567 return 52 - DefaultSafety;
568 }
569 return 64 - DefaultSafety;
570 case PPC::CRRCRegClassID:
571 return 8 - DefaultSafety;
572 }
573 }
574
575 const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass * RC,const MachineFunction & MF) const576 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
577 const MachineFunction &MF) const {
578 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
579 const auto *DefaultSuperclass =
580 TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
581 if (Subtarget.hasVSX()) {
582 // With VSX, we can inflate various sub-register classes to the full VSX
583 // register set.
584
585 // For Power9 we allow the user to enable GPR to vector spills.
586 // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
587 // support to spill GPRC.
588 if (TM.isELFv2ABI() || Subtarget.isAIXABI()) {
589 if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
590 RC == &PPC::G8RCRegClass) {
591 InflateGP8RC++;
592 return &PPC::SPILLTOVSRRCRegClass;
593 }
594 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
595 InflateGPRC++;
596 }
597
598 for (const auto *I = RC->getSuperClasses(); *I; ++I) {
599 if (getRegSizeInBits(**I) != getRegSizeInBits(*RC))
600 continue;
601
602 switch ((*I)->getID()) {
603 case PPC::VSSRCRegClassID:
604 return Subtarget.hasP8Vector() ? *I : DefaultSuperclass;
605 case PPC::VSFRCRegClassID:
606 case PPC::VSRCRegClassID:
607 return *I;
608 case PPC::VSRpRCRegClassID:
609 return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass;
610 case PPC::ACCRCRegClassID:
611 case PPC::UACCRCRegClassID:
612 return Subtarget.hasMMA() ? *I : DefaultSuperclass;
613 }
614 }
615 }
616
617 return DefaultSuperclass;
618 }
619
620 //===----------------------------------------------------------------------===//
621 // Stack Frame Processing methods
622 //===----------------------------------------------------------------------===//
623
624 /// lowerDynamicAlloc - Generate the code for allocating an object in the
625 /// current frame. The sequence of code will be in the general form
626 ///
627 /// addi R0, SP, \#frameSize ; get the address of the previous frame
628 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
629 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
630 ///
lowerDynamicAlloc(MachineBasicBlock::iterator II) const631 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
632 // Get the instruction.
633 MachineInstr &MI = *II;
634 // Get the instruction's basic block.
635 MachineBasicBlock &MBB = *MI.getParent();
636 // Get the basic block's function.
637 MachineFunction &MF = *MBB.getParent();
638 // Get the frame info.
639 MachineFrameInfo &MFI = MF.getFrameInfo();
640 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
641 // Get the instruction info.
642 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
643 // Determine whether 64-bit pointers are used.
644 bool LP64 = TM.isPPC64();
645 DebugLoc dl = MI.getDebugLoc();
646
647 // Get the maximum call stack size.
648 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
649 Align MaxAlign = MFI.getMaxAlign();
650 assert(isAligned(MaxAlign, maxCallFrameSize) &&
651 "Maximum call-frame size not sufficiently aligned");
652 (void)MaxAlign;
653
654 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
656 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
657 bool KillNegSizeReg = MI.getOperand(1).isKill();
658 Register NegSizeReg = MI.getOperand(1).getReg();
659
660 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, Reg);
661 // Grow the stack and update the stack pointer link, then determine the
662 // address of new allocated space.
663 if (LP64) {
664 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
665 .addReg(Reg, RegState::Kill)
666 .addReg(PPC::X1)
667 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
668 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
669 .addReg(PPC::X1)
670 .addImm(maxCallFrameSize);
671 } else {
672 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
673 .addReg(Reg, RegState::Kill)
674 .addReg(PPC::R1)
675 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
676 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
677 .addReg(PPC::R1)
678 .addImm(maxCallFrameSize);
679 }
680
681 // Discard the DYNALLOC instruction.
682 MBB.erase(II);
683 }
684
685 /// To accomplish dynamic stack allocation, we have to calculate exact size
686 /// subtracted from the stack pointer according alignment information and get
687 /// previous frame pointer.
prepareDynamicAlloca(MachineBasicBlock::iterator II,Register & NegSizeReg,bool & KillNegSizeReg,Register & FramePointer) const688 void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II,
689 Register &NegSizeReg,
690 bool &KillNegSizeReg,
691 Register &FramePointer) const {
692 // Get the instruction.
693 MachineInstr &MI = *II;
694 // Get the instruction's basic block.
695 MachineBasicBlock &MBB = *MI.getParent();
696 // Get the basic block's function.
697 MachineFunction &MF = *MBB.getParent();
698 // Get the frame info.
699 MachineFrameInfo &MFI = MF.getFrameInfo();
700 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
701 // Get the instruction info.
702 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
703 // Determine whether 64-bit pointers are used.
704 bool LP64 = TM.isPPC64();
705 DebugLoc dl = MI.getDebugLoc();
706 // Get the total frame size.
707 unsigned FrameSize = MFI.getStackSize();
708
709 // Get stack alignments.
710 const PPCFrameLowering *TFI = getFrameLowering(MF);
711 Align TargetAlign = TFI->getStackAlign();
712 Align MaxAlign = MFI.getMaxAlign();
713
714 // Determine the previous frame's address. If FrameSize can't be
715 // represented as 16 bits or we need special alignment, then we load the
716 // previous frame's address from 0(SP). Why not do an addis of the hi?
717 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
718 // Constructing the constant and adding would take 3 instructions.
719 // Fortunately, a frame greater than 32K is rare.
720 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
721 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
722
723 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
724 if (LP64)
725 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer)
726 .addReg(PPC::X31)
727 .addImm(FrameSize);
728 else
729 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer)
730 .addReg(PPC::R31)
731 .addImm(FrameSize);
732 } else if (LP64) {
733 BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer)
734 .addImm(0)
735 .addReg(PPC::X1);
736 } else {
737 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer)
738 .addImm(0)
739 .addReg(PPC::R1);
740 }
741 // Determine the actual NegSizeReg according to alignment info.
742 if (LP64) {
743 if (MaxAlign > TargetAlign) {
744 unsigned UnalNegSizeReg = NegSizeReg;
745 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
746
747 // Unfortunately, there is no andi, only andi., and we can't insert that
748 // here because we might clobber cr0 while it is live.
749 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
750 .addImm(~(MaxAlign.value() - 1));
751
752 unsigned NegSizeReg1 = NegSizeReg;
753 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
754 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
755 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
756 .addReg(NegSizeReg1, RegState::Kill);
757 KillNegSizeReg = true;
758 }
759 } else {
760 if (MaxAlign > TargetAlign) {
761 unsigned UnalNegSizeReg = NegSizeReg;
762 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
763
764 // Unfortunately, there is no andi, only andi., and we can't insert that
765 // here because we might clobber cr0 while it is live.
766 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
767 .addImm(~(MaxAlign.value() - 1));
768
769 unsigned NegSizeReg1 = NegSizeReg;
770 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
771 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
772 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
773 .addReg(NegSizeReg1, RegState::Kill);
774 KillNegSizeReg = true;
775 }
776 }
777 }
778
lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const779 void PPCRegisterInfo::lowerPrepareProbedAlloca(
780 MachineBasicBlock::iterator II) const {
781 MachineInstr &MI = *II;
782 // Get the instruction's basic block.
783 MachineBasicBlock &MBB = *MI.getParent();
784 // Get the basic block's function.
785 MachineFunction &MF = *MBB.getParent();
786 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
787 // Get the instruction info.
788 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
789 // Determine whether 64-bit pointers are used.
790 bool LP64 = TM.isPPC64();
791 DebugLoc dl = MI.getDebugLoc();
792 Register FramePointer = MI.getOperand(0).getReg();
793 const Register ActualNegSizeReg = MI.getOperand(1).getReg();
794 bool KillNegSizeReg = MI.getOperand(2).isKill();
795 Register NegSizeReg = MI.getOperand(2).getReg();
796 const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR);
797 // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
798 if (FramePointer == NegSizeReg) {
799 assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
800 "NegSizeReg should be killed");
801 // FramePointer is clobbered earlier than the use of NegSizeReg in
802 // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
803 // misuse.
804 BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
805 .addReg(NegSizeReg)
806 .addReg(NegSizeReg);
807 NegSizeReg = ActualNegSizeReg;
808 KillNegSizeReg = false;
809 }
810 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
811 // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
812 // TargetAlign.
813 if (NegSizeReg != ActualNegSizeReg)
814 BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
815 .addReg(NegSizeReg)
816 .addReg(NegSizeReg);
817 MBB.erase(II);
818 }
819
lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const820 void PPCRegisterInfo::lowerDynamicAreaOffset(
821 MachineBasicBlock::iterator II) const {
822 // Get the instruction.
823 MachineInstr &MI = *II;
824 // Get the instruction's basic block.
825 MachineBasicBlock &MBB = *MI.getParent();
826 // Get the basic block's function.
827 MachineFunction &MF = *MBB.getParent();
828 // Get the frame info.
829 MachineFrameInfo &MFI = MF.getFrameInfo();
830 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
831 // Get the instruction info.
832 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
833
834 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
835 bool is64Bit = TM.isPPC64();
836 DebugLoc dl = MI.getDebugLoc();
837 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
838 MI.getOperand(0).getReg())
839 .addImm(maxCallFrameSize);
840 MBB.erase(II);
841 }
842
843 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
844 /// reserving a whole register (R0), we scrounge for one here. This generates
845 /// code like this:
846 ///
847 /// mfcr rA ; Move the conditional register into GPR rA.
848 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
849 /// stw rA, FI ; Store rA to the frame.
850 ///
lowerCRSpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const851 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
852 unsigned FrameIndex) const {
853 // Get the instruction.
854 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
855 // Get the instruction's basic block.
856 MachineBasicBlock &MBB = *MI.getParent();
857 MachineFunction &MF = *MBB.getParent();
858 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
859 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
860 DebugLoc dl = MI.getDebugLoc();
861
862 bool LP64 = TM.isPPC64();
863 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
864 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
865
866 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
867 Register SrcReg = MI.getOperand(0).getReg();
868
869 // We need to store the CR in the low 4-bits of the saved value. First, issue
870 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
871 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
872 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
873
874 // If the saved register wasn't CR0, shift the bits left so that they are in
875 // CR0's slot.
876 if (SrcReg != PPC::CR0) {
877 Register Reg1 = Reg;
878 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
879
880 // rlwinm rA, rA, ShiftBits, 0, 31.
881 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
882 .addReg(Reg1, RegState::Kill)
883 .addImm(getEncodingValue(SrcReg) * 4)
884 .addImm(0)
885 .addImm(31);
886 }
887
888 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
889 .addReg(Reg, RegState::Kill),
890 FrameIndex);
891
892 // Discard the pseudo instruction.
893 MBB.erase(II);
894 }
895
lowerCRRestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const896 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
897 unsigned FrameIndex) const {
898 // Get the instruction.
899 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
900 // Get the instruction's basic block.
901 MachineBasicBlock &MBB = *MI.getParent();
902 MachineFunction &MF = *MBB.getParent();
903 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
904 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
905 DebugLoc dl = MI.getDebugLoc();
906
907 bool LP64 = TM.isPPC64();
908 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
909 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
910
911 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
912 Register DestReg = MI.getOperand(0).getReg();
913 assert(MI.definesRegister(DestReg) &&
914 "RESTORE_CR does not define its destination");
915
916 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
917 Reg), FrameIndex);
918
919 // If the reloaded register isn't CR0, shift the bits right so that they are
920 // in the right CR's slot.
921 if (DestReg != PPC::CR0) {
922 Register Reg1 = Reg;
923 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
924
925 unsigned ShiftBits = getEncodingValue(DestReg)*4;
926 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
927 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
928 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
929 .addImm(31);
930 }
931
932 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
933 .addReg(Reg, RegState::Kill);
934
935 // Discard the pseudo instruction.
936 MBB.erase(II);
937 }
938
lowerCRBitSpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const939 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
940 unsigned FrameIndex) const {
941 // Get the instruction.
942 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
943 // Get the instruction's basic block.
944 MachineBasicBlock &MBB = *MI.getParent();
945 MachineFunction &MF = *MBB.getParent();
946 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
947 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
948 const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
949 DebugLoc dl = MI.getDebugLoc();
950
951 bool LP64 = TM.isPPC64();
952 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
953 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
954
955 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
956 Register SrcReg = MI.getOperand(0).getReg();
957
958 // Search up the BB to find the definition of the CR bit.
959 MachineBasicBlock::reverse_iterator Ins = MI;
960 MachineBasicBlock::reverse_iterator Rend = MBB.rend();
961 ++Ins;
962 unsigned CRBitSpillDistance = 0;
963 bool SeenUse = false;
964 for (; Ins != Rend; ++Ins) {
965 // Definition found.
966 if (Ins->modifiesRegister(SrcReg, TRI))
967 break;
968 // Use found.
969 if (Ins->readsRegister(SrcReg, TRI))
970 SeenUse = true;
971 // Unable to find CR bit definition within maximum search distance.
972 if (CRBitSpillDistance == MaxCRBitSpillDist) {
973 Ins = MI;
974 break;
975 }
976 // Skip debug instructions when counting CR bit spill distance.
977 if (!Ins->isDebugInstr())
978 CRBitSpillDistance++;
979 }
980
981 // Unable to find the definition of the CR bit in the MBB.
982 if (Ins == MBB.rend())
983 Ins = MI;
984
985 bool SpillsKnownBit = false;
986 // There is no need to extract the CR bit if its value is already known.
987 switch (Ins->getOpcode()) {
988 case PPC::CRUNSET:
989 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
990 .addImm(0);
991 SpillsKnownBit = true;
992 break;
993 case PPC::CRSET:
994 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
995 .addImm(-32768);
996 SpillsKnownBit = true;
997 break;
998 default:
999 // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
1000 // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
1001 // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
1002 // register), and SETNBC will set this.
1003 if (Subtarget.isISA3_1()) {
1004 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg)
1005 .addReg(SrcReg, RegState::Undef);
1006 break;
1007 }
1008
1009 // On Power9, we can use SETB to extract the LT bit. This only works for
1010 // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
1011 // of the bit we care about (32-bit sign bit) will be set to the value of
1012 // the LT bit (regardless of the other bits in the CR field).
1013 if (Subtarget.isISA3_0()) {
1014 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
1015 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
1016 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
1017 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
1018 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
1019 .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
1020 break;
1021 }
1022 }
1023
1024 // We need to move the CR field that contains the CR bit we are spilling.
1025 // The super register may not be explicitly defined (i.e. it can be defined
1026 // by a CR-logical that only defines the subreg) so we state that the CR
1027 // field is undef. Also, in order to preserve the kill flag on the CR bit,
1028 // we add it as an implicit use.
1029 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
1030 .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
1031 .addReg(SrcReg,
1032 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
1033
1034 // If the saved register wasn't CR0LT, shift the bits left so that the bit
1035 // to store is the first one. Mask all but that bit.
1036 Register Reg1 = Reg;
1037 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1038
1039 // rlwinm rA, rA, ShiftBits, 0, 0.
1040 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
1041 .addReg(Reg1, RegState::Kill)
1042 .addImm(getEncodingValue(SrcReg))
1043 .addImm(0).addImm(0);
1044 }
1045 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
1046 .addReg(Reg, RegState::Kill),
1047 FrameIndex);
1048
1049 bool KillsCRBit = MI.killsRegister(SrcReg, TRI);
1050 // Discard the pseudo instruction.
1051 MBB.erase(II);
1052 if (SpillsKnownBit && KillsCRBit && !SeenUse) {
1053 Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
1054 Ins->RemoveOperand(0);
1055 }
1056 }
1057
lowerCRBitRestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const1058 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
1059 unsigned FrameIndex) const {
1060 // Get the instruction.
1061 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
1062 // Get the instruction's basic block.
1063 MachineBasicBlock &MBB = *MI.getParent();
1064 MachineFunction &MF = *MBB.getParent();
1065 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1066 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1067 DebugLoc dl = MI.getDebugLoc();
1068
1069 bool LP64 = TM.isPPC64();
1070 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1071 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1072
1073 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1074 Register DestReg = MI.getOperand(0).getReg();
1075 assert(MI.definesRegister(DestReg) &&
1076 "RESTORE_CRBIT does not define its destination");
1077
1078 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
1079 Reg), FrameIndex);
1080
1081 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
1082
1083 Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1084 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
1085 .addReg(getCRFromCRBit(DestReg));
1086
1087 unsigned ShiftBits = getEncodingValue(DestReg);
1088 // rlwimi r11, r10, 32-ShiftBits, ..., ...
1089 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
1090 .addReg(RegO, RegState::Kill)
1091 .addReg(Reg, RegState::Kill)
1092 .addImm(ShiftBits ? 32 - ShiftBits : 0)
1093 .addImm(ShiftBits)
1094 .addImm(ShiftBits);
1095
1096 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
1097 getCRFromCRBit(DestReg))
1098 .addReg(RegO, RegState::Kill)
1099 // Make sure we have a use dependency all the way through this
1100 // sequence of instructions. We can't have the other bits in the CR
1101 // modified in between the mfocrf and the mtocrf.
1102 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
1103
1104 // Discard the pseudo instruction.
1105 MBB.erase(II);
1106 }
1107
emitAccCopyInfo(MachineBasicBlock & MBB,MCRegister DestReg,MCRegister SrcReg)1108 void PPCRegisterInfo::emitAccCopyInfo(MachineBasicBlock &MBB,
1109 MCRegister DestReg, MCRegister SrcReg) {
1110 #ifdef NDEBUG
1111 return;
1112 #else
1113 if (ReportAccMoves) {
1114 std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc";
1115 std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc";
1116 dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n";
1117 MBB.dump();
1118 }
1119 #endif
1120 }
1121
emitAccSpillRestoreInfo(MachineBasicBlock & MBB,bool IsPrimed,bool IsRestore)1122 static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
1123 bool IsRestore) {
1124 #ifdef NDEBUG
1125 return;
1126 #else
1127 if (ReportAccMoves) {
1128 dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register "
1129 << (IsRestore ? "restore" : "spill") << ":\n";
1130 MBB.dump();
1131 }
1132 #endif
1133 }
1134
1135 /// lowerACCSpilling - Generate the code for spilling the accumulator register.
1136 /// Similarly to other spills/reloads that use pseudo-ops, we do not actually
1137 /// eliminate the FrameIndex here nor compute the stack offset. We simply
1138 /// create a real instruction with an FI and rely on eliminateFrameIndex to
1139 /// handle the FI elimination.
lowerACCSpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const1140 void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
1141 unsigned FrameIndex) const {
1142 MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset>
1143 MachineBasicBlock &MBB = *MI.getParent();
1144 MachineFunction &MF = *MBB.getParent();
1145 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1146 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1147 DebugLoc DL = MI.getDebugLoc();
1148 Register SrcReg = MI.getOperand(0).getReg();
1149 bool IsKilled = MI.getOperand(0).isKill();
1150
1151 bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1152 Register Reg =
1153 PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1154 bool IsLittleEndian = Subtarget.isLittleEndian();
1155
1156 emitAccSpillRestoreInfo(MBB, IsPrimed, false);
1157
1158 // De-prime the register being spilled, create two stores for the pair
1159 // subregisters accounting for endianness and then re-prime the register if
1160 // it isn't killed. This uses the Offset parameter to addFrameReference() to
1161 // adjust the offset of the store that is within the 64-byte stack slot.
1162 if (IsPrimed)
1163 BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1164 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1165 .addReg(Reg, getKillRegState(IsKilled)),
1166 FrameIndex, IsLittleEndian ? 32 : 0);
1167 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1168 .addReg(Reg + 1, getKillRegState(IsKilled)),
1169 FrameIndex, IsLittleEndian ? 0 : 32);
1170 if (IsPrimed && !IsKilled)
1171 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
1172
1173 // Discard the pseudo instruction.
1174 MBB.erase(II);
1175 }
1176
1177 /// lowerACCRestore - Generate the code to restore the accumulator register.
lowerACCRestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const1178 void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II,
1179 unsigned FrameIndex) const {
1180 MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset>
1181 MachineBasicBlock &MBB = *MI.getParent();
1182 MachineFunction &MF = *MBB.getParent();
1183 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1185 DebugLoc DL = MI.getDebugLoc();
1186
1187 Register DestReg = MI.getOperand(0).getReg();
1188 assert(MI.definesRegister(DestReg) &&
1189 "RESTORE_ACC does not define its destination");
1190
1191 bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg);
1192 Register Reg =
1193 PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1194 bool IsLittleEndian = Subtarget.isLittleEndian();
1195
1196 emitAccSpillRestoreInfo(MBB, IsPrimed, true);
1197
1198 // Create two loads for the pair subregisters accounting for endianness and
1199 // then prime the accumulator register being restored.
1200 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg),
1201 FrameIndex, IsLittleEndian ? 32 : 0);
1202 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1),
1203 FrameIndex, IsLittleEndian ? 0 : 32);
1204 if (IsPrimed)
1205 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg);
1206
1207 // Discard the pseudo instruction.
1208 MBB.erase(II);
1209 }
1210
1211 /// lowerQuadwordSpilling - Generate code to spill paired general register.
lowerQuadwordSpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const1212 void PPCRegisterInfo::lowerQuadwordSpilling(MachineBasicBlock::iterator II,
1213 unsigned FrameIndex) const {
1214 MachineInstr &MI = *II;
1215 MachineBasicBlock &MBB = *MI.getParent();
1216 MachineFunction &MF = *MBB.getParent();
1217 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1218 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1219 DebugLoc DL = MI.getDebugLoc();
1220
1221 Register SrcReg = MI.getOperand(0).getReg();
1222 bool IsKilled = MI.getOperand(0).isKill();
1223
1224 Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2;
1225 bool IsLittleEndian = Subtarget.isLittleEndian();
1226
1227 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1228 .addReg(Reg, getKillRegState(IsKilled)),
1229 FrameIndex, IsLittleEndian ? 8 : 0);
1230 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1231 .addReg(Reg + 1, getKillRegState(IsKilled)),
1232 FrameIndex, IsLittleEndian ? 0 : 8);
1233
1234 // Discard the pseudo instruction.
1235 MBB.erase(II);
1236 }
1237
1238 /// lowerQuadwordRestore - Generate code to restore paired general register.
lowerQuadwordRestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const1239 void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II,
1240 unsigned FrameIndex) const {
1241 MachineInstr &MI = *II;
1242 MachineBasicBlock &MBB = *MI.getParent();
1243 MachineFunction &MF = *MBB.getParent();
1244 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1245 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1246 DebugLoc DL = MI.getDebugLoc();
1247
1248 Register DestReg = MI.getOperand(0).getReg();
1249 assert(MI.definesRegister(DestReg) &&
1250 "RESTORE_QUADWORD does not define its destination");
1251
1252 Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2;
1253 bool IsLittleEndian = Subtarget.isLittleEndian();
1254
1255 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg), FrameIndex,
1256 IsLittleEndian ? 8 : 0);
1257 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg + 1), FrameIndex,
1258 IsLittleEndian ? 0 : 8);
1259
1260 // Discard the pseudo instruction.
1261 MBB.erase(II);
1262 }
1263
hasReservedSpillSlot(const MachineFunction & MF,Register Reg,int & FrameIdx) const1264 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
1265 Register Reg, int &FrameIdx) const {
1266 // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
1267 // prevent allocating an additional frame slot.
1268 // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
1269 // for 32-bit AIX the CR save area is in the linkage area at SP+4.
1270 // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
1271 // valid.
1272 // For 32-bit ELF, we have previously created the stack slot if needed, so
1273 // return its FrameIdx.
1274 if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
1275 FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
1276 return true;
1277 }
1278 return false;
1279 }
1280
1281 // If the offset must be a multiple of some value, return what that value is.
offsetMinAlignForOpcode(unsigned OpC)1282 static unsigned offsetMinAlignForOpcode(unsigned OpC) {
1283 switch (OpC) {
1284 default:
1285 return 1;
1286 case PPC::LWA:
1287 case PPC::LWA_32:
1288 case PPC::LD:
1289 case PPC::LDU:
1290 case PPC::STD:
1291 case PPC::STDU:
1292 case PPC::DFLOADf32:
1293 case PPC::DFLOADf64:
1294 case PPC::DFSTOREf32:
1295 case PPC::DFSTOREf64:
1296 case PPC::LXSD:
1297 case PPC::LXSSP:
1298 case PPC::STXSD:
1299 case PPC::STXSSP:
1300 case PPC::STQ:
1301 return 4;
1302 case PPC::EVLDD:
1303 case PPC::EVSTDD:
1304 return 8;
1305 case PPC::LXV:
1306 case PPC::STXV:
1307 case PPC::LQ:
1308 case PPC::LXVP:
1309 case PPC::STXVP:
1310 return 16;
1311 }
1312 }
1313
1314 // If the offset must be a multiple of some value, return what that value is.
offsetMinAlign(const MachineInstr & MI)1315 static unsigned offsetMinAlign(const MachineInstr &MI) {
1316 unsigned OpC = MI.getOpcode();
1317 return offsetMinAlignForOpcode(OpC);
1318 }
1319
1320 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
getOffsetONFromFION(const MachineInstr & MI,unsigned FIOperandNum)1321 static unsigned getOffsetONFromFION(const MachineInstr &MI,
1322 unsigned FIOperandNum) {
1323 // Take into account whether it's an add or mem instruction
1324 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
1325 if (MI.isInlineAsm())
1326 OffsetOperandNo = FIOperandNum - 1;
1327 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
1328 MI.getOpcode() == TargetOpcode::PATCHPOINT)
1329 OffsetOperandNo = FIOperandNum + 1;
1330
1331 return OffsetOperandNo;
1332 }
1333
1334 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const1335 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1336 int SPAdj, unsigned FIOperandNum,
1337 RegScavenger *RS) const {
1338 assert(SPAdj == 0 && "Unexpected");
1339
1340 // Get the instruction.
1341 MachineInstr &MI = *II;
1342 // Get the instruction's basic block.
1343 MachineBasicBlock &MBB = *MI.getParent();
1344 // Get the basic block's function.
1345 MachineFunction &MF = *MBB.getParent();
1346 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1347 // Get the instruction info.
1348 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1349 // Get the frame info.
1350 MachineFrameInfo &MFI = MF.getFrameInfo();
1351 DebugLoc dl = MI.getDebugLoc();
1352
1353 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1354
1355 // Get the frame index.
1356 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1357
1358 // Get the frame pointer save index. Users of this index are primarily
1359 // DYNALLOC instructions.
1360 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1361 int FPSI = FI->getFramePointerSaveIndex();
1362 // Get the instruction opcode.
1363 unsigned OpC = MI.getOpcode();
1364
1365 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
1366 lowerDynamicAreaOffset(II);
1367 return;
1368 }
1369
1370 // Special case for dynamic alloca.
1371 if (FPSI && FrameIndex == FPSI &&
1372 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
1373 lowerDynamicAlloc(II);
1374 return;
1375 }
1376
1377 if (FPSI && FrameIndex == FPSI &&
1378 (OpC == PPC::PREPARE_PROBED_ALLOCA_64 ||
1379 OpC == PPC::PREPARE_PROBED_ALLOCA_32 ||
1380 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 ||
1381 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) {
1382 lowerPrepareProbedAlloca(II);
1383 return;
1384 }
1385
1386 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1387 if (OpC == PPC::SPILL_CR) {
1388 lowerCRSpilling(II, FrameIndex);
1389 return;
1390 } else if (OpC == PPC::RESTORE_CR) {
1391 lowerCRRestore(II, FrameIndex);
1392 return;
1393 } else if (OpC == PPC::SPILL_CRBIT) {
1394 lowerCRBitSpilling(II, FrameIndex);
1395 return;
1396 } else if (OpC == PPC::RESTORE_CRBIT) {
1397 lowerCRBitRestore(II, FrameIndex);
1398 return;
1399 } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) {
1400 lowerACCSpilling(II, FrameIndex);
1401 return;
1402 } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) {
1403 lowerACCRestore(II, FrameIndex);
1404 return;
1405 } else if (OpC == PPC::SPILL_QUADWORD) {
1406 lowerQuadwordSpilling(II, FrameIndex);
1407 return;
1408 } else if (OpC == PPC::RESTORE_QUADWORD) {
1409 lowerQuadwordRestore(II, FrameIndex);
1410 return;
1411 }
1412
1413 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1414 MI.getOperand(FIOperandNum).ChangeToRegister(
1415 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
1416
1417 // If the instruction is not present in ImmToIdxMap, then it has no immediate
1418 // form (and must be r+r).
1419 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1420 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
1421
1422 // Now add the frame object offset to the offset from r1.
1423 int Offset = MFI.getObjectOffset(FrameIndex);
1424 Offset += MI.getOperand(OffsetOperandNo).getImm();
1425
1426 // If we're not using a Frame Pointer that has been set to the value of the
1427 // SP before having the stack size subtracted from it, then add the stack size
1428 // to Offset to get the correct offset.
1429 // Naked functions have stack size 0, although getStackSize may not reflect
1430 // that because we didn't call all the pieces that compute it for naked
1431 // functions.
1432 if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1433 if (!(hasBasePointer(MF) && FrameIndex < 0))
1434 Offset += MFI.getStackSize();
1435 }
1436
1437 // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can
1438 // transform it to the prefixed version so we don't have to use the XForm.
1439 if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
1440 (!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1441 Subtarget.hasPrefixInstrs()) {
1442 unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
1443 MI.setDesc(TII.get(NewOpc));
1444 OpC = NewOpc;
1445 }
1446
1447 // If we can, encode the offset directly into the instruction. If this is a
1448 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
1449 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1450 // clear can be encoded. This is extremely uncommon, because normally you
1451 // only "std" to a stack slot that is at least 4-byte aligned, but it can
1452 // happen in invalid code.
1453 assert(OpC != PPC::DBG_VALUE &&
1454 "This should be handled in a target-independent way");
1455 // FIXME: This should be factored out to a separate function as prefixed
1456 // instructions add a number of opcodes for which we can use 34-bit imm.
1457 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1458 isUInt<8>(Offset) :
1459 isInt<16>(Offset);
1460 if (OpC == PPC::PLXVP || OpC == PPC::PSTXVP)
1461 OffsetFitsMnemonic = isInt<34>(Offset);
1462 if (!noImmForm && ((OffsetFitsMnemonic &&
1463 ((Offset % offsetMinAlign(MI)) == 0)) ||
1464 OpC == TargetOpcode::STACKMAP ||
1465 OpC == TargetOpcode::PATCHPOINT)) {
1466 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1467 return;
1468 }
1469
1470 // The offset doesn't fit into a single register, scavenge one to build the
1471 // offset in.
1472
1473 bool is64Bit = TM.isPPC64();
1474 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1475 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1476 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1477 Register SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1478 SReg = MF.getRegInfo().createVirtualRegister(RC);
1479
1480 // Insert a set of rA with the full offset value before the ld, st, or add
1481 if (isInt<16>(Offset))
1482 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1483 .addImm(Offset);
1484 else {
1485 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1486 .addImm(Offset >> 16);
1487 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1488 .addReg(SRegHi, RegState::Kill)
1489 .addImm(Offset);
1490 }
1491
1492 // Convert into indexed form of the instruction:
1493 //
1494 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1495 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1496 unsigned OperandBase;
1497
1498 if (noImmForm)
1499 OperandBase = 1;
1500 else if (OpC != TargetOpcode::INLINEASM &&
1501 OpC != TargetOpcode::INLINEASM_BR) {
1502 assert(ImmToIdxMap.count(OpC) &&
1503 "No indexed form of load or store available!");
1504 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1505 MI.setDesc(TII.get(NewOpcode));
1506 OperandBase = 1;
1507 } else {
1508 OperandBase = OffsetOperandNo;
1509 }
1510
1511 Register StackReg = MI.getOperand(FIOperandNum).getReg();
1512 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1513 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1514 }
1515
getFrameRegister(const MachineFunction & MF) const1516 Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1517 const PPCFrameLowering *TFI = getFrameLowering(MF);
1518
1519 if (!TM.isPPC64())
1520 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1521 else
1522 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1523 }
1524
getBaseRegister(const MachineFunction & MF) const1525 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1526 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1527 if (!hasBasePointer(MF))
1528 return getFrameRegister(MF);
1529
1530 if (TM.isPPC64())
1531 return PPC::X30;
1532
1533 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1534 return PPC::R29;
1535
1536 return PPC::R30;
1537 }
1538
hasBasePointer(const MachineFunction & MF) const1539 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1540 if (!EnableBasePointer)
1541 return false;
1542 if (AlwaysBasePointer)
1543 return true;
1544
1545 // If we need to realign the stack, then the stack pointer can no longer
1546 // serve as an offset into the caller's stack space. As a result, we need a
1547 // base pointer.
1548 return hasStackRealignment(MF);
1549 }
1550
1551 /// Returns true if the instruction's frame index
1552 /// reference would be better served by a base register other than FP
1553 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1554 /// references it should create new base registers for.
1555 bool PPCRegisterInfo::
needsFrameBaseReg(MachineInstr * MI,int64_t Offset) const1556 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1557 assert(Offset < 0 && "Local offset must be negative");
1558
1559 // It's the load/store FI references that cause issues, as it can be difficult
1560 // to materialize the offset if it won't fit in the literal field. Estimate
1561 // based on the size of the local frame and some conservative assumptions
1562 // about the rest of the stack frame (note, this is pre-regalloc, so
1563 // we don't know everything for certain yet) whether this offset is likely
1564 // to be out of range of the immediate. Return true if so.
1565
1566 // We only generate virtual base registers for loads and stores that have
1567 // an r+i form. Return false for everything else.
1568 unsigned OpC = MI->getOpcode();
1569 if (!ImmToIdxMap.count(OpC))
1570 return false;
1571
1572 // Don't generate a new virtual base register just to add zero to it.
1573 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1574 MI->getOperand(2).getImm() == 0)
1575 return false;
1576
1577 MachineBasicBlock &MBB = *MI->getParent();
1578 MachineFunction &MF = *MBB.getParent();
1579 const PPCFrameLowering *TFI = getFrameLowering(MF);
1580 unsigned StackEst = TFI->determineFrameLayout(MF, true);
1581
1582 // If we likely don't need a stack frame, then we probably don't need a
1583 // virtual base register either.
1584 if (!StackEst)
1585 return false;
1586
1587 // Estimate an offset from the stack pointer.
1588 // The incoming offset is relating to the SP at the start of the function,
1589 // but when we access the local it'll be relative to the SP after local
1590 // allocation, so adjust our SP-relative offset by that allocation size.
1591 Offset += StackEst;
1592
1593 // The frame pointer will point to the end of the stack, so estimate the
1594 // offset as the difference between the object offset and the FP location.
1595 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1596 }
1597
1598 /// Insert defining instruction(s) for BaseReg to
1599 /// be a pointer to FrameIdx at the beginning of the basic block.
materializeFrameBaseRegister(MachineBasicBlock * MBB,int FrameIdx,int64_t Offset) const1600 Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
1601 int FrameIdx,
1602 int64_t Offset) const {
1603 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1604
1605 MachineBasicBlock::iterator Ins = MBB->begin();
1606 DebugLoc DL; // Defaults to "unknown"
1607 if (Ins != MBB->end())
1608 DL = Ins->getDebugLoc();
1609
1610 const MachineFunction &MF = *MBB->getParent();
1611 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1612 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1613 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1614 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1615 const TargetRegisterClass *RC = getPointerRegClass(MF);
1616 Register BaseReg = MRI.createVirtualRegister(RC);
1617 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1618
1619 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1620 .addFrameIndex(FrameIdx).addImm(Offset);
1621
1622 return BaseReg;
1623 }
1624
resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const1625 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
1626 int64_t Offset) const {
1627 unsigned FIOperandNum = 0;
1628 while (!MI.getOperand(FIOperandNum).isFI()) {
1629 ++FIOperandNum;
1630 assert(FIOperandNum < MI.getNumOperands() &&
1631 "Instr doesn't have FrameIndex operand!");
1632 }
1633
1634 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1635 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1636 Offset += MI.getOperand(OffsetOperandNo).getImm();
1637 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1638
1639 MachineBasicBlock &MBB = *MI.getParent();
1640 MachineFunction &MF = *MBB.getParent();
1641 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1642 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1643 const MCInstrDesc &MCID = MI.getDesc();
1644 MachineRegisterInfo &MRI = MF.getRegInfo();
1645 MRI.constrainRegClass(BaseReg,
1646 TII.getRegClass(MCID, FIOperandNum, this, MF));
1647 }
1648
isFrameOffsetLegal(const MachineInstr * MI,Register BaseReg,int64_t Offset) const1649 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1650 Register BaseReg,
1651 int64_t Offset) const {
1652 unsigned FIOperandNum = 0;
1653 while (!MI->getOperand(FIOperandNum).isFI()) {
1654 ++FIOperandNum;
1655 assert(FIOperandNum < MI->getNumOperands() &&
1656 "Instr doesn't have FrameIndex operand!");
1657 }
1658
1659 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1660 Offset += MI->getOperand(OffsetOperandNo).getImm();
1661
1662 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1663 MI->getOpcode() == TargetOpcode::STACKMAP ||
1664 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1665 (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1666 }
1667