1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s 3 4; The mask is all-ones, potentially shifted. 5 6;------------------------------------------------------------------------------; 7; 8-bit 8;------------------------------------------------------------------------------; 9 10; lshr 11 12define i8 @test_i8_7_mask_lshr_1(i8 %a0) { 13; CHECK-LABEL: test_i8_7_mask_lshr_1: 14; CHECK: // %bb.0: 15; CHECK-NEXT: ubfx w0, w0, #1, #2 16; CHECK-NEXT: ret 17 %t0 = and i8 %a0, 7 18 %t1 = lshr i8 %t0, 1 19 ret i8 %t1 20} 21 22define i8 @test_i8_28_mask_lshr_1(i8 %a0) { 23; CHECK-LABEL: test_i8_28_mask_lshr_1: 24; CHECK: // %bb.0: 25; CHECK-NEXT: and w8, w0, #0x1c 26; CHECK-NEXT: lsr w0, w8, #1 27; CHECK-NEXT: ret 28 %t0 = and i8 %a0, 28 29 %t1 = lshr i8 %t0, 1 30 ret i8 %t1 31} 32define i8 @test_i8_28_mask_lshr_2(i8 %a0) { 33; CHECK-LABEL: test_i8_28_mask_lshr_2: 34; CHECK: // %bb.0: 35; CHECK-NEXT: ubfx w0, w0, #2, #3 36; CHECK-NEXT: ret 37 %t0 = and i8 %a0, 28 38 %t1 = lshr i8 %t0, 2 39 ret i8 %t1 40} 41define i8 @test_i8_28_mask_lshr_3(i8 %a0) { 42; CHECK-LABEL: test_i8_28_mask_lshr_3: 43; CHECK: // %bb.0: 44; CHECK-NEXT: ubfx w0, w0, #3, #2 45; CHECK-NEXT: ret 46 %t0 = and i8 %a0, 28 47 %t1 = lshr i8 %t0, 3 48 ret i8 %t1 49} 50define i8 @test_i8_28_mask_lshr_4(i8 %a0) { 51; CHECK-LABEL: test_i8_28_mask_lshr_4: 52; CHECK: // %bb.0: 53; CHECK-NEXT: ubfx w0, w0, #4, #1 54; CHECK-NEXT: ret 55 %t0 = and i8 %a0, 28 56 %t1 = lshr i8 %t0, 4 57 ret i8 %t1 58} 59 60define i8 @test_i8_224_mask_lshr_1(i8 %a0) { 61; CHECK-LABEL: test_i8_224_mask_lshr_1: 62; CHECK: // %bb.0: 63; CHECK-NEXT: and w8, w0, #0xe0 64; CHECK-NEXT: lsr w0, w8, #1 65; CHECK-NEXT: ret 66 %t0 = and i8 %a0, 224 67 %t1 = lshr i8 %t0, 1 68 ret i8 %t1 69} 70define i8 @test_i8_224_mask_lshr_4(i8 %a0) { 71; CHECK-LABEL: test_i8_224_mask_lshr_4: 72; CHECK: // %bb.0: 73; CHECK-NEXT: and w8, w0, #0xe0 74; CHECK-NEXT: lsr w0, w8, #4 75; CHECK-NEXT: ret 76 %t0 = and i8 %a0, 224 77 %t1 = lshr i8 %t0, 4 78 ret i8 %t1 79} 80define i8 @test_i8_224_mask_lshr_5(i8 %a0) { 81; CHECK-LABEL: test_i8_224_mask_lshr_5: 82; CHECK: // %bb.0: 83; CHECK-NEXT: ubfx w0, w0, #5, #3 84; CHECK-NEXT: ret 85 %t0 = and i8 %a0, 224 86 %t1 = lshr i8 %t0, 5 87 ret i8 %t1 88} 89define i8 @test_i8_224_mask_lshr_6(i8 %a0) { 90; CHECK-LABEL: test_i8_224_mask_lshr_6: 91; CHECK: // %bb.0: 92; CHECK-NEXT: ubfx w0, w0, #6, #2 93; CHECK-NEXT: ret 94 %t0 = and i8 %a0, 224 95 %t1 = lshr i8 %t0, 6 96 ret i8 %t1 97} 98 99; ashr 100 101define i8 @test_i8_7_mask_ashr_1(i8 %a0) { 102; CHECK-LABEL: test_i8_7_mask_ashr_1: 103; CHECK: // %bb.0: 104; CHECK-NEXT: ubfx w0, w0, #1, #2 105; CHECK-NEXT: ret 106 %t0 = and i8 %a0, 7 107 %t1 = ashr i8 %t0, 1 108 ret i8 %t1 109} 110 111define i8 @test_i8_28_mask_ashr_1(i8 %a0) { 112; CHECK-LABEL: test_i8_28_mask_ashr_1: 113; CHECK: // %bb.0: 114; CHECK-NEXT: and w8, w0, #0x1c 115; CHECK-NEXT: lsr w0, w8, #1 116; CHECK-NEXT: ret 117 %t0 = and i8 %a0, 28 118 %t1 = ashr i8 %t0, 1 119 ret i8 %t1 120} 121define i8 @test_i8_28_mask_ashr_2(i8 %a0) { 122; CHECK-LABEL: test_i8_28_mask_ashr_2: 123; CHECK: // %bb.0: 124; CHECK-NEXT: ubfx w0, w0, #2, #3 125; CHECK-NEXT: ret 126 %t0 = and i8 %a0, 28 127 %t1 = ashr i8 %t0, 2 128 ret i8 %t1 129} 130define i8 @test_i8_28_mask_ashr_3(i8 %a0) { 131; CHECK-LABEL: test_i8_28_mask_ashr_3: 132; CHECK: // %bb.0: 133; CHECK-NEXT: ubfx w0, w0, #3, #2 134; CHECK-NEXT: ret 135 %t0 = and i8 %a0, 28 136 %t1 = ashr i8 %t0, 3 137 ret i8 %t1 138} 139define i8 @test_i8_28_mask_ashr_4(i8 %a0) { 140; CHECK-LABEL: test_i8_28_mask_ashr_4: 141; CHECK: // %bb.0: 142; CHECK-NEXT: ubfx w0, w0, #4, #1 143; CHECK-NEXT: ret 144 %t0 = and i8 %a0, 28 145 %t1 = ashr i8 %t0, 4 146 ret i8 %t1 147} 148 149define i8 @test_i8_224_mask_ashr_1(i8 %a0) { 150; CHECK-LABEL: test_i8_224_mask_ashr_1: 151; CHECK: // %bb.0: 152; CHECK-NEXT: and w8, w0, #0xe0 153; CHECK-NEXT: sbfx w0, w8, #1, #7 154; CHECK-NEXT: ret 155 %t0 = and i8 %a0, 224 156 %t1 = ashr i8 %t0, 1 157 ret i8 %t1 158} 159define i8 @test_i8_224_mask_ashr_4(i8 %a0) { 160; CHECK-LABEL: test_i8_224_mask_ashr_4: 161; CHECK: // %bb.0: 162; CHECK-NEXT: and w8, w0, #0xe0 163; CHECK-NEXT: sbfx w0, w8, #4, #4 164; CHECK-NEXT: ret 165 %t0 = and i8 %a0, 224 166 %t1 = ashr i8 %t0, 4 167 ret i8 %t1 168} 169define i8 @test_i8_224_mask_ashr_5(i8 %a0) { 170; CHECK-LABEL: test_i8_224_mask_ashr_5: 171; CHECK: // %bb.0: 172; CHECK-NEXT: sbfx w0, w0, #5, #3 173; CHECK-NEXT: ret 174 %t0 = and i8 %a0, 224 175 %t1 = ashr i8 %t0, 5 176 ret i8 %t1 177} 178define i8 @test_i8_224_mask_ashr_6(i8 %a0) { 179; CHECK-LABEL: test_i8_224_mask_ashr_6: 180; CHECK: // %bb.0: 181; CHECK-NEXT: sbfx w0, w0, #6, #2 182; CHECK-NEXT: ret 183 %t0 = and i8 %a0, 224 184 %t1 = ashr i8 %t0, 6 185 ret i8 %t1 186} 187 188; shl 189 190define i8 @test_i8_7_mask_shl_1(i8 %a0) { 191; CHECK-LABEL: test_i8_7_mask_shl_1: 192; CHECK: // %bb.0: 193; CHECK-NEXT: and w8, w0, #0x7 194; CHECK-NEXT: lsl w0, w8, #1 195; CHECK-NEXT: ret 196 %t0 = and i8 %a0, 7 197 %t1 = shl i8 %t0, 1 198 ret i8 %t1 199} 200define i8 @test_i8_7_mask_shl_4(i8 %a0) { 201; CHECK-LABEL: test_i8_7_mask_shl_4: 202; CHECK: // %bb.0: 203; CHECK-NEXT: and w8, w0, #0x7 204; CHECK-NEXT: lsl w0, w8, #4 205; CHECK-NEXT: ret 206 %t0 = and i8 %a0, 7 207 %t1 = shl i8 %t0, 4 208 ret i8 %t1 209} 210define i8 @test_i8_7_mask_shl_5(i8 %a0) { 211; CHECK-LABEL: test_i8_7_mask_shl_5: 212; CHECK: // %bb.0: 213; CHECK-NEXT: lsl w0, w0, #5 214; CHECK-NEXT: ret 215 %t0 = and i8 %a0, 7 216 %t1 = shl i8 %t0, 5 217 ret i8 %t1 218} 219define i8 @test_i8_7_mask_shl_6(i8 %a0) { 220; CHECK-LABEL: test_i8_7_mask_shl_6: 221; CHECK: // %bb.0: 222; CHECK-NEXT: lsl w0, w0, #6 223; CHECK-NEXT: ret 224 %t0 = and i8 %a0, 7 225 %t1 = shl i8 %t0, 6 226 ret i8 %t1 227} 228 229define i8 @test_i8_28_mask_shl_1(i8 %a0) { 230; CHECK-LABEL: test_i8_28_mask_shl_1: 231; CHECK: // %bb.0: 232; CHECK-NEXT: and w8, w0, #0x1c 233; CHECK-NEXT: lsl w0, w8, #1 234; CHECK-NEXT: ret 235 %t0 = and i8 %a0, 28 236 %t1 = shl i8 %t0, 1 237 ret i8 %t1 238} 239define i8 @test_i8_28_mask_shl_2(i8 %a0) { 240; CHECK-LABEL: test_i8_28_mask_shl_2: 241; CHECK: // %bb.0: 242; CHECK-NEXT: and w8, w0, #0x1c 243; CHECK-NEXT: lsl w0, w8, #2 244; CHECK-NEXT: ret 245 %t0 = and i8 %a0, 28 246 %t1 = shl i8 %t0, 2 247 ret i8 %t1 248} 249define i8 @test_i8_28_mask_shl_3(i8 %a0) { 250; CHECK-LABEL: test_i8_28_mask_shl_3: 251; CHECK: // %bb.0: 252; CHECK-NEXT: and w8, w0, #0x1c 253; CHECK-NEXT: lsl w0, w8, #3 254; CHECK-NEXT: ret 255 %t0 = and i8 %a0, 28 256 %t1 = shl i8 %t0, 3 257 ret i8 %t1 258} 259define i8 @test_i8_28_mask_shl_4(i8 %a0) { 260; CHECK-LABEL: test_i8_28_mask_shl_4: 261; CHECK: // %bb.0: 262; CHECK-NEXT: and w8, w0, #0xc 263; CHECK-NEXT: lsl w0, w8, #4 264; CHECK-NEXT: ret 265 %t0 = and i8 %a0, 28 266 %t1 = shl i8 %t0, 4 267 ret i8 %t1 268} 269 270define i8 @test_i8_224_mask_shl_1(i8 %a0) { 271; CHECK-LABEL: test_i8_224_mask_shl_1: 272; CHECK: // %bb.0: 273; CHECK-NEXT: and w8, w0, #0x60 274; CHECK-NEXT: lsl w0, w8, #1 275; CHECK-NEXT: ret 276 %t0 = and i8 %a0, 224 277 %t1 = shl i8 %t0, 1 278 ret i8 %t1 279} 280 281;------------------------------------------------------------------------------; 282; 16-bit 283;------------------------------------------------------------------------------; 284 285; lshr 286 287define i16 @test_i16_127_mask_lshr_1(i16 %a0) { 288; CHECK-LABEL: test_i16_127_mask_lshr_1: 289; CHECK: // %bb.0: 290; CHECK-NEXT: ubfx w0, w0, #1, #6 291; CHECK-NEXT: ret 292 %t0 = and i16 %a0, 127 293 %t1 = lshr i16 %t0, 1 294 ret i16 %t1 295} 296 297define i16 @test_i16_2032_mask_lshr_3(i16 %a0) { 298; CHECK-LABEL: test_i16_2032_mask_lshr_3: 299; CHECK: // %bb.0: 300; CHECK-NEXT: and w8, w0, #0x7f0 301; CHECK-NEXT: lsr w0, w8, #3 302; CHECK-NEXT: ret 303 %t0 = and i16 %a0, 2032 304 %t1 = lshr i16 %t0, 3 305 ret i16 %t1 306} 307define i16 @test_i16_2032_mask_lshr_4(i16 %a0) { 308; CHECK-LABEL: test_i16_2032_mask_lshr_4: 309; CHECK: // %bb.0: 310; CHECK-NEXT: ubfx w0, w0, #4, #7 311; CHECK-NEXT: ret 312 %t0 = and i16 %a0, 2032 313 %t1 = lshr i16 %t0, 4 314 ret i16 %t1 315} 316define i16 @test_i16_2032_mask_lshr_5(i16 %a0) { 317; CHECK-LABEL: test_i16_2032_mask_lshr_5: 318; CHECK: // %bb.0: 319; CHECK-NEXT: ubfx w0, w0, #5, #6 320; CHECK-NEXT: ret 321 %t0 = and i16 %a0, 2032 322 %t1 = lshr i16 %t0, 5 323 ret i16 %t1 324} 325define i16 @test_i16_2032_mask_lshr_6(i16 %a0) { 326; CHECK-LABEL: test_i16_2032_mask_lshr_6: 327; CHECK: // %bb.0: 328; CHECK-NEXT: ubfx w0, w0, #6, #5 329; CHECK-NEXT: ret 330 %t0 = and i16 %a0, 2032 331 %t1 = lshr i16 %t0, 6 332 ret i16 %t1 333} 334 335define i16 @test_i16_65024_mask_lshr_1(i16 %a0) { 336; CHECK-LABEL: test_i16_65024_mask_lshr_1: 337; CHECK: // %bb.0: 338; CHECK-NEXT: and w8, w0, #0xfe00 339; CHECK-NEXT: lsr w0, w8, #1 340; CHECK-NEXT: ret 341 %t0 = and i16 %a0, 65024 342 %t1 = lshr i16 %t0, 1 343 ret i16 %t1 344} 345define i16 @test_i16_65024_mask_lshr_8(i16 %a0) { 346; CHECK-LABEL: test_i16_65024_mask_lshr_8: 347; CHECK: // %bb.0: 348; CHECK-NEXT: and w8, w0, #0xfe00 349; CHECK-NEXT: lsr w0, w8, #8 350; CHECK-NEXT: ret 351 %t0 = and i16 %a0, 65024 352 %t1 = lshr i16 %t0, 8 353 ret i16 %t1 354} 355define i16 @test_i16_65024_mask_lshr_9(i16 %a0) { 356; CHECK-LABEL: test_i16_65024_mask_lshr_9: 357; CHECK: // %bb.0: 358; CHECK-NEXT: ubfx w0, w0, #9, #7 359; CHECK-NEXT: ret 360 %t0 = and i16 %a0, 65024 361 %t1 = lshr i16 %t0, 9 362 ret i16 %t1 363} 364define i16 @test_i16_65024_mask_lshr_10(i16 %a0) { 365; CHECK-LABEL: test_i16_65024_mask_lshr_10: 366; CHECK: // %bb.0: 367; CHECK-NEXT: ubfx w0, w0, #10, #6 368; CHECK-NEXT: ret 369 %t0 = and i16 %a0, 65024 370 %t1 = lshr i16 %t0, 10 371 ret i16 %t1 372} 373 374; ashr 375 376define i16 @test_i16_127_mask_ashr_1(i16 %a0) { 377; CHECK-LABEL: test_i16_127_mask_ashr_1: 378; CHECK: // %bb.0: 379; CHECK-NEXT: ubfx w0, w0, #1, #6 380; CHECK-NEXT: ret 381 %t0 = and i16 %a0, 127 382 %t1 = ashr i16 %t0, 1 383 ret i16 %t1 384} 385 386define i16 @test_i16_2032_mask_ashr_3(i16 %a0) { 387; CHECK-LABEL: test_i16_2032_mask_ashr_3: 388; CHECK: // %bb.0: 389; CHECK-NEXT: and w8, w0, #0x7f0 390; CHECK-NEXT: lsr w0, w8, #3 391; CHECK-NEXT: ret 392 %t0 = and i16 %a0, 2032 393 %t1 = ashr i16 %t0, 3 394 ret i16 %t1 395} 396define i16 @test_i16_2032_mask_ashr_4(i16 %a0) { 397; CHECK-LABEL: test_i16_2032_mask_ashr_4: 398; CHECK: // %bb.0: 399; CHECK-NEXT: ubfx w0, w0, #4, #7 400; CHECK-NEXT: ret 401 %t0 = and i16 %a0, 2032 402 %t1 = ashr i16 %t0, 4 403 ret i16 %t1 404} 405define i16 @test_i16_2032_mask_ashr_5(i16 %a0) { 406; CHECK-LABEL: test_i16_2032_mask_ashr_5: 407; CHECK: // %bb.0: 408; CHECK-NEXT: ubfx w0, w0, #5, #6 409; CHECK-NEXT: ret 410 %t0 = and i16 %a0, 2032 411 %t1 = ashr i16 %t0, 5 412 ret i16 %t1 413} 414define i16 @test_i16_2032_mask_ashr_6(i16 %a0) { 415; CHECK-LABEL: test_i16_2032_mask_ashr_6: 416; CHECK: // %bb.0: 417; CHECK-NEXT: ubfx w0, w0, #6, #5 418; CHECK-NEXT: ret 419 %t0 = and i16 %a0, 2032 420 %t1 = ashr i16 %t0, 6 421 ret i16 %t1 422} 423 424define i16 @test_i16_65024_mask_ashr_1(i16 %a0) { 425; CHECK-LABEL: test_i16_65024_mask_ashr_1: 426; CHECK: // %bb.0: 427; CHECK-NEXT: and w8, w0, #0xfe00 428; CHECK-NEXT: sbfx w0, w8, #1, #15 429; CHECK-NEXT: ret 430 %t0 = and i16 %a0, 65024 431 %t1 = ashr i16 %t0, 1 432 ret i16 %t1 433} 434define i16 @test_i16_65024_mask_ashr_8(i16 %a0) { 435; CHECK-LABEL: test_i16_65024_mask_ashr_8: 436; CHECK: // %bb.0: 437; CHECK-NEXT: and w8, w0, #0xfe00 438; CHECK-NEXT: sbfx w0, w8, #8, #8 439; CHECK-NEXT: ret 440 %t0 = and i16 %a0, 65024 441 %t1 = ashr i16 %t0, 8 442 ret i16 %t1 443} 444define i16 @test_i16_65024_mask_ashr_9(i16 %a0) { 445; CHECK-LABEL: test_i16_65024_mask_ashr_9: 446; CHECK: // %bb.0: 447; CHECK-NEXT: sbfx w0, w0, #9, #7 448; CHECK-NEXT: ret 449 %t0 = and i16 %a0, 65024 450 %t1 = ashr i16 %t0, 9 451 ret i16 %t1 452} 453define i16 @test_i16_65024_mask_ashr_10(i16 %a0) { 454; CHECK-LABEL: test_i16_65024_mask_ashr_10: 455; CHECK: // %bb.0: 456; CHECK-NEXT: sbfx w0, w0, #10, #6 457; CHECK-NEXT: ret 458 %t0 = and i16 %a0, 65024 459 %t1 = ashr i16 %t0, 10 460 ret i16 %t1 461} 462 463; shl 464 465define i16 @test_i16_127_mask_shl_1(i16 %a0) { 466; CHECK-LABEL: test_i16_127_mask_shl_1: 467; CHECK: // %bb.0: 468; CHECK-NEXT: and w8, w0, #0x7f 469; CHECK-NEXT: lsl w0, w8, #1 470; CHECK-NEXT: ret 471 %t0 = and i16 %a0, 127 472 %t1 = shl i16 %t0, 1 473 ret i16 %t1 474} 475define i16 @test_i16_127_mask_shl_8(i16 %a0) { 476; CHECK-LABEL: test_i16_127_mask_shl_8: 477; CHECK: // %bb.0: 478; CHECK-NEXT: and w8, w0, #0x7f 479; CHECK-NEXT: lsl w0, w8, #8 480; CHECK-NEXT: ret 481 %t0 = and i16 %a0, 127 482 %t1 = shl i16 %t0, 8 483 ret i16 %t1 484} 485define i16 @test_i16_127_mask_shl_9(i16 %a0) { 486; CHECK-LABEL: test_i16_127_mask_shl_9: 487; CHECK: // %bb.0: 488; CHECK-NEXT: lsl w0, w0, #9 489; CHECK-NEXT: ret 490 %t0 = and i16 %a0, 127 491 %t1 = shl i16 %t0, 9 492 ret i16 %t1 493} 494define i16 @test_i16_127_mask_shl_10(i16 %a0) { 495; CHECK-LABEL: test_i16_127_mask_shl_10: 496; CHECK: // %bb.0: 497; CHECK-NEXT: lsl w0, w0, #10 498; CHECK-NEXT: ret 499 %t0 = and i16 %a0, 127 500 %t1 = shl i16 %t0, 10 501 ret i16 %t1 502} 503 504define i16 @test_i16_2032_mask_shl_3(i16 %a0) { 505; CHECK-LABEL: test_i16_2032_mask_shl_3: 506; CHECK: // %bb.0: 507; CHECK-NEXT: and w8, w0, #0x7f0 508; CHECK-NEXT: lsl w0, w8, #3 509; CHECK-NEXT: ret 510 %t0 = and i16 %a0, 2032 511 %t1 = shl i16 %t0, 3 512 ret i16 %t1 513} 514define i16 @test_i16_2032_mask_shl_4(i16 %a0) { 515; CHECK-LABEL: test_i16_2032_mask_shl_4: 516; CHECK: // %bb.0: 517; CHECK-NEXT: and w8, w0, #0x7f0 518; CHECK-NEXT: lsl w0, w8, #4 519; CHECK-NEXT: ret 520 %t0 = and i16 %a0, 2032 521 %t1 = shl i16 %t0, 4 522 ret i16 %t1 523} 524define i16 @test_i16_2032_mask_shl_5(i16 %a0) { 525; CHECK-LABEL: test_i16_2032_mask_shl_5: 526; CHECK: // %bb.0: 527; CHECK-NEXT: and w8, w0, #0x7f0 528; CHECK-NEXT: lsl w0, w8, #5 529; CHECK-NEXT: ret 530 %t0 = and i16 %a0, 2032 531 %t1 = shl i16 %t0, 5 532 ret i16 %t1 533} 534define i16 @test_i16_2032_mask_shl_6(i16 %a0) { 535; CHECK-LABEL: test_i16_2032_mask_shl_6: 536; CHECK: // %bb.0: 537; CHECK-NEXT: and w8, w0, #0x3f0 538; CHECK-NEXT: lsl w0, w8, #6 539; CHECK-NEXT: ret 540 %t0 = and i16 %a0, 2032 541 %t1 = shl i16 %t0, 6 542 ret i16 %t1 543} 544 545define i16 @test_i16_65024_mask_shl_1(i16 %a0) { 546; CHECK-LABEL: test_i16_65024_mask_shl_1: 547; CHECK: // %bb.0: 548; CHECK-NEXT: and w8, w0, #0x7e00 549; CHECK-NEXT: lsl w0, w8, #1 550; CHECK-NEXT: ret 551 %t0 = and i16 %a0, 65024 552 %t1 = shl i16 %t0, 1 553 ret i16 %t1 554} 555 556;------------------------------------------------------------------------------; 557; 32-bit 558;------------------------------------------------------------------------------; 559 560; lshr 561 562define i32 @test_i32_32767_mask_lshr_1(i32 %a0) { 563; CHECK-LABEL: test_i32_32767_mask_lshr_1: 564; CHECK: // %bb.0: 565; CHECK-NEXT: ubfx w0, w0, #1, #14 566; CHECK-NEXT: ret 567 %t0 = and i32 %a0, 32767 568 %t1 = lshr i32 %t0, 1 569 ret i32 %t1 570} 571 572define i32 @test_i32_8388352_mask_lshr_7(i32 %a0) { 573; CHECK-LABEL: test_i32_8388352_mask_lshr_7: 574; CHECK: // %bb.0: 575; CHECK-NEXT: and w8, w0, #0x7fff00 576; CHECK-NEXT: lsr w0, w8, #7 577; CHECK-NEXT: ret 578 %t0 = and i32 %a0, 8388352 579 %t1 = lshr i32 %t0, 7 580 ret i32 %t1 581} 582define i32 @test_i32_8388352_mask_lshr_8(i32 %a0) { 583; CHECK-LABEL: test_i32_8388352_mask_lshr_8: 584; CHECK: // %bb.0: 585; CHECK-NEXT: ubfx w0, w0, #8, #15 586; CHECK-NEXT: ret 587 %t0 = and i32 %a0, 8388352 588 %t1 = lshr i32 %t0, 8 589 ret i32 %t1 590} 591define i32 @test_i32_8388352_mask_lshr_9(i32 %a0) { 592; CHECK-LABEL: test_i32_8388352_mask_lshr_9: 593; CHECK: // %bb.0: 594; CHECK-NEXT: ubfx w0, w0, #9, #14 595; CHECK-NEXT: ret 596 %t0 = and i32 %a0, 8388352 597 %t1 = lshr i32 %t0, 9 598 ret i32 %t1 599} 600define i32 @test_i32_8388352_mask_lshr_10(i32 %a0) { 601; CHECK-LABEL: test_i32_8388352_mask_lshr_10: 602; CHECK: // %bb.0: 603; CHECK-NEXT: ubfx w0, w0, #10, #13 604; CHECK-NEXT: ret 605 %t0 = and i32 %a0, 8388352 606 %t1 = lshr i32 %t0, 10 607 ret i32 %t1 608} 609 610define i32 @test_i32_4294836224_mask_lshr_1(i32 %a0) { 611; CHECK-LABEL: test_i32_4294836224_mask_lshr_1: 612; CHECK: // %bb.0: 613; CHECK-NEXT: and w8, w0, #0xfffe0000 614; CHECK-NEXT: lsr w0, w8, #1 615; CHECK-NEXT: ret 616 %t0 = and i32 %a0, 4294836224 617 %t1 = lshr i32 %t0, 1 618 ret i32 %t1 619} 620define i32 @test_i32_4294836224_mask_lshr_16(i32 %a0) { 621; CHECK-LABEL: test_i32_4294836224_mask_lshr_16: 622; CHECK: // %bb.0: 623; CHECK-NEXT: and w8, w0, #0xfffe0000 624; CHECK-NEXT: lsr w0, w8, #16 625; CHECK-NEXT: ret 626 %t0 = and i32 %a0, 4294836224 627 %t1 = lshr i32 %t0, 16 628 ret i32 %t1 629} 630define i32 @test_i32_4294836224_mask_lshr_17(i32 %a0) { 631; CHECK-LABEL: test_i32_4294836224_mask_lshr_17: 632; CHECK: // %bb.0: 633; CHECK-NEXT: lsr w0, w0, #17 634; CHECK-NEXT: ret 635 %t0 = and i32 %a0, 4294836224 636 %t1 = lshr i32 %t0, 17 637 ret i32 %t1 638} 639define i32 @test_i32_4294836224_mask_lshr_18(i32 %a0) { 640; CHECK-LABEL: test_i32_4294836224_mask_lshr_18: 641; CHECK: // %bb.0: 642; CHECK-NEXT: lsr w0, w0, #18 643; CHECK-NEXT: ret 644 %t0 = and i32 %a0, 4294836224 645 %t1 = lshr i32 %t0, 18 646 ret i32 %t1 647} 648 649; ashr 650 651define i32 @test_i32_32767_mask_ashr_1(i32 %a0) { 652; CHECK-LABEL: test_i32_32767_mask_ashr_1: 653; CHECK: // %bb.0: 654; CHECK-NEXT: ubfx w0, w0, #1, #14 655; CHECK-NEXT: ret 656 %t0 = and i32 %a0, 32767 657 %t1 = ashr i32 %t0, 1 658 ret i32 %t1 659} 660 661define i32 @test_i32_8388352_mask_ashr_7(i32 %a0) { 662; CHECK-LABEL: test_i32_8388352_mask_ashr_7: 663; CHECK: // %bb.0: 664; CHECK-NEXT: and w8, w0, #0x7fff00 665; CHECK-NEXT: lsr w0, w8, #7 666; CHECK-NEXT: ret 667 %t0 = and i32 %a0, 8388352 668 %t1 = ashr i32 %t0, 7 669 ret i32 %t1 670} 671define i32 @test_i32_8388352_mask_ashr_8(i32 %a0) { 672; CHECK-LABEL: test_i32_8388352_mask_ashr_8: 673; CHECK: // %bb.0: 674; CHECK-NEXT: ubfx w0, w0, #8, #15 675; CHECK-NEXT: ret 676 %t0 = and i32 %a0, 8388352 677 %t1 = ashr i32 %t0, 8 678 ret i32 %t1 679} 680define i32 @test_i32_8388352_mask_ashr_9(i32 %a0) { 681; CHECK-LABEL: test_i32_8388352_mask_ashr_9: 682; CHECK: // %bb.0: 683; CHECK-NEXT: ubfx w0, w0, #9, #14 684; CHECK-NEXT: ret 685 %t0 = and i32 %a0, 8388352 686 %t1 = ashr i32 %t0, 9 687 ret i32 %t1 688} 689define i32 @test_i32_8388352_mask_ashr_10(i32 %a0) { 690; CHECK-LABEL: test_i32_8388352_mask_ashr_10: 691; CHECK: // %bb.0: 692; CHECK-NEXT: ubfx w0, w0, #10, #13 693; CHECK-NEXT: ret 694 %t0 = and i32 %a0, 8388352 695 %t1 = ashr i32 %t0, 10 696 ret i32 %t1 697} 698 699define i32 @test_i32_4294836224_mask_ashr_1(i32 %a0) { 700; CHECK-LABEL: test_i32_4294836224_mask_ashr_1: 701; CHECK: // %bb.0: 702; CHECK-NEXT: and w8, w0, #0xfffe0000 703; CHECK-NEXT: asr w0, w8, #1 704; CHECK-NEXT: ret 705 %t0 = and i32 %a0, 4294836224 706 %t1 = ashr i32 %t0, 1 707 ret i32 %t1 708} 709define i32 @test_i32_4294836224_mask_ashr_16(i32 %a0) { 710; CHECK-LABEL: test_i32_4294836224_mask_ashr_16: 711; CHECK: // %bb.0: 712; CHECK-NEXT: and w8, w0, #0xfffe0000 713; CHECK-NEXT: asr w0, w8, #16 714; CHECK-NEXT: ret 715 %t0 = and i32 %a0, 4294836224 716 %t1 = ashr i32 %t0, 16 717 ret i32 %t1 718} 719define i32 @test_i32_4294836224_mask_ashr_17(i32 %a0) { 720; CHECK-LABEL: test_i32_4294836224_mask_ashr_17: 721; CHECK: // %bb.0: 722; CHECK-NEXT: asr w0, w0, #17 723; CHECK-NEXT: ret 724 %t0 = and i32 %a0, 4294836224 725 %t1 = ashr i32 %t0, 17 726 ret i32 %t1 727} 728define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) { 729; CHECK-LABEL: test_i32_4294836224_mask_ashr_18: 730; CHECK: // %bb.0: 731; CHECK-NEXT: asr w0, w0, #18 732; CHECK-NEXT: ret 733 %t0 = and i32 %a0, 4294836224 734 %t1 = ashr i32 %t0, 18 735 ret i32 %t1 736} 737 738; shl 739 740define i32 @test_i32_32767_mask_shl_1(i32 %a0) { 741; CHECK-LABEL: test_i32_32767_mask_shl_1: 742; CHECK: // %bb.0: 743; CHECK-NEXT: and w8, w0, #0x7fff 744; CHECK-NEXT: lsl w0, w8, #1 745; CHECK-NEXT: ret 746 %t0 = and i32 %a0, 32767 747 %t1 = shl i32 %t0, 1 748 ret i32 %t1 749} 750define i32 @test_i32_32767_mask_shl_16(i32 %a0) { 751; CHECK-LABEL: test_i32_32767_mask_shl_16: 752; CHECK: // %bb.0: 753; CHECK-NEXT: and w8, w0, #0x7fff 754; CHECK-NEXT: lsl w0, w8, #16 755; CHECK-NEXT: ret 756 %t0 = and i32 %a0, 32767 757 %t1 = shl i32 %t0, 16 758 ret i32 %t1 759} 760define i32 @test_i32_32767_mask_shl_17(i32 %a0) { 761; CHECK-LABEL: test_i32_32767_mask_shl_17: 762; CHECK: // %bb.0: 763; CHECK-NEXT: lsl w0, w0, #17 764; CHECK-NEXT: ret 765 %t0 = and i32 %a0, 32767 766 %t1 = shl i32 %t0, 17 767 ret i32 %t1 768} 769define i32 @test_i32_32767_mask_shl_18(i32 %a0) { 770; CHECK-LABEL: test_i32_32767_mask_shl_18: 771; CHECK: // %bb.0: 772; CHECK-NEXT: lsl w0, w0, #18 773; CHECK-NEXT: ret 774 %t0 = and i32 %a0, 32767 775 %t1 = shl i32 %t0, 18 776 ret i32 %t1 777} 778 779define i32 @test_i32_8388352_mask_shl_7(i32 %a0) { 780; CHECK-LABEL: test_i32_8388352_mask_shl_7: 781; CHECK: // %bb.0: 782; CHECK-NEXT: and w8, w0, #0x7fff00 783; CHECK-NEXT: lsl w0, w8, #7 784; CHECK-NEXT: ret 785 %t0 = and i32 %a0, 8388352 786 %t1 = shl i32 %t0, 7 787 ret i32 %t1 788} 789define i32 @test_i32_8388352_mask_shl_8(i32 %a0) { 790; CHECK-LABEL: test_i32_8388352_mask_shl_8: 791; CHECK: // %bb.0: 792; CHECK-NEXT: and w8, w0, #0x7fff00 793; CHECK-NEXT: lsl w0, w8, #8 794; CHECK-NEXT: ret 795 %t0 = and i32 %a0, 8388352 796 %t1 = shl i32 %t0, 8 797 ret i32 %t1 798} 799define i32 @test_i32_8388352_mask_shl_9(i32 %a0) { 800; CHECK-LABEL: test_i32_8388352_mask_shl_9: 801; CHECK: // %bb.0: 802; CHECK-NEXT: and w8, w0, #0x7fff00 803; CHECK-NEXT: lsl w0, w8, #9 804; CHECK-NEXT: ret 805 %t0 = and i32 %a0, 8388352 806 %t1 = shl i32 %t0, 9 807 ret i32 %t1 808} 809define i32 @test_i32_8388352_mask_shl_10(i32 %a0) { 810; CHECK-LABEL: test_i32_8388352_mask_shl_10: 811; CHECK: // %bb.0: 812; CHECK-NEXT: and w8, w0, #0x3fff00 813; CHECK-NEXT: lsl w0, w8, #10 814; CHECK-NEXT: ret 815 %t0 = and i32 %a0, 8388352 816 %t1 = shl i32 %t0, 10 817 ret i32 %t1 818} 819 820define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) { 821; CHECK-LABEL: test_i32_4294836224_mask_shl_1: 822; CHECK: // %bb.0: 823; CHECK-NEXT: and w8, w0, #0x7ffe0000 824; CHECK-NEXT: lsl w0, w8, #1 825; CHECK-NEXT: ret 826 %t0 = and i32 %a0, 4294836224 827 %t1 = shl i32 %t0, 1 828 ret i32 %t1 829} 830 831;------------------------------------------------------------------------------; 832; 64-bit 833;------------------------------------------------------------------------------; 834 835; lshr 836 837define i64 @test_i64_2147483647_mask_lshr_1(i64 %a0) { 838; CHECK-LABEL: test_i64_2147483647_mask_lshr_1: 839; CHECK: // %bb.0: 840; CHECK-NEXT: ubfx x0, x0, #1, #30 841; CHECK-NEXT: ret 842 %t0 = and i64 %a0, 2147483647 843 %t1 = lshr i64 %t0, 1 844 ret i64 %t1 845} 846 847define i64 @test_i64_140737488289792_mask_lshr_15(i64 %a0) { 848; CHECK-LABEL: test_i64_140737488289792_mask_lshr_15: 849; CHECK: // %bb.0: 850; CHECK-NEXT: and x8, x0, #0x7fffffff0000 851; CHECK-NEXT: lsr x0, x8, #15 852; CHECK-NEXT: ret 853 %t0 = and i64 %a0, 140737488289792 854 %t1 = lshr i64 %t0, 15 855 ret i64 %t1 856} 857define i64 @test_i64_140737488289792_mask_lshr_16(i64 %a0) { 858; CHECK-LABEL: test_i64_140737488289792_mask_lshr_16: 859; CHECK: // %bb.0: 860; CHECK-NEXT: ubfx x0, x0, #16, #31 861; CHECK-NEXT: ret 862 %t0 = and i64 %a0, 140737488289792 863 %t1 = lshr i64 %t0, 16 864 ret i64 %t1 865} 866define i64 @test_i64_140737488289792_mask_lshr_17(i64 %a0) { 867; CHECK-LABEL: test_i64_140737488289792_mask_lshr_17: 868; CHECK: // %bb.0: 869; CHECK-NEXT: ubfx x0, x0, #17, #30 870; CHECK-NEXT: ret 871 %t0 = and i64 %a0, 140737488289792 872 %t1 = lshr i64 %t0, 17 873 ret i64 %t1 874} 875define i64 @test_i64_140737488289792_mask_lshr_18(i64 %a0) { 876; CHECK-LABEL: test_i64_140737488289792_mask_lshr_18: 877; CHECK: // %bb.0: 878; CHECK-NEXT: ubfx x0, x0, #18, #29 879; CHECK-NEXT: ret 880 %t0 = and i64 %a0, 140737488289792 881 %t1 = lshr i64 %t0, 18 882 ret i64 %t1 883} 884 885define i64 @test_i64_18446744065119617024_mask_lshr_1(i64 %a0) { 886; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_1: 887; CHECK: // %bb.0: 888; CHECK-NEXT: and x8, x0, #0xfffffffe00000000 889; CHECK-NEXT: lsr x0, x8, #1 890; CHECK-NEXT: ret 891 %t0 = and i64 %a0, 18446744065119617024 892 %t1 = lshr i64 %t0, 1 893 ret i64 %t1 894} 895define i64 @test_i64_18446744065119617024_mask_lshr_32(i64 %a0) { 896; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_32: 897; CHECK: // %bb.0: 898; CHECK-NEXT: and x8, x0, #0xfffffffe00000000 899; CHECK-NEXT: lsr x0, x8, #32 900; CHECK-NEXT: ret 901 %t0 = and i64 %a0, 18446744065119617024 902 %t1 = lshr i64 %t0, 32 903 ret i64 %t1 904} 905define i64 @test_i64_18446744065119617024_mask_lshr_33(i64 %a0) { 906; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_33: 907; CHECK: // %bb.0: 908; CHECK-NEXT: lsr x0, x0, #33 909; CHECK-NEXT: ret 910 %t0 = and i64 %a0, 18446744065119617024 911 %t1 = lshr i64 %t0, 33 912 ret i64 %t1 913} 914define i64 @test_i64_18446744065119617024_mask_lshr_34(i64 %a0) { 915; CHECK-LABEL: test_i64_18446744065119617024_mask_lshr_34: 916; CHECK: // %bb.0: 917; CHECK-NEXT: lsr x0, x0, #34 918; CHECK-NEXT: ret 919 %t0 = and i64 %a0, 18446744065119617024 920 %t1 = lshr i64 %t0, 34 921 ret i64 %t1 922} 923 924; ashr 925 926define i64 @test_i64_2147483647_mask_ashr_1(i64 %a0) { 927; CHECK-LABEL: test_i64_2147483647_mask_ashr_1: 928; CHECK: // %bb.0: 929; CHECK-NEXT: ubfx x0, x0, #1, #30 930; CHECK-NEXT: ret 931 %t0 = and i64 %a0, 2147483647 932 %t1 = ashr i64 %t0, 1 933 ret i64 %t1 934} 935 936define i64 @test_i64_140737488289792_mask_ashr_15(i64 %a0) { 937; CHECK-LABEL: test_i64_140737488289792_mask_ashr_15: 938; CHECK: // %bb.0: 939; CHECK-NEXT: and x8, x0, #0x7fffffff0000 940; CHECK-NEXT: lsr x0, x8, #15 941; CHECK-NEXT: ret 942 %t0 = and i64 %a0, 140737488289792 943 %t1 = ashr i64 %t0, 15 944 ret i64 %t1 945} 946define i64 @test_i64_140737488289792_mask_ashr_16(i64 %a0) { 947; CHECK-LABEL: test_i64_140737488289792_mask_ashr_16: 948; CHECK: // %bb.0: 949; CHECK-NEXT: ubfx x0, x0, #16, #31 950; CHECK-NEXT: ret 951 %t0 = and i64 %a0, 140737488289792 952 %t1 = ashr i64 %t0, 16 953 ret i64 %t1 954} 955define i64 @test_i64_140737488289792_mask_ashr_17(i64 %a0) { 956; CHECK-LABEL: test_i64_140737488289792_mask_ashr_17: 957; CHECK: // %bb.0: 958; CHECK-NEXT: ubfx x0, x0, #17, #30 959; CHECK-NEXT: ret 960 %t0 = and i64 %a0, 140737488289792 961 %t1 = ashr i64 %t0, 17 962 ret i64 %t1 963} 964define i64 @test_i64_140737488289792_mask_ashr_18(i64 %a0) { 965; CHECK-LABEL: test_i64_140737488289792_mask_ashr_18: 966; CHECK: // %bb.0: 967; CHECK-NEXT: ubfx x0, x0, #18, #29 968; CHECK-NEXT: ret 969 %t0 = and i64 %a0, 140737488289792 970 %t1 = ashr i64 %t0, 18 971 ret i64 %t1 972} 973 974define i64 @test_i64_18446744065119617024_mask_ashr_1(i64 %a0) { 975; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_1: 976; CHECK: // %bb.0: 977; CHECK-NEXT: and x8, x0, #0xfffffffe00000000 978; CHECK-NEXT: asr x0, x8, #1 979; CHECK-NEXT: ret 980 %t0 = and i64 %a0, 18446744065119617024 981 %t1 = ashr i64 %t0, 1 982 ret i64 %t1 983} 984define i64 @test_i64_18446744065119617024_mask_ashr_32(i64 %a0) { 985; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_32: 986; CHECK: // %bb.0: 987; CHECK-NEXT: and x8, x0, #0xfffffffe00000000 988; CHECK-NEXT: asr x0, x8, #32 989; CHECK-NEXT: ret 990 %t0 = and i64 %a0, 18446744065119617024 991 %t1 = ashr i64 %t0, 32 992 ret i64 %t1 993} 994define i64 @test_i64_18446744065119617024_mask_ashr_33(i64 %a0) { 995; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_33: 996; CHECK: // %bb.0: 997; CHECK-NEXT: asr x0, x0, #33 998; CHECK-NEXT: ret 999 %t0 = and i64 %a0, 18446744065119617024 1000 %t1 = ashr i64 %t0, 33 1001 ret i64 %t1 1002} 1003define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) { 1004; CHECK-LABEL: test_i64_18446744065119617024_mask_ashr_34: 1005; CHECK: // %bb.0: 1006; CHECK-NEXT: asr x0, x0, #34 1007; CHECK-NEXT: ret 1008 %t0 = and i64 %a0, 18446744065119617024 1009 %t1 = ashr i64 %t0, 34 1010 ret i64 %t1 1011} 1012 1013; shl 1014 1015define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) { 1016; CHECK-LABEL: test_i64_2147483647_mask_shl_1: 1017; CHECK: // %bb.0: 1018; CHECK-NEXT: and x8, x0, #0x7fffffff 1019; CHECK-NEXT: lsl x0, x8, #1 1020; CHECK-NEXT: ret 1021 %t0 = and i64 %a0, 2147483647 1022 %t1 = shl i64 %t0, 1 1023 ret i64 %t1 1024} 1025define i64 @test_i64_2147483647_mask_shl_32(i64 %a0) { 1026; CHECK-LABEL: test_i64_2147483647_mask_shl_32: 1027; CHECK: // %bb.0: 1028; CHECK-NEXT: and w8, w0, #0x7fffffff 1029; CHECK-NEXT: lsl x0, x8, #32 1030; CHECK-NEXT: ret 1031 %t0 = and i64 %a0, 2147483647 1032 %t1 = shl i64 %t0, 32 1033 ret i64 %t1 1034} 1035define i64 @test_i64_2147483647_mask_shl_33(i64 %a0) { 1036; CHECK-LABEL: test_i64_2147483647_mask_shl_33: 1037; CHECK: // %bb.0: 1038; CHECK-NEXT: lsl x0, x0, #33 1039; CHECK-NEXT: ret 1040 %t0 = and i64 %a0, 2147483647 1041 %t1 = shl i64 %t0, 33 1042 ret i64 %t1 1043} 1044define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) { 1045; CHECK-LABEL: test_i64_2147483647_mask_shl_34: 1046; CHECK: // %bb.0: 1047; CHECK-NEXT: lsl x0, x0, #34 1048; CHECK-NEXT: ret 1049 %t0 = and i64 %a0, 2147483647 1050 %t1 = shl i64 %t0, 34 1051 ret i64 %t1 1052} 1053 1054define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) { 1055; CHECK-LABEL: test_i64_140737488289792_mask_shl_15: 1056; CHECK: // %bb.0: 1057; CHECK-NEXT: and x8, x0, #0x7fffffff0000 1058; CHECK-NEXT: lsl x0, x8, #15 1059; CHECK-NEXT: ret 1060 %t0 = and i64 %a0, 140737488289792 1061 %t1 = shl i64 %t0, 15 1062 ret i64 %t1 1063} 1064define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) { 1065; CHECK-LABEL: test_i64_140737488289792_mask_shl_16: 1066; CHECK: // %bb.0: 1067; CHECK-NEXT: and x8, x0, #0x7fffffff0000 1068; CHECK-NEXT: lsl x0, x8, #16 1069; CHECK-NEXT: ret 1070 %t0 = and i64 %a0, 140737488289792 1071 %t1 = shl i64 %t0, 16 1072 ret i64 %t1 1073} 1074define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) { 1075; CHECK-LABEL: test_i64_140737488289792_mask_shl_17: 1076; CHECK: // %bb.0: 1077; CHECK-NEXT: and x8, x0, #0x7fffffff0000 1078; CHECK-NEXT: lsl x0, x8, #17 1079; CHECK-NEXT: ret 1080 %t0 = and i64 %a0, 140737488289792 1081 %t1 = shl i64 %t0, 17 1082 ret i64 %t1 1083} 1084define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) { 1085; CHECK-LABEL: test_i64_140737488289792_mask_shl_18: 1086; CHECK: // %bb.0: 1087; CHECK-NEXT: and x8, x0, #0x3fffffff0000 1088; CHECK-NEXT: lsl x0, x8, #18 1089; CHECK-NEXT: ret 1090 %t0 = and i64 %a0, 140737488289792 1091 %t1 = shl i64 %t0, 18 1092 ret i64 %t1 1093} 1094 1095define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) { 1096; CHECK-LABEL: test_i64_18446744065119617024_mask_shl_1: 1097; CHECK: // %bb.0: 1098; CHECK-NEXT: and x8, x0, #0x7ffffffe00000000 1099; CHECK-NEXT: lsl x0, x8, #1 1100; CHECK-NEXT: ret 1101 %t0 = and i64 %a0, 18446744065119617024 1102 %t1 = shl i64 %t0, 1 1103 ret i64 %t1 1104} 1105