1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3--- |
4
5  define void @mul_i32() {entry: ret void}
6  define void @mul_i8_sext() {entry: ret void}
7  define void @mul_i8_zext() {entry: ret void}
8  define void @mul_i8_aext() {entry: ret void}
9  define void @mul_i16_sext() {entry: ret void}
10  define void @mul_i16_zext() {entry: ret void}
11  define void @mul_i16_aext() {entry: ret void}
12  define void @mul_i64() {entry: ret void}
13  define void @mul_i128() {entry: ret void}
14  define void @umulh_i64() {entry: ret void}
15  define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
16
17...
18---
19name:            mul_i32
20alignment:       4
21tracksRegLiveness: true
22body:             |
23  bb.0.entry:
24    liveins: $a0, $a1
25
26    ; MIPS32-LABEL: name: mul_i32
27    ; MIPS32: liveins: $a0, $a1
28    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
29    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
30    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
31    ; MIPS32: $v0 = COPY [[MUL]](s32)
32    ; MIPS32: RetRA implicit $v0
33    %0:_(s32) = COPY $a0
34    %1:_(s32) = COPY $a1
35    %2:_(s32) = G_MUL %0, %1
36    $v0 = COPY %2(s32)
37    RetRA implicit $v0
38
39...
40---
41name:            mul_i8_sext
42alignment:       4
43tracksRegLiveness: true
44body:             |
45  bb.1.entry:
46    liveins: $a0, $a1
47
48    ; MIPS32-LABEL: name: mul_i8_sext
49    ; MIPS32: liveins: $a0, $a1
50    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
51    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
52    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
53    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
54    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
55    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
56    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
57    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
58    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
59    ; MIPS32: $v0 = COPY [[ASHR]](s32)
60    ; MIPS32: RetRA implicit $v0
61    %2:_(s32) = COPY $a0
62    %0:_(s8) = G_TRUNC %2(s32)
63    %3:_(s32) = COPY $a1
64    %1:_(s8) = G_TRUNC %3(s32)
65    %4:_(s8) = G_MUL %1, %0
66    %5:_(s32) = G_SEXT %4(s8)
67    $v0 = COPY %5(s32)
68    RetRA implicit $v0
69
70...
71---
72name:            mul_i8_zext
73alignment:       4
74tracksRegLiveness: true
75body:             |
76  bb.1.entry:
77    liveins: $a0, $a1
78
79    ; MIPS32-LABEL: name: mul_i8_zext
80    ; MIPS32: liveins: $a0, $a1
81    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
82    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
83    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
84    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
85    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
86    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
87    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
88    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
89    ; MIPS32: $v0 = COPY [[AND]](s32)
90    ; MIPS32: RetRA implicit $v0
91    %2:_(s32) = COPY $a0
92    %0:_(s8) = G_TRUNC %2(s32)
93    %3:_(s32) = COPY $a1
94    %1:_(s8) = G_TRUNC %3(s32)
95    %4:_(s8) = G_MUL %1, %0
96    %5:_(s32) = G_ZEXT %4(s8)
97    $v0 = COPY %5(s32)
98    RetRA implicit $v0
99
100...
101---
102name:            mul_i8_aext
103alignment:       4
104tracksRegLiveness: true
105body:             |
106  bb.1.entry:
107    liveins: $a0, $a1
108
109    ; MIPS32-LABEL: name: mul_i8_aext
110    ; MIPS32: liveins: $a0, $a1
111    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
112    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
113    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
114    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
115    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
116    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
117    ; MIPS32: $v0 = COPY [[COPY4]](s32)
118    ; MIPS32: RetRA implicit $v0
119    %2:_(s32) = COPY $a0
120    %0:_(s8) = G_TRUNC %2(s32)
121    %3:_(s32) = COPY $a1
122    %1:_(s8) = G_TRUNC %3(s32)
123    %4:_(s8) = G_MUL %1, %0
124    %5:_(s32) = G_ANYEXT %4(s8)
125    $v0 = COPY %5(s32)
126    RetRA implicit $v0
127
128...
129---
130name:            mul_i16_sext
131alignment:       4
132tracksRegLiveness: true
133body:             |
134  bb.1.entry:
135    liveins: $a0, $a1
136
137    ; MIPS32-LABEL: name: mul_i16_sext
138    ; MIPS32: liveins: $a0, $a1
139    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
140    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
141    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
142    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
143    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
144    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
145    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
146    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
147    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
148    ; MIPS32: $v0 = COPY [[ASHR]](s32)
149    ; MIPS32: RetRA implicit $v0
150    %2:_(s32) = COPY $a0
151    %0:_(s16) = G_TRUNC %2(s32)
152    %3:_(s32) = COPY $a1
153    %1:_(s16) = G_TRUNC %3(s32)
154    %4:_(s16) = G_MUL %1, %0
155    %5:_(s32) = G_SEXT %4(s16)
156    $v0 = COPY %5(s32)
157    RetRA implicit $v0
158
159...
160---
161name:            mul_i16_zext
162alignment:       4
163tracksRegLiveness: true
164body:             |
165  bb.1.entry:
166    liveins: $a0, $a1
167
168    ; MIPS32-LABEL: name: mul_i16_zext
169    ; MIPS32: liveins: $a0, $a1
170    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
171    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
172    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
173    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
174    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
175    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
176    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
177    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
178    ; MIPS32: $v0 = COPY [[AND]](s32)
179    ; MIPS32: RetRA implicit $v0
180    %2:_(s32) = COPY $a0
181    %0:_(s16) = G_TRUNC %2(s32)
182    %3:_(s32) = COPY $a1
183    %1:_(s16) = G_TRUNC %3(s32)
184    %4:_(s16) = G_MUL %1, %0
185    %5:_(s32) = G_ZEXT %4(s16)
186    $v0 = COPY %5(s32)
187    RetRA implicit $v0
188
189...
190---
191name:            mul_i16_aext
192alignment:       4
193tracksRegLiveness: true
194body:             |
195  bb.1.entry:
196    liveins: $a0, $a1
197
198    ; MIPS32-LABEL: name: mul_i16_aext
199    ; MIPS32: liveins: $a0, $a1
200    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
201    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
202    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
203    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
204    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
205    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
206    ; MIPS32: $v0 = COPY [[COPY4]](s32)
207    ; MIPS32: RetRA implicit $v0
208    %2:_(s32) = COPY $a0
209    %0:_(s16) = G_TRUNC %2(s32)
210    %3:_(s32) = COPY $a1
211    %1:_(s16) = G_TRUNC %3(s32)
212    %4:_(s16) = G_MUL %1, %0
213    %5:_(s32) = G_ANYEXT %4(s16)
214    $v0 = COPY %5(s32)
215    RetRA implicit $v0
216
217...
218---
219name:            mul_i64
220alignment:       4
221tracksRegLiveness: true
222body:             |
223  bb.1.entry:
224    liveins: $a0, $a1, $a2, $a3
225
226    ; MIPS32-LABEL: name: mul_i64
227    ; MIPS32: liveins: $a0, $a1, $a2, $a3
228    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
229    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
230    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
231    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
232    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY]]
233    ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
234    ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
235    ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
236    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
237    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
238    ; MIPS32: $v0 = COPY [[MUL]](s32)
239    ; MIPS32: $v1 = COPY [[ADD1]](s32)
240    ; MIPS32: RetRA implicit $v0, implicit $v1
241    %2:_(s32) = COPY $a0
242    %3:_(s32) = COPY $a1
243    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
244    %4:_(s32) = COPY $a2
245    %5:_(s32) = COPY $a3
246    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
247    %6:_(s64) = G_MUL %1, %0
248    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
249    $v0 = COPY %7(s32)
250    $v1 = COPY %8(s32)
251    RetRA implicit $v0, implicit $v1
252
253...
254---
255name:            mul_i128
256alignment:       4
257tracksRegLiveness: true
258fixedStack:
259  - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true }
260  - { id: 1, offset: 24, size: 4, alignment: 8, stack-id: default, isImmutable: true }
261  - { id: 2, offset: 20, size: 4, alignment: 4, stack-id: default, isImmutable: true }
262  - { id: 3, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
263body:             |
264  bb.1.entry:
265    liveins: $a0, $a1, $a2, $a3
266
267    ; MIPS32-LABEL: name: mul_i128
268    ; MIPS32: liveins: $a0, $a1, $a2, $a3
269    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
270    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
271    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
272    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
273    ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
274    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
275    ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
276    ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
277    ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
278    ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
279    ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
280    ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
281    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY]]
282    ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY]]
283    ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY1]]
284    ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY]]
285    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
286    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
287    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
288    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
289    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
290    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
291    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
292    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
293    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
294    ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
295    ; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
296    ; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
297    ; MIPS32: [[MUL5:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY2]]
298    ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY]]
299    ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
300    ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
301    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
302    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
303    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
304    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
305    ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
306    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
307    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
308    ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
309    ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
310    ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
311    ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
312    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
313    ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
314    ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]]
315    ; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
316    ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ICMP5]](s32)
317    ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
318    ; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]]
319    ; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]]
320    ; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
321    ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP6]](s32)
322    ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
323    ; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]]
324    ; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
325    ; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
326    ; MIPS32: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY2]]
327    ; MIPS32: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY3]]
328    ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LOAD2]], [[COPY]]
329    ; MIPS32: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY1]]
330    ; MIPS32: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY2]]
331    ; MIPS32: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[MUL6]], [[MUL7]]
332    ; MIPS32: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ADD12]], [[MUL8]]
333    ; MIPS32: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[MUL9]]
334    ; MIPS32: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[UMULH3]]
335    ; MIPS32: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[ADD15]], [[UMULH4]]
336    ; MIPS32: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH5]]
337    ; MIPS32: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[ADD11]]
338    ; MIPS32: $v0 = COPY [[MUL]](s32)
339    ; MIPS32: $v1 = COPY [[ADD1]](s32)
340    ; MIPS32: $a0 = COPY [[ADD10]](s32)
341    ; MIPS32: $a1 = COPY [[ADD18]](s32)
342    ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
343    %2:_(s32) = COPY $a0
344    %3:_(s32) = COPY $a1
345    %4:_(s32) = COPY $a2
346    %5:_(s32) = COPY $a3
347    %0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
348    %10:_(p0) = G_FRAME_INDEX %fixed-stack.3
349    %6:_(s32) = G_LOAD %10(p0) :: (load (s32) from %fixed-stack.3, align 8)
350    %11:_(p0) = G_FRAME_INDEX %fixed-stack.2
351    %7:_(s32) = G_LOAD %11(p0) :: (load (s32) from %fixed-stack.2)
352    %12:_(p0) = G_FRAME_INDEX %fixed-stack.1
353    %8:_(s32) = G_LOAD %12(p0) :: (load (s32) from %fixed-stack.1, align 8)
354    %13:_(p0) = G_FRAME_INDEX %fixed-stack.0
355    %9:_(s32) = G_LOAD %13(p0) :: (load (s32) from %fixed-stack.0)
356    %1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
357    %14:_(s128) = G_MUL %1, %0
358    %15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
359    $v0 = COPY %15(s32)
360    $v1 = COPY %16(s32)
361    $a0 = COPY %17(s32)
362    $a1 = COPY %18(s32)
363    RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
364
365...
366---
367name:            umulh_i64
368alignment:       4
369tracksRegLiveness: true
370body:             |
371  bb.1.entry:
372    liveins: $a0, $a1, $a2, $a3
373
374    ; MIPS32-LABEL: name: umulh_i64
375    ; MIPS32: liveins: $a0, $a1, $a2, $a3
376    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
377    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
378    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
379    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
380    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
381    ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
382    ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
383    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]]
384    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]]
385    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
386    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
387    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
388    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
389    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
390    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
391    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
392    ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
393    ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
394    ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
395    ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
396    ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
397    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
398    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
399    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
400    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]
401    ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
402    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
403    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
404    ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
405    ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]]
406    ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
407    ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
408    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
409    ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
410    ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
411    ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
412    ; MIPS32: $v0 = COPY [[ADD6]](s32)
413    ; MIPS32: $v1 = COPY [[ADD8]](s32)
414    ; MIPS32: RetRA implicit $v0, implicit $v1
415    %2:_(s32) = COPY $a0
416    %3:_(s32) = COPY $a1
417    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
418    %4:_(s32) = COPY $a2
419    %5:_(s32) = COPY $a3
420    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
421    %6:_(s64) = G_UMULH %1, %0
422    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
423    $v0 = COPY %7(s32)
424    $v1 = COPY %8(s32)
425    RetRA implicit $v0, implicit $v1
426
427...
428---
429name:            umul_with_overflow
430alignment:       4
431tracksRegLiveness: true
432body:             |
433  bb.1 (%ir-block.0):
434    liveins: $a0, $a1, $a2, $a3
435
436    ; MIPS32-LABEL: name: umul_with_overflow
437    ; MIPS32: liveins: $a0, $a1, $a2, $a3
438    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
439    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
440    ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
441    ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
442    ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
443    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
444    ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
445    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
446    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
447    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
448    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
449    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C1]]
450    ; MIPS32: G_STORE [[AND1]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
451    ; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
452    ; MIPS32: RetRA
453    %0:_(s32) = COPY $a0
454    %1:_(s32) = COPY $a1
455    %2:_(p0) = COPY $a2
456    %3:_(p0) = COPY $a3
457    %4:_(s32), %5:_(s1) = G_UMULO %0, %1
458    G_STORE %5(s1), %3(p0) :: (store (s1) into %ir.pcarry_flag)
459    G_STORE %4(s32), %2(p0) :: (store (s32) into %ir.pmul)
460    RetRA
461
462...
463