1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc %s -mtriple=thumbv6m-arm-none-eabi -o - -asm-verbose=false | FileCheck %s --check-prefix=CHECK-V6M 3; RUN: llc %s -mtriple=thumbv7m-arm-none-eabi -o - -asm-verbose=false | FileCheck %s --check-prefix=CHECK-V7M 4 5define i32 @test_values(i32 %a, i32 %b) minsize optsize { 6; CHECK-V6M-LABEL: test_values: 7; CHECK-V6M: mov r2, r0 8; CHECK-V6M-NEXT: ldr r0, .LCPI0_0 9; CHECK-V6M-NEXT: cmp r2, #50 10; CHECK-V6M-NEXT: beq .LBB0_5 11; CHECK-V6M-NEXT: cmp r2, #1 12; CHECK-V6M-NEXT: beq .LBB0_7 13; CHECK-V6M-NEXT: cmp r2, #30 14; CHECK-V6M-NEXT: beq .LBB0_8 15; CHECK-V6M-NEXT: cmp r2, #0 16; CHECK-V6M-NEXT: bne .LBB0_6 17; CHECK-V6M-NEXT: adds r0, r1, r0 18; CHECK-V6M-NEXT: bx lr 19; CHECK-V6M-NEXT: .LBB0_5: 20; CHECK-V6M-NEXT: adds r0, r0, r1 21; CHECK-V6M-NEXT: adds r0, r0, #4 22; CHECK-V6M-NEXT: .LBB0_6: 23; CHECK-V6M-NEXT: bx lr 24; CHECK-V6M-NEXT: .LBB0_7: 25; CHECK-V6M-NEXT: adds r0, r0, r1 26; CHECK-V6M-NEXT: adds r0, r0, #1 27; CHECK-V6M-NEXT: bx lr 28; CHECK-V6M-NEXT: .LBB0_8: 29; CHECK-V6M-NEXT: adds r0, r0, r1 30; CHECK-V6M-NEXT: adds r0, r0, #2 31; CHECK-V6M-NEXT: bx lr 32; CHECK-V6M-NEXT: .p2align 2 33; CHECK-V6M-NEXT: .LCPI0_0: 34; CHECK-V6M-NEXT: .long 537923600 35; 36; CHECK-V7M-LABEL: test_values: 37; CHECK-V7M: mov r2, r0 38; CHECK-V7M-NEXT: ldr r0, .LCPI0_0 39; CHECK-V7M-NEXT: cmp r2, #50 40; CHECK-V7M-NEXT: beq .LBB0_5 41; CHECK-V7M-NEXT: cmp r2, #1 42; CHECK-V7M-NEXT: ittt eq 43; CHECK-V7M-NEXT: addeq r0, r1 44; CHECK-V7M-NEXT: addeq r0, #1 45; CHECK-V7M-NEXT: bxeq lr 46; CHECK-V7M-NEXT: .LBB0_2: 47; CHECK-V7M-NEXT: cmp r2, #30 48; CHECK-V7M-NEXT: ittt eq 49; CHECK-V7M-NEXT: addeq r0, r1 50; CHECK-V7M-NEXT: addeq r0, #2 51; CHECK-V7M-NEXT: bxeq lr 52; CHECK-V7M-NEXT: .LBB0_3: 53; CHECK-V7M-NEXT: cbnz r2, .LBB0_6 54; CHECK-V7M-NEXT: add r0, r1 55; CHECK-V7M-NEXT: bx lr 56; CHECK-V7M-NEXT: .LBB0_5: 57; CHECK-V7M-NEXT: add r0, r1 58; CHECK-V7M-NEXT: adds r0, #4 59; CHECK-V7M-NEXT: .LBB0_6: 60; CHECK-V7M-NEXT: bx lr 61; CHECK-V7M-NEXT: .p2align 2 62; CHECK-V7M-NEXT: .LCPI0_0: 63; CHECK-V7M-NEXT: .long 537923600 64entry: 65 switch i32 %a, label %return [ 66 i32 0, label %sw.bb 67 i32 1, label %sw.bb1 68 i32 30, label %sw.bb3 69 i32 50, label %sw.bb5 70 ] 71 72sw.bb: ; preds = %entry 73 %add = add nsw i32 %b, 537923600 74 br label %return 75 76sw.bb1: ; preds = %entry 77 %add2 = add nsw i32 %b, 537923601 78 br label %return 79 80sw.bb3: ; preds = %entry 81 %add4 = add nsw i32 %b, 537923602 82 br label %return 83 84sw.bb5: ; preds = %entry 85 %add6 = add nsw i32 %b, 537923604 86 br label %return 87 88return: ; preds = %entry, %sw.bb5, %sw.bb3, %sw.bb1, %sw.bb 89 %retval.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 537923600, %entry ] 90 ret i32 %retval.0 91} 92 93define i32 @test_addr(i32 %a, i8* nocapture readonly %b) { 94; CHECK-V6M-LABEL: test_addr: 95; CHECK-V6M: mov r2, r0 96; CHECK-V6M-NEXT: movs r0, #19 97; CHECK-V6M-NEXT: lsls r3, r0, #4 98; CHECK-V6M-NEXT: movs r0, #0 99; CHECK-V6M-NEXT: cmp r2, #29 100; CHECK-V6M-NEXT: bgt .LBB1_4 101; CHECK-V6M-NEXT: cmp r2, #0 102; CHECK-V6M-NEXT: beq .LBB1_8 103; CHECK-V6M-NEXT: cmp r2, #1 104; CHECK-V6M-NEXT: bne .LBB1_9 105; CHECK-V6M-NEXT: adds r3, r3, #1 106; CHECK-V6M-NEXT: b .LBB1_8 107; CHECK-V6M-NEXT: .LBB1_4: 108; CHECK-V6M-NEXT: cmp r2, #30 109; CHECK-V6M-NEXT: beq .LBB1_7 110; CHECK-V6M-NEXT: cmp r2, #50 111; CHECK-V6M-NEXT: bne .LBB1_9 112; CHECK-V6M-NEXT: adds r3, r3, #3 113; CHECK-V6M-NEXT: b .LBB1_8 114; CHECK-V6M-NEXT: .LBB1_7: 115; CHECK-V6M-NEXT: adds r3, r3, #2 116; CHECK-V6M-NEXT: .LBB1_8: 117; CHECK-V6M-NEXT: ldrb r0, [r1, r3] 118; CHECK-V6M-NEXT: .LBB1_9: 119; CHECK-V6M-NEXT: bx lr 120; 121; CHECK-V7M-LABEL: test_addr: 122; CHECK-V7M: mov r2, r0 123; CHECK-V7M-NEXT: movs r0, #0 124; CHECK-V7M-NEXT: cmp r2, #29 125; CHECK-V7M-NEXT: bgt .LBB1_4 126; CHECK-V7M-NEXT: cbz r2, .LBB1_7 127; CHECK-V7M-NEXT: cmp r2, #1 128; CHECK-V7M-NEXT: it ne 129; CHECK-V7M-NEXT: bxne lr 130; CHECK-V7M-NEXT: .LBB1_3: 131; CHECK-V7M-NEXT: movw r0, #305 132; CHECK-V7M-NEXT: b .LBB1_9 133; CHECK-V7M-NEXT: .LBB1_4: 134; CHECK-V7M-NEXT: cmp r2, #30 135; CHECK-V7M-NEXT: beq .LBB1_8 136; CHECK-V7M-NEXT: cmp r2, #50 137; CHECK-V7M-NEXT: bne .LBB1_10 138; CHECK-V7M-NEXT: movw r0, #307 139; CHECK-V7M-NEXT: b .LBB1_9 140; CHECK-V7M-NEXT: .LBB1_7: 141; CHECK-V7M-NEXT: mov.w r0, #304 142; CHECK-V7M-NEXT: b .LBB1_9 143; CHECK-V7M-NEXT: .LBB1_8: 144; CHECK-V7M-NEXT: mov.w r0, #306 145; CHECK-V7M-NEXT: .LBB1_9: 146; CHECK-V7M-NEXT: ldrb r0, [r1, r0] 147; CHECK-V7M-NEXT: .LBB1_10: 148; CHECK-V7M-NEXT: bx lr 149entry: 150 switch i32 %a, label %return [ 151 i32 0, label %return.sink.split 152 i32 1, label %sw.bb1 153 i32 30, label %sw.bb4 154 i32 50, label %sw.bb7 155 ] 156 157sw.bb1: ; preds = %entry 158 br label %return.sink.split 159 160sw.bb4: ; preds = %entry 161 br label %return.sink.split 162 163sw.bb7: ; preds = %entry 164 br label %return.sink.split 165 166return.sink.split: ; preds = %entry, %sw.bb1, %sw.bb4, %sw.bb7 167 %.sink = phi i32 [ 307, %sw.bb7 ], [ 306, %sw.bb4 ], [ 305, %sw.bb1 ], [ 304, %entry ] 168 %arrayidx8 = getelementptr inbounds i8, i8* %b, i32 %.sink 169 %0 = load i8, i8* %arrayidx8, align 1 170 %phitmp = zext i8 %0 to i32 171 br label %return 172 173return: ; preds = %return.sink.split, %entry 174 %retval.0.shrunk = phi i32 [ 0, %entry ], [ %phitmp, %return.sink.split ] 175 ret i32 %retval.0.shrunk 176} 177 178