1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
3
4; i16 -> i32
5
6define arm_aapcs_vfpcc <4 x i32> @sext_i32_0246(<8 x i16> %src) {
7; CHECK-LABEL: sext_i32_0246:
8; CHECK:       @ %bb.0: @ %entry
9; CHECK-NEXT:    vmovlb.s16 q0, q0
10; CHECK-NEXT:    bx lr
11entry:
12  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
13  %out = sext <4 x i16> %strided.vec to <4 x i32>
14  ret <4 x i32> %out
15}
16
17define arm_aapcs_vfpcc <4 x i32> @sext_i32_0246_swapped(<8 x i16> %src) {
18; CHECK-LABEL: sext_i32_0246_swapped:
19; CHECK:       @ %bb.0: @ %entry
20; CHECK-NEXT:    .pad #16
21; CHECK-NEXT:    sub sp, #16
22; CHECK-NEXT:    mov r0, sp
23; CHECK-NEXT:    vstrw.32 q0, [r0]
24; CHECK-NEXT:    vldrh.s32 q0, [r0]
25; CHECK-NEXT:    vldrh.s32 q1, [r0, #8]
26; CHECK-NEXT:    vmov.f32 s1, s2
27; CHECK-NEXT:    vmov.f32 s2, s4
28; CHECK-NEXT:    vmov.f32 s3, s6
29; CHECK-NEXT:    add sp, #16
30; CHECK-NEXT:    bx lr
31entry:
32  %out = sext <8 x i16> %src to <8 x i32>
33  %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
34  ret <4 x i32> %strided.vec
35}
36
37define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357(<8 x i16> %src) {
38; CHECK-LABEL: sext_i32_1357:
39; CHECK:       @ %bb.0: @ %entry
40; CHECK-NEXT:    vmovlt.s16 q0, q0
41; CHECK-NEXT:    bx lr
42entry:
43  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
44  %out = sext <4 x i16> %strided.vec to <4 x i32>
45  ret <4 x i32> %out
46}
47
48define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357_swapped(<8 x i16> %src) {
49; CHECK-LABEL: sext_i32_1357_swapped:
50; CHECK:       @ %bb.0: @ %entry
51; CHECK-NEXT:    .pad #16
52; CHECK-NEXT:    sub sp, #16
53; CHECK-NEXT:    mov r0, sp
54; CHECK-NEXT:    vstrw.32 q0, [r0]
55; CHECK-NEXT:    vldrh.s32 q2, [r0]
56; CHECK-NEXT:    vldrh.s32 q1, [r0, #8]
57; CHECK-NEXT:    vmov.f32 s0, s9
58; CHECK-NEXT:    vmov.f32 s1, s11
59; CHECK-NEXT:    vmov.f32 s2, s5
60; CHECK-NEXT:    vmov.f32 s3, s7
61; CHECK-NEXT:    add sp, #16
62; CHECK-NEXT:    bx lr
63entry:
64  %out = sext <8 x i16> %src to <8 x i32>
65  %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
66  ret <4 x i32> %strided.vec
67}
68
69define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214(<16 x i16> %src) {
70; CHECK-LABEL: sext_i32_02468101214:
71; CHECK:       @ %bb.0: @ %entry
72; CHECK-NEXT:    vmovlb.s16 q0, q0
73; CHECK-NEXT:    vmovlb.s16 q1, q1
74; CHECK-NEXT:    bx lr
75entry:
76  %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
77  %out = sext <8 x i16> %strided.vec to <8 x i32>
78  ret <8 x i32> %out
79}
80
81define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214_swapped(<16 x i16> %src) {
82; CHECK-LABEL: sext_i32_02468101214_swapped:
83; CHECK:       @ %bb.0: @ %entry
84; CHECK-NEXT:    .pad #32
85; CHECK-NEXT:    sub sp, #32
86; CHECK-NEXT:    mov r0, sp
87; CHECK-NEXT:    add r1, sp, #16
88; CHECK-NEXT:    vstrw.32 q0, [r0]
89; CHECK-NEXT:    vstrw.32 q1, [r1]
90; CHECK-NEXT:    vldrh.s32 q0, [r0]
91; CHECK-NEXT:    vldrh.s32 q1, [r0, #8]
92; CHECK-NEXT:    vldrh.s32 q2, [r1, #8]
93; CHECK-NEXT:    vmov.f32 s1, s2
94; CHECK-NEXT:    vmov.f32 s2, s4
95; CHECK-NEXT:    vmov.f32 s3, s6
96; CHECK-NEXT:    vldrh.s32 q1, [r1]
97; CHECK-NEXT:    vmov.f32 s5, s6
98; CHECK-NEXT:    vmov.f32 s6, s8
99; CHECK-NEXT:    vmov.f32 s7, s10
100; CHECK-NEXT:    add sp, #32
101; CHECK-NEXT:    bx lr
102entry:
103  %out = sext <16 x i16> %src to <16 x i32>
104  %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
105  ret <8 x i32> %strided.vec
106}
107
108define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315(<16 x i16> %src) {
109; CHECK-LABEL: sext_i32_13579111315:
110; CHECK:       @ %bb.0: @ %entry
111; CHECK-NEXT:    vmovlt.s16 q0, q0
112; CHECK-NEXT:    vmovlt.s16 q1, q1
113; CHECK-NEXT:    bx lr
114entry:
115  %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
116  %out = sext <8 x i16> %strided.vec to <8 x i32>
117  ret <8 x i32> %out
118}
119
120define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315_swapped(<16 x i16> %src) {
121; CHECK-LABEL: sext_i32_13579111315_swapped:
122; CHECK:       @ %bb.0: @ %entry
123; CHECK-NEXT:    .pad #32
124; CHECK-NEXT:    sub sp, #32
125; CHECK-NEXT:    mov r0, sp
126; CHECK-NEXT:    add r1, sp, #16
127; CHECK-NEXT:    vstrw.32 q0, [r0]
128; CHECK-NEXT:    vstrw.32 q1, [r1]
129; CHECK-NEXT:    vldrh.s32 q2, [r0]
130; CHECK-NEXT:    vldrh.s32 q1, [r0, #8]
131; CHECK-NEXT:    vldrh.s32 q3, [r1]
132; CHECK-NEXT:    vmov.f32 s0, s9
133; CHECK-NEXT:    vmov.f32 s1, s11
134; CHECK-NEXT:    vldrh.s32 q2, [r1, #8]
135; CHECK-NEXT:    vmov.f32 s2, s5
136; CHECK-NEXT:    vmov.f32 s3, s7
137; CHECK-NEXT:    vmov.f32 s4, s13
138; CHECK-NEXT:    vmov.f32 s5, s15
139; CHECK-NEXT:    vmov.f32 s6, s9
140; CHECK-NEXT:    vmov.f32 s7, s11
141; CHECK-NEXT:    add sp, #32
142; CHECK-NEXT:    bx lr
143entry:
144  %out = sext <16 x i16> %src to <16 x i32>
145  %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
146  ret <8 x i32> %strided.vec
147}
148
149define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246(<8 x i16> %src) {
150; CHECK-LABEL: zext_i32_0246:
151; CHECK:       @ %bb.0: @ %entry
152; CHECK-NEXT:    vmovlb.u16 q0, q0
153; CHECK-NEXT:    bx lr
154entry:
155  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
156  %out = zext <4 x i16> %strided.vec to <4 x i32>
157  ret <4 x i32> %out
158}
159
160define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246_swapped(<8 x i16> %src) {
161; CHECK-LABEL: zext_i32_0246_swapped:
162; CHECK:       @ %bb.0: @ %entry
163; CHECK-NEXT:    .pad #16
164; CHECK-NEXT:    sub sp, #16
165; CHECK-NEXT:    mov r0, sp
166; CHECK-NEXT:    vstrw.32 q0, [r0]
167; CHECK-NEXT:    vldrh.u32 q0, [r0]
168; CHECK-NEXT:    vldrh.u32 q1, [r0, #8]
169; CHECK-NEXT:    vmov.f32 s1, s2
170; CHECK-NEXT:    vmov.f32 s2, s4
171; CHECK-NEXT:    vmov.f32 s3, s6
172; CHECK-NEXT:    add sp, #16
173; CHECK-NEXT:    bx lr
174entry:
175  %out = zext <8 x i16> %src to <8 x i32>
176  %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
177  ret <4 x i32> %strided.vec
178}
179
180define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357(<8 x i16> %src) {
181; CHECK-LABEL: zext_i32_1357:
182; CHECK:       @ %bb.0: @ %entry
183; CHECK-NEXT:    vmovlt.u16 q0, q0
184; CHECK-NEXT:    bx lr
185entry:
186  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
187  %out = zext <4 x i16> %strided.vec to <4 x i32>
188  ret <4 x i32> %out
189}
190
191define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357_swapped(<8 x i16> %src) {
192; CHECK-LABEL: zext_i32_1357_swapped:
193; CHECK:       @ %bb.0: @ %entry
194; CHECK-NEXT:    .pad #16
195; CHECK-NEXT:    sub sp, #16
196; CHECK-NEXT:    mov r0, sp
197; CHECK-NEXT:    vstrw.32 q0, [r0]
198; CHECK-NEXT:    vldrh.u32 q2, [r0]
199; CHECK-NEXT:    vldrh.u32 q1, [r0, #8]
200; CHECK-NEXT:    vmov.f32 s0, s9
201; CHECK-NEXT:    vmov.f32 s1, s11
202; CHECK-NEXT:    vmov.f32 s2, s5
203; CHECK-NEXT:    vmov.f32 s3, s7
204; CHECK-NEXT:    add sp, #16
205; CHECK-NEXT:    bx lr
206entry:
207  %out = zext <8 x i16> %src to <8 x i32>
208  %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
209  ret <4 x i32> %strided.vec
210}
211
212define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214(<16 x i16> %src) {
213; CHECK-LABEL: zext_i32_02468101214:
214; CHECK:       @ %bb.0: @ %entry
215; CHECK-NEXT:    vmovlb.u16 q0, q0
216; CHECK-NEXT:    vmovlb.u16 q1, q1
217; CHECK-NEXT:    bx lr
218entry:
219  %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
220  %out = zext <8 x i16> %strided.vec to <8 x i32>
221  ret <8 x i32> %out
222}
223
224define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214_swapped(<16 x i16> %src) {
225; CHECK-LABEL: zext_i32_02468101214_swapped:
226; CHECK:       @ %bb.0: @ %entry
227; CHECK-NEXT:    .pad #32
228; CHECK-NEXT:    sub sp, #32
229; CHECK-NEXT:    mov r0, sp
230; CHECK-NEXT:    add r1, sp, #16
231; CHECK-NEXT:    vstrw.32 q0, [r0]
232; CHECK-NEXT:    vstrw.32 q1, [r1]
233; CHECK-NEXT:    vldrh.u32 q0, [r0]
234; CHECK-NEXT:    vldrh.u32 q1, [r0, #8]
235; CHECK-NEXT:    vldrh.u32 q2, [r1, #8]
236; CHECK-NEXT:    vmov.f32 s1, s2
237; CHECK-NEXT:    vmov.f32 s2, s4
238; CHECK-NEXT:    vmov.f32 s3, s6
239; CHECK-NEXT:    vldrh.u32 q1, [r1]
240; CHECK-NEXT:    vmov.f32 s5, s6
241; CHECK-NEXT:    vmov.f32 s6, s8
242; CHECK-NEXT:    vmov.f32 s7, s10
243; CHECK-NEXT:    add sp, #32
244; CHECK-NEXT:    bx lr
245entry:
246  %out = zext <16 x i16> %src to <16 x i32>
247  %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
248  ret <8 x i32> %strided.vec
249}
250
251define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315(<16 x i16> %src) {
252; CHECK-LABEL: zext_i32_13579111315:
253; CHECK:       @ %bb.0: @ %entry
254; CHECK-NEXT:    vmovlt.u16 q0, q0
255; CHECK-NEXT:    vmovlt.u16 q1, q1
256; CHECK-NEXT:    bx lr
257entry:
258  %strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
259  %out = zext <8 x i16> %strided.vec to <8 x i32>
260  ret <8 x i32> %out
261}
262
263define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315_swapped(<16 x i16> %src) {
264; CHECK-LABEL: zext_i32_13579111315_swapped:
265; CHECK:       @ %bb.0: @ %entry
266; CHECK-NEXT:    .pad #32
267; CHECK-NEXT:    sub sp, #32
268; CHECK-NEXT:    mov r0, sp
269; CHECK-NEXT:    add r1, sp, #16
270; CHECK-NEXT:    vstrw.32 q0, [r0]
271; CHECK-NEXT:    vstrw.32 q1, [r1]
272; CHECK-NEXT:    vldrh.u32 q2, [r0]
273; CHECK-NEXT:    vldrh.u32 q1, [r0, #8]
274; CHECK-NEXT:    vldrh.u32 q3, [r1]
275; CHECK-NEXT:    vmov.f32 s0, s9
276; CHECK-NEXT:    vmov.f32 s1, s11
277; CHECK-NEXT:    vldrh.u32 q2, [r1, #8]
278; CHECK-NEXT:    vmov.f32 s2, s5
279; CHECK-NEXT:    vmov.f32 s3, s7
280; CHECK-NEXT:    vmov.f32 s4, s13
281; CHECK-NEXT:    vmov.f32 s5, s15
282; CHECK-NEXT:    vmov.f32 s6, s9
283; CHECK-NEXT:    vmov.f32 s7, s11
284; CHECK-NEXT:    add sp, #32
285; CHECK-NEXT:    bx lr
286entry:
287  %out = zext <16 x i16> %src to <16 x i32>
288  %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
289  ret <8 x i32> %strided.vec
290}
291
292define arm_aapcs_vfpcc <8 x i32> @sext_i32_02481357(<8 x i16> %src) {
293; CHECK-LABEL: sext_i32_02481357:
294; CHECK:       @ %bb.0: @ %entry
295; CHECK-NEXT:    vmovlb.s16 q2, q0
296; CHECK-NEXT:    vmovlt.s16 q1, q0
297; CHECK-NEXT:    vmov q0, q2
298; CHECK-NEXT:    bx lr
299entry:
300  %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
301  %out = sext <8 x i16> %strided.vec to <8 x i32>
302  ret <8 x i32> %out
303}
304
305
306; i8 -> i16
307
308define arm_aapcs_vfpcc <8 x i16> @sext_i16_02468101214(<16 x i8> %src) {
309; CHECK-LABEL: sext_i16_02468101214:
310; CHECK:       @ %bb.0: @ %entry
311; CHECK-NEXT:    vmovlb.s8 q0, q0
312; CHECK-NEXT:    bx lr
313entry:
314  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
315  %out = sext <8 x i8> %strided.vec to <8 x i16>
316  ret <8 x i16> %out
317}
318
319define arm_aapcs_vfpcc <8 x i16> @sext_i16_13579111315(<16 x i8> %src) {
320; CHECK-LABEL: sext_i16_13579111315:
321; CHECK:       @ %bb.0: @ %entry
322; CHECK-NEXT:    vmovlt.s8 q0, q0
323; CHECK-NEXT:    bx lr
324entry:
325  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
326  %out = sext <8 x i8> %strided.vec to <8 x i16>
327  ret <8 x i16> %out
328}
329
330define arm_aapcs_vfpcc <16 x i16> @sext_i16_024681012141618202224262830(<32 x i8> %src) {
331; CHECK-LABEL: sext_i16_024681012141618202224262830:
332; CHECK:       @ %bb.0: @ %entry
333; CHECK-NEXT:    vmovlb.s8 q0, q0
334; CHECK-NEXT:    vmovlb.s8 q1, q1
335; CHECK-NEXT:    bx lr
336entry:
337  %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
338  %out = sext <16 x i8> %strided.vec to <16 x i16>
339  ret <16 x i16> %out
340}
341
342define arm_aapcs_vfpcc <16 x i16> @sext_i16_135791113151719212325272931(<32 x i8> %src) {
343; CHECK-LABEL: sext_i16_135791113151719212325272931:
344; CHECK:       @ %bb.0: @ %entry
345; CHECK-NEXT:    vmovlt.s8 q0, q0
346; CHECK-NEXT:    vmovlt.s8 q1, q1
347; CHECK-NEXT:    bx lr
348entry:
349  %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
350  %out = sext <16 x i8> %strided.vec to <16 x i16>
351  ret <16 x i16> %out
352}
353
354define arm_aapcs_vfpcc <8 x i16> @zext_i16_02468101214(<16 x i8> %src) {
355; CHECK-LABEL: zext_i16_02468101214:
356; CHECK:       @ %bb.0: @ %entry
357; CHECK-NEXT:    vmovlb.u8 q0, q0
358; CHECK-NEXT:    bx lr
359entry:
360  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
361  %out = zext <8 x i8> %strided.vec to <8 x i16>
362  ret <8 x i16> %out
363}
364
365define arm_aapcs_vfpcc <8 x i16> @zext_i16_13579111315(<16 x i8> %src) {
366; CHECK-LABEL: zext_i16_13579111315:
367; CHECK:       @ %bb.0: @ %entry
368; CHECK-NEXT:    vmovlt.u8 q0, q0
369; CHECK-NEXT:    bx lr
370entry:
371  %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
372  %out = zext <8 x i8> %strided.vec to <8 x i16>
373  ret <8 x i16> %out
374}
375
376define arm_aapcs_vfpcc <16 x i16> @zext_i16_024681012141618202224262830(<32 x i8> %src) {
377; CHECK-LABEL: zext_i16_024681012141618202224262830:
378; CHECK:       @ %bb.0: @ %entry
379; CHECK-NEXT:    vmovlb.u8 q0, q0
380; CHECK-NEXT:    vmovlb.u8 q1, q1
381; CHECK-NEXT:    bx lr
382entry:
383  %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
384  %out = zext <16 x i8> %strided.vec to <16 x i16>
385  ret <16 x i16> %out
386}
387
388define arm_aapcs_vfpcc <16 x i16> @zext_i16_135791113151719212325272931(<32 x i8> %src) {
389; CHECK-LABEL: zext_i16_135791113151719212325272931:
390; CHECK:       @ %bb.0: @ %entry
391; CHECK-NEXT:    vmovlt.u8 q0, q0
392; CHECK-NEXT:    vmovlt.u8 q1, q1
393; CHECK-NEXT:    bx lr
394entry:
395  %strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
396  %out = zext <16 x i8> %strided.vec to <16 x i16>
397  ret <16 x i16> %out
398}
399
400
401; f16 -> f32
402
403define arm_aapcs_vfpcc <4 x float> @fpext_0246(<8 x half> %src) {
404; CHECK-LABEL: fpext_0246:
405; CHECK:       @ %bb.0: @ %entry
406; CHECK-NEXT:    vcvtb.f32.f16 q0, q0
407; CHECK-NEXT:    bx lr
408entry:
409  %strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
410  %out = fpext <4 x half> %strided.vec to <4 x float>
411  ret <4 x float> %out
412}
413
414define arm_aapcs_vfpcc <4 x float> @fpext_1357(<8 x half> %src) {
415; CHECK-LABEL: fpext_1357:
416; CHECK:       @ %bb.0: @ %entry
417; CHECK-NEXT:    vcvtt.f32.f16 q0, q0
418; CHECK-NEXT:    bx lr
419entry:
420  %strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
421  %out = fpext <4 x half> %strided.vec to <4 x float>
422  ret <4 x float> %out
423}
424
425define arm_aapcs_vfpcc <8 x float> @fpext_02468101214(<16 x half> %src) {
426; CHECK-LABEL: fpext_02468101214:
427; CHECK:       @ %bb.0: @ %entry
428; CHECK-NEXT:    vcvtb.f32.f16 q0, q0
429; CHECK-NEXT:    vcvtb.f32.f16 q1, q1
430; CHECK-NEXT:    bx lr
431entry:
432  %strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
433  %out = fpext <8 x half> %strided.vec to <8 x float>
434  ret <8 x float> %out
435}
436
437define arm_aapcs_vfpcc <8 x float> @fpext_13579111315(<16 x half> %src) {
438; CHECK-LABEL: fpext_13579111315:
439; CHECK:       @ %bb.0: @ %entry
440; CHECK-NEXT:    vcvtt.f32.f16 q0, q0
441; CHECK-NEXT:    vcvtt.f32.f16 q1, q1
442; CHECK-NEXT:    bx lr
443entry:
444  %strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
445  %out = fpext <8 x half> %strided.vec to <8 x float>
446  ret <8 x float> %out
447}
448