1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE 4; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE 5 6define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() { 7; CHECK-LABEL: mov_int8_1: 8; CHECK: @ %bb.0: @ %entry 9; CHECK-NEXT: vmov.i8 q0, #0x1 10; CHECK-NEXT: bx lr 11entry: 12 ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 13} 14 15define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() { 16; CHECK-LABEL: mov_int8_m1: 17; CHECK: @ %bb.0: @ %entry 18; CHECK-NEXT: vmov.i8 q0, #0xff 19; CHECK-NEXT: bx lr 20entry: 21 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 22} 23 24; This has 0x01020304 or 0x04030201 vdup.32'd to q reg depending on endianness. 25; The big endian is different as there is an implicit vrev64.8 out of the 26; function, which gets constant folded away. 27define arm_aapcs_vfpcc <16 x i8> @mov_int8_1234() { 28; CHECKLE-LABEL: mov_int8_1234: 29; CHECKLE: @ %bb.0: @ %entry 30; CHECKLE-NEXT: movw r0, #513 31; CHECKLE-NEXT: movt r0, #1027 32; CHECKLE-NEXT: vdup.32 q0, r0 33; CHECKLE-NEXT: bx lr 34; 35; CHECKBE-LABEL: mov_int8_1234: 36; CHECKBE: @ %bb.0: @ %entry 37; CHECKBE-NEXT: movw r0, #772 38; CHECKBE-NEXT: movt r0, #258 39; CHECKBE-NEXT: vdup.32 q0, r0 40; CHECKBE-NEXT: bx lr 41entry: 42 ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4> 43} 44 45define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() { 46; CHECK-LABEL: mov_int16_1: 47; CHECK: @ %bb.0: @ %entry 48; CHECK-NEXT: vmov.i16 q0, #0x1 49; CHECK-NEXT: bx lr 50entry: 51 ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 52} 53 54define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() { 55; CHECK-LABEL: mov_int16_m1: 56; CHECK: @ %bb.0: @ %entry 57; CHECK-NEXT: vmov.i8 q0, #0xff 58; CHECK-NEXT: bx lr 59entry: 60 ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 61} 62 63define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() { 64; CHECK-LABEL: mov_int16_256: 65; CHECK: @ %bb.0: @ %entry 66; CHECK-NEXT: vmov.i16 q0, #0x100 67; CHECK-NEXT: bx lr 68entry: 69 ret <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256> 70} 71 72define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() { 73; CHECK-LABEL: mov_int16_257: 74; CHECK: @ %bb.0: @ %entry 75; CHECK-NEXT: vmov.i8 q0, #0x1 76; CHECK-NEXT: bx lr 77entry: 78 ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257> 79} 80 81define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() { 82; CHECK-LABEL: mov_int16_258: 83; CHECK: @ %bb.0: @ %entry 84; CHECK-NEXT: mov.w r0, #258 85; CHECK-NEXT: vdup.16 q0, r0 86; CHECK-NEXT: bx lr 87entry: 88 ret <8 x i16> <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258> 89} 90 91define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() { 92; CHECK-LABEL: mov_int32_1: 93; CHECK: @ %bb.0: @ %entry 94; CHECK-NEXT: vmov.i32 q0, #0x1 95; CHECK-NEXT: bx lr 96entry: 97 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 98} 99 100define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() { 101; CHECK-LABEL: mov_int32_256: 102; CHECK: @ %bb.0: @ %entry 103; CHECK-NEXT: vmov.i32 q0, #0x100 104; CHECK-NEXT: bx lr 105entry: 106 ret <4 x i32> <i32 256, i32 256, i32 256, i32 256> 107} 108 109define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() { 110; CHECK-LABEL: mov_int32_65536: 111; CHECK: @ %bb.0: @ %entry 112; CHECK-NEXT: vmov.i32 q0, #0x10000 113; CHECK-NEXT: bx lr 114entry: 115 ret <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536> 116} 117 118define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() { 119; CHECK-LABEL: mov_int32_16777216: 120; CHECK: @ %bb.0: @ %entry 121; CHECK-NEXT: vmov.i32 q0, #0x1000000 122; CHECK-NEXT: bx lr 123entry: 124 ret <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216> 125} 126 127define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() { 128; CHECK-LABEL: mov_int32_16777217: 129; CHECK: @ %bb.0: @ %entry 130; CHECK-NEXT: movs r0, #1 131; CHECK-NEXT: movt r0, #256 132; CHECK-NEXT: vdup.32 q0, r0 133; CHECK-NEXT: bx lr 134entry: 135 ret <4 x i32> <i32 16777217, i32 16777217, i32 16777217, i32 16777217> 136} 137 138define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() { 139; CHECK-LABEL: mov_int32_17919: 140; CHECK: @ %bb.0: @ %entry 141; CHECK-NEXT: vmov.i32 q0, #0x45ff 142; CHECK-NEXT: bx lr 143entry: 144 ret <4 x i32> <i32 17919, i32 17919, i32 17919, i32 17919> 145} 146 147define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() { 148; CHECK-LABEL: mov_int32_4587519: 149; CHECK: @ %bb.0: @ %entry 150; CHECK-NEXT: vmov.i32 q0, #0x45ffff 151; CHECK-NEXT: bx lr 152entry: 153 ret <4 x i32> <i32 4587519, i32 4587519, i32 4587519, i32 4587519> 154} 155 156define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() { 157; CHECK-LABEL: mov_int32_m1: 158; CHECK: @ %bb.0: @ %entry 159; CHECK-NEXT: vmov.i8 q0, #0xff 160; CHECK-NEXT: bx lr 161entry: 162 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 163} 164 165define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() { 166; CHECK-LABEL: mov_int32_4294901760: 167; CHECK: @ %bb.0: @ %entry 168; CHECK-NEXT: vmvn.i32 q0, #0xffff 169; CHECK-NEXT: bx lr 170entry: 171 ret <4 x i32> <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760> 172} 173 174define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() { 175; CHECK-LABEL: mov_int32_4278190335: 176; CHECK: @ %bb.0: @ %entry 177; CHECK-NEXT: movs r0, #255 178; CHECK-NEXT: movt r0, #65280 179; CHECK-NEXT: vdup.32 q0, r0 180; CHECK-NEXT: bx lr 181entry: 182 ret <4 x i32> <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335> 183} 184 185define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() { 186; CHECK-LABEL: mov_int32_4278255615: 187; CHECK: @ %bb.0: @ %entry 188; CHECK-NEXT: vmvn.i32 q0, #0xff0000 189; CHECK-NEXT: bx lr 190entry: 191 ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615> 192} 193 194define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() { 195; CHECK-LABEL: mov_int32_16908546: 196; CHECK: @ %bb.0: @ %entry 197; CHECK-NEXT: mov.w r0, #258 198; CHECK-NEXT: vdup.16 q0, r0 199; CHECK-NEXT: bx lr 200entry: 201 ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546> 202} 203 204define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() { 205; CHECKLE-LABEL: mov_int64_1: 206; CHECKLE: @ %bb.0: @ %entry 207; CHECKLE-NEXT: adr r0, .LCPI20_0 208; CHECKLE-NEXT: vldrw.u32 q0, [r0] 209; CHECKLE-NEXT: bx lr 210; CHECKLE-NEXT: .p2align 4 211; CHECKLE-NEXT: @ %bb.1: 212; CHECKLE-NEXT: .LCPI20_0: 213; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324 214; CHECKLE-NEXT: .long 0 215; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324 216; CHECKLE-NEXT: .long 0 217; 218; CHECKBE-LABEL: mov_int64_1: 219; CHECKBE: @ %bb.0: @ %entry 220; CHECKBE-NEXT: adr r0, .LCPI20_0 221; CHECKBE-NEXT: vldrb.u8 q1, [r0] 222; CHECKBE-NEXT: vrev64.8 q0, q1 223; CHECKBE-NEXT: bx lr 224; CHECKBE-NEXT: .p2align 4 225; CHECKBE-NEXT: @ %bb.1: 226; CHECKBE-NEXT: .LCPI20_0: 227; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324 228; CHECKBE-NEXT: .long 1 229; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324 230; CHECKBE-NEXT: .long 1 231entry: 232 ret <2 x i64> <i64 1, i64 1> 233} 234 235define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() { 236; CHECK-LABEL: mov_int64_ff: 237; CHECK: @ %bb.0: @ %entry 238; CHECK-NEXT: vmov.i64 q0, #0xff 239; CHECK-NEXT: bx lr 240entry: 241 ret <2 x i64> < i64 255, i64 255 > 242} 243 244define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() { 245; CHECK-LABEL: mov_int64_m1: 246; CHECK: @ %bb.0: @ %entry 247; CHECK-NEXT: vmov.i8 q0, #0xff 248; CHECK-NEXT: bx lr 249entry: 250 ret <2 x i64> < i64 -1, i64 -1 > 251} 252 253define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() { 254; CHECK-LABEL: mov_int64_ff0000ff0000ffff: 255; CHECK: @ %bb.0: @ %entry 256; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff 257; CHECK-NEXT: bx lr 258entry: 259 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > 260} 261 262define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() { 263; CHECKLE-LABEL: mov_int64_f_0: 264; CHECKLE: @ %bb.0: @ %entry 265; CHECKLE-NEXT: adr r0, .LCPI24_0 266; CHECKLE-NEXT: vldrw.u32 q0, [r0] 267; CHECKLE-NEXT: bx lr 268; CHECKLE-NEXT: .p2align 4 269; CHECKLE-NEXT: @ %bb.1: 270; CHECKLE-NEXT: .LCPI24_0: 271; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321 272; CHECKLE-NEXT: .long 0 273; CHECKLE-NEXT: .long 0 @ double 0 274; CHECKLE-NEXT: .long 0 275; 276; CHECKBE-LABEL: mov_int64_f_0: 277; CHECKBE: @ %bb.0: @ %entry 278; CHECKBE-NEXT: adr r0, .LCPI24_0 279; CHECKBE-NEXT: vldrb.u8 q1, [r0] 280; CHECKBE-NEXT: vrev64.8 q0, q1 281; CHECKBE-NEXT: bx lr 282; CHECKBE-NEXT: .p2align 4 283; CHECKBE-NEXT: @ %bb.1: 284; CHECKBE-NEXT: .LCPI24_0: 285; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321 286; CHECKBE-NEXT: .long 255 287; CHECKBE-NEXT: .long 0 @ double 0 288; CHECKBE-NEXT: .long 0 289entry: 290 ret <2 x i64> < i64 255, i64 0 > 291} 292 293define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() { 294; CHECKLE-LABEL: mov_int64_0f000f0f: 295; CHECKLE: @ %bb.0: @ %entry 296; CHECKLE-NEXT: vmov.i64 q0, #0xff000000ff00ff 297; CHECKLE-NEXT: bx lr 298; 299; CHECKBE-LABEL: mov_int64_0f000f0f: 300; CHECKBE: @ %bb.0: @ %entry 301; CHECKBE-NEXT: vmov.i64 q0, #0xff00ff000000ff00 302; CHECKBE-NEXT: bx lr 303entry: 304 ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0> 305} 306 307define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() { 308; CHECKLE-LABEL: mov_int64_ff00ffff: 309; CHECKLE: @ %bb.0: @ %entry 310; CHECKLE-NEXT: vmov.i64 q0, #0xffffffff0000ffff 311; CHECKLE-NEXT: bx lr 312; 313; CHECKBE-LABEL: mov_int64_ff00ffff: 314; CHECKBE: @ %bb.0: @ %entry 315; CHECKBE-NEXT: vmov.i64 q0, #0xffff0000ffffffff 316; CHECKBE-NEXT: bx lr 317entry: 318 ret <8 x i16> <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1> 319} 320 321define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() { 322; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f: 323; CHECKLE: @ %bb.0: @ %entry 324; CHECKLE-NEXT: vmov.i16 q0, #0xff 325; CHECKLE-NEXT: bx lr 326; 327; CHECKBE-LABEL: mov_int64_0f0f0f0f0f0f0f0f: 328; CHECKBE: @ %bb.0: @ %entry 329; CHECKBE-NEXT: vmov.i16 q0, #0xff00 330; CHECKBE-NEXT: bx lr 331entry: 332 ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0> 333} 334 335define arm_aapcs_vfpcc <4 x float> @mov_float_1() { 336; CHECK-LABEL: mov_float_1: 337; CHECK: @ %bb.0: @ %entry 338; CHECK-NEXT: mov.w r0, #1065353216 339; CHECK-NEXT: vdup.32 q0, r0 340; CHECK-NEXT: bx lr 341entry: 342 ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 343} 344 345define arm_aapcs_vfpcc <4 x float> @mov_float_m3() { 346; CHECK-LABEL: mov_float_m3: 347; CHECK: @ %bb.0: @ %entry 348; CHECK-NEXT: movs r0, #0 349; CHECK-NEXT: movt r0, #49216 350; CHECK-NEXT: vdup.32 q0, r0 351; CHECK-NEXT: bx lr 352entry: 353 ret <4 x float> <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00> 354} 355 356define arm_aapcs_vfpcc <8 x half> @mov_float16_1() { 357; CHECK-LABEL: mov_float16_1: 358; CHECK: @ %bb.0: @ %entry 359; CHECK-NEXT: vmov.i16 q0, #0x3c00 360; CHECK-NEXT: bx lr 361 362entry: 363 ret <8 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00> 364} 365 366define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() { 367; CHECK-LABEL: mov_float16_m3: 368; CHECK: @ %bb.0: @ %entry 369; CHECK-NEXT: vmov.i16 q0, #0xc200 370; CHECK-NEXT: bx lr 371 372entry: 373 ret <8 x half> <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00> 374} 375 376define arm_aapcs_vfpcc <2 x double> @mov_double_1() { 377; CHECKLE-LABEL: mov_double_1: 378; CHECKLE: @ %bb.0: @ %entry 379; CHECKLE-NEXT: adr r0, .LCPI32_0 380; CHECKLE-NEXT: vldrw.u32 q0, [r0] 381; CHECKLE-NEXT: bx lr 382; CHECKLE-NEXT: .p2align 4 383; CHECKLE-NEXT: @ %bb.1: 384; CHECKLE-NEXT: .LCPI32_0: 385; CHECKLE-NEXT: .long 0 @ double 1 386; CHECKLE-NEXT: .long 1072693248 387; CHECKLE-NEXT: .long 0 @ double 1 388; CHECKLE-NEXT: .long 1072693248 389; 390; CHECKBE-LABEL: mov_double_1: 391; CHECKBE: @ %bb.0: @ %entry 392; CHECKBE-NEXT: adr r0, .LCPI32_0 393; CHECKBE-NEXT: vldrb.u8 q1, [r0] 394; CHECKBE-NEXT: vrev64.8 q0, q1 395; CHECKBE-NEXT: bx lr 396; CHECKBE-NEXT: .p2align 4 397; CHECKBE-NEXT: @ %bb.1: 398; CHECKBE-NEXT: .LCPI32_0: 399; CHECKBE-NEXT: .long 1072693248 @ double 1 400; CHECKBE-NEXT: .long 0 401; CHECKBE-NEXT: .long 1072693248 @ double 1 402; CHECKBE-NEXT: .long 0 403entry: 404 ret <2 x double> <double 1.000000e+00, double 1.000000e+00> 405} 406 407define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) { 408; CHECKLE-LABEL: test: 409; CHECKLE: @ %bb.0: @ %entry 410; CHECKLE-NEXT: vmov.i64 q1, #0xff000000ff00ff 411; CHECKLE-NEXT: vorr q0, q0, q1 412; CHECKLE-NEXT: bx lr 413; 414; CHECKBE-LABEL: test: 415; CHECKBE: @ %bb.0: @ %entry 416; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff000000ff00 417; CHECKBE-NEXT: vrev64.8 q2, q1 418; CHECKBE-NEXT: vrev64.8 q1, q0 419; CHECKBE-NEXT: vorr q1, q1, q2 420; CHECKBE-NEXT: vrev64.8 q0, q1 421; CHECKBE-NEXT: bx lr 422entry: 423 %o = or <16 x i8> %i, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0> 424 ret <16 x i8> %o 425} 426 427define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) { 428; CHECKLE-LABEL: test2: 429; CHECKLE: @ %bb.0: @ %entry 430; CHECKLE-NEXT: vmov.i64 q1, #0xffffffff0000ffff 431; CHECKLE-NEXT: vorr q0, q0, q1 432; CHECKLE-NEXT: bx lr 433; 434; CHECKBE-LABEL: test2: 435; CHECKBE: @ %bb.0: @ %entry 436; CHECKBE-NEXT: vmov.i64 q1, #0xffff0000ffffffff 437; CHECKBE-NEXT: vrev64.16 q2, q1 438; CHECKBE-NEXT: vrev64.16 q1, q0 439; CHECKBE-NEXT: vorr q1, q1, q2 440; CHECKBE-NEXT: vrev64.16 q0, q1 441; CHECKBE-NEXT: bx lr 442entry: 443 %o = or <8 x i16> %i, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1> 444 ret <8 x i16> %o 445} 446 447define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) { 448; CHECKLE-LABEL: i1and_vmov: 449; CHECKLE: @ %bb.0: @ %entry 450; CHECKLE-NEXT: cmp r0, #0 451; CHECKLE-NEXT: mov.w r1, #15 452; CHECKLE-NEXT: csetm r0, eq 453; CHECKLE-NEXT: ands r0, r1 454; CHECKLE-NEXT: vmsr p0, r0 455; CHECKLE-NEXT: vpsel q0, q0, q1 456; CHECKLE-NEXT: bx lr 457; 458; CHECKBE-LABEL: i1and_vmov: 459; CHECKBE: @ %bb.0: @ %entry 460; CHECKBE-NEXT: cmp r0, #0 461; CHECKBE-NEXT: mov.w r1, #15 462; CHECKBE-NEXT: csetm r0, eq 463; CHECKBE-NEXT: vrev64.32 q2, q1 464; CHECKBE-NEXT: ands r0, r1 465; CHECKBE-NEXT: vrev64.32 q1, q0 466; CHECKBE-NEXT: vmsr p0, r0 467; CHECKBE-NEXT: vpsel q1, q1, q2 468; CHECKBE-NEXT: vrev64.32 q0, q1 469; CHECKBE-NEXT: bx lr 470entry: 471 %c1 = icmp eq i32 %c, zeroinitializer 472 %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0 473 %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer 474 %l699 = and <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false> 475 %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b 476 ret <4 x i32> %s 477} 478 479define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) { 480; CHECKLE-LABEL: i1or_vmov: 481; CHECKLE: @ %bb.0: @ %entry 482; CHECKLE-NEXT: cmp r0, #0 483; CHECKLE-NEXT: mov.w r1, #15 484; CHECKLE-NEXT: csetm r0, eq 485; CHECKLE-NEXT: orrs r0, r1 486; CHECKLE-NEXT: vmsr p0, r0 487; CHECKLE-NEXT: vpsel q0, q0, q1 488; CHECKLE-NEXT: bx lr 489; 490; CHECKBE-LABEL: i1or_vmov: 491; CHECKBE: @ %bb.0: @ %entry 492; CHECKBE-NEXT: cmp r0, #0 493; CHECKBE-NEXT: mov.w r1, #15 494; CHECKBE-NEXT: csetm r0, eq 495; CHECKBE-NEXT: vrev64.32 q2, q1 496; CHECKBE-NEXT: orrs r0, r1 497; CHECKBE-NEXT: vrev64.32 q1, q0 498; CHECKBE-NEXT: vmsr p0, r0 499; CHECKBE-NEXT: vpsel q1, q1, q2 500; CHECKBE-NEXT: vrev64.32 q0, q1 501; CHECKBE-NEXT: bx lr 502entry: 503 %c1 = icmp eq i32 %c, zeroinitializer 504 %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0 505 %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer 506 %l699 = or <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false> 507 %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b 508 ret <4 x i32> %s 509} 510