1; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
2
3; These tests could be improved by 'movs r0, #0' being rematerialized below the
4; test as 'mov.w r0, #0'.
5
6define i32 @f1(i32 %a, i32 %b) {
7    %nb = sub i32 0, %b
8    %tmp = icmp ne i32 %a, %nb
9    %ret = select i1 %tmp, i32 42, i32 24
10    ret i32 %ret
11}
12; CHECK-LABEL: f1:
13; CHECK: 	cmn	{{.*}}, r1
14
15define i32 @f2(i32 %a, i32 %b) {
16    %nb = sub i32 0, %b
17    %tmp = icmp ne i32 %nb, %a
18    %ret = select i1 %tmp, i32 42, i32 24
19    ret i32 %ret
20}
21; CHECK-LABEL: f2:
22; CHECK: 	cmn	{{.*}}, r1
23
24define i32 @f3(i32 %a, i32 %b) {
25    %nb = sub i32 0, %b
26    %tmp = icmp eq i32 %a, %nb
27    %ret = select i1 %tmp, i32 42, i32 24
28    ret i32 %ret
29}
30; CHECK-LABEL: f3:
31; CHECK: 	cmn	{{.*}}, r1
32
33define i32 @f4(i32 %a, i32 %b) {
34    %nb = sub i32 0, %b
35    %tmp = icmp eq i32 %nb, %a
36    %ret = select i1 %tmp, i32 42, i32 24
37    ret i32 %ret
38}
39; CHECK-LABEL: f4:
40; CHECK: 	cmn	{{.*}}, r1
41
42define i32 @f5(i32 %a, i32 %b) {
43    %tmp = shl i32 %b, 5
44    %nb = sub i32 0, %tmp
45    %tmp1 = icmp eq i32 %nb, %a
46    %ret = select i1 %tmp1, i32 42, i32 24
47    ret i32 %ret
48}
49; CHECK-LABEL: f5:
50; CHECK: 	cmn.w	{{.*}}, r1, lsl #5
51
52define i32 @f6(i32 %a, i32 %b) {
53    %tmp = lshr i32 %b, 6
54    %nb = sub i32 0, %tmp
55    %tmp1 = icmp ne i32 %nb, %a
56    %ret = select i1 %tmp1, i32 42, i32 24
57    ret i32 %ret
58}
59; CHECK-LABEL: f6:
60; CHECK: 	cmn.w	{{.*}}, r1, lsr #6
61
62define i32 @f7(i32 %a, i32 %b) {
63    %tmp = ashr i32 %b, 7
64    %nb = sub i32 0, %tmp
65    %tmp1 = icmp eq i32 %a, %nb
66    %ret = select i1 %tmp1, i32 42, i32 24
67    ret i32 %ret
68}
69; CHECK-LABEL: f7:
70; CHECK: 	cmn.w	{{.*}}, r1, asr #7
71
72define i32 @f8(i32 %a, i32 %b) {
73    %l8 = shl i32 %a, 24
74    %r8 = lshr i32 %a, 8
75    %tmp = or i32 %l8, %r8
76    %nb = sub i32 0, %tmp
77    %tmp1 = icmp ne i32 %a, %nb
78    %ret = select i1 %tmp1, i32 42, i32 24
79    ret i32 %ret
80}
81; CHECK-LABEL: f8:
82; CHECK: 	cmn.w	{{.*}}, {{.*}}, ror #8
83
84
85define void @f9(i32 %a, i32 %b) nounwind optsize {
86  tail call void asm sideeffect "cmn.w     r0, r1", ""() nounwind, !srcloc !0
87  ret void
88}
89
90!0 = !{i32 81}
91
92; CHECK-LABEL: f9:
93; CHECK: 	cmn.w	r0, r1
94