1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv7-none-eabi < %s | FileCheck %s 3 4define i1 @test_urem_odd(i13 %X) nounwind { 5; CHECK-LABEL: test_urem_odd: 6; CHECK: @ %bb.0: 7; CHECK-NEXT: movw r1, #3277 8; CHECK-NEXT: movw r2, #1639 9; CHECK-NEXT: muls r1, r0, r1 10; CHECK-NEXT: movs r0, #0 11; CHECK-NEXT: bfc r1, #13, #19 12; CHECK-NEXT: cmp r1, r2 13; CHECK-NEXT: it lo 14; CHECK-NEXT: movlo r0, #1 15; CHECK-NEXT: bx lr 16 %urem = urem i13 %X, 5 17 %cmp = icmp eq i13 %urem, 0 18 ret i1 %cmp 19} 20 21define i1 @test_urem_even(i27 %X) nounwind { 22; CHECK-LABEL: test_urem_even: 23; CHECK: @ %bb.0: 24; CHECK-NEXT: movw r1, #28087 25; CHECK-NEXT: movw r2, #18725 26; CHECK-NEXT: movt r1, #1755 27; CHECK-NEXT: movt r2, #146 28; CHECK-NEXT: muls r0, r1, r0 29; CHECK-NEXT: ubfx r1, r0, #1, #26 30; CHECK-NEXT: orr.w r0, r1, r0, lsl #26 31; CHECK-NEXT: bic r1, r0, #-134217728 32; CHECK-NEXT: movs r0, #0 33; CHECK-NEXT: cmp r1, r2 34; CHECK-NEXT: it lo 35; CHECK-NEXT: movlo r0, #1 36; CHECK-NEXT: bx lr 37 %urem = urem i27 %X, 14 38 %cmp = icmp eq i27 %urem, 0 39 ret i1 %cmp 40} 41 42define i1 @test_urem_odd_setne(i4 %X) nounwind { 43; CHECK-LABEL: test_urem_odd_setne: 44; CHECK: @ %bb.0: 45; CHECK-NEXT: movs r1, #13 46; CHECK-NEXT: muls r0, r1, r0 47; CHECK-NEXT: and r1, r0, #15 48; CHECK-NEXT: movs r0, #0 49; CHECK-NEXT: cmp r1, #3 50; CHECK-NEXT: it hi 51; CHECK-NEXT: movhi r0, #1 52; CHECK-NEXT: bx lr 53 %urem = urem i4 %X, 5 54 %cmp = icmp ne i4 %urem, 0 55 ret i1 %cmp 56} 57 58define i1 @test_urem_negative_odd(i9 %X) nounwind { 59; CHECK-LABEL: test_urem_negative_odd: 60; CHECK: @ %bb.0: 61; CHECK-NEXT: movw r1, #307 62; CHECK-NEXT: muls r1, r0, r1 63; CHECK-NEXT: movs r0, #0 64; CHECK-NEXT: bfc r1, #9, #23 65; CHECK-NEXT: cmp r1, #1 66; CHECK-NEXT: it hi 67; CHECK-NEXT: movhi r0, #1 68; CHECK-NEXT: bx lr 69 %urem = urem i9 %X, -5 70 %cmp = icmp ne i9 %urem, 0 71 ret i1 %cmp 72} 73 74define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind { 75; CHECK-LABEL: test_urem_vec: 76; CHECK: @ %bb.0: 77; CHECK-NEXT: vmov.16 d16[0], r0 78; CHECK-NEXT: vldr d17, .LCPI4_0 79; CHECK-NEXT: vmov.16 d16[1], r1 80; CHECK-NEXT: vldr d19, .LCPI4_3 81; CHECK-NEXT: vmov.16 d16[2], r2 82; CHECK-NEXT: vsub.i16 d16, d16, d17 83; CHECK-NEXT: vldr d17, .LCPI4_1 84; CHECK-NEXT: vmul.i16 d16, d16, d17 85; CHECK-NEXT: vldr d17, .LCPI4_2 86; CHECK-NEXT: vneg.s16 d17, d17 87; CHECK-NEXT: vshl.i16 d18, d16, #1 88; CHECK-NEXT: vbic.i16 d16, #0xf800 89; CHECK-NEXT: vshl.u16 d16, d16, d17 90; CHECK-NEXT: vshl.u16 d17, d18, d19 91; CHECK-NEXT: vorr d16, d16, d17 92; CHECK-NEXT: vldr d17, .LCPI4_4 93; CHECK-NEXT: vbic.i16 d16, #0xf800 94; CHECK-NEXT: vcgt.u16 d16, d16, d17 95; CHECK-NEXT: vmov.u16 r0, d16[0] 96; CHECK-NEXT: vmov.u16 r1, d16[1] 97; CHECK-NEXT: vmov.u16 r2, d16[2] 98; CHECK-NEXT: bx lr 99; CHECK-NEXT: .p2align 3 100; CHECK-NEXT: @ %bb.1: 101; CHECK-NEXT: .LCPI4_0: 102; CHECK-NEXT: .short 0 @ 0x0 103; CHECK-NEXT: .short 1 @ 0x1 104; CHECK-NEXT: .short 2 @ 0x2 105; CHECK-NEXT: .zero 2 106; CHECK-NEXT: .LCPI4_1: 107; CHECK-NEXT: .short 683 @ 0x2ab 108; CHECK-NEXT: .short 1463 @ 0x5b7 109; CHECK-NEXT: .short 819 @ 0x333 110; CHECK-NEXT: .zero 2 111; CHECK-NEXT: .LCPI4_2: 112; CHECK-NEXT: .short 1 @ 0x1 113; CHECK-NEXT: .short 0 @ 0x0 114; CHECK-NEXT: .short 0 @ 0x0 115; CHECK-NEXT: .short 0 @ 0x0 116; CHECK-NEXT: .LCPI4_3: 117; CHECK-NEXT: .short 9 @ 0x9 118; CHECK-NEXT: .short 10 @ 0xa 119; CHECK-NEXT: .short 10 @ 0xa 120; CHECK-NEXT: .short 10 @ 0xa 121; CHECK-NEXT: .LCPI4_4: 122; CHECK-NEXT: .short 341 @ 0x155 123; CHECK-NEXT: .short 292 @ 0x124 124; CHECK-NEXT: .short 1 @ 0x1 125; CHECK-NEXT: .short 0 @ 0x0 126 %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5> 127 %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2> 128 ret <3 x i1> %cmp 129} 130