1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s 3 4declare dso_local void @bar(i32) 5declare dso_local void @car(i32) 6declare dso_local void @dar(i32) 7declare dso_local void @ear(i32) 8declare dso_local void @far(i32) 9declare i1 @qux() 10 11@GHJK = dso_local global i32 0 12@HABC = dso_local global i32 0 13 14; BranchFolding should tail-merge the stores since they all precede 15; direct branches to the same place. 16 17define dso_local void @tail_merge_me() nounwind { 18; CHECK-LABEL: tail_merge_me: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: pushq %rax 21; CHECK-NEXT: callq qux@PLT 22; CHECK-NEXT: testb $1, %al 23; CHECK-NEXT: je .LBB0_1 24; CHECK-NEXT: # %bb.6: # %A 25; CHECK-NEXT: xorl %edi, %edi 26; CHECK-NEXT: callq bar 27; CHECK-NEXT: jmp .LBB0_4 28; CHECK-NEXT: .LBB0_1: # %next 29; CHECK-NEXT: callq qux@PLT 30; CHECK-NEXT: testb $1, %al 31; CHECK-NEXT: je .LBB0_3 32; CHECK-NEXT: # %bb.2: # %B 33; CHECK-NEXT: movl $1, %edi 34; CHECK-NEXT: callq car 35; CHECK-NEXT: jmp .LBB0_4 36; CHECK-NEXT: .LBB0_3: # %C 37; CHECK-NEXT: movl $2, %edi 38; CHECK-NEXT: callq dar 39; CHECK-NEXT: .LBB0_4: # %M 40; CHECK-NEXT: movl $0, GHJK(%rip) 41; CHECK-NEXT: movl $1, HABC(%rip) 42; CHECK-NEXT: callq qux@PLT 43; CHECK-NEXT: testb $1, %al 44; CHECK-NEXT: je .LBB0_5 45; CHECK-NEXT: # %bb.7: # %return 46; CHECK-NEXT: movl $1000, %edi # imm = 0x3E8 47; CHECK-NEXT: callq ear 48; CHECK-NEXT: popq %rax 49; CHECK-NEXT: retq 50; CHECK-NEXT: .LBB0_5: # %altret 51; CHECK-NEXT: movl $1001, %edi # imm = 0x3E9 52; CHECK-NEXT: callq far 53; CHECK-NEXT: popq %rax 54; CHECK-NEXT: retq 55entry: 56 %a = call i1 @qux() 57 br i1 %a, label %A, label %next 58next: 59 %b = call i1 @qux() 60 br i1 %b, label %B, label %C 61 62A: 63 call void @bar(i32 0) 64 store i32 0, i32* @GHJK 65 br label %M 66 67B: 68 call void @car(i32 1) 69 store i32 0, i32* @GHJK 70 br label %M 71 72C: 73 call void @dar(i32 2) 74 store i32 0, i32* @GHJK 75 br label %M 76 77M: 78 store i32 1, i32* @HABC 79 %c = call i1 @qux() 80 br i1 %c, label %return, label %altret 81 82return: 83 call void @ear(i32 1000) 84 ret void 85altret: 86 call void @far(i32 1001) 87 ret void 88} 89 90declare i8* @choose(i8*, i8*) 91 92; BranchFolding should tail-duplicate the indirect jump to avoid 93; redundant branching. 94 95define dso_local void @tail_duplicate_me() nounwind { 96; CHECK-LABEL: tail_duplicate_me: 97; CHECK: # %bb.0: # %entry 98; CHECK-NEXT: pushq %r14 99; CHECK-NEXT: pushq %rbx 100; CHECK-NEXT: pushq %rax 101; CHECK-NEXT: callq qux@PLT 102; CHECK-NEXT: movl $.Ltmp0, %edi 103; CHECK-NEXT: movl $.Ltmp1, %esi 104; CHECK-NEXT: movl %eax, %ebx 105; CHECK-NEXT: callq choose@PLT 106; CHECK-NEXT: movq %rax, %r14 107; CHECK-NEXT: testb $1, %bl 108; CHECK-NEXT: je .LBB1_1 109; CHECK-NEXT: # %bb.7: # %A 110; CHECK-NEXT: xorl %edi, %edi 111; CHECK-NEXT: callq bar 112; CHECK-NEXT: movl $0, GHJK(%rip) 113; CHECK-NEXT: jmpq *%r14 114; CHECK-NEXT: .Ltmp0: # Block address taken 115; CHECK-NEXT: .LBB1_4: # %return 116; CHECK-NEXT: movl $1000, %edi # imm = 0x3E8 117; CHECK-NEXT: callq ear 118; CHECK-NEXT: jmp .LBB1_5 119; CHECK-NEXT: .LBB1_1: # %next 120; CHECK-NEXT: callq qux@PLT 121; CHECK-NEXT: testb $1, %al 122; CHECK-NEXT: je .LBB1_3 123; CHECK-NEXT: # %bb.2: # %B 124; CHECK-NEXT: movl $1, %edi 125; CHECK-NEXT: callq car 126; CHECK-NEXT: movl $0, GHJK(%rip) 127; CHECK-NEXT: jmpq *%r14 128; CHECK-NEXT: .Ltmp1: # Block address taken 129; CHECK-NEXT: .LBB1_6: # %altret 130; CHECK-NEXT: movl $1001, %edi # imm = 0x3E9 131; CHECK-NEXT: callq far 132; CHECK-NEXT: .LBB1_5: # %return 133; CHECK-NEXT: addq $8, %rsp 134; CHECK-NEXT: popq %rbx 135; CHECK-NEXT: popq %r14 136; CHECK-NEXT: retq 137; CHECK-NEXT: .LBB1_3: # %C 138; CHECK-NEXT: movl $2, %edi 139; CHECK-NEXT: callq dar 140; CHECK-NEXT: movl $0, GHJK(%rip) 141; CHECK-NEXT: jmpq *%r14 142entry: 143 %a = call i1 @qux() 144 %c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return), 145 i8* blockaddress(@tail_duplicate_me, %altret)) 146 br i1 %a, label %A, label %next 147next: 148 %b = call i1 @qux() 149 br i1 %b, label %B, label %C 150 151A: 152 call void @bar(i32 0) 153 store i32 0, i32* @GHJK 154 br label %M 155 156B: 157 call void @car(i32 1) 158 store i32 0, i32* @GHJK 159 br label %M 160 161C: 162 call void @dar(i32 2) 163 store i32 0, i32* @GHJK 164 br label %M 165 166M: 167 indirectbr i8* %c, [label %return, label %altret] 168 169return: 170 call void @ear(i32 1000) 171 ret void 172altret: 173 call void @far(i32 1001) 174 ret void 175} 176 177; BranchFolding shouldn't try to merge the tails of two blocks 178; with only a branch in common, regardless of the fallthrough situation. 179 180define i1 @dont_merge_oddly(float* %result) nounwind { 181; CHECK-LABEL: dont_merge_oddly: 182; CHECK: # %bb.0: # %entry 183; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero 184; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero 185; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 186; CHECK-NEXT: ucomiss %xmm1, %xmm2 187; CHECK-NEXT: jbe .LBB2_3 188; CHECK-NEXT: # %bb.1: # %bb 189; CHECK-NEXT: ucomiss %xmm0, %xmm1 190; CHECK-NEXT: ja .LBB2_4 191; CHECK-NEXT: .LBB2_2: # %bb30 192; CHECK-NEXT: movb $1, %al 193; CHECK-NEXT: retq 194; CHECK-NEXT: .LBB2_3: # %bb21 195; CHECK-NEXT: ucomiss %xmm0, %xmm2 196; CHECK-NEXT: jbe .LBB2_2 197; CHECK-NEXT: .LBB2_4: # %bb26 198; CHECK-NEXT: xorl %eax, %eax 199; CHECK-NEXT: retq 200entry: 201 %tmp4 = getelementptr float, float* %result, i32 2 202 %tmp5 = load float, float* %tmp4, align 4 203 %tmp7 = getelementptr float, float* %result, i32 4 204 %tmp8 = load float, float* %tmp7, align 4 205 %tmp10 = getelementptr float, float* %result, i32 6 206 %tmp11 = load float, float* %tmp10, align 4 207 %tmp12 = fcmp olt float %tmp8, %tmp11 208 br i1 %tmp12, label %bb, label %bb21 209 210bb: 211 %tmp23469 = fcmp olt float %tmp5, %tmp8 212 br i1 %tmp23469, label %bb26, label %bb30 213 214bb21: 215 %tmp23 = fcmp olt float %tmp5, %tmp11 216 br i1 %tmp23, label %bb26, label %bb30 217 218bb26: 219 ret i1 0 220 221bb30: 222 ret i1 1 223} 224 225; Do any-size tail-merging when two candidate blocks will both require 226; an unconditional jump to complete a two-way conditional branch. 227; 228; This test only works when register allocation happens to use %rax for both 229; load addresses. 230 231%0 = type { %struct.rtx_def* } 232%struct.lang_decl = type opaque 233%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] } 234%struct.tree_decl = type { [24 x i8], i8*, i32, %union.tree_node*, i32, i8, i8, i8, i8, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %union..2anon, %0, %union.tree_node*, %struct.lang_decl* } 235%union..2anon = type { i32 } 236%union.rtunion = type { i8* } 237%union.tree_node = type { %struct.tree_decl } 238 239define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind { 240; CHECK-LABEL: c_expand_expr_stmt: 241; CHECK: # %bb.0: # %entry 242; CHECK-NEXT: pushq %rbx 243; CHECK-NEXT: xorl %eax, %eax 244; CHECK-NEXT: testb %al, %al 245; CHECK-NEXT: jne .LBB3_9 246; CHECK-NEXT: # %bb.1: # %entry 247; CHECK-NEXT: movb 0, %bl 248; CHECK-NEXT: xorl %eax, %eax 249; CHECK-NEXT: testb %al, %al 250; CHECK-NEXT: jne .LBB3_8 251; CHECK-NEXT: # %bb.2: # %bb.i 252; CHECK-NEXT: xorl %eax, %eax 253; CHECK-NEXT: testb %al, %al 254; CHECK-NEXT: je .LBB3_8 255; CHECK-NEXT: # %bb.3: # %lvalue_p.exit 256; CHECK-NEXT: movq 0, %rax 257; CHECK-NEXT: movzbl (%rax), %ecx 258; CHECK-NEXT: testl %ecx, %ecx 259; CHECK-NEXT: je .LBB3_10 260; CHECK-NEXT: # %bb.4: # %lvalue_p.exit 261; CHECK-NEXT: cmpl $2, %ecx 262; CHECK-NEXT: jne .LBB3_15 263; CHECK-NEXT: # %bb.5: # %bb.i1 264; CHECK-NEXT: movq 32(%rax), %rax 265; CHECK-NEXT: movzbl 16(%rax), %ecx 266; CHECK-NEXT: testl %ecx, %ecx 267; CHECK-NEXT: je .LBB3_13 268; CHECK-NEXT: # %bb.6: # %bb.i1 269; CHECK-NEXT: cmpl $2, %ecx 270; CHECK-NEXT: jne .LBB3_15 271; CHECK-NEXT: # %bb.7: # %bb.i.i 272; CHECK-NEXT: xorl %edi, %edi 273; CHECK-NEXT: callq lvalue_p@PLT 274; CHECK-NEXT: testl %eax, %eax 275; CHECK-NEXT: setne %al 276; CHECK-NEXT: jmp .LBB3_16 277; CHECK-NEXT: .LBB3_8: # %bb1 278; CHECK-NEXT: cmpb $23, %bl 279; CHECK-NEXT: .LBB3_9: # %bb3 280; CHECK-NEXT: .LBB3_15: 281; CHECK-NEXT: xorl %eax, %eax 282; CHECK-NEXT: .LBB3_16: # %lvalue_p.exit4 283; CHECK-NEXT: testb %al, %al 284; CHECK-NEXT: jne .LBB3_9 285; CHECK-NEXT: # %bb.17: # %lvalue_p.exit4 286; CHECK-NEXT: testb %bl, %bl 287; CHECK-NEXT: .LBB3_10: # %bb2.i3 288; CHECK-NEXT: movq 8(%rax), %rax 289; CHECK-NEXT: movb 16(%rax), %cl 290; CHECK-NEXT: xorl %eax, %eax 291; CHECK-NEXT: cmpb $23, %cl 292; CHECK-NEXT: je .LBB3_16 293; CHECK-NEXT: # %bb.11: # %bb2.i3 294; CHECK-NEXT: cmpb $16, %cl 295; CHECK-NEXT: je .LBB3_16 296; CHECK-NEXT: jmp .LBB3_9 297; CHECK-NEXT: .LBB3_13: # %bb2.i.i2 298; CHECK-NEXT: movq 8(%rax), %rax 299; CHECK-NEXT: movb 16(%rax), %cl 300; CHECK-NEXT: xorl %eax, %eax 301; CHECK-NEXT: cmpb $16, %cl 302; CHECK-NEXT: je .LBB3_16 303; CHECK-NEXT: # %bb.14: # %bb2.i.i2 304; CHECK-NEXT: cmpb $23, %cl 305; CHECK-NEXT: je .LBB3_16 306; CHECK-NEXT: jmp .LBB3_9 307entry: 308 %tmp4 = load i8, i8* null, align 8 ; <i8> [#uses=3] 309 switch i8 %tmp4, label %bb3 [ 310 i8 18, label %bb 311 ] 312 313bb: ; preds = %entry 314 switch i32 undef, label %bb1 [ 315 i32 0, label %bb2.i 316 i32 37, label %bb.i 317 ] 318 319bb.i: ; preds = %bb 320 switch i32 undef, label %bb1 [ 321 i32 0, label %lvalue_p.exit 322 ] 323 324bb2.i: ; preds = %bb 325 br label %bb3 326 327lvalue_p.exit: ; preds = %bb.i 328 %tmp21 = load %union.tree_node*, %union.tree_node** null, align 8 ; <%union.tree_node*> [#uses=3] 329 %tmp22 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1] 330 %tmp23 = load i8, i8* %tmp22, align 8 ; <i8> [#uses=1] 331 %tmp24 = zext i8 %tmp23 to i32 ; <i32> [#uses=1] 332 switch i32 %tmp24, label %lvalue_p.exit4 [ 333 i32 0, label %bb2.i3 334 i32 2, label %bb.i1 335 ] 336 337bb.i1: ; preds = %lvalue_p.exit 338 %tmp25 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1] 339 %tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1] 340 %tmp27 = load %union.tree_node*, %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2] 341 %tmp28 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1] 342 %tmp29 = load i8, i8* %tmp28, align 8 ; <i8> [#uses=1] 343 %tmp30 = zext i8 %tmp29 to i32 ; <i32> [#uses=1] 344 switch i32 %tmp30, label %lvalue_p.exit4 [ 345 i32 0, label %bb2.i.i2 346 i32 2, label %bb.i.i 347 ] 348 349bb.i.i: ; preds = %bb.i1 350 %tmp34 = tail call fastcc i32 @lvalue_p(%union.tree_node* null) nounwind ; <i32> [#uses=1] 351 %phitmp = icmp ne i32 %tmp34, 0 ; <i1> [#uses=1] 352 br label %lvalue_p.exit4 353 354bb2.i.i2: ; preds = %bb.i1 355 %tmp35 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1] 356 %tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1] 357 %tmp37 = load %union.tree_node*, %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1] 358 %tmp38 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1] 359 %tmp39 = load i8, i8* %tmp38, align 8 ; <i8> [#uses=1] 360 switch i8 %tmp39, label %bb2 [ 361 i8 16, label %lvalue_p.exit4 362 i8 23, label %lvalue_p.exit4 363 ] 364 365bb2.i3: ; preds = %lvalue_p.exit 366 %tmp40 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1] 367 %tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1] 368 %tmp42 = load %union.tree_node*, %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1] 369 %tmp43 = getelementptr inbounds %union.tree_node, %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1] 370 %tmp44 = load i8, i8* %tmp43, align 8 ; <i8> [#uses=1] 371 switch i8 %tmp44, label %bb2 [ 372 i8 16, label %lvalue_p.exit4 373 i8 23, label %lvalue_p.exit4 374 ] 375 376lvalue_p.exit4: ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit 377 %tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1] 378 %tmp46 = icmp eq i8 %tmp4, 0 ; <i1> [#uses=1] 379 %or.cond = or i1 %tmp45, %tmp46 ; <i1> [#uses=1] 380 br i1 %or.cond, label %bb2, label %bb3 381 382bb1: ; preds = %bb2.i.i, %bb.i, %bb 383 %.old = icmp eq i8 %tmp4, 23 ; <i1> [#uses=1] 384 br i1 %.old, label %bb2, label %bb3 385 386bb2: ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2 387 br label %bb3 388 389bb3: ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry 390 %expr_addr.0 = phi %union.tree_node* [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <%union.tree_node*> [#uses=0] 391 unreachable 392} 393 394declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly 395 396declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind 397 398 399; If one tail merging candidate falls through into the other, 400; tail merging is likely profitable regardless of how few 401; instructions are involved. This function should have only 402; one ret instruction. 403 404define dso_local void @foo(i1* %V) nounwind { 405; CHECK-LABEL: foo: 406; CHECK: # %bb.0: # %entry 407; CHECK-NEXT: testq %rdi, %rdi 408; CHECK-NEXT: je .LBB4_2 409; CHECK-NEXT: # %bb.1: # %bb 410; CHECK-NEXT: pushq %rax 411; CHECK-NEXT: callq func 412; CHECK-NEXT: popq %rax 413; CHECK-NEXT: .LBB4_2: # %return 414; CHECK-NEXT: retq 415entry: 416 %t0 = icmp eq i1* %V, null 417 br i1 %t0, label %return, label %bb 418 419bb: 420 call void @func() 421 ret void 422 423return: 424 ret void 425} 426 427declare dso_local void @func() 428 429; one - One instruction may be tail-duplicated even with optsize. 430 431@XYZ = external dso_local global i32 432 433declare dso_local void @tail_call_me() 434 435define dso_local void @one(i32 %v) nounwind optsize { 436; CHECK-LABEL: one: 437; CHECK: # %bb.0: # %entry 438; CHECK-NEXT: testl %edi, %edi 439; CHECK-NEXT: je .LBB5_3 440; CHECK-NEXT: # %bb.1: # %bby 441; CHECK-NEXT: cmpl $16, %edi 442; CHECK-NEXT: je .LBB5_4 443; CHECK-NEXT: # %bb.2: # %bb7 444; CHECK-NEXT: jmp tail_call_me # TAILCALL 445; CHECK-NEXT: .LBB5_3: # %bbx 446; CHECK-NEXT: cmpl $128, %edi 447; CHECK-NEXT: jne tail_call_me # TAILCALL 448; CHECK-NEXT: .LBB5_4: # %return 449; CHECK-NEXT: retq 450entry: 451 %0 = icmp eq i32 %v, 0 452 br i1 %0, label %bbx, label %bby 453 454bby: 455 switch i32 %v, label %bb7 [ 456 i32 16, label %return 457 ] 458 459bb7: 460 tail call void @tail_call_me() 461 ret void 462 463bbx: 464 switch i32 %v, label %bb12 [ 465 i32 128, label %return 466 ] 467 468bb12: 469 tail call void @tail_call_me() 470 ret void 471 472return: 473 ret void 474} 475 476define dso_local void @one_pgso(i32 %v) nounwind !prof !14 { 477; CHECK-LABEL: one_pgso: 478; CHECK: # %bb.0: # %entry 479; CHECK-NEXT: testl %edi, %edi 480; CHECK-NEXT: je .LBB6_3 481; CHECK-NEXT: # %bb.1: # %bby 482; CHECK-NEXT: cmpl $16, %edi 483; CHECK-NEXT: je .LBB6_4 484; CHECK-NEXT: # %bb.2: # %bb7 485; CHECK-NEXT: jmp tail_call_me # TAILCALL 486; CHECK-NEXT: .LBB6_3: # %bbx 487; CHECK-NEXT: cmpl $128, %edi 488; CHECK-NEXT: jne tail_call_me # TAILCALL 489; CHECK-NEXT: .LBB6_4: # %return 490; CHECK-NEXT: retq 491entry: 492 %0 = icmp eq i32 %v, 0 493 br i1 %0, label %bbx, label %bby 494 495bby: 496 switch i32 %v, label %bb7 [ 497 i32 16, label %return 498 ] 499 500bb7: 501 tail call void @tail_call_me() 502 ret void 503 504bbx: 505 switch i32 %v, label %bb12 [ 506 i32 128, label %return 507 ] 508 509bb12: 510 tail call void @tail_call_me() 511 ret void 512 513return: 514 ret void 515} 516 517; two - Same as one, but with two instructions in the common 518; tail instead of one. This is too much to be merged, given 519; the optsize attribute. 520 521define dso_local void @two() nounwind optsize { 522; CHECK-LABEL: two: 523; CHECK: # %bb.0: # %entry 524; CHECK-NEXT: xorl %eax, %eax 525; CHECK-NEXT: testb %al, %al 526; CHECK-NEXT: xorl %eax, %eax 527; CHECK-NEXT: testb %al, %al 528; CHECK-NEXT: je .LBB7_1 529; CHECK-NEXT: # %bb.2: # %return 530; CHECK-NEXT: retq 531; CHECK-NEXT: .LBB7_1: # %bb7 532; CHECK-NEXT: movl $0, XYZ(%rip) 533; CHECK-NEXT: movl $1, XYZ(%rip) 534entry: 535 %0 = icmp eq i32 undef, 0 536 br i1 %0, label %bbx, label %bby 537 538bby: 539 switch i32 undef, label %bb7 [ 540 i32 16, label %return 541 ] 542 543bb7: 544 store volatile i32 0, i32* @XYZ 545 store volatile i32 1, i32* @XYZ 546 unreachable 547 548bbx: 549 switch i32 undef, label %bb12 [ 550 i32 128, label %return 551 ] 552 553bb12: 554 store volatile i32 0, i32* @XYZ 555 store volatile i32 1, i32* @XYZ 556 unreachable 557 558return: 559 ret void 560} 561 562define dso_local void @two_pgso() nounwind !prof !14 { 563; CHECK-LABEL: two_pgso: 564; CHECK: # %bb.0: # %entry 565; CHECK-NEXT: xorl %eax, %eax 566; CHECK-NEXT: testb %al, %al 567; CHECK-NEXT: xorl %eax, %eax 568; CHECK-NEXT: testb %al, %al 569; CHECK-NEXT: je .LBB8_1 570; CHECK-NEXT: # %bb.2: # %return 571; CHECK-NEXT: retq 572; CHECK-NEXT: .LBB8_1: # %bb7 573; CHECK-NEXT: movl $0, XYZ(%rip) 574; CHECK-NEXT: movl $1, XYZ(%rip) 575entry: 576 %0 = icmp eq i32 undef, 0 577 br i1 %0, label %bbx, label %bby 578 579bby: 580 switch i32 undef, label %bb7 [ 581 i32 16, label %return 582 ] 583 584bb7: 585 store volatile i32 0, i32* @XYZ 586 store volatile i32 1, i32* @XYZ 587 unreachable 588 589bbx: 590 switch i32 undef, label %bb12 [ 591 i32 128, label %return 592 ] 593 594bb12: 595 store volatile i32 0, i32* @XYZ 596 store volatile i32 1, i32* @XYZ 597 unreachable 598 599return: 600 ret void 601} 602 603; two_minsize - Same as two, but with minsize instead of optsize. 604 605define dso_local void @two_minsize() nounwind minsize { 606; CHECK-LABEL: two_minsize: 607; CHECK: # %bb.0: # %entry 608; CHECK-NEXT: xorl %eax, %eax 609; CHECK-NEXT: testb %al, %al 610; CHECK-NEXT: xorl %eax, %eax 611; CHECK-NEXT: testb %al, %al 612; CHECK-NEXT: je .LBB9_1 613; CHECK-NEXT: # %bb.2: # %return 614; CHECK-NEXT: retq 615; CHECK-NEXT: .LBB9_1: # %bb7 616; CHECK-NEXT: movl $0, XYZ(%rip) 617; CHECK-NEXT: movl $1, XYZ(%rip) 618entry: 619 %0 = icmp eq i32 undef, 0 620 br i1 %0, label %bbx, label %bby 621 622bby: 623 switch i32 undef, label %bb7 [ 624 i32 16, label %return 625 ] 626 627bb7: 628 store volatile i32 0, i32* @XYZ 629 store volatile i32 1, i32* @XYZ 630 unreachable 631 632bbx: 633 switch i32 undef, label %bb12 [ 634 i32 128, label %return 635 ] 636 637bb12: 638 store volatile i32 0, i32* @XYZ 639 store volatile i32 1, i32* @XYZ 640 unreachable 641 642return: 643 ret void 644} 645 646; two_nosize - Same as two, but without the optsize attribute. 647; Now two instructions are enough to be tail-duplicated. 648 649define dso_local void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind { 650; CHECK-LABEL: two_nosize: 651; CHECK: # %bb.0: # %entry 652; CHECK-NEXT: testl %edi, %edi 653; CHECK-NEXT: je .LBB10_3 654; CHECK-NEXT: # %bb.1: # %bby 655; CHECK-NEXT: testl %esi, %esi 656; CHECK-NEXT: je .LBB10_4 657; CHECK-NEXT: # %bb.2: # %bb7 658; CHECK-NEXT: movl $0, XYZ(%rip) 659; CHECK-NEXT: jmp tail_call_me # TAILCALL 660; CHECK-NEXT: .LBB10_3: # %bbx 661; CHECK-NEXT: cmpl $-1, %edx 662; CHECK-NEXT: je .LBB10_4 663; CHECK-NEXT: # %bb.5: # %bb12 664; CHECK-NEXT: movl $0, XYZ(%rip) 665; CHECK-NEXT: jmp tail_call_me # TAILCALL 666; CHECK-NEXT: .LBB10_4: # %return 667; CHECK-NEXT: retq 668entry: 669 %0 = icmp eq i32 %x, 0 670 br i1 %0, label %bbx, label %bby 671 672bby: 673 switch i32 %y, label %bb7 [ 674 i32 0, label %return 675 ] 676 677bb7: 678 store volatile i32 0, i32* @XYZ 679 tail call void @tail_call_me() 680 ret void 681 682bbx: 683 switch i32 %z, label %bb12 [ 684 i32 -1, label %return 685 ] 686 687bb12: 688 store volatile i32 0, i32* @XYZ 689 tail call void @tail_call_me() 690 ret void 691 692return: 693 ret void 694} 695 696; Tail-merging should merge the two ret instructions since one side 697; can fall-through into the ret and the other side has to branch anyway. 698 699define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone { 700; CHECK-LABEL: TESTE: 701; CHECK: # %bb.0: # %entry 702; CHECK-NEXT: testq %rdi, %rdi 703; CHECK-NEXT: movl $1, %eax 704; CHECK-NEXT: cmovgq %rdi, %rax 705; CHECK-NEXT: testq %rsi, %rsi 706; CHECK-NEXT: jle .LBB11_2 707; CHECK-NEXT: # %bb.1: # %bb.nph 708; CHECK-NEXT: imulq %rdi, %rsi 709; CHECK-NEXT: movq %rsi, %rax 710; CHECK-NEXT: .LBB11_2: # %for.end 711; CHECK-NEXT: retq 712entry: 713 %cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1] 714 %varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1] 715 %cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1] 716 br i1 %cmp410, label %for.end, label %bb.nph 717 718bb.nph: ; preds = %entry 719 %tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1] 720 ret i64 %tmp15 721 722for.end: ; preds = %entry 723 ret i64 %varx.0 724} 725 726; We should tail merge small blocks that don't end in a tail call or return 727; instruction. Those blocks are typically unreachable and will be placed 728; out-of-line after the main return, so we should try to eliminate as many of 729; them as possible. 730 731declare dso_local void @abort() 732define dso_local void @merge_aborts() { 733; CHECK-LABEL: merge_aborts: 734; CHECK: # %bb.0: # %entry 735; CHECK-NEXT: pushq %rax 736; CHECK-NEXT: .cfi_def_cfa_offset 16 737; CHECK-NEXT: callq qux@PLT 738; CHECK-NEXT: testb $1, %al 739; CHECK-NEXT: je .LBB12_5 740; CHECK-NEXT: # %bb.1: # %cont1 741; CHECK-NEXT: callq qux@PLT 742; CHECK-NEXT: testb $1, %al 743; CHECK-NEXT: je .LBB12_5 744; CHECK-NEXT: # %bb.2: # %cont2 745; CHECK-NEXT: callq qux@PLT 746; CHECK-NEXT: testb $1, %al 747; CHECK-NEXT: je .LBB12_5 748; CHECK-NEXT: # %bb.3: # %cont3 749; CHECK-NEXT: callq qux@PLT 750; CHECK-NEXT: testb $1, %al 751; CHECK-NEXT: je .LBB12_5 752; CHECK-NEXT: # %bb.4: # %cont4 753; CHECK-NEXT: popq %rax 754; CHECK-NEXT: .cfi_def_cfa_offset 8 755; CHECK-NEXT: retq 756; CHECK-NEXT: .LBB12_5: # %abort1 757; CHECK-NEXT: .cfi_def_cfa_offset 16 758; CHECK-NEXT: callq abort 759entry: 760 %c1 = call i1 @qux() 761 br i1 %c1, label %cont1, label %abort1 762abort1: 763 call void @abort() 764 unreachable 765cont1: 766 %c2 = call i1 @qux() 767 br i1 %c2, label %cont2, label %abort2 768abort2: 769 call void @abort() 770 unreachable 771cont2: 772 %c3 = call i1 @qux() 773 br i1 %c3, label %cont3, label %abort3 774abort3: 775 call void @abort() 776 unreachable 777cont3: 778 %c4 = call i1 @qux() 779 br i1 %c4, label %cont4, label %abort4 780abort4: 781 call void @abort() 782 unreachable 783cont4: 784 ret void 785} 786 787; Use alternating abort functions so that the blocks we wish to merge are not 788; layout successors during branch folding. 789 790declare dso_local void @alt_abort() 791 792define dso_local void @merge_alternating_aborts() { 793; CHECK-LABEL: merge_alternating_aborts: 794; CHECK: # %bb.0: # %entry 795; CHECK-NEXT: pushq %rax 796; CHECK-NEXT: .cfi_def_cfa_offset 16 797; CHECK-NEXT: callq qux@PLT 798; CHECK-NEXT: testb $1, %al 799; CHECK-NEXT: je .LBB13_5 800; CHECK-NEXT: # %bb.1: # %cont1 801; CHECK-NEXT: callq qux@PLT 802; CHECK-NEXT: testb $1, %al 803; CHECK-NEXT: je .LBB13_6 804; CHECK-NEXT: # %bb.2: # %cont2 805; CHECK-NEXT: callq qux@PLT 806; CHECK-NEXT: testb $1, %al 807; CHECK-NEXT: je .LBB13_5 808; CHECK-NEXT: # %bb.3: # %cont3 809; CHECK-NEXT: callq qux@PLT 810; CHECK-NEXT: testb $1, %al 811; CHECK-NEXT: je .LBB13_6 812; CHECK-NEXT: # %bb.4: # %cont4 813; CHECK-NEXT: popq %rax 814; CHECK-NEXT: .cfi_def_cfa_offset 8 815; CHECK-NEXT: retq 816; CHECK-NEXT: .LBB13_5: # %abort1 817; CHECK-NEXT: .cfi_def_cfa_offset 16 818; CHECK-NEXT: callq abort 819; CHECK-NEXT: .LBB13_6: # %abort2 820; CHECK-NEXT: callq alt_abort 821entry: 822 %c1 = call i1 @qux() 823 br i1 %c1, label %cont1, label %abort1 824abort1: 825 call void @abort() 826 unreachable 827cont1: 828 %c2 = call i1 @qux() 829 br i1 %c2, label %cont2, label %abort2 830abort2: 831 call void @alt_abort() 832 unreachable 833cont2: 834 %c3 = call i1 @qux() 835 br i1 %c3, label %cont3, label %abort3 836abort3: 837 call void @abort() 838 unreachable 839cont3: 840 %c4 = call i1 @qux() 841 br i1 %c4, label %cont4, label %abort4 842abort4: 843 call void @alt_abort() 844 unreachable 845cont4: 846 ret void 847} 848 849; This triggers a situation where a new block (bb4 is split) is created and then 850; would be passed to the PGSO interface llvm::shouldOptimizeForSize(). 851@GV = dso_local global i32 0 852define dso_local void @bfi_new_block_pgso(i32 %c) nounwind { 853; CHECK-LABEL: bfi_new_block_pgso: 854; CHECK: # %bb.0: # %entry 855; CHECK-NEXT: testl %edi, %edi 856; CHECK-NEXT: je .LBB14_4 857; CHECK-NEXT: # %bb.1: # %bb1 858; CHECK-NEXT: pushq %rax 859; CHECK-NEXT: cmpl $16, %edi 860; CHECK-NEXT: je .LBB14_6 861; CHECK-NEXT: # %bb.2: # %bb1 862; CHECK-NEXT: cmpl $17, %edi 863; CHECK-NEXT: je .LBB14_7 864; CHECK-NEXT: # %bb.3: # %bb4 865; CHECK-NEXT: popq %rax 866; CHECK-NEXT: jmp tail_call_me # TAILCALL 867; CHECK-NEXT: .LBB14_4: # %bb5 868; CHECK-NEXT: cmpl $128, %edi 869; CHECK-NEXT: jne .LBB14_8 870; CHECK-NEXT: # %bb.5: # %return 871; CHECK-NEXT: retq 872; CHECK-NEXT: .LBB14_6: # %bb3 873; CHECK-NEXT: movl $0, GV(%rip) 874; CHECK-NEXT: .LBB14_7: # %bb4 875; CHECK-NEXT: callq func 876; CHECK-NEXT: popq %rax 877; CHECK-NEXT: .LBB14_8: # %bb6 878; CHECK-NEXT: jmp tail_call_me # TAILCALL 879entry: 880 %0 = icmp eq i32 %c, 0 881 br i1 %0, label %bb5, label %bb1 882 883bb1: 884 switch i32 %c, label %bb4 [ 885 i32 16, label %bb3 886 i32 17, label %bb2 887 ] 888 889bb2: 890 call void @func() 891 br label %bb4 892 893bb3: 894 store i32 0, i32* @GV 895 call void @func() 896 br label %bb4 897 898bb4: 899 tail call void @tail_call_me() 900 br label %return 901 902bb5: 903 switch i32 %c, label %bb6 [ 904 i32 128, label %return 905 ] 906 907bb6: 908 tail call void @tail_call_me() 909 br label %return 910 911return: 912 ret void 913} 914 915!llvm.module.flags = !{!0} 916!0 = !{i32 1, !"ProfileSummary", !1} 917!1 = !{!2, !3, !4, !5, !6, !7, !8, !9} 918!2 = !{!"ProfileFormat", !"InstrProf"} 919!3 = !{!"TotalCount", i64 10000} 920!4 = !{!"MaxCount", i64 10} 921!5 = !{!"MaxInternalCount", i64 1} 922!6 = !{!"MaxFunctionCount", i64 1000} 923!7 = !{!"NumCounts", i64 3} 924!8 = !{!"NumFunctions", i64 3} 925!9 = !{!"DetailedSummary", !10} 926!10 = !{!11, !12, !13} 927!11 = !{i32 10000, i64 100, i32 1} 928!12 = !{i32 999000, i64 100, i32 1} 929!13 = !{i32 999999, i64 1, i32 2} 930!14 = !{!"function_entry_count", i64 0} 931