1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M3 3# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M4 4# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M5 5 6st2 {v0.s, v1.s}[0], [sp] 7st2 {v0.2s, v1.2s}, [sp] 8 9st2 {v0.d, v1.d}[0], [sp] 10st2 {v0.2d, v1.2d}, [sp] 11 12st2 {v0.s, v1.s}[0], [sp], #8 13st2 {v0.2s, v1.2s}, [sp], #16 14 15st2 {v0.d, v1.d}[0], [sp], #16 16st2 {v0.2d, v1.2d}, [sp], #32 17 18st2 {v0.s, v1.s}[0], [sp], x0 19st2 {v0.2s, v1.2s}, [sp], x0 20 21st2 {v0.d, v1.d}[0], [sp], x0 22st2 {v0.2d, v1.2d}, [sp], x0 23 24# ALL: Iterations: 100 25# ALL-NEXT: Instructions: 1200 26 27# M3-NEXT: Total Cycles: 8703 28# M3-NEXT: Total uOps: 5400 29 30# M4-NEXT: Total Cycles: 2403 31# M4-NEXT: Total uOps: 2300 32 33# M5-NEXT: Total Cycles: 2403 34# M5-NEXT: Total uOps: 2000 35 36# ALL: Dispatch Width: 6 37 38# M3-NEXT: uOps Per Cycle: 0.62 39# M3-NEXT: IPC: 0.14 40# M3-NEXT: Block RThroughput: 40.5 41 42# M4-NEXT: uOps Per Cycle: 0.96 43# M4-NEXT: IPC: 0.50 44# M4-NEXT: Block RThroughput: 7.5 45 46# M5-NEXT: uOps Per Cycle: 0.83 47# M5-NEXT: IPC: 0.50 48# M5-NEXT: Block RThroughput: 7.5 49 50# ALL: Instruction Info: 51# ALL-NEXT: [1]: #uOps 52# ALL-NEXT: [2]: Latency 53# ALL-NEXT: [3]: RThroughput 54# ALL-NEXT: [4]: MayLoad 55# ALL-NEXT: [5]: MayStore 56# ALL-NEXT: [6]: HasSideEffects (U) 57 58# ALL: [1] [2] [3] [4] [5] [6] Instructions: 59 60# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp] 61# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp] 62# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp] 63# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp] 64# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp], #8 65# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp], #16 66# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp], #16 67# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp], #32 68# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp], x0 69# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp], x0 70# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp], x0 71# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp], x0 72 73# M4-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp] 74# M4-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp] 75# M4-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp] 76# M4-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp] 77# M4-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], #8 78# M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], #16 79# M4-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], #16 80# M4-NEXT: 3 2 1.00 * st2 { v0.2d, v1.2d }, [sp], #32 81# M4-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], x0 82# M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x0 83# M4-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], x0 84# M4-NEXT: 3 2 1.00 * st2 { v0.2d, v1.2d }, [sp], x0 85 86# M5-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp] 87# M5-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp] 88# M5-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp] 89# M5-NEXT: 1 2 1.00 * st2 { v0.2d, v1.2d }, [sp] 90# M5-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], #8 91# M5-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], #16 92# M5-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], #16 93# M5-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp], #32 94# M5-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], x0 95# M5-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x0 96# M5-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], x0 97# M5-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp], x0 98