1; RUN: llc -verify-machineinstrs < %s | FileCheck --check-prefix=P8 --check-prefix=CHECK %s 2; RUN: llc -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck --check-prefix=P9 --check-prefix=CHECK %s 3target datalayout = "e-m:e-i64:64-n32:64" 4target triple = "powerpc64le-unknown-linux-gnu" 5 6; CHECK-LABEL: lshr: 7; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64 8; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64 9; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5 10; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]] 11; CHECK-DAG: srd [[R4:[0-9]+]], 4, [[R1]] 12; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]] 13; CHECK-DAG: or 3, [[R5]], [[R4]] 14; CHECK-DAG: srd 4, 4, 5 15; CHECK: blr 16define i128 @lshr(i128 %x, i128 %y) { 17 %r = lshr i128 %x, %y 18 ret i128 %r 19} 20; CHECK-LABEL: ashr: 21; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64 22; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64 23; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5 24; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]] 25; CHECK-DAG: srad [[R4:[0-9]+]], 4, [[R1]] 26; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]] 27; CHECK-DAG: cmpwi [[R1]], 1 28; CHECK-DAG: srad 4, 4, 5 29; CHECK-DAG: isel 3, [[R5]], [[R4]], 0 30; CHECK: blr 31define i128 @ashr(i128 %x, i128 %y) { 32 %r = ashr i128 %x, %y 33 ret i128 %r 34} 35; CHECK-LABEL: shl: 36; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64 37; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64 38; CHECK-DAG: sld [[R2:[0-9]+]], 4, 5 39; CHECK-DAG: srd [[R3:[0-9]+]], 3, [[R0]] 40; CHECK-DAG: sld [[R4:[0-9]+]], 3, [[R1]] 41; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]] 42; CHECK-DAG: or 4, [[R5]], [[R4]] 43; CHECK-DAG: sld 3, 3, 5 44; CHECK: blr 45define i128 @shl(i128 %x, i128 %y) { 46 %r = shl i128 %x, %y 47 ret i128 %r 48} 49 50; CHECK-LABEL: shl_v1i128: 51; P8-NOT: {{\b}}vslo 52; P8-NOT: {{\b}}vsl 53; P9-DAG: vslo 54; P9-DAG: vspltb 55; P9: vsl 56; P9-NOT: {{\b}}sld 57; P9-NOT: {{\b}}srd 58; CHECK: blr 59define i128 @shl_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 { 60entry: 61 %0 = insertelement <1 x i128> undef, i128 %arg, i32 0 62 %1 = insertelement <1 x i128> undef, i128 %amt, i32 0 63 %2 = shl <1 x i128> %0, %1 64 %retval = extractelement <1 x i128> %2, i32 0 65 ret i128 %retval 66} 67 68; CHECK-LABEL: lshr_v1i128: 69; P8-NOT: {{\b}}vsro 70; P8-NOT: {{\b}}vsr 71; P9-DAG: vsro 72; P9-DAG: vspltb 73; P9: vsr 74; P9-NOT: {{\b}}srd 75; P9-NOT: {{\b}}sld 76; CHECK: blr 77define i128 @lshr_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 { 78entry: 79 %0 = insertelement <1 x i128> undef, i128 %arg, i32 0 80 %1 = insertelement <1 x i128> undef, i128 %amt, i32 0 81 %2 = lshr <1 x i128> %0, %1 82 %retval = extractelement <1 x i128> %2, i32 0 83 ret i128 %retval 84} 85 86; Arithmetic shift right is not available as an operation on the vector registers. 87; CHECK-LABEL: ashr_v1i128: 88; CHECK-NOT: {{\b}}vsro 89; CHECK-NOT: {{\b}}vsr 90; CHECK: blr 91define i128 @ashr_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 { 92entry: 93 %0 = insertelement <1 x i128> undef, i128 %arg, i32 0 94 %1 = insertelement <1 x i128> undef, i128 %amt, i32 0 95 %2 = ashr <1 x i128> %0, %1 96 %retval = extractelement <1 x i128> %2, i32 0 97 ret i128 %retval 98} 99