1 //===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAG::LegalizeVectors method.
11 //
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
21 //
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
27 //
28 //===----------------------------------------------------------------------===//
29
30 #include "llvm/ADT/APInt.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineMemOperand.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/TargetLowering.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/MachineValueType.h"
44 #include "llvm/Support/MathExtras.h"
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49
50 using namespace llvm;
51
52 #define DEBUG_TYPE "legalizevectorops"
53
54 namespace {
55
56 class VectorLegalizer {
57 SelectionDAG& DAG;
58 const TargetLowering &TLI;
59 bool Changed = false; // Keep track of whether anything changed
60
61 /// For nodes that are of legal width, and that have more than one use, this
62 /// map indicates what regularized operand to use. This allows us to avoid
63 /// legalizing the same thing more than once.
64 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
65
66 /// Adds a node to the translation cache.
AddLegalizedOperand(SDValue From,SDValue To)67 void AddLegalizedOperand(SDValue From, SDValue To) {
68 LegalizedNodes.insert(std::make_pair(From, To));
69 // If someone requests legalization of the new node, return itself.
70 if (From != To)
71 LegalizedNodes.insert(std::make_pair(To, To));
72 }
73
74 /// Legalizes the given node.
75 SDValue LegalizeOp(SDValue Op);
76
77 /// Assuming the node is legal, "legalize" the results.
78 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
79
80 /// Implements unrolling a VSETCC.
81 SDValue UnrollVSETCC(SDValue Op);
82
83 /// Implement expand-based legalization of vector operations.
84 ///
85 /// This is just a high-level routine to dispatch to specific code paths for
86 /// operations to legalize them.
87 SDValue Expand(SDValue Op);
88
89 /// Implements expansion for FP_TO_UINT; falls back to UnrollVectorOp if
90 /// FP_TO_SINT isn't legal.
91 SDValue ExpandFP_TO_UINT(SDValue Op);
92
93 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
94 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
95 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
96
97 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
98 SDValue ExpandSEXTINREG(SDValue Op);
99
100 /// Implement expansion for ANY_EXTEND_VECTOR_INREG.
101 ///
102 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
103 /// type. The contents of the bits in the extended part of each element are
104 /// undef.
105 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
106
107 /// Implement expansion for SIGN_EXTEND_VECTOR_INREG.
108 ///
109 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
110 /// type, then shifts left and arithmetic shifts right to introduce a sign
111 /// extension.
112 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
113
114 /// Implement expansion for ZERO_EXTEND_VECTOR_INREG.
115 ///
116 /// Shuffles the low lanes of the operand into place and blends zeros into
117 /// the remaining lanes, finally bitcasting to the proper type.
118 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
119
120 /// Implement expand-based legalization of ABS vector operations.
121 /// If following expanding is legal/custom then do it:
122 /// (ABS x) --> (XOR (ADD x, (SRA x, sizeof(x)-1)), (SRA x, sizeof(x)-1))
123 /// else unroll the operation.
124 SDValue ExpandABS(SDValue Op);
125
126 /// Expand bswap of vectors into a shuffle if legal.
127 SDValue ExpandBSWAP(SDValue Op);
128
129 /// Implement vselect in terms of XOR, AND, OR when blend is not
130 /// supported by the target.
131 SDValue ExpandVSELECT(SDValue Op);
132 SDValue ExpandSELECT(SDValue Op);
133 SDValue ExpandLoad(SDValue Op);
134 SDValue ExpandStore(SDValue Op);
135 SDValue ExpandFNEG(SDValue Op);
136 SDValue ExpandFSUB(SDValue Op);
137 SDValue ExpandBITREVERSE(SDValue Op);
138 SDValue ExpandCTPOP(SDValue Op);
139 SDValue ExpandCTLZ(SDValue Op);
140 SDValue ExpandCTTZ(SDValue Op);
141 SDValue ExpandFunnelShift(SDValue Op);
142 SDValue ExpandROT(SDValue Op);
143 SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
144 SDValue ExpandAddSubSat(SDValue Op);
145 SDValue ExpandStrictFPOp(SDValue Op);
146
147 /// Implements vector promotion.
148 ///
149 /// This is essentially just bitcasting the operands to a different type and
150 /// bitcasting the result back to the original type.
151 SDValue Promote(SDValue Op);
152
153 /// Implements [SU]INT_TO_FP vector promotion.
154 ///
155 /// This is a [zs]ext of the input operand to a larger integer type.
156 SDValue PromoteINT_TO_FP(SDValue Op);
157
158 /// Implements FP_TO_[SU]INT vector promotion of the result type.
159 ///
160 /// It is promoted to a larger integer type. The result is then
161 /// truncated back to the original type.
162 SDValue PromoteFP_TO_INT(SDValue Op);
163
164 public:
VectorLegalizer(SelectionDAG & dag)165 VectorLegalizer(SelectionDAG& dag) :
166 DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
167
168 /// Begin legalizer the vector operations in the DAG.
169 bool Run();
170 };
171
172 } // end anonymous namespace
173
Run()174 bool VectorLegalizer::Run() {
175 // Before we start legalizing vector nodes, check if there are any vectors.
176 bool HasVectors = false;
177 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
178 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
179 // Check if the values of the nodes contain vectors. We don't need to check
180 // the operands because we are going to check their values at some point.
181 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
182 J != E; ++J)
183 HasVectors |= J->isVector();
184
185 // If we found a vector node we can start the legalization.
186 if (HasVectors)
187 break;
188 }
189
190 // If this basic block has no vectors then no need to legalize vectors.
191 if (!HasVectors)
192 return false;
193
194 // The legalize process is inherently a bottom-up recursive process (users
195 // legalize their uses before themselves). Given infinite stack space, we
196 // could just start legalizing on the root and traverse the whole graph. In
197 // practice however, this causes us to run out of stack space on large basic
198 // blocks. To avoid this problem, compute an ordering of the nodes where each
199 // node is only legalized after all of its operands are legalized.
200 DAG.AssignTopologicalOrder();
201 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
202 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
203 LegalizeOp(SDValue(&*I, 0));
204
205 // Finally, it's possible the root changed. Get the new root.
206 SDValue OldRoot = DAG.getRoot();
207 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
208 DAG.setRoot(LegalizedNodes[OldRoot]);
209
210 LegalizedNodes.clear();
211
212 // Remove dead nodes now.
213 DAG.RemoveDeadNodes();
214
215 return Changed;
216 }
217
TranslateLegalizeResults(SDValue Op,SDValue Result)218 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
219 // Generic legalization: just pass the operand through.
220 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
221 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
222 return Result.getValue(Op.getResNo());
223 }
224
LegalizeOp(SDValue Op)225 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
226 // Note that LegalizeOp may be reentered even from single-use nodes, which
227 // means that we always must cache transformed nodes.
228 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
229 if (I != LegalizedNodes.end()) return I->second;
230
231 SDNode* Node = Op.getNode();
232
233 // Legalize the operands
234 SmallVector<SDValue, 8> Ops;
235 for (const SDValue &Op : Node->op_values())
236 Ops.push_back(LegalizeOp(Op));
237
238 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops),
239 Op.getResNo());
240
241 if (Op.getOpcode() == ISD::LOAD) {
242 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
243 ISD::LoadExtType ExtType = LD->getExtensionType();
244 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
245 LLVM_DEBUG(dbgs() << "\nLegalizing extending vector load: ";
246 Node->dump(&DAG));
247 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
248 LD->getMemoryVT())) {
249 default: llvm_unreachable("This action is not supported yet!");
250 case TargetLowering::Legal:
251 return TranslateLegalizeResults(Op, Result);
252 case TargetLowering::Custom:
253 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
254 assert(Lowered->getNumValues() == Op->getNumValues() &&
255 "Unexpected number of results");
256 if (Lowered != Result) {
257 // Make sure the new code is also legal.
258 Lowered = LegalizeOp(Lowered);
259 Changed = true;
260 }
261 return TranslateLegalizeResults(Op, Lowered);
262 }
263 LLVM_FALLTHROUGH;
264 case TargetLowering::Expand:
265 Changed = true;
266 return LegalizeOp(ExpandLoad(Op));
267 }
268 }
269 } else if (Op.getOpcode() == ISD::STORE) {
270 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
271 EVT StVT = ST->getMemoryVT();
272 MVT ValVT = ST->getValue().getSimpleValueType();
273 if (StVT.isVector() && ST->isTruncatingStore()) {
274 LLVM_DEBUG(dbgs() << "\nLegalizing truncating vector store: ";
275 Node->dump(&DAG));
276 switch (TLI.getTruncStoreAction(ValVT, StVT)) {
277 default: llvm_unreachable("This action is not supported yet!");
278 case TargetLowering::Legal:
279 return TranslateLegalizeResults(Op, Result);
280 case TargetLowering::Custom: {
281 SDValue Lowered = TLI.LowerOperation(Result, DAG);
282 if (Lowered != Result) {
283 // Make sure the new code is also legal.
284 Lowered = LegalizeOp(Lowered);
285 Changed = true;
286 }
287 return TranslateLegalizeResults(Op, Lowered);
288 }
289 case TargetLowering::Expand:
290 Changed = true;
291 return LegalizeOp(ExpandStore(Op));
292 }
293 }
294 }
295
296 bool HasVectorValue = false;
297 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
298 J != E;
299 ++J)
300 HasVectorValue |= J->isVector();
301 if (!HasVectorValue)
302 return TranslateLegalizeResults(Op, Result);
303
304 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
305 switch (Op.getOpcode()) {
306 default:
307 return TranslateLegalizeResults(Op, Result);
308 case ISD::STRICT_FADD:
309 case ISD::STRICT_FSUB:
310 case ISD::STRICT_FMUL:
311 case ISD::STRICT_FDIV:
312 case ISD::STRICT_FREM:
313 case ISD::STRICT_FSQRT:
314 case ISD::STRICT_FMA:
315 case ISD::STRICT_FPOW:
316 case ISD::STRICT_FPOWI:
317 case ISD::STRICT_FSIN:
318 case ISD::STRICT_FCOS:
319 case ISD::STRICT_FEXP:
320 case ISD::STRICT_FEXP2:
321 case ISD::STRICT_FLOG:
322 case ISD::STRICT_FLOG10:
323 case ISD::STRICT_FLOG2:
324 case ISD::STRICT_FRINT:
325 case ISD::STRICT_FNEARBYINT:
326 case ISD::STRICT_FMAXNUM:
327 case ISD::STRICT_FMINNUM:
328 case ISD::STRICT_FCEIL:
329 case ISD::STRICT_FFLOOR:
330 case ISD::STRICT_FROUND:
331 case ISD::STRICT_FTRUNC:
332 // These pseudo-ops get legalized as if they were their non-strict
333 // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
334 // is also legal, but if ISD::FSQRT requires expansion then so does
335 // ISD::STRICT_FSQRT.
336 Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
337 Node->getValueType(0));
338 break;
339 case ISD::ADD:
340 case ISD::SUB:
341 case ISD::MUL:
342 case ISD::MULHS:
343 case ISD::MULHU:
344 case ISD::SDIV:
345 case ISD::UDIV:
346 case ISD::SREM:
347 case ISD::UREM:
348 case ISD::SDIVREM:
349 case ISD::UDIVREM:
350 case ISD::FADD:
351 case ISD::FSUB:
352 case ISD::FMUL:
353 case ISD::FDIV:
354 case ISD::FREM:
355 case ISD::AND:
356 case ISD::OR:
357 case ISD::XOR:
358 case ISD::SHL:
359 case ISD::SRA:
360 case ISD::SRL:
361 case ISD::FSHL:
362 case ISD::FSHR:
363 case ISD::ROTL:
364 case ISD::ROTR:
365 case ISD::ABS:
366 case ISD::BSWAP:
367 case ISD::BITREVERSE:
368 case ISD::CTLZ:
369 case ISD::CTTZ:
370 case ISD::CTLZ_ZERO_UNDEF:
371 case ISD::CTTZ_ZERO_UNDEF:
372 case ISD::CTPOP:
373 case ISD::SELECT:
374 case ISD::VSELECT:
375 case ISD::SELECT_CC:
376 case ISD::SETCC:
377 case ISD::ZERO_EXTEND:
378 case ISD::ANY_EXTEND:
379 case ISD::TRUNCATE:
380 case ISD::SIGN_EXTEND:
381 case ISD::FP_TO_SINT:
382 case ISD::FP_TO_UINT:
383 case ISD::FNEG:
384 case ISD::FABS:
385 case ISD::FMINNUM:
386 case ISD::FMAXNUM:
387 case ISD::FMINNUM_IEEE:
388 case ISD::FMAXNUM_IEEE:
389 case ISD::FMINIMUM:
390 case ISD::FMAXIMUM:
391 case ISD::FCOPYSIGN:
392 case ISD::FSQRT:
393 case ISD::FSIN:
394 case ISD::FCOS:
395 case ISD::FPOWI:
396 case ISD::FPOW:
397 case ISD::FLOG:
398 case ISD::FLOG2:
399 case ISD::FLOG10:
400 case ISD::FEXP:
401 case ISD::FEXP2:
402 case ISD::FCEIL:
403 case ISD::FTRUNC:
404 case ISD::FRINT:
405 case ISD::FNEARBYINT:
406 case ISD::FROUND:
407 case ISD::FFLOOR:
408 case ISD::FP_ROUND:
409 case ISD::FP_EXTEND:
410 case ISD::FMA:
411 case ISD::SIGN_EXTEND_INREG:
412 case ISD::ANY_EXTEND_VECTOR_INREG:
413 case ISD::SIGN_EXTEND_VECTOR_INREG:
414 case ISD::ZERO_EXTEND_VECTOR_INREG:
415 case ISD::SMIN:
416 case ISD::SMAX:
417 case ISD::UMIN:
418 case ISD::UMAX:
419 case ISD::SMUL_LOHI:
420 case ISD::UMUL_LOHI:
421 case ISD::FCANONICALIZE:
422 case ISD::SADDSAT:
423 case ISD::UADDSAT:
424 case ISD::SSUBSAT:
425 case ISD::USUBSAT:
426 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
427 break;
428 case ISD::SMULFIX: {
429 unsigned Scale = Node->getConstantOperandVal(2);
430 Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
431 Node->getValueType(0), Scale);
432 break;
433 }
434 case ISD::FP_ROUND_INREG:
435 Action = TLI.getOperationAction(Node->getOpcode(),
436 cast<VTSDNode>(Node->getOperand(1))->getVT());
437 break;
438 case ISD::SINT_TO_FP:
439 case ISD::UINT_TO_FP:
440 Action = TLI.getOperationAction(Node->getOpcode(),
441 Node->getOperand(0).getValueType());
442 break;
443 }
444
445 LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
446
447 switch (Action) {
448 default: llvm_unreachable("This action is not supported yet!");
449 case TargetLowering::Promote:
450 Result = Promote(Op);
451 Changed = true;
452 break;
453 case TargetLowering::Legal:
454 LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
455 break;
456 case TargetLowering::Custom: {
457 LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
458 if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
459 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
460 Result = Tmp1;
461 break;
462 }
463 LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
464 LLVM_FALLTHROUGH;
465 }
466 case TargetLowering::Expand:
467 Result = Expand(Op);
468 }
469
470 // Make sure that the generated code is itself legal.
471 if (Result != Op) {
472 Result = LegalizeOp(Result);
473 Changed = true;
474 }
475
476 // Note that LegalizeOp may be reentered even from single-use nodes, which
477 // means that we always must cache transformed nodes.
478 AddLegalizedOperand(Op, Result);
479 return Result;
480 }
481
Promote(SDValue Op)482 SDValue VectorLegalizer::Promote(SDValue Op) {
483 // For a few operations there is a specific concept for promotion based on
484 // the operand's type.
485 switch (Op.getOpcode()) {
486 case ISD::SINT_TO_FP:
487 case ISD::UINT_TO_FP:
488 // "Promote" the operation by extending the operand.
489 return PromoteINT_TO_FP(Op);
490 case ISD::FP_TO_UINT:
491 case ISD::FP_TO_SINT:
492 // Promote the operation by extending the operand.
493 return PromoteFP_TO_INT(Op);
494 }
495
496 // There are currently two cases of vector promotion:
497 // 1) Bitcasting a vector of integers to a different type to a vector of the
498 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
499 // 2) Extending a vector of floats to a vector of the same number of larger
500 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
501 MVT VT = Op.getSimpleValueType();
502 assert(Op.getNode()->getNumValues() == 1 &&
503 "Can't promote a vector with multiple results!");
504 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
505 SDLoc dl(Op);
506 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
507
508 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
509 if (Op.getOperand(j).getValueType().isVector())
510 if (Op.getOperand(j)
511 .getValueType()
512 .getVectorElementType()
513 .isFloatingPoint() &&
514 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
515 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
516 else
517 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
518 else
519 Operands[j] = Op.getOperand(j);
520 }
521
522 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
523 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
524 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
525 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
526 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
527 else
528 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
529 }
530
PromoteINT_TO_FP(SDValue Op)531 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
532 // INT_TO_FP operations may require the input operand be promoted even
533 // when the type is otherwise legal.
534 MVT VT = Op.getOperand(0).getSimpleValueType();
535 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
536 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
537 "Vectors have different number of elements!");
538
539 SDLoc dl(Op);
540 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
541
542 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
543 ISD::SIGN_EXTEND;
544 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
545 if (Op.getOperand(j).getValueType().isVector())
546 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
547 else
548 Operands[j] = Op.getOperand(j);
549 }
550
551 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
552 }
553
554 // For FP_TO_INT we promote the result type to a vector type with wider
555 // elements and then truncate the result. This is different from the default
556 // PromoteVector which uses bitcast to promote thus assumning that the
557 // promoted vector type has the same overall size.
PromoteFP_TO_INT(SDValue Op)558 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
559 MVT VT = Op.getSimpleValueType();
560 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
561 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
562 "Vectors have different number of elements!");
563
564 unsigned NewOpc = Op->getOpcode();
565 // Change FP_TO_UINT to FP_TO_SINT if possible.
566 // TODO: Should we only do this if FP_TO_UINT itself isn't legal?
567 if (NewOpc == ISD::FP_TO_UINT &&
568 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
569 NewOpc = ISD::FP_TO_SINT;
570
571 SDLoc dl(Op);
572 SDValue Promoted = DAG.getNode(NewOpc, dl, NVT, Op.getOperand(0));
573
574 // Assert that the converted value fits in the original type. If it doesn't
575 // (eg: because the value being converted is too big), then the result of the
576 // original operation was undefined anyway, so the assert is still correct.
577 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
578 : ISD::AssertSext,
579 dl, NVT, Promoted,
580 DAG.getValueType(VT.getScalarType()));
581 return DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
582 }
583
ExpandLoad(SDValue Op)584 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
585 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
586
587 EVT SrcVT = LD->getMemoryVT();
588 EVT SrcEltVT = SrcVT.getScalarType();
589 unsigned NumElem = SrcVT.getVectorNumElements();
590
591 SDValue NewChain;
592 SDValue Value;
593 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
594 SDLoc dl(Op);
595
596 SmallVector<SDValue, 8> Vals;
597 SmallVector<SDValue, 8> LoadChains;
598
599 EVT DstEltVT = LD->getValueType(0).getScalarType();
600 SDValue Chain = LD->getChain();
601 SDValue BasePTR = LD->getBasePtr();
602 ISD::LoadExtType ExtType = LD->getExtensionType();
603
604 // When elements in a vector is not byte-addressable, we cannot directly
605 // load each element by advancing pointer, which could only address bytes.
606 // Instead, we load all significant words, mask bits off, and concatenate
607 // them to form each element. Finally, they are extended to destination
608 // scalar type to build the destination vector.
609 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
610
611 assert(WideVT.isRound() &&
612 "Could not handle the sophisticated case when the widest integer is"
613 " not power of 2.");
614 assert(WideVT.bitsGE(SrcEltVT) &&
615 "Type is not legalized?");
616
617 unsigned WideBytes = WideVT.getStoreSize();
618 unsigned Offset = 0;
619 unsigned RemainingBytes = SrcVT.getStoreSize();
620 SmallVector<SDValue, 8> LoadVals;
621 while (RemainingBytes > 0) {
622 SDValue ScalarLoad;
623 unsigned LoadBytes = WideBytes;
624
625 if (RemainingBytes >= LoadBytes) {
626 ScalarLoad =
627 DAG.getLoad(WideVT, dl, Chain, BasePTR,
628 LD->getPointerInfo().getWithOffset(Offset),
629 MinAlign(LD->getAlignment(), Offset),
630 LD->getMemOperand()->getFlags(), LD->getAAInfo());
631 } else {
632 EVT LoadVT = WideVT;
633 while (RemainingBytes < LoadBytes) {
634 LoadBytes >>= 1; // Reduce the load size by half.
635 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
636 }
637 ScalarLoad =
638 DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
639 LD->getPointerInfo().getWithOffset(Offset), LoadVT,
640 MinAlign(LD->getAlignment(), Offset),
641 LD->getMemOperand()->getFlags(), LD->getAAInfo());
642 }
643
644 RemainingBytes -= LoadBytes;
645 Offset += LoadBytes;
646
647 BasePTR = DAG.getObjectPtrOffset(dl, BasePTR, LoadBytes);
648
649 LoadVals.push_back(ScalarLoad.getValue(0));
650 LoadChains.push_back(ScalarLoad.getValue(1));
651 }
652
653 // Extract bits, pack and extend/trunc them into destination type.
654 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
655 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
656
657 unsigned BitOffset = 0;
658 unsigned WideIdx = 0;
659 unsigned WideBits = WideVT.getSizeInBits();
660
661 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
662 SDValue Lo, Hi, ShAmt;
663
664 if (BitOffset < WideBits) {
665 ShAmt = DAG.getConstant(
666 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
667 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
668 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
669 }
670
671 BitOffset += SrcEltBits;
672 if (BitOffset >= WideBits) {
673 WideIdx++;
674 BitOffset -= WideBits;
675 if (BitOffset > 0) {
676 ShAmt = DAG.getConstant(
677 SrcEltBits - BitOffset, dl,
678 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
679 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
680 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
681 }
682 }
683
684 if (Hi.getNode())
685 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
686
687 switch (ExtType) {
688 default: llvm_unreachable("Unknown extended-load op!");
689 case ISD::EXTLOAD:
690 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
691 break;
692 case ISD::ZEXTLOAD:
693 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
694 break;
695 case ISD::SEXTLOAD:
696 ShAmt =
697 DAG.getConstant(WideBits - SrcEltBits, dl,
698 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
699 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
700 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
701 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
702 break;
703 }
704 Vals.push_back(Lo);
705 }
706
707 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
708 Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
709 } else {
710 SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
711 // Skip past MERGE_VALUE node if known.
712 if (Scalarized->getOpcode() == ISD::MERGE_VALUES) {
713 NewChain = Scalarized.getOperand(1);
714 Value = Scalarized.getOperand(0);
715 } else {
716 NewChain = Scalarized.getValue(1);
717 Value = Scalarized.getValue(0);
718 }
719 }
720
721 AddLegalizedOperand(Op.getValue(0), Value);
722 AddLegalizedOperand(Op.getValue(1), NewChain);
723
724 return (Op.getResNo() ? NewChain : Value);
725 }
726
ExpandStore(SDValue Op)727 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
728 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
729 SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
730 AddLegalizedOperand(Op, TF);
731 return TF;
732 }
733
Expand(SDValue Op)734 SDValue VectorLegalizer::Expand(SDValue Op) {
735 switch (Op->getOpcode()) {
736 case ISD::SIGN_EXTEND_INREG:
737 return ExpandSEXTINREG(Op);
738 case ISD::ANY_EXTEND_VECTOR_INREG:
739 return ExpandANY_EXTEND_VECTOR_INREG(Op);
740 case ISD::SIGN_EXTEND_VECTOR_INREG:
741 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
742 case ISD::ZERO_EXTEND_VECTOR_INREG:
743 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
744 case ISD::BSWAP:
745 return ExpandBSWAP(Op);
746 case ISD::VSELECT:
747 return ExpandVSELECT(Op);
748 case ISD::SELECT:
749 return ExpandSELECT(Op);
750 case ISD::FP_TO_UINT:
751 return ExpandFP_TO_UINT(Op);
752 case ISD::UINT_TO_FP:
753 return ExpandUINT_TO_FLOAT(Op);
754 case ISD::FNEG:
755 return ExpandFNEG(Op);
756 case ISD::FSUB:
757 return ExpandFSUB(Op);
758 case ISD::SETCC:
759 return UnrollVSETCC(Op);
760 case ISD::ABS:
761 return ExpandABS(Op);
762 case ISD::BITREVERSE:
763 return ExpandBITREVERSE(Op);
764 case ISD::CTPOP:
765 return ExpandCTPOP(Op);
766 case ISD::CTLZ:
767 case ISD::CTLZ_ZERO_UNDEF:
768 return ExpandCTLZ(Op);
769 case ISD::CTTZ:
770 case ISD::CTTZ_ZERO_UNDEF:
771 return ExpandCTTZ(Op);
772 case ISD::FSHL:
773 case ISD::FSHR:
774 return ExpandFunnelShift(Op);
775 case ISD::ROTL:
776 case ISD::ROTR:
777 return ExpandROT(Op);
778 case ISD::FMINNUM:
779 case ISD::FMAXNUM:
780 return ExpandFMINNUM_FMAXNUM(Op);
781 case ISD::USUBSAT:
782 case ISD::SSUBSAT:
783 case ISD::UADDSAT:
784 case ISD::SADDSAT:
785 return ExpandAddSubSat(Op);
786 case ISD::STRICT_FADD:
787 case ISD::STRICT_FSUB:
788 case ISD::STRICT_FMUL:
789 case ISD::STRICT_FDIV:
790 case ISD::STRICT_FREM:
791 case ISD::STRICT_FSQRT:
792 case ISD::STRICT_FMA:
793 case ISD::STRICT_FPOW:
794 case ISD::STRICT_FPOWI:
795 case ISD::STRICT_FSIN:
796 case ISD::STRICT_FCOS:
797 case ISD::STRICT_FEXP:
798 case ISD::STRICT_FEXP2:
799 case ISD::STRICT_FLOG:
800 case ISD::STRICT_FLOG10:
801 case ISD::STRICT_FLOG2:
802 case ISD::STRICT_FRINT:
803 case ISD::STRICT_FNEARBYINT:
804 case ISD::STRICT_FMAXNUM:
805 case ISD::STRICT_FMINNUM:
806 case ISD::STRICT_FCEIL:
807 case ISD::STRICT_FFLOOR:
808 case ISD::STRICT_FROUND:
809 case ISD::STRICT_FTRUNC:
810 return ExpandStrictFPOp(Op);
811 default:
812 return DAG.UnrollVectorOp(Op.getNode());
813 }
814 }
815
ExpandSELECT(SDValue Op)816 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
817 // Lower a select instruction where the condition is a scalar and the
818 // operands are vectors. Lower this select to VSELECT and implement it
819 // using XOR AND OR. The selector bit is broadcasted.
820 EVT VT = Op.getValueType();
821 SDLoc DL(Op);
822
823 SDValue Mask = Op.getOperand(0);
824 SDValue Op1 = Op.getOperand(1);
825 SDValue Op2 = Op.getOperand(2);
826
827 assert(VT.isVector() && !Mask.getValueType().isVector()
828 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
829
830 // If we can't even use the basic vector operations of
831 // AND,OR,XOR, we will have to scalarize the op.
832 // Notice that the operation may be 'promoted' which means that it is
833 // 'bitcasted' to another type which is handled.
834 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
835 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
836 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
837 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
838 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
839 return DAG.UnrollVectorOp(Op.getNode());
840
841 // Generate a mask operand.
842 EVT MaskTy = VT.changeVectorElementTypeToInteger();
843
844 // What is the size of each element in the vector mask.
845 EVT BitTy = MaskTy.getScalarType();
846
847 Mask = DAG.getSelect(DL, BitTy, Mask,
848 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
849 BitTy),
850 DAG.getConstant(0, DL, BitTy));
851
852 // Broadcast the mask so that the entire vector is all-one or all zero.
853 Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
854
855 // Bitcast the operands to be the same type as the mask.
856 // This is needed when we select between FP types because
857 // the mask is a vector of integers.
858 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
859 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
860
861 SDValue AllOnes = DAG.getConstant(
862 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
863 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
864
865 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
866 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
867 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
868 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
869 }
870
ExpandSEXTINREG(SDValue Op)871 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
872 EVT VT = Op.getValueType();
873
874 // Make sure that the SRA and SHL instructions are available.
875 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
876 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
877 return DAG.UnrollVectorOp(Op.getNode());
878
879 SDLoc DL(Op);
880 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
881
882 unsigned BW = VT.getScalarSizeInBits();
883 unsigned OrigBW = OrigTy.getScalarSizeInBits();
884 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
885
886 Op = Op.getOperand(0);
887 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
888 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
889 }
890
891 // Generically expand a vector anyext in register to a shuffle of the relevant
892 // lanes into the appropriate locations, with other lanes left undef.
ExpandANY_EXTEND_VECTOR_INREG(SDValue Op)893 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
894 SDLoc DL(Op);
895 EVT VT = Op.getValueType();
896 int NumElements = VT.getVectorNumElements();
897 SDValue Src = Op.getOperand(0);
898 EVT SrcVT = Src.getValueType();
899 int NumSrcElements = SrcVT.getVectorNumElements();
900
901 // Build a base mask of undef shuffles.
902 SmallVector<int, 16> ShuffleMask;
903 ShuffleMask.resize(NumSrcElements, -1);
904
905 // Place the extended lanes into the correct locations.
906 int ExtLaneScale = NumSrcElements / NumElements;
907 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
908 for (int i = 0; i < NumElements; ++i)
909 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
910
911 return DAG.getNode(
912 ISD::BITCAST, DL, VT,
913 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
914 }
915
ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op)916 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
917 SDLoc DL(Op);
918 EVT VT = Op.getValueType();
919 SDValue Src = Op.getOperand(0);
920 EVT SrcVT = Src.getValueType();
921
922 // First build an any-extend node which can be legalized above when we
923 // recurse through it.
924 Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
925
926 // Now we need sign extend. Do this by shifting the elements. Even if these
927 // aren't legal operations, they have a better chance of being legalized
928 // without full scalarization than the sign extension does.
929 unsigned EltWidth = VT.getScalarSizeInBits();
930 unsigned SrcEltWidth = SrcVT.getScalarSizeInBits();
931 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
932 return DAG.getNode(ISD::SRA, DL, VT,
933 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
934 ShiftAmount);
935 }
936
937 // Generically expand a vector zext in register to a shuffle of the relevant
938 // lanes into the appropriate locations, a blend of zero into the high bits,
939 // and a bitcast to the wider element type.
ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op)940 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
941 SDLoc DL(Op);
942 EVT VT = Op.getValueType();
943 int NumElements = VT.getVectorNumElements();
944 SDValue Src = Op.getOperand(0);
945 EVT SrcVT = Src.getValueType();
946 int NumSrcElements = SrcVT.getVectorNumElements();
947
948 // Build up a zero vector to blend into this one.
949 SDValue Zero = DAG.getConstant(0, DL, SrcVT);
950
951 // Shuffle the incoming lanes into the correct position, and pull all other
952 // lanes from the zero vector.
953 SmallVector<int, 16> ShuffleMask;
954 ShuffleMask.reserve(NumSrcElements);
955 for (int i = 0; i < NumSrcElements; ++i)
956 ShuffleMask.push_back(i);
957
958 int ExtLaneScale = NumSrcElements / NumElements;
959 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
960 for (int i = 0; i < NumElements; ++i)
961 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
962
963 return DAG.getNode(ISD::BITCAST, DL, VT,
964 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
965 }
966
createBSWAPShuffleMask(EVT VT,SmallVectorImpl<int> & ShuffleMask)967 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
968 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
969 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
970 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
971 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
972 }
973
ExpandBSWAP(SDValue Op)974 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
975 EVT VT = Op.getValueType();
976
977 // Generate a byte wise shuffle mask for the BSWAP.
978 SmallVector<int, 16> ShuffleMask;
979 createBSWAPShuffleMask(VT, ShuffleMask);
980 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
981
982 // Only emit a shuffle if the mask is legal.
983 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
984 return DAG.UnrollVectorOp(Op.getNode());
985
986 SDLoc DL(Op);
987 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
988 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
989 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
990 }
991
ExpandBITREVERSE(SDValue Op)992 SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
993 EVT VT = Op.getValueType();
994
995 // If we have the scalar operation, it's probably cheaper to unroll it.
996 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
997 return DAG.UnrollVectorOp(Op.getNode());
998
999 // If the vector element width is a whole number of bytes, test if its legal
1000 // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
1001 // vector. This greatly reduces the number of bit shifts necessary.
1002 unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
1003 if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {
1004 SmallVector<int, 16> BSWAPMask;
1005 createBSWAPShuffleMask(VT, BSWAPMask);
1006
1007 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, BSWAPMask.size());
1008 if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) &&
1009 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
1010 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
1011 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
1012 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
1013 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
1014 SDLoc DL(Op);
1015 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
1016 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
1017 BSWAPMask);
1018 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
1019 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1020 }
1021 }
1022
1023 // If we have the appropriate vector bit operations, it is better to use them
1024 // than unrolling and expanding each component.
1025 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
1026 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
1027 !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
1028 !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1029 return DAG.UnrollVectorOp(Op.getNode());
1030
1031 // Let LegalizeDAG handle this later.
1032 return Op;
1033 }
1034
ExpandVSELECT(SDValue Op)1035 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
1036 // Implement VSELECT in terms of XOR, AND, OR
1037 // on platforms which do not support blend natively.
1038 SDLoc DL(Op);
1039
1040 SDValue Mask = Op.getOperand(0);
1041 SDValue Op1 = Op.getOperand(1);
1042 SDValue Op2 = Op.getOperand(2);
1043
1044 EVT VT = Mask.getValueType();
1045
1046 // If we can't even use the basic vector operations of
1047 // AND,OR,XOR, we will have to scalarize the op.
1048 // Notice that the operation may be 'promoted' which means that it is
1049 // 'bitcasted' to another type which is handled.
1050 // This operation also isn't safe with AND, OR, XOR when the boolean
1051 // type is 0/1 as we need an all ones vector constant to mask with.
1052 // FIXME: Sign extend 1 to all ones if thats legal on the target.
1053 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1054 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
1055 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
1056 TLI.getBooleanContents(Op1.getValueType()) !=
1057 TargetLowering::ZeroOrNegativeOneBooleanContent)
1058 return DAG.UnrollVectorOp(Op.getNode());
1059
1060 // If the mask and the type are different sizes, unroll the vector op. This
1061 // can occur when getSetCCResultType returns something that is different in
1062 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
1063 if (VT.getSizeInBits() != Op1.getValueSizeInBits())
1064 return DAG.UnrollVectorOp(Op.getNode());
1065
1066 // Bitcast the operands to be the same type as the mask.
1067 // This is needed when we select between FP types because
1068 // the mask is a vector of integers.
1069 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
1070 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
1071
1072 SDValue AllOnes = DAG.getConstant(
1073 APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT);
1074 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
1075
1076 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
1077 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
1078 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
1079 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
1080 }
1081
ExpandABS(SDValue Op)1082 SDValue VectorLegalizer::ExpandABS(SDValue Op) {
1083 // Attempt to expand using TargetLowering.
1084 SDValue Result;
1085 if (TLI.expandABS(Op.getNode(), Result, DAG))
1086 return Result;
1087
1088 // Otherwise go ahead and unroll.
1089 return DAG.UnrollVectorOp(Op.getNode());
1090 }
1091
ExpandFP_TO_UINT(SDValue Op)1092 SDValue VectorLegalizer::ExpandFP_TO_UINT(SDValue Op) {
1093 // Attempt to expand using TargetLowering.
1094 SDValue Result;
1095 if (TLI.expandFP_TO_UINT(Op.getNode(), Result, DAG))
1096 return Result;
1097
1098 // Otherwise go ahead and unroll.
1099 return DAG.UnrollVectorOp(Op.getNode());
1100 }
1101
ExpandUINT_TO_FLOAT(SDValue Op)1102 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
1103 EVT VT = Op.getOperand(0).getValueType();
1104 SDLoc DL(Op);
1105
1106 // Attempt to expand using TargetLowering.
1107 SDValue Result;
1108 if (TLI.expandUINT_TO_FP(Op.getNode(), Result, DAG))
1109 return Result;
1110
1111 // Make sure that the SINT_TO_FP and SRL instructions are available.
1112 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
1113 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
1114 return DAG.UnrollVectorOp(Op.getNode());
1115
1116 unsigned BW = VT.getScalarSizeInBits();
1117 assert((BW == 64 || BW == 32) &&
1118 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
1119
1120 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
1121
1122 // Constants to clear the upper part of the word.
1123 // Notice that we can also use SHL+SHR, but using a constant is slightly
1124 // faster on x86.
1125 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
1126 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1127
1128 // Two to the power of half-word-size.
1129 SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, Op.getValueType());
1130
1131 // Clear upper part of LO, lower HI
1132 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1133 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1134
1135 // Convert hi and lo to floats
1136 // Convert the hi part back to the upper values
1137 // TODO: Can any fast-math-flags be set on these nodes?
1138 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1139 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1140 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1141
1142 // Add the two halves
1143 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1144 }
1145
ExpandFNEG(SDValue Op)1146 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1147 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1148 SDLoc DL(Op);
1149 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1150 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1151 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1152 Zero, Op.getOperand(0));
1153 }
1154 return DAG.UnrollVectorOp(Op.getNode());
1155 }
1156
ExpandFSUB(SDValue Op)1157 SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
1158 // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1159 // we can defer this to operation legalization where it will be lowered as
1160 // a+(-b).
1161 EVT VT = Op.getValueType();
1162 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
1163 TLI.isOperationLegalOrCustom(ISD::FADD, VT))
1164 return Op; // Defer to LegalizeDAG
1165
1166 return DAG.UnrollVectorOp(Op.getNode());
1167 }
1168
ExpandCTPOP(SDValue Op)1169 SDValue VectorLegalizer::ExpandCTPOP(SDValue Op) {
1170 SDValue Result;
1171 if (TLI.expandCTPOP(Op.getNode(), Result, DAG))
1172 return Result;
1173
1174 return DAG.UnrollVectorOp(Op.getNode());
1175 }
1176
ExpandCTLZ(SDValue Op)1177 SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
1178 SDValue Result;
1179 if (TLI.expandCTLZ(Op.getNode(), Result, DAG))
1180 return Result;
1181
1182 return DAG.UnrollVectorOp(Op.getNode());
1183 }
1184
ExpandCTTZ(SDValue Op)1185 SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {
1186 SDValue Result;
1187 if (TLI.expandCTTZ(Op.getNode(), Result, DAG))
1188 return Result;
1189
1190 return DAG.UnrollVectorOp(Op.getNode());
1191 }
1192
ExpandFunnelShift(SDValue Op)1193 SDValue VectorLegalizer::ExpandFunnelShift(SDValue Op) {
1194 SDValue Result;
1195 if (TLI.expandFunnelShift(Op.getNode(), Result, DAG))
1196 return Result;
1197
1198 return DAG.UnrollVectorOp(Op.getNode());
1199 }
1200
ExpandROT(SDValue Op)1201 SDValue VectorLegalizer::ExpandROT(SDValue Op) {
1202 SDValue Result;
1203 if (TLI.expandROT(Op.getNode(), Result, DAG))
1204 return Result;
1205
1206 return DAG.UnrollVectorOp(Op.getNode());
1207 }
1208
ExpandFMINNUM_FMAXNUM(SDValue Op)1209 SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
1210 if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Op.getNode(), DAG))
1211 return Expanded;
1212 return DAG.UnrollVectorOp(Op.getNode());
1213 }
1214
ExpandAddSubSat(SDValue Op)1215 SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) {
1216 if (SDValue Expanded = TLI.expandAddSubSat(Op.getNode(), DAG))
1217 return Expanded;
1218 return DAG.UnrollVectorOp(Op.getNode());
1219 }
1220
ExpandStrictFPOp(SDValue Op)1221 SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
1222 EVT VT = Op.getValueType();
1223 EVT EltVT = VT.getVectorElementType();
1224 unsigned NumElems = VT.getVectorNumElements();
1225 unsigned NumOpers = Op.getNumOperands();
1226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1227 EVT ValueVTs[] = {EltVT, MVT::Other};
1228 SDValue Chain = Op.getOperand(0);
1229 SDLoc dl(Op);
1230
1231 SmallVector<SDValue, 32> OpValues;
1232 SmallVector<SDValue, 32> OpChains;
1233 for (unsigned i = 0; i < NumElems; ++i) {
1234 SmallVector<SDValue, 4> Opers;
1235 SDValue Idx = DAG.getConstant(i, dl,
1236 TLI.getVectorIdxTy(DAG.getDataLayout()));
1237
1238 // The Chain is the first operand.
1239 Opers.push_back(Chain);
1240
1241 // Now process the remaining operands.
1242 for (unsigned j = 1; j < NumOpers; ++j) {
1243 SDValue Oper = Op.getOperand(j);
1244 EVT OperVT = Oper.getValueType();
1245
1246 if (OperVT.isVector())
1247 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1248 EltVT, Oper, Idx);
1249
1250 Opers.push_back(Oper);
1251 }
1252
1253 SDValue ScalarOp = DAG.getNode(Op->getOpcode(), dl, ValueVTs, Opers);
1254
1255 OpValues.push_back(ScalarOp.getValue(0));
1256 OpChains.push_back(ScalarOp.getValue(1));
1257 }
1258
1259 SDValue Result = DAG.getBuildVector(VT, dl, OpValues);
1260 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains);
1261
1262 AddLegalizedOperand(Op.getValue(0), Result);
1263 AddLegalizedOperand(Op.getValue(1), NewChain);
1264
1265 return Op.getResNo() ? NewChain : Result;
1266 }
1267
UnrollVSETCC(SDValue Op)1268 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1269 EVT VT = Op.getValueType();
1270 unsigned NumElems = VT.getVectorNumElements();
1271 EVT EltVT = VT.getVectorElementType();
1272 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1273 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1274 SDLoc dl(Op);
1275 SmallVector<SDValue, 8> Ops(NumElems);
1276 for (unsigned i = 0; i < NumElems; ++i) {
1277 SDValue LHSElem = DAG.getNode(
1278 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1279 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1280 SDValue RHSElem = DAG.getNode(
1281 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1282 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1283 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1284 TLI.getSetCCResultType(DAG.getDataLayout(),
1285 *DAG.getContext(), TmpEltVT),
1286 LHSElem, RHSElem, CC);
1287 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1288 DAG.getConstant(APInt::getAllOnesValue
1289 (EltVT.getSizeInBits()), dl, EltVT),
1290 DAG.getConstant(0, dl, EltVT));
1291 }
1292 return DAG.getBuildVector(VT, dl, Ops);
1293 }
1294
LegalizeVectors()1295 bool SelectionDAG::LegalizeVectors() {
1296 return VectorLegalizer(*this).Run();
1297 }
1298