1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that AVR uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_AVR_ISEL_LOWERING_H 16 #define LLVM_AVR_ISEL_LOWERING_H 17 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 23 namespace AVRISD { 24 25 /// AVR Specific DAG Nodes 26 enum NodeType { 27 /// Start the numbering where the builtin ops leave off. 28 FIRST_NUMBER = ISD::BUILTIN_OP_END, 29 /// Return from subroutine. 30 RET_FLAG, 31 /// Return from ISR. 32 RETI_FLAG, 33 /// Represents an abstract call instruction, 34 /// which includes a bunch of information. 35 CALL, 36 /// A wrapper node for TargetConstantPool, 37 /// TargetExternalSymbol, and TargetGlobalAddress. 38 WRAPPER, 39 LSL, ///< Logical shift left. 40 LSR, ///< Logical shift right. 41 ASR, ///< Arithmetic shift right. 42 ROR, ///< Bit rotate right. 43 ROL, ///< Bit rotate left. 44 LSLLOOP, ///< A loop of single logical shift left instructions. 45 LSRLOOP, ///< A loop of single logical shift right instructions. 46 ROLLOOP, ///< A loop of single left bit rotate instructions. 47 RORLOOP, ///< A loop of single right bit rotate instructions. 48 ASRLOOP, ///< A loop of single arithmetic shift right instructions. 49 /// AVR conditional branches. Operand 0 is the chain operand, operand 1 50 /// is the block to branch if condition is true, operand 2 is the 51 /// condition code, and operand 3 is the flag operand produced by a CMP 52 /// or TEST instruction. 53 BRCOND, 54 /// Compare instruction. 55 CMP, 56 /// Compare with carry instruction. 57 CMPC, 58 /// Test for zero or minus instruction. 59 TST, 60 /// Operand 0 and operand 1 are selection variable, operand 2 61 /// is condition code and operand 3 is flag operand. 62 SELECT_CC 63 }; 64 65 } // end of namespace AVRISD 66 67 class AVRSubtarget; 68 class AVRTargetMachine; 69 70 /// Performs target lowering for the AVR. 71 class AVRTargetLowering : public TargetLowering { 72 public: 73 explicit AVRTargetLowering(const AVRTargetMachine &TM, 74 const AVRSubtarget &STI); 75 76 public: getScalarShiftAmountTy(const DataLayout &,EVT LHSTy)77 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override { 78 return MVT::i8; 79 } 80 getCmpLibcallReturnType()81 MVT::SimpleValueType getCmpLibcallReturnType() const override { 82 return MVT::i8; 83 } 84 85 const char *getTargetNodeName(unsigned Opcode) const override; 86 87 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 88 89 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 90 SelectionDAG &DAG) const override; 91 92 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 93 unsigned AS, 94 Instruction *I = nullptr) const override; 95 96 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 97 ISD::MemIndexedMode &AM, 98 SelectionDAG &DAG) const override; 99 100 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 101 SDValue &Offset, ISD::MemIndexedMode &AM, 102 SelectionDAG &DAG) const override; 103 104 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 105 106 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 107 EVT VT) const override; 108 109 MachineBasicBlock * 110 EmitInstrWithCustomInserter(MachineInstr &MI, 111 MachineBasicBlock *MBB) const override; 112 113 ConstraintType getConstraintType(StringRef Constraint) const override; 114 115 ConstraintWeight 116 getSingleConstraintMatchWeight(AsmOperandInfo &info, 117 const char *constraint) const override; 118 119 std::pair<unsigned, const TargetRegisterClass *> 120 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 121 StringRef Constraint, MVT VT) const override; 122 123 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 124 125 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 126 std::vector<SDValue> &Ops, 127 SelectionDAG &DAG) const override; 128 129 unsigned getRegisterByName(const char* RegName, EVT VT, 130 SelectionDAG &DAG) const override; 131 132 private: 133 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc, 134 SelectionDAG &DAG, SDLoc dl) const; 135 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 136 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 138 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 139 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 141 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 142 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 143 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 144 145 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 146 147 bool CanLowerReturn(CallingConv::ID CallConv, 148 MachineFunction &MF, bool isVarArg, 149 const SmallVectorImpl<ISD::OutputArg> &Outs, 150 LLVMContext &Context) const override; 151 152 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 153 const SmallVectorImpl<ISD::OutputArg> &Outs, 154 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, 155 SelectionDAG &DAG) const override; 156 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 157 bool isVarArg, 158 const SmallVectorImpl<ISD::InputArg> &Ins, 159 const SDLoc &dl, SelectionDAG &DAG, 160 SmallVectorImpl<SDValue> &InVals) const override; 161 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 162 SmallVectorImpl<SDValue> &InVals) const override; 163 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 164 CallingConv::ID CallConv, bool isVarArg, 165 const SmallVectorImpl<ISD::InputArg> &Ins, 166 const SDLoc &dl, SelectionDAG &DAG, 167 SmallVectorImpl<SDValue> &InVals) const; 168 169 protected: 170 171 const AVRSubtarget &Subtarget; 172 173 private: 174 MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const; 175 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const; 176 }; 177 178 } // end namespace llvm 179 180 #endif // LLVM_AVR_ISEL_LOWERING_H 181