1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, 43 SDTCisVT<1, i32>]>; 44 45def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 46def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 47def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 48def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 49 [SDNPHasChain, SDNPOptInGlue]>; 50def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 51def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 52def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 53 SDT_MipsExtractElementF64>; 54 55def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>; 56 57// Operand for printing out a condition code. 58let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 59 def condcode : Operand<i32>; 60 61//===----------------------------------------------------------------------===// 62// Feature predicates. 63//===----------------------------------------------------------------------===// 64 65def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 66 AssemblerPredicate<"FeatureFP64Bit">; 67def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 68 AssemblerPredicate<"!FeatureFP64Bit">; 69def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 70 AssemblerPredicate<"FeatureSingleFloat">; 71def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 72 AssemblerPredicate<"!FeatureSingleFloat">; 73def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, 74 AssemblerPredicate<"!FeatureSoftFloat">; 75 76//===----------------------------------------------------------------------===// 77// Mips FGR size adjectives. 78// They are mutually exclusive. 79//===----------------------------------------------------------------------===// 80 81class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 82class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 83class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; } 84 85//===----------------------------------------------------------------------===// 86 87// FP immediate patterns. 88def fpimm0 : PatLeaf<(fpimm), [{ 89 return N->isExactlyValue(+0.0); 90}]>; 91 92def fpimm0neg : PatLeaf<(fpimm), [{ 93 return N->isExactlyValue(-0.0); 94}]>; 95 96//===----------------------------------------------------------------------===// 97// Instruction Class Templates 98// 99// A set of multiclasses is used to address the register usage. 100// 101// S32 - single precision in 16 32bit even fp registers 102// single precision in 32 32bit fp registers in SingleOnly mode 103// S64 - single precision in 32 64bit fp registers (In64BitMode) 104// D32 - double precision in 16 32bit even fp registers 105// D64 - double precision in 32 64bit fp registers (In64BitMode) 106// 107// Only S32 and D32 are supported right now. 108//===----------------------------------------------------------------------===// 109class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 110 SDPatternOperator OpNode= null_frag> : 111 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 112 !strconcat(opstr, "\t$fd, $fs, $ft"), 113 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>, 114 HARDFLOAT { 115 let isCommutable = IsComm; 116} 117 118multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 119 SDPatternOperator OpNode = null_frag> { 120 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32; 121 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { 122 string DecoderNamespace = "MipsFP64"; 123 } 124} 125 126class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 127 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 130 HARDFLOAT, 131 NeverHasSideEffects; 132 133class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm, 134 SDPatternOperator OpNode= null_frag> : 135 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft), 136 !strconcat(opstr, "\t$fd, $fs, $ft"), 137 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>, 138 HARDFLOAT { 139 let isCommutable = IsComm; 140} 141 142multiclass ABSS_M<string opstr, InstrItinClass Itin, 143 SDPatternOperator OpNode= null_frag> { 144 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 145 FGR_32; 146 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { 147 string DecoderNamespace = "MipsFP64"; 148 } 149} 150 151multiclass ROUND_M<string opstr, InstrItinClass Itin> { 152 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32; 153 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 { 154 let DecoderNamespace = "MipsFP64"; 155 } 156} 157 158class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 159 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 160 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 161 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT { 162 let isMoveReg = 1; 163} 164 165class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 166 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 167 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 168 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT { 169 let isMoveReg = 1; 170} 171 172class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 173 InstrItinClass Itin> : 174 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 175 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT { 176 // $fs_in is part of a white lie to work around a widespread bug in the FPU 177 // implementation. See expandBuildPairF64 for details. 178 let Constraints = "$fs = $fs_in"; 179} 180 181class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 182 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 183 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 184 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>, 185 HARDFLOAT { 186 let DecoderMethod = "DecodeFMem"; 187 let mayLoad = 1; 188} 189 190class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 191 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 192 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 193 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT { 194 let DecoderMethod = "DecodeFMem"; 195 let mayStore = 1; 196} 197 198class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 199 SDPatternOperator OpNode = null_frag> : 200 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 201 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 202 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 203 FrmFR, opstr>, HARDFLOAT; 204 205class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 206 SDPatternOperator OpNode = null_frag> : 207 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 208 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 209 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 210 Itin, FrmFR, opstr>, HARDFLOAT; 211 212class LWXC1_FT<string opstr, RegisterOperand DRC, 213 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 214 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 215 !strconcat(opstr, "\t$fd, ${index}(${base})"), 216 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 217 FrmFI, opstr>, HARDFLOAT { 218 let AddedComplexity = 20; 219} 220 221class SWXC1_FT<string opstr, RegisterOperand DRC, 222 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 223 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 224 !strconcat(opstr, "\t$fs, ${index}(${base})"), 225 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 226 FrmFI, opstr>, HARDFLOAT { 227 let AddedComplexity = 20; 228} 229 230class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 231 SDPatternOperator Op = null_frag> : 232 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 233 !strconcat(opstr, "\t$fcc, $offset"), 234 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 235 FrmFI, opstr>, HARDFLOAT { 236 let isBranch = 1; 237 let isTerminator = 1; 238 let hasDelaySlot = 1; 239 let Defs = [AT]; 240 let hasFCCRegOperand = 1; 241} 242 243class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> : 244 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 245 !strconcat(opstr, "\t$fcc, $offset"), [], Itin, 246 FrmFI, opstr>, HARDFLOAT { 247 let isBranch = 1; 248 let isTerminator = 1; 249 let hasDelaySlot = 1; 250 let Defs = [AT]; 251 let hasFCCRegOperand = 1; 252} 253 254class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 255 SDPatternOperator OpNode = null_frag> : 256 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 257 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 258 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 259 !strconcat("c.$cond.", typestr)>, HARDFLOAT { 260 let Defs = [FCC0]; 261 let isCodeGenOnly = 1; 262 let hasFCCRegOperand = 1; 263} 264 265 266// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather 267// duplicating the instruction definition for MIPS1 - MIPS3, we expand 268// c.cond.ft if necessary, and reject it after constructing the 269// instruction if the ISA doesn't support it. 270class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 271 InstrItinClass itin> : 272 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), 273 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, 274 FrmFR>, HARDFLOAT { 275 let isCompare = 1; 276 let hasFCCRegOperand = 1; 277} 278 279 280multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 281 InstrItinClass itin> { 282 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 283 C_COND_FM<fmt, 0> { 284 let BaseOpcode = "c.f."#NAME; 285 let isCommutable = 1; 286 } 287 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 288 C_COND_FM<fmt, 1> { 289 let BaseOpcode = "c.un."#NAME; 290 let isCommutable = 1; 291 } 292 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 293 C_COND_FM<fmt, 2> { 294 let BaseOpcode = "c.eq."#NAME; 295 let isCommutable = 1; 296 } 297 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 298 C_COND_FM<fmt, 3> { 299 let BaseOpcode = "c.ueq."#NAME; 300 let isCommutable = 1; 301 } 302 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 303 C_COND_FM<fmt, 4> { 304 let BaseOpcode = "c.olt."#NAME; 305 } 306 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 307 C_COND_FM<fmt, 5> { 308 let BaseOpcode = "c.ult."#NAME; 309 } 310 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 311 C_COND_FM<fmt, 6> { 312 let BaseOpcode = "c.ole."#NAME; 313 } 314 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 315 C_COND_FM<fmt, 7> { 316 let BaseOpcode = "c.ule."#NAME; 317 } 318 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 319 C_COND_FM<fmt, 8> { 320 let BaseOpcode = "c.sf."#NAME; 321 let isCommutable = 1; 322 } 323 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 324 C_COND_FM<fmt, 9> { 325 let BaseOpcode = "c.ngle."#NAME; 326 } 327 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 328 C_COND_FM<fmt, 10> { 329 let BaseOpcode = "c.seq."#NAME; 330 let isCommutable = 1; 331 } 332 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 333 C_COND_FM<fmt, 11> { 334 let BaseOpcode = "c.ngl."#NAME; 335 } 336 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 337 C_COND_FM<fmt, 12> { 338 let BaseOpcode = "c.lt."#NAME; 339 } 340 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 341 C_COND_FM<fmt, 13> { 342 let BaseOpcode = "c.nge."#NAME; 343 } 344 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 345 C_COND_FM<fmt, 14> { 346 let BaseOpcode = "c.le."#NAME; 347 } 348 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 349 C_COND_FM<fmt, 15> { 350 let BaseOpcode = "c.ngt."#NAME; 351 } 352} 353 354let AdditionalPredicates = [NotInMicroMips] in { 355defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 356defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 357 FGR_32; 358let DecoderNamespace = "MipsFP64" in 359defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 360 FGR_64; 361} 362//===----------------------------------------------------------------------===// 363// Floating Point Instructions 364//===----------------------------------------------------------------------===// 365let AdditionalPredicates = [NotInMicroMips] in { 366 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 367 ABSS_FM<0xc, 16>, ISA_MIPS2; 368 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 369 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 370 ABSS_FM<0xd, 16>, ISA_MIPS2; 371 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 372 ABSS_FM<0xe, 16>, ISA_MIPS2; 373 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 374 ABSS_FM<0xf, 16>, ISA_MIPS2; 375 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 376 ABSS_FM<0x24, 16>, ISA_MIPS1; 377 378 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 379 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 380 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 381 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1; 382} 383 384let AdditionalPredicates = [NotInMicroMips] in { 385 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, 386 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; 387 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, 388 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { 389 let BaseOpcode = "RECIP_D32"; 390 } 391 let DecoderNamespace = "MipsFP64" in 392 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 393 II_RECIP_D>, ABSS_FM<0b010101, 0x11>, 394 INSN_MIPS4_32R2, FGR_64; 395 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, 396 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; 397 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>, 398 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 { 399 let BaseOpcode = "RSQRT_D32"; 400 } 401 let DecoderNamespace = "MipsFP64" in 402 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 403 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>, 404 INSN_MIPS4_32R2, FGR_64; 405} 406let DecoderNamespace = "MipsFP64" in { 407 let AdditionalPredicates = [NotInMicroMips] in { 408 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 409 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64; 410 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 411 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64; 412 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 413 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64; 414 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 415 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64; 416 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 417 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64; 418 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 419 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64; 420 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 421 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64; 422 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 423 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64; 424 } 425} 426 427let AdditionalPredicates = [NotInMicroMips] in{ 428 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 429 ABSS_FM<0x20, 20>, ISA_MIPS1; 430 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 431 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 432 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 433 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 434} 435 436let AdditionalPredicates = [NotInMicroMips] in { 437 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 438 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32; 439 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 440 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32; 441 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 442 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; 443} 444 445let DecoderNamespace = "MipsFP64" in { 446 let AdditionalPredicates = [NotInMicroMips] in { 447 def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>, 448 ADDS_FM<0x2C, 22>, 449 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 450 def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>, 451 ADDS_FM<0x2D, 22>, 452 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 453 454 def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>, 455 ABSS_FM<0x20, 22>, 456 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 457 def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>, 458 ABSS_FM<0x28, 22>, 459 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 460 461 def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>, 462 ADDS_FM<0x26, 16>, 463 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 464 } 465} 466 467let DecoderNamespace = "MipsFP64" in { 468 let AdditionalPredicates = [NotInMicroMips] in { 469 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 470 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; 471 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 472 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64; 473 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 474 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64; 475 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 476 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64; 477 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 478 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64; 479 } 480} 481 482let isPseudo = 1, isCodeGenOnly = 1 in { 483 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 484 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 485 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 486 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 487 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 488} 489 490let AdditionalPredicates = [NotInMicroMips] in { 491 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 492 ABSS_FM<0x5, 16>, ISA_MIPS1; 493 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1; 494} 495 496def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 497 ABSS_FM<0x7, 16>, ISA_MIPS1; 498let AdditionalPredicates = [NotInMicroMips] in { 499 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1; 500} 501 502let AdditionalPredicates = [NotInMicroMips] in { 503 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, 504 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; 505 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 506} 507 508// The odd-numbered registers are only referenced when doing loads, 509// stores, and moves between floating-point and integer registers. 510// When defining instructions, we reference all 32-bit registers, 511// regardless of register aliasing. 512 513/// Move Control Registers From/To CPU Registers 514let AdditionalPredicates = [NotInMicroMips] in { 515 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>, 516 ISA_MIPS1; 517 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, 518 ISA_MIPS1; 519 520 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 521 bitconvert>, MFC1_FM<0>, ISA_MIPS1; 522 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, 523 ISA_MIPS1, FGR_64 { 524 let DecoderNamespace = "MipsFP64"; 525 } 526 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 527 bitconvert>, MFC1_FM<4>, ISA_MIPS1; 528 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, 529 ISA_MIPS1, FGR_64 { 530 let DecoderNamespace = "MipsFP64"; 531 } 532 533 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 534 MFC1_FM<3>, ISA_MIPS32R2, FGR_32; 535 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 536 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { 537 let DecoderNamespace = "MipsFP64"; 538 } 539 540 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 541 MFC1_FM<7>, ISA_MIPS32R2, FGR_32; 542 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 543 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { 544 let DecoderNamespace = "MipsFP64"; 545 } 546 547 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 548 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 549 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 550 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 551 let isMoveReg = 1 in { 552 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 553 ABSS_FM<0x6, 16>, ISA_MIPS1; 554 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 555 ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_32; 556 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 557 ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_64 { 558 let DecoderNamespace = "MipsFP64"; 559 } 560 } // isMoveReg 561} 562 563/// Floating Point Memory Instructions 564let AdditionalPredicates = [NotInMicroMips] in { 565 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, 566 LW_FM<0x31>, ISA_MIPS1; 567 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, 568 LW_FM<0x39>, ISA_MIPS1; 569} 570 571let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { 572 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>, 573 LW_FM<0x35>, ISA_MIPS2, FGR_64 { 574 let BaseOpcode = "LDC164"; 575 } 576 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>, 577 LW_FM<0x3d>, ISA_MIPS2, FGR_64; 578} 579 580let AdditionalPredicates = [NotInMicroMips] in { 581 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1, 582 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 { 583 let BaseOpcode = "LDC132"; 584 } 585 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>, 586 LW_FM<0x3d>, ISA_MIPS2, FGR_32; 587} 588 589// Indexed loads and stores. 590// Base register + offset register addressing mode (indicated by "x" in the 591// instruction mnemonic) is disallowed under NaCl. 592let AdditionalPredicates = [IsNotNaCl] in { 593 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 594 INSN_MIPS4_32R2_NOT_32R6_64R6; 595 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 596 INSN_MIPS4_32R2_NOT_32R6_64R6; 597} 598 599let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 600 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 601 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 602 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 603 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 604} 605 606let DecoderNamespace="MipsFP64" in { 607 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 608 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 609 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 610 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 611} 612 613// Load/store doubleword indexed unaligned. 614// FIXME: This instruction should not be defined for FGR_32. 615let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in { 616 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 617 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 618 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 619 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 620} 621 622let AdditionalPredicates = [IsNotNaCl, NotInMicroMips], 623 DecoderNamespace="MipsFP64" in { 624 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 625 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 626 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 627 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 628} 629 630/// Floating-point Aritmetic 631let AdditionalPredicates = [NotInMicroMips] in { 632 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 633 ADDS_FM<0x00, 16>, ISA_MIPS1; 634 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>, 635 ISA_MIPS1; 636 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 637 ADDS_FM<0x03, 16>, ISA_MIPS1; 638 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>, 639 ISA_MIPS1; 640 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 641 ADDS_FM<0x02, 16>, ISA_MIPS1; 642 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>, 643 ISA_MIPS1; 644 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 645 ADDS_FM<0x01, 16>, ISA_MIPS1; 646 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>, 647 ISA_MIPS1; 648} 649 650let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { 651 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 652 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 653 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 654 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 655 656 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 657 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 658 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 659 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 660 661 let DecoderNamespace = "MipsFP64" in { 662 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 663 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 664 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 665 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 666 } 667} 668 669let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 670 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 671 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 672 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 673 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 674 675 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 676 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 677 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 678 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 679 680 let DecoderNamespace = "MipsFP64" in { 681 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, 682 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 683 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, 684 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 685 } 686} 687//===----------------------------------------------------------------------===// 688// Floating Point Branch Codes 689//===----------------------------------------------------------------------===// 690// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 691// They must be kept in synch. 692def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 693def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 694 695let AdditionalPredicates = [NotInMicroMips] in { 696 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>, 697 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 698 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>, 699 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; 700 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, 701 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 702 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>, 703 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; 704 705/// Floating Point Compare 706 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, 707 ISA_MIPS1_NOT_32R6_64R6 { 708 709 // FIXME: This is a required to work around the fact that these instructions 710 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 711 // fcc register set is used directly. 712 bits<3> fcc = 0; 713 } 714 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 715 ISA_MIPS1_NOT_32R6_64R6, FGR_32 { 716 // FIXME: This is a required to work around the fact that these instructions 717 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 718 // fcc register set is used directly. 719 bits<3> fcc = 0; 720 } 721} 722let DecoderNamespace = "MipsFP64" in 723def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 724 ISA_MIPS1_NOT_32R6_64R6, FGR_64 { 725 // FIXME: This is a required to work around the fact that thiese instructions 726 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 727 // fcc register set is used directly. 728 bits<3> fcc = 0; 729} 730 731//===----------------------------------------------------------------------===// 732// Floating Point Pseudo-Instructions 733//===----------------------------------------------------------------------===// 734 735// This pseudo instr gets expanded into 2 mtc1 instrs after register 736// allocation. 737class BuildPairF64Base<RegisterOperand RO> : 738 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 739 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))], 740 II_MTC1>; 741 742def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 743def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 744 745// This pseudo instr gets expanded into 2 mfc1 instrs after register 746// allocation. 747// if n is 0, lower part of src is extracted. 748// if n is 1, higher part of src is extracted. 749// This node has associated scheduling information as the pre RA scheduler 750// asserts otherwise. 751class ExtractElementF64Base<RegisterOperand RO> : 752 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 753 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))], 754 II_MFC1>; 755 756def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 757def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 758 759def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 760 (ins FGR32Opnd:$fs, GPR32Opnd:$rs), 761 "trunc.w.s\t$fd, $fs, $rs">; 762 763def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 764 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs), 765 "trunc.w.d\t$fd, $fs, $rs">, 766 FGR_32, HARDFLOAT; 767 768def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 769 (ins FGR64Opnd:$fs, GPR32Opnd:$rs), 770 "trunc.w.d\t$fd, $fs, $rs">, 771 FGR_64, HARDFLOAT; 772 773def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 774 (ins imm64:$fpimm), 775 "li.s\t$rd, $fpimm">; 776 777def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd), 778 (ins imm64:$fpimm), 779 "li.s\t$rd, $fpimm">, 780 HARDFLOAT; 781 782def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 783 (ins imm64:$fpimm), 784 "li.d\t$rd, $fpimm">; 785 786def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd), 787 (ins imm64:$fpimm), 788 "li.d\t$rd, $fpimm">, 789 FGR_32, HARDFLOAT; 790 791def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), 792 (ins imm64:$fpimm), 793 "li.d\t$rd, $fpimm">, 794 FGR_64, HARDFLOAT; 795 796//===----------------------------------------------------------------------===// 797// InstAliases. 798//===----------------------------------------------------------------------===// 799def : MipsInstAlias 800 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 801 ISA_MIPS2, HARDFLOAT; 802def : MipsInstAlias 803 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 804 FGR_32, ISA_MIPS2, HARDFLOAT; 805def : MipsInstAlias 806 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 807 FGR_64, ISA_MIPS2, HARDFLOAT; 808 809def : MipsInstAlias 810 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 811 ISA_MIPS2, HARDFLOAT; 812def : MipsInstAlias 813 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 814 FGR_32, ISA_MIPS2, HARDFLOAT; 815def : MipsInstAlias 816 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 817 FGR_64, ISA_MIPS2, HARDFLOAT; 818 819multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { 820 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), 821 (!cast<Instruction>("C_F_"#NAME) FCC0, 822 RC:$fs, RC:$ft), 1>; 823 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), 824 (!cast<Instruction>("C_UN_"#NAME) FCC0, 825 RC:$fs, RC:$ft), 1>; 826 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), 827 (!cast<Instruction>("C_EQ_"#NAME) FCC0, 828 RC:$fs, RC:$ft), 1>; 829 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), 830 (!cast<Instruction>("C_UEQ_"#NAME) FCC0, 831 RC:$fs, RC:$ft), 1>; 832 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), 833 (!cast<Instruction>("C_OLT_"#NAME) FCC0, 834 RC:$fs, RC:$ft), 1>; 835 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), 836 (!cast<Instruction>("C_ULT_"#NAME) FCC0, 837 RC:$fs, RC:$ft), 1>; 838 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), 839 (!cast<Instruction>("C_OLE_"#NAME) FCC0, 840 RC:$fs, RC:$ft), 1>; 841 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), 842 (!cast<Instruction>("C_ULE_"#NAME) FCC0, 843 RC:$fs, RC:$ft), 1>; 844 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), 845 (!cast<Instruction>("C_SF_"#NAME) FCC0, 846 RC:$fs, RC:$ft), 1>; 847 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), 848 (!cast<Instruction>("C_NGLE_"#NAME) FCC0, 849 RC:$fs, RC:$ft), 1>; 850 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), 851 (!cast<Instruction>("C_SEQ_"#NAME) FCC0, 852 RC:$fs, RC:$ft), 1>; 853 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), 854 (!cast<Instruction>("C_NGL_"#NAME) FCC0, 855 RC:$fs, RC:$ft), 1>; 856 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), 857 (!cast<Instruction>("C_LT_"#NAME) FCC0, 858 RC:$fs, RC:$ft), 1>; 859 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), 860 (!cast<Instruction>("C_NGE_"#NAME) FCC0, 861 RC:$fs, RC:$ft), 1>; 862 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), 863 (!cast<Instruction>("C_LE_"#NAME) FCC0, 864 RC:$fs, RC:$ft), 1>; 865 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), 866 (!cast<Instruction>("C_NGT_"#NAME) FCC0, 867 RC:$fs, RC:$ft), 1>; 868} 869 870multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, 871 Instruction BCFalse, string BCFalseString> { 872 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), 873 (BCTrue FCC0, brtarget:$offset), 1>; 874 875 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), 876 (BCFalse FCC0, brtarget:$offset), 1>; 877} 878 879let AdditionalPredicates = [NotInMicroMips] in { 880 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 881 ISA_MIPS1_NOT_32R6_64R6; 882 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 883 ISA_MIPS1_NOT_32R6_64R6, FGR_32; 884 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 885 ISA_MIPS1_NOT_32R6_64R6, FGR_64; 886 887 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, 888 HARDFLOAT; 889 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, 890 HARDFLOAT; 891} 892//===----------------------------------------------------------------------===// 893// Floating Point Patterns 894//===----------------------------------------------------------------------===// 895def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1; 896def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1; 897 898def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 899 (PseudoCVT_S_W GPR32Opnd:$src)>; 900def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 901 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1; 902 903def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 904 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64; 905 906def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 907 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 908let AdditionalPredicates = [NotInMicroMips] in { 909 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 910 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32; 911 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 912 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32; 913 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 914 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32; 915} 916 917def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64; 918def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64, 919 FGR_64; 920 921def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 922 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 923def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 924 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 925def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 926 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 927 928def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 929 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 930def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 931 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64; 932def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 933 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 934 935let AdditionalPredicates = [NotInMicroMips] in { 936 def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 937 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64; 938 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 939 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64; 940} 941 942// To generate NMADD and NMSUB instructions when fneg node is present 943multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { 944 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), 945 (Nmadd RC:$fr, RC:$fs, RC:$ft)>; 946 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)), 947 (Nmsub RC:$fr, RC:$fs, RC:$ft)>; 948} 949 950let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 951 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, INSN_MIPS4_32R2_NOT_32R6_64R6; 952 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6; 953 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6; 954} 955 956// Patterns for loads/stores with a reg+imm operand. 957let AdditionalPredicates = [NotInMicroMips] in { 958 let AddedComplexity = 40 in { 959 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1; 960 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1; 961 962 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64; 963 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64; 964 965 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32; 966 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32; 967 } 968} 969