1 //===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "NVPTXISelLowering.h"
16 #include "MCTargetDesc/NVPTXBaseInfo.h"
17 #include "NVPTX.h"
18 #include "NVPTXSubtarget.h"
19 #include "NVPTXTargetMachine.h"
20 #include "NVPTXTargetObjectFile.h"
21 #include "NVPTXUtilities.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/CodeGen/TargetCallingConv.h"
31 #include "llvm/CodeGen/TargetLowering.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/IR/Argument.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/IR/Value.h"
46 #include "llvm/Support/Casting.h"
47 #include "llvm/Support/CodeGen.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MachineValueType.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include <algorithm>
56 #include <cassert>
57 #include <cstdint>
58 #include <iterator>
59 #include <sstream>
60 #include <string>
61 #include <utility>
62 #include <vector>
63 
64 #define DEBUG_TYPE "nvptx-lower"
65 
66 using namespace llvm;
67 
68 static unsigned int uniqueCallSite = 0;
69 
70 static cl::opt<bool> sched4reg(
71     "nvptx-sched4reg",
72     cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
73 
74 static cl::opt<unsigned>
75 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
76                     cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
77                              " 1: do it  2: do it aggressively"),
78                     cl::init(2));
79 
80 static cl::opt<int> UsePrecDivF32(
81     "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
82     cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
83              " IEEE Compliant F32 div.rnd if available."),
84     cl::init(2));
85 
86 static cl::opt<bool> UsePrecSqrtF32(
87     "nvptx-prec-sqrtf32", cl::Hidden,
88     cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
89     cl::init(true));
90 
91 static cl::opt<bool> FtzEnabled(
92     "nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
93     cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
94     cl::init(false));
95 
getDivF32Level() const96 int NVPTXTargetLowering::getDivF32Level() const {
97   if (UsePrecDivF32.getNumOccurrences() > 0) {
98     // If nvptx-prec-div32=N is used on the command-line, always honor it
99     return UsePrecDivF32;
100   } else {
101     // Otherwise, use div.approx if fast math is enabled
102     if (getTargetMachine().Options.UnsafeFPMath)
103       return 0;
104     else
105       return 2;
106   }
107 }
108 
usePrecSqrtF32() const109 bool NVPTXTargetLowering::usePrecSqrtF32() const {
110   if (UsePrecSqrtF32.getNumOccurrences() > 0) {
111     // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
112     return UsePrecSqrtF32;
113   } else {
114     // Otherwise, use sqrt.approx if fast math is enabled
115     return !getTargetMachine().Options.UnsafeFPMath;
116   }
117 }
118 
useF32FTZ(const MachineFunction & MF) const119 bool NVPTXTargetLowering::useF32FTZ(const MachineFunction &MF) const {
120   // TODO: Get rid of this flag; there can be only one way to do this.
121   if (FtzEnabled.getNumOccurrences() > 0) {
122     // If nvptx-f32ftz is used on the command-line, always honor it
123     return FtzEnabled;
124   } else {
125     const Function &F = MF.getFunction();
126     // Otherwise, check for an nvptx-f32ftz attribute on the function
127     if (F.hasFnAttribute("nvptx-f32ftz"))
128       return F.getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
129     else
130       return false;
131   }
132 }
133 
IsPTXVectorType(MVT VT)134 static bool IsPTXVectorType(MVT VT) {
135   switch (VT.SimpleTy) {
136   default:
137     return false;
138   case MVT::v2i1:
139   case MVT::v4i1:
140   case MVT::v2i8:
141   case MVT::v4i8:
142   case MVT::v2i16:
143   case MVT::v4i16:
144   case MVT::v2i32:
145   case MVT::v4i32:
146   case MVT::v2i64:
147   case MVT::v2f16:
148   case MVT::v4f16:
149   case MVT::v8f16: // <4 x f16x2>
150   case MVT::v2f32:
151   case MVT::v4f32:
152   case MVT::v2f64:
153     return true;
154   }
155 }
156 
157 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
158 /// EVTs that compose it.  Unlike ComputeValueVTs, this will break apart vectors
159 /// into their primitive components.
160 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
161 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
162 /// LowerCall, and LowerReturn.
ComputePTXValueVTs(const TargetLowering & TLI,const DataLayout & DL,Type * Ty,SmallVectorImpl<EVT> & ValueVTs,SmallVectorImpl<uint64_t> * Offsets=nullptr,uint64_t StartingOffset=0)163 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
164                                Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
165                                SmallVectorImpl<uint64_t> *Offsets = nullptr,
166                                uint64_t StartingOffset = 0) {
167   SmallVector<EVT, 16> TempVTs;
168   SmallVector<uint64_t, 16> TempOffsets;
169 
170   // Special case for i128 - decompose to (i64, i64)
171   if (Ty->isIntegerTy(128)) {
172     ValueVTs.push_back(EVT(MVT::i64));
173     ValueVTs.push_back(EVT(MVT::i64));
174 
175     if (Offsets) {
176       Offsets->push_back(StartingOffset + 0);
177       Offsets->push_back(StartingOffset + 8);
178     }
179 
180     return;
181   }
182 
183   // Given a struct type, recursively traverse the elements with custom ComputePTXValueVTs.
184   if (StructType *STy = dyn_cast<StructType>(Ty)) {
185     auto const *SL = DL.getStructLayout(STy);
186     auto ElementNum = 0;
187     for(auto *EI : STy->elements()) {
188       ComputePTXValueVTs(TLI, DL, EI, ValueVTs, Offsets,
189                          StartingOffset + SL->getElementOffset(ElementNum));
190       ++ElementNum;
191     }
192     return;
193   }
194 
195   ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
196   for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
197     EVT VT = TempVTs[i];
198     uint64_t Off = TempOffsets[i];
199     // Split vectors into individual elements, except for v2f16, which
200     // we will pass as a single scalar.
201     if (VT.isVector()) {
202       unsigned NumElts = VT.getVectorNumElements();
203       EVT EltVT = VT.getVectorElementType();
204       // Vectors with an even number of f16 elements will be passed to
205       // us as an array of v2f16 elements. We must match this so we
206       // stay in sync with Ins/Outs.
207       if (EltVT == MVT::f16 && NumElts % 2 == 0) {
208         EltVT = MVT::v2f16;
209         NumElts /= 2;
210       }
211       for (unsigned j = 0; j != NumElts; ++j) {
212         ValueVTs.push_back(EltVT);
213         if (Offsets)
214           Offsets->push_back(Off + j * EltVT.getStoreSize());
215       }
216     } else {
217       ValueVTs.push_back(VT);
218       if (Offsets)
219         Offsets->push_back(Off);
220     }
221   }
222 }
223 
224 // Check whether we can merge loads/stores of some of the pieces of a
225 // flattened function parameter or return value into a single vector
226 // load/store.
227 //
228 // The flattened parameter is represented as a list of EVTs and
229 // offsets, and the whole structure is aligned to ParamAlignment. This
230 // function determines whether we can load/store pieces of the
231 // parameter starting at index Idx using a single vectorized op of
232 // size AccessSize. If so, it returns the number of param pieces
233 // covered by the vector op. Otherwise, it returns 1.
CanMergeParamLoadStoresStartingAt(unsigned Idx,uint32_t AccessSize,const SmallVectorImpl<EVT> & ValueVTs,const SmallVectorImpl<uint64_t> & Offsets,unsigned ParamAlignment)234 static unsigned CanMergeParamLoadStoresStartingAt(
235     unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs,
236     const SmallVectorImpl<uint64_t> &Offsets, unsigned ParamAlignment) {
237   assert(isPowerOf2_32(AccessSize) && "must be a power of 2!");
238 
239   // Can't vectorize if param alignment is not sufficient.
240   if (AccessSize > ParamAlignment)
241     return 1;
242   // Can't vectorize if offset is not aligned.
243   if (Offsets[Idx] & (AccessSize - 1))
244     return 1;
245 
246   EVT EltVT = ValueVTs[Idx];
247   unsigned EltSize = EltVT.getStoreSize();
248 
249   // Element is too large to vectorize.
250   if (EltSize >= AccessSize)
251     return 1;
252 
253   unsigned NumElts = AccessSize / EltSize;
254   // Can't vectorize if AccessBytes if not a multiple of EltSize.
255   if (AccessSize != EltSize * NumElts)
256     return 1;
257 
258   // We don't have enough elements to vectorize.
259   if (Idx + NumElts > ValueVTs.size())
260     return 1;
261 
262   // PTX ISA can only deal with 2- and 4-element vector ops.
263   if (NumElts != 4 && NumElts != 2)
264     return 1;
265 
266   for (unsigned j = Idx + 1; j < Idx + NumElts; ++j) {
267     // Types do not match.
268     if (ValueVTs[j] != EltVT)
269       return 1;
270 
271     // Elements are not contiguous.
272     if (Offsets[j] - Offsets[j - 1] != EltSize)
273       return 1;
274   }
275   // OK. We can vectorize ValueVTs[i..i+NumElts)
276   return NumElts;
277 }
278 
279 // Flags for tracking per-element vectorization state of loads/stores
280 // of a flattened function parameter or return value.
281 enum ParamVectorizationFlags {
282   PVF_INNER = 0x0, // Middle elements of a vector.
283   PVF_FIRST = 0x1, // First element of the vector.
284   PVF_LAST = 0x2,  // Last element of the vector.
285   // Scalar is effectively a 1-element vector.
286   PVF_SCALAR = PVF_FIRST | PVF_LAST
287 };
288 
289 // Computes whether and how we can vectorize the loads/stores of a
290 // flattened function parameter or return value.
291 //
292 // The flattened parameter is represented as the list of ValueVTs and
293 // Offsets, and is aligned to ParamAlignment bytes. We return a vector
294 // of the same size as ValueVTs indicating how each piece should be
295 // loaded/stored (i.e. as a scalar, or as part of a vector
296 // load/store).
297 static SmallVector<ParamVectorizationFlags, 16>
VectorizePTXValueVTs(const SmallVectorImpl<EVT> & ValueVTs,const SmallVectorImpl<uint64_t> & Offsets,unsigned ParamAlignment)298 VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
299                      const SmallVectorImpl<uint64_t> &Offsets,
300                      unsigned ParamAlignment) {
301   // Set vector size to match ValueVTs and mark all elements as
302   // scalars by default.
303   SmallVector<ParamVectorizationFlags, 16> VectorInfo;
304   VectorInfo.assign(ValueVTs.size(), PVF_SCALAR);
305 
306   // Check what we can vectorize using 128/64/32-bit accesses.
307   for (int I = 0, E = ValueVTs.size(); I != E; ++I) {
308     // Skip elements we've already processed.
309     assert(VectorInfo[I] == PVF_SCALAR && "Unexpected vector info state.");
310     for (unsigned AccessSize : {16, 8, 4, 2}) {
311       unsigned NumElts = CanMergeParamLoadStoresStartingAt(
312           I, AccessSize, ValueVTs, Offsets, ParamAlignment);
313       // Mark vectorized elements.
314       switch (NumElts) {
315       default:
316         llvm_unreachable("Unexpected return value");
317       case 1:
318         // Can't vectorize using this size, try next smaller size.
319         continue;
320       case 2:
321         assert(I + 1 < E && "Not enough elements.");
322         VectorInfo[I] = PVF_FIRST;
323         VectorInfo[I + 1] = PVF_LAST;
324         I += 1;
325         break;
326       case 4:
327         assert(I + 3 < E && "Not enough elements.");
328         VectorInfo[I] = PVF_FIRST;
329         VectorInfo[I + 1] = PVF_INNER;
330         VectorInfo[I + 2] = PVF_INNER;
331         VectorInfo[I + 3] = PVF_LAST;
332         I += 3;
333         break;
334       }
335       // Break out of the inner loop because we've already succeeded
336       // using largest possible AccessSize.
337       break;
338     }
339   }
340   return VectorInfo;
341 }
342 
343 // NVPTXTargetLowering Constructor.
NVPTXTargetLowering(const NVPTXTargetMachine & TM,const NVPTXSubtarget & STI)344 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
345                                          const NVPTXSubtarget &STI)
346     : TargetLowering(TM), nvTM(&TM), STI(STI) {
347   // always lower memset, memcpy, and memmove intrinsics to load/store
348   // instructions, rather
349   // then generating calls to memset, mempcy or memmove.
350   MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
351   MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
352   MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
353 
354   setBooleanContents(ZeroOrNegativeOneBooleanContent);
355   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
356 
357   // Jump is Expensive. Don't create extra control flow for 'and', 'or'
358   // condition branches.
359   setJumpIsExpensive(true);
360 
361   // Wide divides are _very_ slow. Try to reduce the width of the divide if
362   // possible.
363   addBypassSlowDiv(64, 32);
364 
365   // By default, use the Source scheduling
366   if (sched4reg)
367     setSchedulingPreference(Sched::RegPressure);
368   else
369     setSchedulingPreference(Sched::Source);
370 
371   auto setFP16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
372                                     LegalizeAction NoF16Action) {
373     setOperationAction(Op, VT, STI.allowFP16Math() ? Action : NoF16Action);
374   };
375 
376   addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
377   addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
378   addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
379   addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
380   addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
381   addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
382   addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
383   addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass);
384 
385   // Conversion to/from FP16/FP16x2 is always legal.
386   setOperationAction(ISD::SINT_TO_FP, MVT::f16, Legal);
387   setOperationAction(ISD::FP_TO_SINT, MVT::f16, Legal);
388   setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
389   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
390   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand);
391   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);
392 
393   setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
394   setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
395 
396   // Operations not directly supported by NVPTX.
397   for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
398                  MVT::i16, MVT::i32, MVT::i64}) {
399     setOperationAction(ISD::SELECT_CC, VT, Expand);
400     setOperationAction(ISD::BR_CC, VT, Expand);
401   }
402 
403   // Some SIGN_EXTEND_INREG can be done using cvt instruction.
404   // For others we will expand to a SHL/SRA pair.
405   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
406   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
407   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
408   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
409   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
410 
411   setOperationAction(ISD::SHL_PARTS, MVT::i32  , Custom);
412   setOperationAction(ISD::SRA_PARTS, MVT::i32  , Custom);
413   setOperationAction(ISD::SRL_PARTS, MVT::i32  , Custom);
414   setOperationAction(ISD::SHL_PARTS, MVT::i64  , Custom);
415   setOperationAction(ISD::SRA_PARTS, MVT::i64  , Custom);
416   setOperationAction(ISD::SRL_PARTS, MVT::i64  , Custom);
417 
418   setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
419   setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
420 
421   // TODO: we may consider expanding ROTL/ROTR on older GPUs.  Currently on GPUs
422   // that don't have h/w rotation we lower them to multi-instruction assembly.
423   // See ROT*_sw in NVPTXIntrInfo.td
424   setOperationAction(ISD::ROTL, MVT::i64, Legal);
425   setOperationAction(ISD::ROTR, MVT::i64, Legal);
426   setOperationAction(ISD::ROTL, MVT::i32, Legal);
427   setOperationAction(ISD::ROTR, MVT::i32, Legal);
428 
429   setOperationAction(ISD::ROTL, MVT::i16, Expand);
430   setOperationAction(ISD::ROTR, MVT::i16, Expand);
431   setOperationAction(ISD::ROTL, MVT::i8, Expand);
432   setOperationAction(ISD::ROTR, MVT::i8, Expand);
433   setOperationAction(ISD::BSWAP, MVT::i16, Expand);
434   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
435   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
436 
437   // Indirect branch is not supported.
438   // This also disables Jump Table creation.
439   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
440   setOperationAction(ISD::BRIND, MVT::Other, Expand);
441 
442   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
443   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
444 
445   // We want to legalize constant related memmove and memcopy
446   // intrinsics.
447   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
448 
449   // Turn FP extload into load/fpextend
450   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
451   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
452   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
453   setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
454   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
455   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
456   setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
457   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
458   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
459   // Turn FP truncstore into trunc + store.
460   // FIXME: vector types should also be expanded
461   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
462   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
463   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
464 
465   // PTX does not support load / store predicate registers
466   setOperationAction(ISD::LOAD, MVT::i1, Custom);
467   setOperationAction(ISD::STORE, MVT::i1, Custom);
468 
469   for (MVT VT : MVT::integer_valuetypes()) {
470     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
471     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
472     setTruncStoreAction(VT, MVT::i1, Expand);
473   }
474 
475   // This is legal in NVPTX
476   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
477   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
478   setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
479 
480   // TRAP can be lowered to PTX trap
481   setOperationAction(ISD::TRAP, MVT::Other, Legal);
482 
483   // Register custom handling for vector loads/stores
484   for (MVT VT : MVT::vector_valuetypes()) {
485     if (IsPTXVectorType(VT)) {
486       setOperationAction(ISD::LOAD, VT, Custom);
487       setOperationAction(ISD::STORE, VT, Custom);
488       setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
489     }
490   }
491 
492   // Custom handling for i8 intrinsics
493   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
494 
495   for (const auto& Ty : {MVT::i16, MVT::i32, MVT::i64}) {
496     setOperationAction(ISD::ABS,  Ty, Legal);
497     setOperationAction(ISD::SMIN, Ty, Legal);
498     setOperationAction(ISD::SMAX, Ty, Legal);
499     setOperationAction(ISD::UMIN, Ty, Legal);
500     setOperationAction(ISD::UMAX, Ty, Legal);
501 
502     setOperationAction(ISD::CTPOP, Ty, Legal);
503     setOperationAction(ISD::CTLZ, Ty, Legal);
504   }
505 
506   setOperationAction(ISD::CTTZ, MVT::i16, Expand);
507   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
508   setOperationAction(ISD::CTTZ, MVT::i64, Expand);
509 
510   // PTX does not directly support SELP of i1, so promote to i32 first
511   setOperationAction(ISD::SELECT, MVT::i1, Custom);
512 
513   // PTX cannot multiply two i64s in a single instruction.
514   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
515   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
516 
517   // We have some custom DAG combine patterns for these nodes
518   setTargetDAGCombine(ISD::ADD);
519   setTargetDAGCombine(ISD::AND);
520   setTargetDAGCombine(ISD::FADD);
521   setTargetDAGCombine(ISD::MUL);
522   setTargetDAGCombine(ISD::SHL);
523   setTargetDAGCombine(ISD::SREM);
524   setTargetDAGCombine(ISD::UREM);
525 
526   // setcc for f16x2 needs special handling to prevent legalizer's
527   // attempt to scalarize it due to v2i1 not being legal.
528   if (STI.allowFP16Math())
529     setTargetDAGCombine(ISD::SETCC);
530 
531   // Promote fp16 arithmetic if fp16 hardware isn't available or the
532   // user passed --nvptx-no-fp16-math. The flag is useful because,
533   // although sm_53+ GPUs have some sort of FP16 support in
534   // hardware, only sm_53 and sm_60 have full implementation. Others
535   // only have token amount of hardware and are likely to run faster
536   // by using fp32 units instead.
537   for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
538     setFP16OperationAction(Op, MVT::f16, Legal, Promote);
539     setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
540   }
541 
542   // There's no neg.f16 instruction. Expand to (0-x).
543   setOperationAction(ISD::FNEG, MVT::f16, Expand);
544   setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
545 
546   // (would be) Library functions.
547 
548   // These map to conversion instructions for scalar FP types.
549   for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
550                          ISD::FROUND, ISD::FTRUNC}) {
551     setOperationAction(Op, MVT::f16, Legal);
552     setOperationAction(Op, MVT::f32, Legal);
553     setOperationAction(Op, MVT::f64, Legal);
554     setOperationAction(Op, MVT::v2f16, Expand);
555   }
556 
557   // 'Expand' implements FCOPYSIGN without calling an external library.
558   setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
559   setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand);
560   setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
561   setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
562 
563   // These map to corresponding instructions for f32/f64. f16 must be
564   // promoted to f32. v2f16 is expanded to f16, which is then promoted
565   // to f32.
566   for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
567                          ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
568     setOperationAction(Op, MVT::f16, Promote);
569     setOperationAction(Op, MVT::f32, Legal);
570     setOperationAction(Op, MVT::f64, Legal);
571     setOperationAction(Op, MVT::v2f16, Expand);
572   }
573   setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
574   setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
575   setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
576   setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
577 
578   // No FEXP2, FLOG2.  The PTX ex2 and log2 functions are always approximate.
579   // No FPOW or FREM in PTX.
580 
581   // Now deduce the information based on the above mentioned
582   // actions
583   computeRegisterProperties(STI.getRegisterInfo());
584 }
585 
getTargetNodeName(unsigned Opcode) const586 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
587   switch ((NVPTXISD::NodeType)Opcode) {
588   case NVPTXISD::FIRST_NUMBER:
589     break;
590   case NVPTXISD::CALL:
591     return "NVPTXISD::CALL";
592   case NVPTXISD::RET_FLAG:
593     return "NVPTXISD::RET_FLAG";
594   case NVPTXISD::LOAD_PARAM:
595     return "NVPTXISD::LOAD_PARAM";
596   case NVPTXISD::Wrapper:
597     return "NVPTXISD::Wrapper";
598   case NVPTXISD::DeclareParam:
599     return "NVPTXISD::DeclareParam";
600   case NVPTXISD::DeclareScalarParam:
601     return "NVPTXISD::DeclareScalarParam";
602   case NVPTXISD::DeclareRet:
603     return "NVPTXISD::DeclareRet";
604   case NVPTXISD::DeclareScalarRet:
605     return "NVPTXISD::DeclareScalarRet";
606   case NVPTXISD::DeclareRetParam:
607     return "NVPTXISD::DeclareRetParam";
608   case NVPTXISD::PrintCall:
609     return "NVPTXISD::PrintCall";
610   case NVPTXISD::PrintConvergentCall:
611     return "NVPTXISD::PrintConvergentCall";
612   case NVPTXISD::PrintCallUni:
613     return "NVPTXISD::PrintCallUni";
614   case NVPTXISD::PrintConvergentCallUni:
615     return "NVPTXISD::PrintConvergentCallUni";
616   case NVPTXISD::LoadParam:
617     return "NVPTXISD::LoadParam";
618   case NVPTXISD::LoadParamV2:
619     return "NVPTXISD::LoadParamV2";
620   case NVPTXISD::LoadParamV4:
621     return "NVPTXISD::LoadParamV4";
622   case NVPTXISD::StoreParam:
623     return "NVPTXISD::StoreParam";
624   case NVPTXISD::StoreParamV2:
625     return "NVPTXISD::StoreParamV2";
626   case NVPTXISD::StoreParamV4:
627     return "NVPTXISD::StoreParamV4";
628   case NVPTXISD::StoreParamS32:
629     return "NVPTXISD::StoreParamS32";
630   case NVPTXISD::StoreParamU32:
631     return "NVPTXISD::StoreParamU32";
632   case NVPTXISD::CallArgBegin:
633     return "NVPTXISD::CallArgBegin";
634   case NVPTXISD::CallArg:
635     return "NVPTXISD::CallArg";
636   case NVPTXISD::LastCallArg:
637     return "NVPTXISD::LastCallArg";
638   case NVPTXISD::CallArgEnd:
639     return "NVPTXISD::CallArgEnd";
640   case NVPTXISD::CallVoid:
641     return "NVPTXISD::CallVoid";
642   case NVPTXISD::CallVal:
643     return "NVPTXISD::CallVal";
644   case NVPTXISD::CallSymbol:
645     return "NVPTXISD::CallSymbol";
646   case NVPTXISD::Prototype:
647     return "NVPTXISD::Prototype";
648   case NVPTXISD::MoveParam:
649     return "NVPTXISD::MoveParam";
650   case NVPTXISD::StoreRetval:
651     return "NVPTXISD::StoreRetval";
652   case NVPTXISD::StoreRetvalV2:
653     return "NVPTXISD::StoreRetvalV2";
654   case NVPTXISD::StoreRetvalV4:
655     return "NVPTXISD::StoreRetvalV4";
656   case NVPTXISD::PseudoUseParam:
657     return "NVPTXISD::PseudoUseParam";
658   case NVPTXISD::RETURN:
659     return "NVPTXISD::RETURN";
660   case NVPTXISD::CallSeqBegin:
661     return "NVPTXISD::CallSeqBegin";
662   case NVPTXISD::CallSeqEnd:
663     return "NVPTXISD::CallSeqEnd";
664   case NVPTXISD::CallPrototype:
665     return "NVPTXISD::CallPrototype";
666   case NVPTXISD::ProxyReg:
667     return "NVPTXISD::ProxyReg";
668   case NVPTXISD::LoadV2:
669     return "NVPTXISD::LoadV2";
670   case NVPTXISD::LoadV4:
671     return "NVPTXISD::LoadV4";
672   case NVPTXISD::LDGV2:
673     return "NVPTXISD::LDGV2";
674   case NVPTXISD::LDGV4:
675     return "NVPTXISD::LDGV4";
676   case NVPTXISD::LDUV2:
677     return "NVPTXISD::LDUV2";
678   case NVPTXISD::LDUV4:
679     return "NVPTXISD::LDUV4";
680   case NVPTXISD::StoreV2:
681     return "NVPTXISD::StoreV2";
682   case NVPTXISD::StoreV4:
683     return "NVPTXISD::StoreV4";
684   case NVPTXISD::FUN_SHFL_CLAMP:
685     return "NVPTXISD::FUN_SHFL_CLAMP";
686   case NVPTXISD::FUN_SHFR_CLAMP:
687     return "NVPTXISD::FUN_SHFR_CLAMP";
688   case NVPTXISD::IMAD:
689     return "NVPTXISD::IMAD";
690   case NVPTXISD::SETP_F16X2:
691     return "NVPTXISD::SETP_F16X2";
692   case NVPTXISD::Dummy:
693     return "NVPTXISD::Dummy";
694   case NVPTXISD::MUL_WIDE_SIGNED:
695     return "NVPTXISD::MUL_WIDE_SIGNED";
696   case NVPTXISD::MUL_WIDE_UNSIGNED:
697     return "NVPTXISD::MUL_WIDE_UNSIGNED";
698   case NVPTXISD::Tex1DFloatS32:        return "NVPTXISD::Tex1DFloatS32";
699   case NVPTXISD::Tex1DFloatFloat:      return "NVPTXISD::Tex1DFloatFloat";
700   case NVPTXISD::Tex1DFloatFloatLevel:
701     return "NVPTXISD::Tex1DFloatFloatLevel";
702   case NVPTXISD::Tex1DFloatFloatGrad:
703     return "NVPTXISD::Tex1DFloatFloatGrad";
704   case NVPTXISD::Tex1DS32S32:          return "NVPTXISD::Tex1DS32S32";
705   case NVPTXISD::Tex1DS32Float:        return "NVPTXISD::Tex1DS32Float";
706   case NVPTXISD::Tex1DS32FloatLevel:
707     return "NVPTXISD::Tex1DS32FloatLevel";
708   case NVPTXISD::Tex1DS32FloatGrad:
709     return "NVPTXISD::Tex1DS32FloatGrad";
710   case NVPTXISD::Tex1DU32S32:          return "NVPTXISD::Tex1DU32S32";
711   case NVPTXISD::Tex1DU32Float:        return "NVPTXISD::Tex1DU32Float";
712   case NVPTXISD::Tex1DU32FloatLevel:
713     return "NVPTXISD::Tex1DU32FloatLevel";
714   case NVPTXISD::Tex1DU32FloatGrad:
715     return "NVPTXISD::Tex1DU32FloatGrad";
716   case NVPTXISD::Tex1DArrayFloatS32:   return "NVPTXISD::Tex1DArrayFloatS32";
717   case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
718   case NVPTXISD::Tex1DArrayFloatFloatLevel:
719     return "NVPTXISD::Tex1DArrayFloatFloatLevel";
720   case NVPTXISD::Tex1DArrayFloatFloatGrad:
721     return "NVPTXISD::Tex1DArrayFloatFloatGrad";
722   case NVPTXISD::Tex1DArrayS32S32:     return "NVPTXISD::Tex1DArrayS32S32";
723   case NVPTXISD::Tex1DArrayS32Float:   return "NVPTXISD::Tex1DArrayS32Float";
724   case NVPTXISD::Tex1DArrayS32FloatLevel:
725     return "NVPTXISD::Tex1DArrayS32FloatLevel";
726   case NVPTXISD::Tex1DArrayS32FloatGrad:
727     return "NVPTXISD::Tex1DArrayS32FloatGrad";
728   case NVPTXISD::Tex1DArrayU32S32:     return "NVPTXISD::Tex1DArrayU32S32";
729   case NVPTXISD::Tex1DArrayU32Float:   return "NVPTXISD::Tex1DArrayU32Float";
730   case NVPTXISD::Tex1DArrayU32FloatLevel:
731     return "NVPTXISD::Tex1DArrayU32FloatLevel";
732   case NVPTXISD::Tex1DArrayU32FloatGrad:
733     return "NVPTXISD::Tex1DArrayU32FloatGrad";
734   case NVPTXISD::Tex2DFloatS32:        return "NVPTXISD::Tex2DFloatS32";
735   case NVPTXISD::Tex2DFloatFloat:      return "NVPTXISD::Tex2DFloatFloat";
736   case NVPTXISD::Tex2DFloatFloatLevel:
737     return "NVPTXISD::Tex2DFloatFloatLevel";
738   case NVPTXISD::Tex2DFloatFloatGrad:
739     return "NVPTXISD::Tex2DFloatFloatGrad";
740   case NVPTXISD::Tex2DS32S32:          return "NVPTXISD::Tex2DS32S32";
741   case NVPTXISD::Tex2DS32Float:        return "NVPTXISD::Tex2DS32Float";
742   case NVPTXISD::Tex2DS32FloatLevel:
743     return "NVPTXISD::Tex2DS32FloatLevel";
744   case NVPTXISD::Tex2DS32FloatGrad:
745     return "NVPTXISD::Tex2DS32FloatGrad";
746   case NVPTXISD::Tex2DU32S32:          return "NVPTXISD::Tex2DU32S32";
747   case NVPTXISD::Tex2DU32Float:        return "NVPTXISD::Tex2DU32Float";
748   case NVPTXISD::Tex2DU32FloatLevel:
749     return "NVPTXISD::Tex2DU32FloatLevel";
750   case NVPTXISD::Tex2DU32FloatGrad:
751     return "NVPTXISD::Tex2DU32FloatGrad";
752   case NVPTXISD::Tex2DArrayFloatS32:   return "NVPTXISD::Tex2DArrayFloatS32";
753   case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
754   case NVPTXISD::Tex2DArrayFloatFloatLevel:
755     return "NVPTXISD::Tex2DArrayFloatFloatLevel";
756   case NVPTXISD::Tex2DArrayFloatFloatGrad:
757     return "NVPTXISD::Tex2DArrayFloatFloatGrad";
758   case NVPTXISD::Tex2DArrayS32S32:     return "NVPTXISD::Tex2DArrayS32S32";
759   case NVPTXISD::Tex2DArrayS32Float:   return "NVPTXISD::Tex2DArrayS32Float";
760   case NVPTXISD::Tex2DArrayS32FloatLevel:
761     return "NVPTXISD::Tex2DArrayS32FloatLevel";
762   case NVPTXISD::Tex2DArrayS32FloatGrad:
763     return "NVPTXISD::Tex2DArrayS32FloatGrad";
764   case NVPTXISD::Tex2DArrayU32S32:     return "NVPTXISD::Tex2DArrayU32S32";
765   case NVPTXISD::Tex2DArrayU32Float:   return "NVPTXISD::Tex2DArrayU32Float";
766   case NVPTXISD::Tex2DArrayU32FloatLevel:
767     return "NVPTXISD::Tex2DArrayU32FloatLevel";
768   case NVPTXISD::Tex2DArrayU32FloatGrad:
769     return "NVPTXISD::Tex2DArrayU32FloatGrad";
770   case NVPTXISD::Tex3DFloatS32:        return "NVPTXISD::Tex3DFloatS32";
771   case NVPTXISD::Tex3DFloatFloat:      return "NVPTXISD::Tex3DFloatFloat";
772   case NVPTXISD::Tex3DFloatFloatLevel:
773     return "NVPTXISD::Tex3DFloatFloatLevel";
774   case NVPTXISD::Tex3DFloatFloatGrad:
775     return "NVPTXISD::Tex3DFloatFloatGrad";
776   case NVPTXISD::Tex3DS32S32:          return "NVPTXISD::Tex3DS32S32";
777   case NVPTXISD::Tex3DS32Float:        return "NVPTXISD::Tex3DS32Float";
778   case NVPTXISD::Tex3DS32FloatLevel:
779     return "NVPTXISD::Tex3DS32FloatLevel";
780   case NVPTXISD::Tex3DS32FloatGrad:
781     return "NVPTXISD::Tex3DS32FloatGrad";
782   case NVPTXISD::Tex3DU32S32:          return "NVPTXISD::Tex3DU32S32";
783   case NVPTXISD::Tex3DU32Float:        return "NVPTXISD::Tex3DU32Float";
784   case NVPTXISD::Tex3DU32FloatLevel:
785     return "NVPTXISD::Tex3DU32FloatLevel";
786   case NVPTXISD::Tex3DU32FloatGrad:
787     return "NVPTXISD::Tex3DU32FloatGrad";
788   case NVPTXISD::TexCubeFloatFloat:      return "NVPTXISD::TexCubeFloatFloat";
789   case NVPTXISD::TexCubeFloatFloatLevel:
790     return "NVPTXISD::TexCubeFloatFloatLevel";
791   case NVPTXISD::TexCubeS32Float:        return "NVPTXISD::TexCubeS32Float";
792   case NVPTXISD::TexCubeS32FloatLevel:
793     return "NVPTXISD::TexCubeS32FloatLevel";
794   case NVPTXISD::TexCubeU32Float:        return "NVPTXISD::TexCubeU32Float";
795   case NVPTXISD::TexCubeU32FloatLevel:
796     return "NVPTXISD::TexCubeU32FloatLevel";
797   case NVPTXISD::TexCubeArrayFloatFloat:
798     return "NVPTXISD::TexCubeArrayFloatFloat";
799   case NVPTXISD::TexCubeArrayFloatFloatLevel:
800     return "NVPTXISD::TexCubeArrayFloatFloatLevel";
801   case NVPTXISD::TexCubeArrayS32Float:
802     return "NVPTXISD::TexCubeArrayS32Float";
803   case NVPTXISD::TexCubeArrayS32FloatLevel:
804     return "NVPTXISD::TexCubeArrayS32FloatLevel";
805   case NVPTXISD::TexCubeArrayU32Float:
806     return "NVPTXISD::TexCubeArrayU32Float";
807   case NVPTXISD::TexCubeArrayU32FloatLevel:
808     return "NVPTXISD::TexCubeArrayU32FloatLevel";
809   case NVPTXISD::Tld4R2DFloatFloat:
810     return "NVPTXISD::Tld4R2DFloatFloat";
811   case NVPTXISD::Tld4G2DFloatFloat:
812     return "NVPTXISD::Tld4G2DFloatFloat";
813   case NVPTXISD::Tld4B2DFloatFloat:
814     return "NVPTXISD::Tld4B2DFloatFloat";
815   case NVPTXISD::Tld4A2DFloatFloat:
816     return "NVPTXISD::Tld4A2DFloatFloat";
817   case NVPTXISD::Tld4R2DS64Float:
818     return "NVPTXISD::Tld4R2DS64Float";
819   case NVPTXISD::Tld4G2DS64Float:
820     return "NVPTXISD::Tld4G2DS64Float";
821   case NVPTXISD::Tld4B2DS64Float:
822     return "NVPTXISD::Tld4B2DS64Float";
823   case NVPTXISD::Tld4A2DS64Float:
824     return "NVPTXISD::Tld4A2DS64Float";
825   case NVPTXISD::Tld4R2DU64Float:
826     return "NVPTXISD::Tld4R2DU64Float";
827   case NVPTXISD::Tld4G2DU64Float:
828     return "NVPTXISD::Tld4G2DU64Float";
829   case NVPTXISD::Tld4B2DU64Float:
830     return "NVPTXISD::Tld4B2DU64Float";
831   case NVPTXISD::Tld4A2DU64Float:
832     return "NVPTXISD::Tld4A2DU64Float";
833 
834   case NVPTXISD::TexUnified1DFloatS32:
835     return "NVPTXISD::TexUnified1DFloatS32";
836   case NVPTXISD::TexUnified1DFloatFloat:
837     return "NVPTXISD::TexUnified1DFloatFloat";
838   case NVPTXISD::TexUnified1DFloatFloatLevel:
839     return "NVPTXISD::TexUnified1DFloatFloatLevel";
840   case NVPTXISD::TexUnified1DFloatFloatGrad:
841     return "NVPTXISD::TexUnified1DFloatFloatGrad";
842   case NVPTXISD::TexUnified1DS32S32:
843     return "NVPTXISD::TexUnified1DS32S32";
844   case NVPTXISD::TexUnified1DS32Float:
845     return "NVPTXISD::TexUnified1DS32Float";
846   case NVPTXISD::TexUnified1DS32FloatLevel:
847     return "NVPTXISD::TexUnified1DS32FloatLevel";
848   case NVPTXISD::TexUnified1DS32FloatGrad:
849     return "NVPTXISD::TexUnified1DS32FloatGrad";
850   case NVPTXISD::TexUnified1DU32S32:
851     return "NVPTXISD::TexUnified1DU32S32";
852   case NVPTXISD::TexUnified1DU32Float:
853     return "NVPTXISD::TexUnified1DU32Float";
854   case NVPTXISD::TexUnified1DU32FloatLevel:
855     return "NVPTXISD::TexUnified1DU32FloatLevel";
856   case NVPTXISD::TexUnified1DU32FloatGrad:
857     return "NVPTXISD::TexUnified1DU32FloatGrad";
858   case NVPTXISD::TexUnified1DArrayFloatS32:
859     return "NVPTXISD::TexUnified1DArrayFloatS32";
860   case NVPTXISD::TexUnified1DArrayFloatFloat:
861     return "NVPTXISD::TexUnified1DArrayFloatFloat";
862   case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
863     return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
864   case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
865     return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
866   case NVPTXISD::TexUnified1DArrayS32S32:
867     return "NVPTXISD::TexUnified1DArrayS32S32";
868   case NVPTXISD::TexUnified1DArrayS32Float:
869     return "NVPTXISD::TexUnified1DArrayS32Float";
870   case NVPTXISD::TexUnified1DArrayS32FloatLevel:
871     return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
872   case NVPTXISD::TexUnified1DArrayS32FloatGrad:
873     return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
874   case NVPTXISD::TexUnified1DArrayU32S32:
875     return "NVPTXISD::TexUnified1DArrayU32S32";
876   case NVPTXISD::TexUnified1DArrayU32Float:
877     return "NVPTXISD::TexUnified1DArrayU32Float";
878   case NVPTXISD::TexUnified1DArrayU32FloatLevel:
879     return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
880   case NVPTXISD::TexUnified1DArrayU32FloatGrad:
881     return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
882   case NVPTXISD::TexUnified2DFloatS32:
883     return "NVPTXISD::TexUnified2DFloatS32";
884   case NVPTXISD::TexUnified2DFloatFloat:
885     return "NVPTXISD::TexUnified2DFloatFloat";
886   case NVPTXISD::TexUnified2DFloatFloatLevel:
887     return "NVPTXISD::TexUnified2DFloatFloatLevel";
888   case NVPTXISD::TexUnified2DFloatFloatGrad:
889     return "NVPTXISD::TexUnified2DFloatFloatGrad";
890   case NVPTXISD::TexUnified2DS32S32:
891     return "NVPTXISD::TexUnified2DS32S32";
892   case NVPTXISD::TexUnified2DS32Float:
893     return "NVPTXISD::TexUnified2DS32Float";
894   case NVPTXISD::TexUnified2DS32FloatLevel:
895     return "NVPTXISD::TexUnified2DS32FloatLevel";
896   case NVPTXISD::TexUnified2DS32FloatGrad:
897     return "NVPTXISD::TexUnified2DS32FloatGrad";
898   case NVPTXISD::TexUnified2DU32S32:
899     return "NVPTXISD::TexUnified2DU32S32";
900   case NVPTXISD::TexUnified2DU32Float:
901     return "NVPTXISD::TexUnified2DU32Float";
902   case NVPTXISD::TexUnified2DU32FloatLevel:
903     return "NVPTXISD::TexUnified2DU32FloatLevel";
904   case NVPTXISD::TexUnified2DU32FloatGrad:
905     return "NVPTXISD::TexUnified2DU32FloatGrad";
906   case NVPTXISD::TexUnified2DArrayFloatS32:
907     return "NVPTXISD::TexUnified2DArrayFloatS32";
908   case NVPTXISD::TexUnified2DArrayFloatFloat:
909     return "NVPTXISD::TexUnified2DArrayFloatFloat";
910   case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
911     return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
912   case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
913     return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
914   case NVPTXISD::TexUnified2DArrayS32S32:
915     return "NVPTXISD::TexUnified2DArrayS32S32";
916   case NVPTXISD::TexUnified2DArrayS32Float:
917     return "NVPTXISD::TexUnified2DArrayS32Float";
918   case NVPTXISD::TexUnified2DArrayS32FloatLevel:
919     return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
920   case NVPTXISD::TexUnified2DArrayS32FloatGrad:
921     return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
922   case NVPTXISD::TexUnified2DArrayU32S32:
923     return "NVPTXISD::TexUnified2DArrayU32S32";
924   case NVPTXISD::TexUnified2DArrayU32Float:
925     return "NVPTXISD::TexUnified2DArrayU32Float";
926   case NVPTXISD::TexUnified2DArrayU32FloatLevel:
927     return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
928   case NVPTXISD::TexUnified2DArrayU32FloatGrad:
929     return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
930   case NVPTXISD::TexUnified3DFloatS32:
931     return "NVPTXISD::TexUnified3DFloatS32";
932   case NVPTXISD::TexUnified3DFloatFloat:
933     return "NVPTXISD::TexUnified3DFloatFloat";
934   case NVPTXISD::TexUnified3DFloatFloatLevel:
935     return "NVPTXISD::TexUnified3DFloatFloatLevel";
936   case NVPTXISD::TexUnified3DFloatFloatGrad:
937     return "NVPTXISD::TexUnified3DFloatFloatGrad";
938   case NVPTXISD::TexUnified3DS32S32:
939     return "NVPTXISD::TexUnified3DS32S32";
940   case NVPTXISD::TexUnified3DS32Float:
941     return "NVPTXISD::TexUnified3DS32Float";
942   case NVPTXISD::TexUnified3DS32FloatLevel:
943     return "NVPTXISD::TexUnified3DS32FloatLevel";
944   case NVPTXISD::TexUnified3DS32FloatGrad:
945     return "NVPTXISD::TexUnified3DS32FloatGrad";
946   case NVPTXISD::TexUnified3DU32S32:
947     return "NVPTXISD::TexUnified3DU32S32";
948   case NVPTXISD::TexUnified3DU32Float:
949     return "NVPTXISD::TexUnified3DU32Float";
950   case NVPTXISD::TexUnified3DU32FloatLevel:
951     return "NVPTXISD::TexUnified3DU32FloatLevel";
952   case NVPTXISD::TexUnified3DU32FloatGrad:
953     return "NVPTXISD::TexUnified3DU32FloatGrad";
954   case NVPTXISD::TexUnifiedCubeFloatFloat:
955     return "NVPTXISD::TexUnifiedCubeFloatFloat";
956   case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
957     return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
958   case NVPTXISD::TexUnifiedCubeS32Float:
959     return "NVPTXISD::TexUnifiedCubeS32Float";
960   case NVPTXISD::TexUnifiedCubeS32FloatLevel:
961     return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
962   case NVPTXISD::TexUnifiedCubeU32Float:
963     return "NVPTXISD::TexUnifiedCubeU32Float";
964   case NVPTXISD::TexUnifiedCubeU32FloatLevel:
965     return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
966   case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
967     return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
968   case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
969     return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
970   case NVPTXISD::TexUnifiedCubeArrayS32Float:
971     return "NVPTXISD::TexUnifiedCubeArrayS32Float";
972   case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
973     return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
974   case NVPTXISD::TexUnifiedCubeArrayU32Float:
975     return "NVPTXISD::TexUnifiedCubeArrayU32Float";
976   case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
977     return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
978   case NVPTXISD::Tld4UnifiedR2DFloatFloat:
979     return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
980   case NVPTXISD::Tld4UnifiedG2DFloatFloat:
981     return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
982   case NVPTXISD::Tld4UnifiedB2DFloatFloat:
983     return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
984   case NVPTXISD::Tld4UnifiedA2DFloatFloat:
985     return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
986   case NVPTXISD::Tld4UnifiedR2DS64Float:
987     return "NVPTXISD::Tld4UnifiedR2DS64Float";
988   case NVPTXISD::Tld4UnifiedG2DS64Float:
989     return "NVPTXISD::Tld4UnifiedG2DS64Float";
990   case NVPTXISD::Tld4UnifiedB2DS64Float:
991     return "NVPTXISD::Tld4UnifiedB2DS64Float";
992   case NVPTXISD::Tld4UnifiedA2DS64Float:
993     return "NVPTXISD::Tld4UnifiedA2DS64Float";
994   case NVPTXISD::Tld4UnifiedR2DU64Float:
995     return "NVPTXISD::Tld4UnifiedR2DU64Float";
996   case NVPTXISD::Tld4UnifiedG2DU64Float:
997     return "NVPTXISD::Tld4UnifiedG2DU64Float";
998   case NVPTXISD::Tld4UnifiedB2DU64Float:
999     return "NVPTXISD::Tld4UnifiedB2DU64Float";
1000   case NVPTXISD::Tld4UnifiedA2DU64Float:
1001     return "NVPTXISD::Tld4UnifiedA2DU64Float";
1002 
1003   case NVPTXISD::Suld1DI8Clamp:          return "NVPTXISD::Suld1DI8Clamp";
1004   case NVPTXISD::Suld1DI16Clamp:         return "NVPTXISD::Suld1DI16Clamp";
1005   case NVPTXISD::Suld1DI32Clamp:         return "NVPTXISD::Suld1DI32Clamp";
1006   case NVPTXISD::Suld1DI64Clamp:         return "NVPTXISD::Suld1DI64Clamp";
1007   case NVPTXISD::Suld1DV2I8Clamp:        return "NVPTXISD::Suld1DV2I8Clamp";
1008   case NVPTXISD::Suld1DV2I16Clamp:       return "NVPTXISD::Suld1DV2I16Clamp";
1009   case NVPTXISD::Suld1DV2I32Clamp:       return "NVPTXISD::Suld1DV2I32Clamp";
1010   case NVPTXISD::Suld1DV2I64Clamp:       return "NVPTXISD::Suld1DV2I64Clamp";
1011   case NVPTXISD::Suld1DV4I8Clamp:        return "NVPTXISD::Suld1DV4I8Clamp";
1012   case NVPTXISD::Suld1DV4I16Clamp:       return "NVPTXISD::Suld1DV4I16Clamp";
1013   case NVPTXISD::Suld1DV4I32Clamp:       return "NVPTXISD::Suld1DV4I32Clamp";
1014 
1015   case NVPTXISD::Suld1DArrayI8Clamp:   return "NVPTXISD::Suld1DArrayI8Clamp";
1016   case NVPTXISD::Suld1DArrayI16Clamp:  return "NVPTXISD::Suld1DArrayI16Clamp";
1017   case NVPTXISD::Suld1DArrayI32Clamp:  return "NVPTXISD::Suld1DArrayI32Clamp";
1018   case NVPTXISD::Suld1DArrayI64Clamp:  return "NVPTXISD::Suld1DArrayI64Clamp";
1019   case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
1020   case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
1021   case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
1022   case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
1023   case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
1024   case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
1025   case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
1026 
1027   case NVPTXISD::Suld2DI8Clamp:          return "NVPTXISD::Suld2DI8Clamp";
1028   case NVPTXISD::Suld2DI16Clamp:         return "NVPTXISD::Suld2DI16Clamp";
1029   case NVPTXISD::Suld2DI32Clamp:         return "NVPTXISD::Suld2DI32Clamp";
1030   case NVPTXISD::Suld2DI64Clamp:         return "NVPTXISD::Suld2DI64Clamp";
1031   case NVPTXISD::Suld2DV2I8Clamp:        return "NVPTXISD::Suld2DV2I8Clamp";
1032   case NVPTXISD::Suld2DV2I16Clamp:       return "NVPTXISD::Suld2DV2I16Clamp";
1033   case NVPTXISD::Suld2DV2I32Clamp:       return "NVPTXISD::Suld2DV2I32Clamp";
1034   case NVPTXISD::Suld2DV2I64Clamp:       return "NVPTXISD::Suld2DV2I64Clamp";
1035   case NVPTXISD::Suld2DV4I8Clamp:        return "NVPTXISD::Suld2DV4I8Clamp";
1036   case NVPTXISD::Suld2DV4I16Clamp:       return "NVPTXISD::Suld2DV4I16Clamp";
1037   case NVPTXISD::Suld2DV4I32Clamp:       return "NVPTXISD::Suld2DV4I32Clamp";
1038 
1039   case NVPTXISD::Suld2DArrayI8Clamp:   return "NVPTXISD::Suld2DArrayI8Clamp";
1040   case NVPTXISD::Suld2DArrayI16Clamp:  return "NVPTXISD::Suld2DArrayI16Clamp";
1041   case NVPTXISD::Suld2DArrayI32Clamp:  return "NVPTXISD::Suld2DArrayI32Clamp";
1042   case NVPTXISD::Suld2DArrayI64Clamp:  return "NVPTXISD::Suld2DArrayI64Clamp";
1043   case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
1044   case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
1045   case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
1046   case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
1047   case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
1048   case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
1049   case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
1050 
1051   case NVPTXISD::Suld3DI8Clamp:          return "NVPTXISD::Suld3DI8Clamp";
1052   case NVPTXISD::Suld3DI16Clamp:         return "NVPTXISD::Suld3DI16Clamp";
1053   case NVPTXISD::Suld3DI32Clamp:         return "NVPTXISD::Suld3DI32Clamp";
1054   case NVPTXISD::Suld3DI64Clamp:         return "NVPTXISD::Suld3DI64Clamp";
1055   case NVPTXISD::Suld3DV2I8Clamp:        return "NVPTXISD::Suld3DV2I8Clamp";
1056   case NVPTXISD::Suld3DV2I16Clamp:       return "NVPTXISD::Suld3DV2I16Clamp";
1057   case NVPTXISD::Suld3DV2I32Clamp:       return "NVPTXISD::Suld3DV2I32Clamp";
1058   case NVPTXISD::Suld3DV2I64Clamp:       return "NVPTXISD::Suld3DV2I64Clamp";
1059   case NVPTXISD::Suld3DV4I8Clamp:        return "NVPTXISD::Suld3DV4I8Clamp";
1060   case NVPTXISD::Suld3DV4I16Clamp:       return "NVPTXISD::Suld3DV4I16Clamp";
1061   case NVPTXISD::Suld3DV4I32Clamp:       return "NVPTXISD::Suld3DV4I32Clamp";
1062 
1063   case NVPTXISD::Suld1DI8Trap:          return "NVPTXISD::Suld1DI8Trap";
1064   case NVPTXISD::Suld1DI16Trap:         return "NVPTXISD::Suld1DI16Trap";
1065   case NVPTXISD::Suld1DI32Trap:         return "NVPTXISD::Suld1DI32Trap";
1066   case NVPTXISD::Suld1DI64Trap:         return "NVPTXISD::Suld1DI64Trap";
1067   case NVPTXISD::Suld1DV2I8Trap:        return "NVPTXISD::Suld1DV2I8Trap";
1068   case NVPTXISD::Suld1DV2I16Trap:       return "NVPTXISD::Suld1DV2I16Trap";
1069   case NVPTXISD::Suld1DV2I32Trap:       return "NVPTXISD::Suld1DV2I32Trap";
1070   case NVPTXISD::Suld1DV2I64Trap:       return "NVPTXISD::Suld1DV2I64Trap";
1071   case NVPTXISD::Suld1DV4I8Trap:        return "NVPTXISD::Suld1DV4I8Trap";
1072   case NVPTXISD::Suld1DV4I16Trap:       return "NVPTXISD::Suld1DV4I16Trap";
1073   case NVPTXISD::Suld1DV4I32Trap:       return "NVPTXISD::Suld1DV4I32Trap";
1074 
1075   case NVPTXISD::Suld1DArrayI8Trap:     return "NVPTXISD::Suld1DArrayI8Trap";
1076   case NVPTXISD::Suld1DArrayI16Trap:    return "NVPTXISD::Suld1DArrayI16Trap";
1077   case NVPTXISD::Suld1DArrayI32Trap:    return "NVPTXISD::Suld1DArrayI32Trap";
1078   case NVPTXISD::Suld1DArrayI64Trap:    return "NVPTXISD::Suld1DArrayI64Trap";
1079   case NVPTXISD::Suld1DArrayV2I8Trap:   return "NVPTXISD::Suld1DArrayV2I8Trap";
1080   case NVPTXISD::Suld1DArrayV2I16Trap:  return "NVPTXISD::Suld1DArrayV2I16Trap";
1081   case NVPTXISD::Suld1DArrayV2I32Trap:  return "NVPTXISD::Suld1DArrayV2I32Trap";
1082   case NVPTXISD::Suld1DArrayV2I64Trap:  return "NVPTXISD::Suld1DArrayV2I64Trap";
1083   case NVPTXISD::Suld1DArrayV4I8Trap:   return "NVPTXISD::Suld1DArrayV4I8Trap";
1084   case NVPTXISD::Suld1DArrayV4I16Trap:  return "NVPTXISD::Suld1DArrayV4I16Trap";
1085   case NVPTXISD::Suld1DArrayV4I32Trap:  return "NVPTXISD::Suld1DArrayV4I32Trap";
1086 
1087   case NVPTXISD::Suld2DI8Trap:          return "NVPTXISD::Suld2DI8Trap";
1088   case NVPTXISD::Suld2DI16Trap:         return "NVPTXISD::Suld2DI16Trap";
1089   case NVPTXISD::Suld2DI32Trap:         return "NVPTXISD::Suld2DI32Trap";
1090   case NVPTXISD::Suld2DI64Trap:         return "NVPTXISD::Suld2DI64Trap";
1091   case NVPTXISD::Suld2DV2I8Trap:        return "NVPTXISD::Suld2DV2I8Trap";
1092   case NVPTXISD::Suld2DV2I16Trap:       return "NVPTXISD::Suld2DV2I16Trap";
1093   case NVPTXISD::Suld2DV2I32Trap:       return "NVPTXISD::Suld2DV2I32Trap";
1094   case NVPTXISD::Suld2DV2I64Trap:       return "NVPTXISD::Suld2DV2I64Trap";
1095   case NVPTXISD::Suld2DV4I8Trap:        return "NVPTXISD::Suld2DV4I8Trap";
1096   case NVPTXISD::Suld2DV4I16Trap:       return "NVPTXISD::Suld2DV4I16Trap";
1097   case NVPTXISD::Suld2DV4I32Trap:       return "NVPTXISD::Suld2DV4I32Trap";
1098 
1099   case NVPTXISD::Suld2DArrayI8Trap:     return "NVPTXISD::Suld2DArrayI8Trap";
1100   case NVPTXISD::Suld2DArrayI16Trap:    return "NVPTXISD::Suld2DArrayI16Trap";
1101   case NVPTXISD::Suld2DArrayI32Trap:    return "NVPTXISD::Suld2DArrayI32Trap";
1102   case NVPTXISD::Suld2DArrayI64Trap:    return "NVPTXISD::Suld2DArrayI64Trap";
1103   case NVPTXISD::Suld2DArrayV2I8Trap:   return "NVPTXISD::Suld2DArrayV2I8Trap";
1104   case NVPTXISD::Suld2DArrayV2I16Trap:  return "NVPTXISD::Suld2DArrayV2I16Trap";
1105   case NVPTXISD::Suld2DArrayV2I32Trap:  return "NVPTXISD::Suld2DArrayV2I32Trap";
1106   case NVPTXISD::Suld2DArrayV2I64Trap:  return "NVPTXISD::Suld2DArrayV2I64Trap";
1107   case NVPTXISD::Suld2DArrayV4I8Trap:   return "NVPTXISD::Suld2DArrayV4I8Trap";
1108   case NVPTXISD::Suld2DArrayV4I16Trap:  return "NVPTXISD::Suld2DArrayV4I16Trap";
1109   case NVPTXISD::Suld2DArrayV4I32Trap:  return "NVPTXISD::Suld2DArrayV4I32Trap";
1110 
1111   case NVPTXISD::Suld3DI8Trap:          return "NVPTXISD::Suld3DI8Trap";
1112   case NVPTXISD::Suld3DI16Trap:         return "NVPTXISD::Suld3DI16Trap";
1113   case NVPTXISD::Suld3DI32Trap:         return "NVPTXISD::Suld3DI32Trap";
1114   case NVPTXISD::Suld3DI64Trap:         return "NVPTXISD::Suld3DI64Trap";
1115   case NVPTXISD::Suld3DV2I8Trap:        return "NVPTXISD::Suld3DV2I8Trap";
1116   case NVPTXISD::Suld3DV2I16Trap:       return "NVPTXISD::Suld3DV2I16Trap";
1117   case NVPTXISD::Suld3DV2I32Trap:       return "NVPTXISD::Suld3DV2I32Trap";
1118   case NVPTXISD::Suld3DV2I64Trap:       return "NVPTXISD::Suld3DV2I64Trap";
1119   case NVPTXISD::Suld3DV4I8Trap:        return "NVPTXISD::Suld3DV4I8Trap";
1120   case NVPTXISD::Suld3DV4I16Trap:       return "NVPTXISD::Suld3DV4I16Trap";
1121   case NVPTXISD::Suld3DV4I32Trap:       return "NVPTXISD::Suld3DV4I32Trap";
1122 
1123   case NVPTXISD::Suld1DI8Zero:          return "NVPTXISD::Suld1DI8Zero";
1124   case NVPTXISD::Suld1DI16Zero:         return "NVPTXISD::Suld1DI16Zero";
1125   case NVPTXISD::Suld1DI32Zero:         return "NVPTXISD::Suld1DI32Zero";
1126   case NVPTXISD::Suld1DI64Zero:         return "NVPTXISD::Suld1DI64Zero";
1127   case NVPTXISD::Suld1DV2I8Zero:        return "NVPTXISD::Suld1DV2I8Zero";
1128   case NVPTXISD::Suld1DV2I16Zero:       return "NVPTXISD::Suld1DV2I16Zero";
1129   case NVPTXISD::Suld1DV2I32Zero:       return "NVPTXISD::Suld1DV2I32Zero";
1130   case NVPTXISD::Suld1DV2I64Zero:       return "NVPTXISD::Suld1DV2I64Zero";
1131   case NVPTXISD::Suld1DV4I8Zero:        return "NVPTXISD::Suld1DV4I8Zero";
1132   case NVPTXISD::Suld1DV4I16Zero:       return "NVPTXISD::Suld1DV4I16Zero";
1133   case NVPTXISD::Suld1DV4I32Zero:       return "NVPTXISD::Suld1DV4I32Zero";
1134 
1135   case NVPTXISD::Suld1DArrayI8Zero:     return "NVPTXISD::Suld1DArrayI8Zero";
1136   case NVPTXISD::Suld1DArrayI16Zero:    return "NVPTXISD::Suld1DArrayI16Zero";
1137   case NVPTXISD::Suld1DArrayI32Zero:    return "NVPTXISD::Suld1DArrayI32Zero";
1138   case NVPTXISD::Suld1DArrayI64Zero:    return "NVPTXISD::Suld1DArrayI64Zero";
1139   case NVPTXISD::Suld1DArrayV2I8Zero:   return "NVPTXISD::Suld1DArrayV2I8Zero";
1140   case NVPTXISD::Suld1DArrayV2I16Zero:  return "NVPTXISD::Suld1DArrayV2I16Zero";
1141   case NVPTXISD::Suld1DArrayV2I32Zero:  return "NVPTXISD::Suld1DArrayV2I32Zero";
1142   case NVPTXISD::Suld1DArrayV2I64Zero:  return "NVPTXISD::Suld1DArrayV2I64Zero";
1143   case NVPTXISD::Suld1DArrayV4I8Zero:   return "NVPTXISD::Suld1DArrayV4I8Zero";
1144   case NVPTXISD::Suld1DArrayV4I16Zero:  return "NVPTXISD::Suld1DArrayV4I16Zero";
1145   case NVPTXISD::Suld1DArrayV4I32Zero:  return "NVPTXISD::Suld1DArrayV4I32Zero";
1146 
1147   case NVPTXISD::Suld2DI8Zero:          return "NVPTXISD::Suld2DI8Zero";
1148   case NVPTXISD::Suld2DI16Zero:         return "NVPTXISD::Suld2DI16Zero";
1149   case NVPTXISD::Suld2DI32Zero:         return "NVPTXISD::Suld2DI32Zero";
1150   case NVPTXISD::Suld2DI64Zero:         return "NVPTXISD::Suld2DI64Zero";
1151   case NVPTXISD::Suld2DV2I8Zero:        return "NVPTXISD::Suld2DV2I8Zero";
1152   case NVPTXISD::Suld2DV2I16Zero:       return "NVPTXISD::Suld2DV2I16Zero";
1153   case NVPTXISD::Suld2DV2I32Zero:       return "NVPTXISD::Suld2DV2I32Zero";
1154   case NVPTXISD::Suld2DV2I64Zero:       return "NVPTXISD::Suld2DV2I64Zero";
1155   case NVPTXISD::Suld2DV4I8Zero:        return "NVPTXISD::Suld2DV4I8Zero";
1156   case NVPTXISD::Suld2DV4I16Zero:       return "NVPTXISD::Suld2DV4I16Zero";
1157   case NVPTXISD::Suld2DV4I32Zero:       return "NVPTXISD::Suld2DV4I32Zero";
1158 
1159   case NVPTXISD::Suld2DArrayI8Zero:     return "NVPTXISD::Suld2DArrayI8Zero";
1160   case NVPTXISD::Suld2DArrayI16Zero:    return "NVPTXISD::Suld2DArrayI16Zero";
1161   case NVPTXISD::Suld2DArrayI32Zero:    return "NVPTXISD::Suld2DArrayI32Zero";
1162   case NVPTXISD::Suld2DArrayI64Zero:    return "NVPTXISD::Suld2DArrayI64Zero";
1163   case NVPTXISD::Suld2DArrayV2I8Zero:   return "NVPTXISD::Suld2DArrayV2I8Zero";
1164   case NVPTXISD::Suld2DArrayV2I16Zero:  return "NVPTXISD::Suld2DArrayV2I16Zero";
1165   case NVPTXISD::Suld2DArrayV2I32Zero:  return "NVPTXISD::Suld2DArrayV2I32Zero";
1166   case NVPTXISD::Suld2DArrayV2I64Zero:  return "NVPTXISD::Suld2DArrayV2I64Zero";
1167   case NVPTXISD::Suld2DArrayV4I8Zero:   return "NVPTXISD::Suld2DArrayV4I8Zero";
1168   case NVPTXISD::Suld2DArrayV4I16Zero:  return "NVPTXISD::Suld2DArrayV4I16Zero";
1169   case NVPTXISD::Suld2DArrayV4I32Zero:  return "NVPTXISD::Suld2DArrayV4I32Zero";
1170 
1171   case NVPTXISD::Suld3DI8Zero:          return "NVPTXISD::Suld3DI8Zero";
1172   case NVPTXISD::Suld3DI16Zero:         return "NVPTXISD::Suld3DI16Zero";
1173   case NVPTXISD::Suld3DI32Zero:         return "NVPTXISD::Suld3DI32Zero";
1174   case NVPTXISD::Suld3DI64Zero:         return "NVPTXISD::Suld3DI64Zero";
1175   case NVPTXISD::Suld3DV2I8Zero:        return "NVPTXISD::Suld3DV2I8Zero";
1176   case NVPTXISD::Suld3DV2I16Zero:       return "NVPTXISD::Suld3DV2I16Zero";
1177   case NVPTXISD::Suld3DV2I32Zero:       return "NVPTXISD::Suld3DV2I32Zero";
1178   case NVPTXISD::Suld3DV2I64Zero:       return "NVPTXISD::Suld3DV2I64Zero";
1179   case NVPTXISD::Suld3DV4I8Zero:        return "NVPTXISD::Suld3DV4I8Zero";
1180   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
1181   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
1182   }
1183   return nullptr;
1184 }
1185 
1186 TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(MVT VT) const1187 NVPTXTargetLowering::getPreferredVectorAction(MVT VT) const {
1188   if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
1189     return TypeSplitVector;
1190   if (VT == MVT::v2f16)
1191     return TypeLegal;
1192   return TargetLoweringBase::getPreferredVectorAction(VT);
1193 }
1194 
getSqrtEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & ExtraSteps,bool & UseOneConst,bool Reciprocal) const1195 SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
1196                                              int Enabled, int &ExtraSteps,
1197                                              bool &UseOneConst,
1198                                              bool Reciprocal) const {
1199   if (!(Enabled == ReciprocalEstimate::Enabled ||
1200         (Enabled == ReciprocalEstimate::Unspecified && !usePrecSqrtF32())))
1201     return SDValue();
1202 
1203   if (ExtraSteps == ReciprocalEstimate::Unspecified)
1204     ExtraSteps = 0;
1205 
1206   SDLoc DL(Operand);
1207   EVT VT = Operand.getValueType();
1208   bool Ftz = useF32FTZ(DAG.getMachineFunction());
1209 
1210   auto MakeIntrinsicCall = [&](Intrinsic::ID IID) {
1211     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
1212                        DAG.getConstant(IID, DL, MVT::i32), Operand);
1213   };
1214 
1215   // The sqrt and rsqrt refinement processes assume we always start out with an
1216   // approximation of the rsqrt.  Therefore, if we're going to do any refinement
1217   // (i.e. ExtraSteps > 0), we must return an rsqrt.  But if we're *not* doing
1218   // any refinement, we must return a regular sqrt.
1219   if (Reciprocal || ExtraSteps > 0) {
1220     if (VT == MVT::f32)
1221       return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_rsqrt_approx_ftz_f
1222                                    : Intrinsic::nvvm_rsqrt_approx_f);
1223     else if (VT == MVT::f64)
1224       return MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d);
1225     else
1226       return SDValue();
1227   } else {
1228     if (VT == MVT::f32)
1229       return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_sqrt_approx_ftz_f
1230                                    : Intrinsic::nvvm_sqrt_approx_f);
1231     else {
1232       // There's no sqrt.approx.f64 instruction, so we emit
1233       // reciprocal(rsqrt(x)).  This is faster than
1234       // select(x == 0, 0, x * rsqrt(x)).  (In fact, it's faster than plain
1235       // x * rsqrt(x).)
1236       return DAG.getNode(
1237           ISD::INTRINSIC_WO_CHAIN, DL, VT,
1238           DAG.getConstant(Intrinsic::nvvm_rcp_approx_ftz_d, DL, MVT::i32),
1239           MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d));
1240     }
1241   }
1242 }
1243 
1244 SDValue
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1245 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
1246   SDLoc dl(Op);
1247   const GlobalAddressSDNode *GAN = cast<GlobalAddressSDNode>(Op);
1248   auto PtrVT = getPointerTy(DAG.getDataLayout(), GAN->getAddressSpace());
1249   Op = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, PtrVT);
1250   return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
1251 }
1252 
getPrototype(const DataLayout & DL,Type * retTy,const ArgListTy & Args,const SmallVectorImpl<ISD::OutputArg> & Outs,unsigned retAlignment,ImmutableCallSite CS) const1253 std::string NVPTXTargetLowering::getPrototype(
1254     const DataLayout &DL, Type *retTy, const ArgListTy &Args,
1255     const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
1256     ImmutableCallSite CS) const {
1257   auto PtrVT = getPointerTy(DL);
1258 
1259   bool isABI = (STI.getSmVersion() >= 20);
1260   assert(isABI && "Non-ABI compilation is not supported");
1261   if (!isABI)
1262     return "";
1263 
1264   std::stringstream O;
1265   O << "prototype_" << uniqueCallSite << " : .callprototype ";
1266 
1267   if (retTy->getTypeID() == Type::VoidTyID) {
1268     O << "()";
1269   } else {
1270     O << "(";
1271     if (retTy->isFloatingPointTy() || (retTy->isIntegerTy() && !retTy->isIntegerTy(128))) {
1272       unsigned size = 0;
1273       if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
1274         size = ITy->getBitWidth();
1275       } else {
1276         assert(retTy->isFloatingPointTy() &&
1277                "Floating point type expected here");
1278         size = retTy->getPrimitiveSizeInBits();
1279       }
1280       // PTX ABI requires all scalar return values to be at least 32
1281       // bits in size.  fp16 normally uses .b16 as its storage type in
1282       // PTX, so its size must be adjusted here, too.
1283       if (size < 32)
1284         size = 32;
1285 
1286       O << ".param .b" << size << " _";
1287     } else if (isa<PointerType>(retTy)) {
1288       O << ".param .b" << PtrVT.getSizeInBits() << " _";
1289     } else if (retTy->isAggregateType() || retTy->isVectorTy() || retTy->isIntegerTy(128)) {
1290       auto &DL = CS.getCalledFunction()->getParent()->getDataLayout();
1291       O << ".param .align " << retAlignment << " .b8 _["
1292         << DL.getTypeAllocSize(retTy) << "]";
1293     } else {
1294       llvm_unreachable("Unknown return type");
1295     }
1296     O << ") ";
1297   }
1298   O << "_ (";
1299 
1300   bool first = true;
1301 
1302   unsigned OIdx = 0;
1303   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1304     Type *Ty = Args[i].Ty;
1305     if (!first) {
1306       O << ", ";
1307     }
1308     first = false;
1309 
1310     if (!Outs[OIdx].Flags.isByVal()) {
1311       if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
1312         unsigned align = 0;
1313         const CallInst *CallI = cast<CallInst>(CS.getInstruction());
1314         // +1 because index 0 is reserved for return type alignment
1315         if (!getAlign(*CallI, i + 1, align))
1316           align = DL.getABITypeAlignment(Ty);
1317         unsigned sz = DL.getTypeAllocSize(Ty);
1318         O << ".param .align " << align << " .b8 ";
1319         O << "_";
1320         O << "[" << sz << "]";
1321         // update the index for Outs
1322         SmallVector<EVT, 16> vtparts;
1323         ComputeValueVTs(*this, DL, Ty, vtparts);
1324         if (unsigned len = vtparts.size())
1325           OIdx += len - 1;
1326         continue;
1327       }
1328       // i8 types in IR will be i16 types in SDAG
1329       assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
1330               (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
1331              "type mismatch between callee prototype and arguments");
1332       // scalar type
1333       unsigned sz = 0;
1334       if (isa<IntegerType>(Ty)) {
1335         sz = cast<IntegerType>(Ty)->getBitWidth();
1336         if (sz < 32)
1337           sz = 32;
1338       } else if (isa<PointerType>(Ty)) {
1339         sz = PtrVT.getSizeInBits();
1340       } else if (Ty->isHalfTy())
1341         // PTX ABI requires all scalar parameters to be at least 32
1342         // bits in size.  fp16 normally uses .b16 as its storage type
1343         // in PTX, so its size must be adjusted here, too.
1344         sz = 32;
1345       else
1346         sz = Ty->getPrimitiveSizeInBits();
1347       O << ".param .b" << sz << " ";
1348       O << "_";
1349       continue;
1350     }
1351     auto *PTy = dyn_cast<PointerType>(Ty);
1352     assert(PTy && "Param with byval attribute should be a pointer type");
1353     Type *ETy = PTy->getElementType();
1354 
1355     unsigned align = Outs[OIdx].Flags.getByValAlign();
1356     unsigned sz = DL.getTypeAllocSize(ETy);
1357     O << ".param .align " << align << " .b8 ";
1358     O << "_";
1359     O << "[" << sz << "]";
1360   }
1361   O << ");";
1362   return O.str();
1363 }
1364 
getArgumentAlignment(SDValue Callee,ImmutableCallSite CS,Type * Ty,unsigned Idx,const DataLayout & DL) const1365 unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1366                                                    ImmutableCallSite CS,
1367                                                    Type *Ty, unsigned Idx,
1368                                                    const DataLayout &DL) const {
1369   if (!CS) {
1370     // CallSite is zero, fallback to ABI type alignment
1371     return DL.getABITypeAlignment(Ty);
1372   }
1373 
1374   unsigned Align = 0;
1375   const Value *DirectCallee = CS.getCalledFunction();
1376 
1377   if (!DirectCallee) {
1378     // We don't have a direct function symbol, but that may be because of
1379     // constant cast instructions in the call.
1380     const Instruction *CalleeI = CS.getInstruction();
1381     assert(CalleeI && "Call target is not a function or derived value?");
1382 
1383     // With bitcast'd call targets, the instruction will be the call
1384     if (isa<CallInst>(CalleeI)) {
1385       // Check if we have call alignment metadata
1386       if (getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1387         return Align;
1388 
1389       const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1390       // Ignore any bitcast instructions
1391       while (isa<ConstantExpr>(CalleeV)) {
1392         const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1393         if (!CE->isCast())
1394           break;
1395         // Look through the bitcast
1396         CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1397       }
1398 
1399       // We have now looked past all of the bitcasts.  Do we finally have a
1400       // Function?
1401       if (isa<Function>(CalleeV))
1402         DirectCallee = CalleeV;
1403     }
1404   }
1405 
1406   // Check for function alignment information if we found that the
1407   // ultimate target is a Function
1408   if (DirectCallee)
1409     if (getAlign(*cast<Function>(DirectCallee), Idx, Align))
1410       return Align;
1411 
1412   // Call is indirect or alignment information is not available, fall back to
1413   // the ABI type alignment
1414   return DL.getABITypeAlignment(Ty);
1415 }
1416 
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1417 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1418                                        SmallVectorImpl<SDValue> &InVals) const {
1419   SelectionDAG &DAG = CLI.DAG;
1420   SDLoc dl = CLI.DL;
1421   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1422   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1423   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1424   SDValue Chain = CLI.Chain;
1425   SDValue Callee = CLI.Callee;
1426   bool &isTailCall = CLI.IsTailCall;
1427   ArgListTy &Args = CLI.getArgs();
1428   Type *RetTy = CLI.RetTy;
1429   ImmutableCallSite CS = CLI.CS;
1430   const DataLayout &DL = DAG.getDataLayout();
1431 
1432   bool isABI = (STI.getSmVersion() >= 20);
1433   assert(isABI && "Non-ABI compilation is not supported");
1434   if (!isABI)
1435     return Chain;
1436 
1437   SDValue tempChain = Chain;
1438   Chain = DAG.getCALLSEQ_START(Chain, uniqueCallSite, 0, dl);
1439   SDValue InFlag = Chain.getValue(1);
1440 
1441   unsigned paramCount = 0;
1442   // Args.size() and Outs.size() need not match.
1443   // Outs.size() will be larger
1444   //   * if there is an aggregate argument with multiple fields (each field
1445   //     showing up separately in Outs)
1446   //   * if there is a vector argument with more than typical vector-length
1447   //     elements (generally if more than 4) where each vector element is
1448   //     individually present in Outs.
1449   // So a different index should be used for indexing into Outs/OutVals.
1450   // See similar issue in LowerFormalArguments.
1451   unsigned OIdx = 0;
1452   // Declare the .params or .reg need to pass values
1453   // to the function
1454   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1455     EVT VT = Outs[OIdx].VT;
1456     Type *Ty = Args[i].Ty;
1457 
1458     if (!Outs[OIdx].Flags.isByVal()) {
1459       SmallVector<EVT, 16> VTs;
1460       SmallVector<uint64_t, 16> Offsets;
1461       ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets);
1462       unsigned ArgAlign =
1463           getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1464       unsigned AllocSize = DL.getTypeAllocSize(Ty);
1465       SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1466       bool NeedAlign; // Does argument declaration specify alignment?
1467       if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
1468         // declare .param .align <align> .b8 .param<n>[<size>];
1469         SDValue DeclareParamOps[] = {
1470             Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1471             DAG.getConstant(paramCount, dl, MVT::i32),
1472             DAG.getConstant(AllocSize, dl, MVT::i32), InFlag};
1473         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1474                             DeclareParamOps);
1475         NeedAlign = true;
1476       } else {
1477         // declare .param .b<size> .param<n>;
1478         if ((VT.isInteger() || VT.isFloatingPoint()) && AllocSize < 4) {
1479           // PTX ABI requires integral types to be at least 32 bits in
1480           // size. FP16 is loaded/stored using i16, so it's handled
1481           // here as well.
1482           AllocSize = 4;
1483         }
1484         SDValue DeclareScalarParamOps[] = {
1485             Chain, DAG.getConstant(paramCount, dl, MVT::i32),
1486             DAG.getConstant(AllocSize * 8, dl, MVT::i32),
1487             DAG.getConstant(0, dl, MVT::i32), InFlag};
1488         Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1489                             DeclareScalarParamOps);
1490         NeedAlign = false;
1491       }
1492       InFlag = Chain.getValue(1);
1493 
1494       // PTX Interoperability Guide 3.3(A): [Integer] Values shorter
1495       // than 32-bits are sign extended or zero extended, depending on
1496       // whether they are signed or unsigned types. This case applies
1497       // only to scalar parameters and not to aggregate values.
1498       bool ExtendIntegerParam =
1499           Ty->isIntegerTy() && DL.getTypeAllocSizeInBits(Ty) < 32;
1500 
1501       auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, ArgAlign);
1502       SmallVector<SDValue, 6> StoreOperands;
1503       for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1504         // New store.
1505         if (VectorInfo[j] & PVF_FIRST) {
1506           assert(StoreOperands.empty() && "Unfinished preceeding store.");
1507           StoreOperands.push_back(Chain);
1508           StoreOperands.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1509           StoreOperands.push_back(DAG.getConstant(Offsets[j], dl, MVT::i32));
1510         }
1511 
1512         EVT EltVT = VTs[j];
1513         SDValue StVal = OutVals[OIdx];
1514         if (ExtendIntegerParam) {
1515           assert(VTs.size() == 1 && "Scalar can't have multiple parts.");
1516           // zext/sext to i32
1517           StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
1518                                                         : ISD::ZERO_EXTEND,
1519                               dl, MVT::i32, StVal);
1520         } else if (EltVT.getSizeInBits() < 16) {
1521           // Use 16-bit registers for small stores as it's the
1522           // smallest general purpose register size supported by NVPTX.
1523           StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1524         }
1525 
1526         // Record the value to store.
1527         StoreOperands.push_back(StVal);
1528 
1529         if (VectorInfo[j] & PVF_LAST) {
1530           unsigned NumElts = StoreOperands.size() - 3;
1531           NVPTXISD::NodeType Op;
1532           switch (NumElts) {
1533           case 1:
1534             Op = NVPTXISD::StoreParam;
1535             break;
1536           case 2:
1537             Op = NVPTXISD::StoreParamV2;
1538             break;
1539           case 4:
1540             Op = NVPTXISD::StoreParamV4;
1541             break;
1542           default:
1543             llvm_unreachable("Invalid vector info.");
1544           }
1545 
1546           StoreOperands.push_back(InFlag);
1547 
1548           // Adjust type of the store op if we've extended the scalar
1549           // return value.
1550           EVT TheStoreType = ExtendIntegerParam ? MVT::i32 : VTs[j];
1551           unsigned EltAlign =
1552               NeedAlign ? GreatestCommonDivisor64(ArgAlign, Offsets[j]) : 0;
1553 
1554           Chain = DAG.getMemIntrinsicNode(
1555               Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
1556               TheStoreType, MachinePointerInfo(), EltAlign,
1557               MachineMemOperand::MOStore);
1558           InFlag = Chain.getValue(1);
1559 
1560           // Cleanup.
1561           StoreOperands.clear();
1562         }
1563         ++OIdx;
1564       }
1565       assert(StoreOperands.empty() && "Unfinished parameter store.");
1566       if (VTs.size() > 0)
1567         --OIdx;
1568       ++paramCount;
1569       continue;
1570     }
1571 
1572     // ByVal arguments
1573     SmallVector<EVT, 16> VTs;
1574     SmallVector<uint64_t, 16> Offsets;
1575     auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1576     assert(PTy && "Type of a byval parameter should be pointer");
1577     ComputePTXValueVTs(*this, DL, PTy->getElementType(), VTs, &Offsets, 0);
1578 
1579     // declare .param .align <align> .b8 .param<n>[<size>];
1580     unsigned sz = Outs[OIdx].Flags.getByValSize();
1581     SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1582     unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1583     // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1584     // so we don't need to worry about natural alignment or not.
1585     // See TargetLowering::LowerCallTo().
1586 
1587     // Enforce minumum alignment of 4 to work around ptxas miscompile
1588     // for sm_50+. See corresponding alignment adjustment in
1589     // emitFunctionParamList() for details.
1590     if (ArgAlign < 4)
1591       ArgAlign = 4;
1592     SDValue DeclareParamOps[] = {Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1593                                  DAG.getConstant(paramCount, dl, MVT::i32),
1594                                  DAG.getConstant(sz, dl, MVT::i32), InFlag};
1595     Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1596                         DeclareParamOps);
1597     InFlag = Chain.getValue(1);
1598     for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1599       EVT elemtype = VTs[j];
1600       int curOffset = Offsets[j];
1601       unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1602       auto PtrVT = getPointerTy(DL);
1603       SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1604                                     DAG.getConstant(curOffset, dl, PtrVT));
1605       SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1606                                    MachinePointerInfo(), PartAlign);
1607       if (elemtype.getSizeInBits() < 16) {
1608         theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1609       }
1610       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1611       SDValue CopyParamOps[] = { Chain,
1612                                  DAG.getConstant(paramCount, dl, MVT::i32),
1613                                  DAG.getConstant(curOffset, dl, MVT::i32),
1614                                  theVal, InFlag };
1615       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1616                                       CopyParamOps, elemtype,
1617                                       MachinePointerInfo(), /* Align */ 0,
1618                                       MachineMemOperand::MOStore);
1619 
1620       InFlag = Chain.getValue(1);
1621     }
1622     ++paramCount;
1623   }
1624 
1625   GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1626   unsigned retAlignment = 0;
1627 
1628   // Handle Result
1629   if (Ins.size() > 0) {
1630     SmallVector<EVT, 16> resvtparts;
1631     ComputeValueVTs(*this, DL, RetTy, resvtparts);
1632 
1633     // Declare
1634     //  .param .align 16 .b8 retval0[<size-in-bytes>], or
1635     //  .param .b<size-in-bits> retval0
1636     unsigned resultsz = DL.getTypeAllocSizeInBits(RetTy);
1637     // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1638     // these three types to match the logic in
1639     // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1640     // Plus, this behavior is consistent with nvcc's.
1641     if (RetTy->isFloatingPointTy() || RetTy->isPointerTy() ||
1642         (RetTy->isIntegerTy() && !RetTy->isIntegerTy(128))) {
1643       // Scalar needs to be at least 32bit wide
1644       if (resultsz < 32)
1645         resultsz = 32;
1646       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1647       SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1648                                   DAG.getConstant(resultsz, dl, MVT::i32),
1649                                   DAG.getConstant(0, dl, MVT::i32), InFlag };
1650       Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1651                           DeclareRetOps);
1652       InFlag = Chain.getValue(1);
1653     } else {
1654       retAlignment = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1655       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1656       SDValue DeclareRetOps[] = { Chain,
1657                                   DAG.getConstant(retAlignment, dl, MVT::i32),
1658                                   DAG.getConstant(resultsz / 8, dl, MVT::i32),
1659                                   DAG.getConstant(0, dl, MVT::i32), InFlag };
1660       Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1661                           DeclareRetOps);
1662       InFlag = Chain.getValue(1);
1663     }
1664   }
1665 
1666   // Both indirect calls and libcalls have nullptr Func. In order to distinguish
1667   // between them we must rely on the call site value which is valid for
1668   // indirect calls but is always null for libcalls.
1669   bool isIndirectCall = !Func && CS;
1670 
1671   if (isa<ExternalSymbolSDNode>(Callee)) {
1672     Function* CalleeFunc = nullptr;
1673 
1674     // Try to find the callee in the current module.
1675     Callee = DAG.getSymbolFunctionGlobalAddress(Callee, &CalleeFunc);
1676     assert(CalleeFunc != nullptr && "Libcall callee must be set.");
1677 
1678     // Set the "libcall callee" attribute to indicate that the function
1679     // must always have a declaration.
1680     CalleeFunc->addFnAttr("nvptx-libcall-callee", "true");
1681   }
1682 
1683   if (isIndirectCall) {
1684     // This is indirect function call case : PTX requires a prototype of the
1685     // form
1686     // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1687     // to be emitted, and the label has to used as the last arg of call
1688     // instruction.
1689     // The prototype is embedded in a string and put as the operand for a
1690     // CallPrototype SDNode which will print out to the value of the string.
1691     SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1692     std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, CS);
1693     const char *ProtoStr =
1694       nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1695     SDValue ProtoOps[] = {
1696       Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1697     };
1698     Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1699     InFlag = Chain.getValue(1);
1700   }
1701   // Op to just print "call"
1702   SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1703   SDValue PrintCallOps[] = {
1704     Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1705   };
1706   // We model convergent calls as separate opcodes.
1707   unsigned Opcode = isIndirectCall ? NVPTXISD::PrintCall : NVPTXISD::PrintCallUni;
1708   if (CLI.IsConvergent)
1709     Opcode = Opcode == NVPTXISD::PrintCallUni ? NVPTXISD::PrintConvergentCallUni
1710                                               : NVPTXISD::PrintConvergentCall;
1711   Chain = DAG.getNode(Opcode, dl, PrintCallVTs, PrintCallOps);
1712   InFlag = Chain.getValue(1);
1713 
1714   // Ops to print out the function name
1715   SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1716   SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1717   Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1718   InFlag = Chain.getValue(1);
1719 
1720   // Ops to print out the param list
1721   SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1722   SDValue CallArgBeginOps[] = { Chain, InFlag };
1723   Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1724                       CallArgBeginOps);
1725   InFlag = Chain.getValue(1);
1726 
1727   for (unsigned i = 0, e = paramCount; i != e; ++i) {
1728     unsigned opcode;
1729     if (i == (e - 1))
1730       opcode = NVPTXISD::LastCallArg;
1731     else
1732       opcode = NVPTXISD::CallArg;
1733     SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1734     SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1735                              DAG.getConstant(i, dl, MVT::i32), InFlag };
1736     Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1737     InFlag = Chain.getValue(1);
1738   }
1739   SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1740   SDValue CallArgEndOps[] = { Chain,
1741                               DAG.getConstant(isIndirectCall ? 0 : 1, dl, MVT::i32),
1742                               InFlag };
1743   Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1744   InFlag = Chain.getValue(1);
1745 
1746   if (isIndirectCall) {
1747     SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1748     SDValue PrototypeOps[] = { Chain,
1749                                DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1750                                InFlag };
1751     Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1752     InFlag = Chain.getValue(1);
1753   }
1754 
1755   SmallVector<SDValue, 16> ProxyRegOps;
1756   SmallVector<Optional<MVT>, 16> ProxyRegTruncates;
1757 
1758   // Generate loads from param memory/moves from registers for result
1759   if (Ins.size() > 0) {
1760     SmallVector<EVT, 16> VTs;
1761     SmallVector<uint64_t, 16> Offsets;
1762     ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0);
1763     assert(VTs.size() == Ins.size() && "Bad value decomposition");
1764 
1765     unsigned RetAlign = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1766     auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign);
1767 
1768     SmallVector<EVT, 6> LoadVTs;
1769     int VecIdx = -1; // Index of the first element of the vector.
1770 
1771     // PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
1772     // 32-bits are sign extended or zero extended, depending on whether
1773     // they are signed or unsigned types.
1774     bool ExtendIntegerRetVal =
1775         RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
1776 
1777     for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
1778       bool needTruncate = false;
1779       EVT TheLoadType = VTs[i];
1780       EVT EltType = Ins[i].VT;
1781       unsigned EltAlign = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1782       if (ExtendIntegerRetVal) {
1783         TheLoadType = MVT::i32;
1784         EltType = MVT::i32;
1785         needTruncate = true;
1786       } else if (TheLoadType.getSizeInBits() < 16) {
1787         if (VTs[i].isInteger())
1788           needTruncate = true;
1789         EltType = MVT::i16;
1790       }
1791 
1792       // Record index of the very first element of the vector.
1793       if (VectorInfo[i] & PVF_FIRST) {
1794         assert(VecIdx == -1 && LoadVTs.empty() && "Orphaned operand list.");
1795         VecIdx = i;
1796       }
1797 
1798       LoadVTs.push_back(EltType);
1799 
1800       if (VectorInfo[i] & PVF_LAST) {
1801         unsigned NumElts = LoadVTs.size();
1802         LoadVTs.push_back(MVT::Other);
1803         LoadVTs.push_back(MVT::Glue);
1804         NVPTXISD::NodeType Op;
1805         switch (NumElts) {
1806         case 1:
1807           Op = NVPTXISD::LoadParam;
1808           break;
1809         case 2:
1810           Op = NVPTXISD::LoadParamV2;
1811           break;
1812         case 4:
1813           Op = NVPTXISD::LoadParamV4;
1814           break;
1815         default:
1816           llvm_unreachable("Invalid vector info.");
1817         }
1818 
1819         SDValue LoadOperands[] = {
1820             Chain, DAG.getConstant(1, dl, MVT::i32),
1821             DAG.getConstant(Offsets[VecIdx], dl, MVT::i32), InFlag};
1822         SDValue RetVal = DAG.getMemIntrinsicNode(
1823             Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
1824             MachinePointerInfo(), EltAlign,
1825             MachineMemOperand::MOLoad);
1826 
1827         for (unsigned j = 0; j < NumElts; ++j) {
1828           ProxyRegOps.push_back(RetVal.getValue(j));
1829 
1830           if (needTruncate)
1831             ProxyRegTruncates.push_back(Optional<MVT>(Ins[VecIdx + j].VT));
1832           else
1833             ProxyRegTruncates.push_back(Optional<MVT>());
1834         }
1835 
1836         Chain = RetVal.getValue(NumElts);
1837         InFlag = RetVal.getValue(NumElts + 1);
1838 
1839         // Cleanup
1840         VecIdx = -1;
1841         LoadVTs.clear();
1842       }
1843     }
1844   }
1845 
1846   Chain = DAG.getCALLSEQ_END(Chain,
1847                              DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1848                              DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1849                                                    true),
1850                              InFlag, dl);
1851   InFlag = Chain.getValue(1);
1852   uniqueCallSite++;
1853 
1854   // Append ProxyReg instructions to the chain to make sure that `callseq_end`
1855   // will not get lost. Otherwise, during libcalls expansion, the nodes can become
1856   // dangling.
1857   for (unsigned i = 0; i < ProxyRegOps.size(); ++i) {
1858     SDValue Ret = DAG.getNode(
1859       NVPTXISD::ProxyReg, dl,
1860       DAG.getVTList(ProxyRegOps[i].getSimpleValueType(), MVT::Other, MVT::Glue),
1861       { Chain, ProxyRegOps[i], InFlag }
1862     );
1863 
1864     Chain = Ret.getValue(1);
1865     InFlag = Ret.getValue(2);
1866 
1867     if (ProxyRegTruncates[i].hasValue()) {
1868       Ret = DAG.getNode(ISD::TRUNCATE, dl, ProxyRegTruncates[i].getValue(), Ret);
1869     }
1870 
1871     InVals.push_back(Ret);
1872   }
1873 
1874   // set isTailCall to false for now, until we figure out how to express
1875   // tail call optimization in PTX
1876   isTailCall = false;
1877   return Chain;
1878 }
1879 
1880 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1881 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1882 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1883 SDValue
LowerCONCAT_VECTORS(SDValue Op,SelectionDAG & DAG) const1884 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1885   SDNode *Node = Op.getNode();
1886   SDLoc dl(Node);
1887   SmallVector<SDValue, 8> Ops;
1888   unsigned NumOperands = Node->getNumOperands();
1889   for (unsigned i = 0; i < NumOperands; ++i) {
1890     SDValue SubOp = Node->getOperand(i);
1891     EVT VVT = SubOp.getNode()->getValueType(0);
1892     EVT EltVT = VVT.getVectorElementType();
1893     unsigned NumSubElem = VVT.getVectorNumElements();
1894     for (unsigned j = 0; j < NumSubElem; ++j) {
1895       Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1896                                 DAG.getIntPtrConstant(j, dl)));
1897     }
1898   }
1899   return DAG.getBuildVector(Node->getValueType(0), dl, Ops);
1900 }
1901 
1902 // We can init constant f16x2 with a single .b32 move.  Normally it
1903 // would get lowered as two constant loads and vector-packing move.
1904 //        mov.b16         %h1, 0x4000;
1905 //        mov.b16         %h2, 0x3C00;
1906 //        mov.b32         %hh2, {%h2, %h1};
1907 // Instead we want just a constant move:
1908 //        mov.b32         %hh2, 0x40003C00
1909 //
1910 // This results in better SASS code with CUDA 7.x. Ptxas in CUDA 8.0
1911 // generates good SASS in both cases.
LowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG) const1912 SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
1913                                                SelectionDAG &DAG) const {
1914   //return Op;
1915   if (!(Op->getValueType(0) == MVT::v2f16 &&
1916         isa<ConstantFPSDNode>(Op->getOperand(0)) &&
1917         isa<ConstantFPSDNode>(Op->getOperand(1))))
1918     return Op;
1919 
1920   APInt E0 =
1921       cast<ConstantFPSDNode>(Op->getOperand(0))->getValueAPF().bitcastToAPInt();
1922   APInt E1 =
1923       cast<ConstantFPSDNode>(Op->getOperand(1))->getValueAPF().bitcastToAPInt();
1924   SDValue Const =
1925       DAG.getConstant(E1.zext(32).shl(16) | E0.zext(32), SDLoc(Op), MVT::i32);
1926   return DAG.getNode(ISD::BITCAST, SDLoc(Op), MVT::v2f16, Const);
1927 }
1928 
LowerEXTRACT_VECTOR_ELT(SDValue Op,SelectionDAG & DAG) const1929 SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
1930                                                      SelectionDAG &DAG) const {
1931   SDValue Index = Op->getOperand(1);
1932   // Constant index will be matched by tablegen.
1933   if (isa<ConstantSDNode>(Index.getNode()))
1934     return Op;
1935 
1936   // Extract individual elements and select one of them.
1937   SDValue Vector = Op->getOperand(0);
1938   EVT VectorVT = Vector.getValueType();
1939   assert(VectorVT == MVT::v2f16 && "Unexpected vector type.");
1940   EVT EltVT = VectorVT.getVectorElementType();
1941 
1942   SDLoc dl(Op.getNode());
1943   SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1944                            DAG.getIntPtrConstant(0, dl));
1945   SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1946                            DAG.getIntPtrConstant(1, dl));
1947   return DAG.getSelectCC(dl, Index, DAG.getIntPtrConstant(0, dl), E0, E1,
1948                          ISD::CondCode::SETEQ);
1949 }
1950 
1951 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1952 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1953 ///    amount, or
1954 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1955 ///    amount.
LowerShiftRightParts(SDValue Op,SelectionDAG & DAG) const1956 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1957                                                   SelectionDAG &DAG) const {
1958   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1959   assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1960 
1961   EVT VT = Op.getValueType();
1962   unsigned VTBits = VT.getSizeInBits();
1963   SDLoc dl(Op);
1964   SDValue ShOpLo = Op.getOperand(0);
1965   SDValue ShOpHi = Op.getOperand(1);
1966   SDValue ShAmt  = Op.getOperand(2);
1967   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1968 
1969   if (VTBits == 32 && STI.getSmVersion() >= 35) {
1970     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1971     // {dHi, dLo} = {aHi, aLo} >> Amt
1972     //   dHi = aHi >> Amt
1973     //   dLo = shf.r.clamp aLo, aHi, Amt
1974 
1975     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1976     SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1977                              ShAmt);
1978 
1979     SDValue Ops[2] = { Lo, Hi };
1980     return DAG.getMergeValues(Ops, dl);
1981   }
1982   else {
1983     // {dHi, dLo} = {aHi, aLo} >> Amt
1984     // - if (Amt>=size) then
1985     //      dLo = aHi >> (Amt-size)
1986     //      dHi = aHi >> Amt (this is either all 0 or all 1)
1987     //   else
1988     //      dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1989     //      dHi = aHi >> Amt
1990 
1991     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1992                                    DAG.getConstant(VTBits, dl, MVT::i32),
1993                                    ShAmt);
1994     SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1995     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1996                                      DAG.getConstant(VTBits, dl, MVT::i32));
1997     SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1998     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1999     SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2000 
2001     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
2002                                DAG.getConstant(VTBits, dl, MVT::i32),
2003                                ISD::SETGE);
2004     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2005     SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2006 
2007     SDValue Ops[2] = { Lo, Hi };
2008     return DAG.getMergeValues(Ops, dl);
2009   }
2010 }
2011 
2012 /// LowerShiftLeftParts - Lower SHL_PARTS, which
2013 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
2014 ///    amount, or
2015 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
2016 ///    amount.
LowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const2017 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
2018                                                  SelectionDAG &DAG) const {
2019   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2020   assert(Op.getOpcode() == ISD::SHL_PARTS);
2021 
2022   EVT VT = Op.getValueType();
2023   unsigned VTBits = VT.getSizeInBits();
2024   SDLoc dl(Op);
2025   SDValue ShOpLo = Op.getOperand(0);
2026   SDValue ShOpHi = Op.getOperand(1);
2027   SDValue ShAmt  = Op.getOperand(2);
2028 
2029   if (VTBits == 32 && STI.getSmVersion() >= 35) {
2030     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
2031     // {dHi, dLo} = {aHi, aLo} << Amt
2032     //   dHi = shf.l.clamp aLo, aHi, Amt
2033     //   dLo = aLo << Amt
2034 
2035     SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
2036                              ShAmt);
2037     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2038 
2039     SDValue Ops[2] = { Lo, Hi };
2040     return DAG.getMergeValues(Ops, dl);
2041   }
2042   else {
2043     // {dHi, dLo} = {aHi, aLo} << Amt
2044     // - if (Amt>=size) then
2045     //      dLo = aLo << Amt (all 0)
2046     //      dLo = aLo << (Amt-size)
2047     //   else
2048     //      dLo = aLo << Amt
2049     //      dHi = (aHi << Amt) | (aLo >> (size-Amt))
2050 
2051     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2052                                    DAG.getConstant(VTBits, dl, MVT::i32),
2053                                    ShAmt);
2054     SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2055     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2056                                      DAG.getConstant(VTBits, dl, MVT::i32));
2057     SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2058     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2059     SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2060 
2061     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
2062                                DAG.getConstant(VTBits, dl, MVT::i32),
2063                                ISD::SETGE);
2064     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2065     SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2066 
2067     SDValue Ops[2] = { Lo, Hi };
2068     return DAG.getMergeValues(Ops, dl);
2069   }
2070 }
2071 
2072 SDValue
LowerOperation(SDValue Op,SelectionDAG & DAG) const2073 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2074   switch (Op.getOpcode()) {
2075   case ISD::RETURNADDR:
2076     return SDValue();
2077   case ISD::FRAMEADDR:
2078     return SDValue();
2079   case ISD::GlobalAddress:
2080     return LowerGlobalAddress(Op, DAG);
2081   case ISD::INTRINSIC_W_CHAIN:
2082     return Op;
2083   case ISD::BUILD_VECTOR:
2084     return LowerBUILD_VECTOR(Op, DAG);
2085   case ISD::EXTRACT_SUBVECTOR:
2086     return Op;
2087   case ISD::EXTRACT_VECTOR_ELT:
2088     return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2089   case ISD::CONCAT_VECTORS:
2090     return LowerCONCAT_VECTORS(Op, DAG);
2091   case ISD::STORE:
2092     return LowerSTORE(Op, DAG);
2093   case ISD::LOAD:
2094     return LowerLOAD(Op, DAG);
2095   case ISD::SHL_PARTS:
2096     return LowerShiftLeftParts(Op, DAG);
2097   case ISD::SRA_PARTS:
2098   case ISD::SRL_PARTS:
2099     return LowerShiftRightParts(Op, DAG);
2100   case ISD::SELECT:
2101     return LowerSelect(Op, DAG);
2102   default:
2103     llvm_unreachable("Custom lowering not defined for operation");
2104   }
2105 }
2106 
LowerSelect(SDValue Op,SelectionDAG & DAG) const2107 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
2108   SDValue Op0 = Op->getOperand(0);
2109   SDValue Op1 = Op->getOperand(1);
2110   SDValue Op2 = Op->getOperand(2);
2111   SDLoc DL(Op.getNode());
2112 
2113   assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
2114 
2115   Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
2116   Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
2117   SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
2118   SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
2119 
2120   return Trunc;
2121 }
2122 
LowerLOAD(SDValue Op,SelectionDAG & DAG) const2123 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2124   if (Op.getValueType() == MVT::i1)
2125     return LowerLOADi1(Op, DAG);
2126 
2127   // v2f16 is legal, so we can't rely on legalizer to handle unaligned
2128   // loads and have to handle it here.
2129   if (Op.getValueType() == MVT::v2f16) {
2130     LoadSDNode *Load = cast<LoadSDNode>(Op);
2131     EVT MemVT = Load->getMemoryVT();
2132     if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
2133                             Load->getAddressSpace(), Load->getAlignment())) {
2134       SDValue Ops[2];
2135       std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
2136       return DAG.getMergeValues(Ops, SDLoc(Op));
2137     }
2138   }
2139 
2140   return SDValue();
2141 }
2142 
2143 // v = ld i1* addr
2144 //   =>
2145 // v1 = ld i8* addr (-> i16)
2146 // v = trunc i16 to i1
LowerLOADi1(SDValue Op,SelectionDAG & DAG) const2147 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
2148   SDNode *Node = Op.getNode();
2149   LoadSDNode *LD = cast<LoadSDNode>(Node);
2150   SDLoc dl(Node);
2151   assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
2152   assert(Node->getValueType(0) == MVT::i1 &&
2153          "Custom lowering for i1 load only");
2154   SDValue newLD = DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
2155                               LD->getPointerInfo(), LD->getAlignment(),
2156                               LD->getMemOperand()->getFlags());
2157   SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
2158   // The legalizer (the caller) is expecting two values from the legalized
2159   // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
2160   // in LegalizeDAG.cpp which also uses MergeValues.
2161   SDValue Ops[] = { result, LD->getChain() };
2162   return DAG.getMergeValues(Ops, dl);
2163 }
2164 
LowerSTORE(SDValue Op,SelectionDAG & DAG) const2165 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2166   StoreSDNode *Store = cast<StoreSDNode>(Op);
2167   EVT VT = Store->getMemoryVT();
2168 
2169   if (VT == MVT::i1)
2170     return LowerSTOREi1(Op, DAG);
2171 
2172   // v2f16 is legal, so we can't rely on legalizer to handle unaligned
2173   // stores and have to handle it here.
2174   if (VT == MVT::v2f16 &&
2175       !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
2176                           Store->getAddressSpace(), Store->getAlignment()))
2177     return expandUnalignedStore(Store, DAG);
2178 
2179   if (VT.isVector())
2180     return LowerSTOREVector(Op, DAG);
2181 
2182   return SDValue();
2183 }
2184 
2185 SDValue
LowerSTOREVector(SDValue Op,SelectionDAG & DAG) const2186 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
2187   SDNode *N = Op.getNode();
2188   SDValue Val = N->getOperand(1);
2189   SDLoc DL(N);
2190   EVT ValVT = Val.getValueType();
2191 
2192   if (ValVT.isVector()) {
2193     // We only handle "native" vector sizes for now, e.g. <4 x double> is not
2194     // legal.  We can (and should) split that into 2 stores of <2 x double> here
2195     // but I'm leaving that as a TODO for now.
2196     if (!ValVT.isSimple())
2197       return SDValue();
2198     switch (ValVT.getSimpleVT().SimpleTy) {
2199     default:
2200       return SDValue();
2201     case MVT::v2i8:
2202     case MVT::v2i16:
2203     case MVT::v2i32:
2204     case MVT::v2i64:
2205     case MVT::v2f16:
2206     case MVT::v2f32:
2207     case MVT::v2f64:
2208     case MVT::v4i8:
2209     case MVT::v4i16:
2210     case MVT::v4i32:
2211     case MVT::v4f16:
2212     case MVT::v4f32:
2213     case MVT::v8f16: // <4 x f16x2>
2214       // This is a "native" vector type
2215       break;
2216     }
2217 
2218     MemSDNode *MemSD = cast<MemSDNode>(N);
2219     const DataLayout &TD = DAG.getDataLayout();
2220 
2221     unsigned Align = MemSD->getAlignment();
2222     unsigned PrefAlign =
2223         TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
2224     if (Align < PrefAlign) {
2225       // This store is not sufficiently aligned, so bail out and let this vector
2226       // store be scalarized.  Note that we may still be able to emit smaller
2227       // vector stores.  For example, if we are storing a <4 x float> with an
2228       // alignment of 8, this check will fail but the legalizer will try again
2229       // with 2 x <2 x float>, which will succeed with an alignment of 8.
2230       return SDValue();
2231     }
2232 
2233     unsigned Opcode = 0;
2234     EVT EltVT = ValVT.getVectorElementType();
2235     unsigned NumElts = ValVT.getVectorNumElements();
2236 
2237     // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
2238     // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
2239     // stored type to i16 and propagate the "real" type as the memory type.
2240     bool NeedExt = false;
2241     if (EltVT.getSizeInBits() < 16)
2242       NeedExt = true;
2243 
2244     bool StoreF16x2 = false;
2245     switch (NumElts) {
2246     default:
2247       return SDValue();
2248     case 2:
2249       Opcode = NVPTXISD::StoreV2;
2250       break;
2251     case 4:
2252       Opcode = NVPTXISD::StoreV4;
2253       break;
2254     case 8:
2255       // v8f16 is a special case. PTX doesn't have st.v8.f16
2256       // instruction. Instead, we split the vector into v2f16 chunks and
2257       // store them with st.v4.b32.
2258       assert(EltVT == MVT::f16 && "Wrong type for the vector.");
2259       Opcode = NVPTXISD::StoreV4;
2260       StoreF16x2 = true;
2261       break;
2262     }
2263 
2264     SmallVector<SDValue, 8> Ops;
2265 
2266     // First is the chain
2267     Ops.push_back(N->getOperand(0));
2268 
2269     if (StoreF16x2) {
2270       // Combine f16,f16 -> v2f16
2271       NumElts /= 2;
2272       for (unsigned i = 0; i < NumElts; ++i) {
2273         SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2274                                  DAG.getIntPtrConstant(i * 2, DL));
2275         SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2276                                  DAG.getIntPtrConstant(i * 2 + 1, DL));
2277         SDValue V2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f16, E0, E1);
2278         Ops.push_back(V2);
2279       }
2280     } else {
2281       // Then the split values
2282       for (unsigned i = 0; i < NumElts; ++i) {
2283         SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
2284                                      DAG.getIntPtrConstant(i, DL));
2285         if (NeedExt)
2286           ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2287         Ops.push_back(ExtVal);
2288       }
2289     }
2290 
2291     // Then any remaining arguments
2292     Ops.append(N->op_begin() + 2, N->op_end());
2293 
2294     SDValue NewSt =
2295         DAG.getMemIntrinsicNode(Opcode, DL, DAG.getVTList(MVT::Other), Ops,
2296                                 MemSD->getMemoryVT(), MemSD->getMemOperand());
2297 
2298     // return DCI.CombineTo(N, NewSt, true);
2299     return NewSt;
2300   }
2301 
2302   return SDValue();
2303 }
2304 
2305 // st i1 v, addr
2306 //    =>
2307 // v1 = zxt v to i16
2308 // st.u8 i16, addr
LowerSTOREi1(SDValue Op,SelectionDAG & DAG) const2309 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2310   SDNode *Node = Op.getNode();
2311   SDLoc dl(Node);
2312   StoreSDNode *ST = cast<StoreSDNode>(Node);
2313   SDValue Tmp1 = ST->getChain();
2314   SDValue Tmp2 = ST->getBasePtr();
2315   SDValue Tmp3 = ST->getValue();
2316   assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2317   Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2318   SDValue Result =
2319       DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
2320                         ST->getAlignment(), ST->getMemOperand()->getFlags());
2321   return Result;
2322 }
2323 
2324 SDValue
getParamSymbol(SelectionDAG & DAG,int idx,EVT v) const2325 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2326   std::string ParamSym;
2327   raw_string_ostream ParamStr(ParamSym);
2328 
2329   ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2330   ParamStr.flush();
2331 
2332   std::string *SavedStr =
2333     nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2334   return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2335 }
2336 
2337 // Check to see if the kernel argument is image*_t or sampler_t
2338 
isImageOrSamplerVal(const Value * arg,const Module * context)2339 static bool isImageOrSamplerVal(const Value *arg, const Module *context) {
2340   static const char *const specialTypes[] = { "struct._image2d_t",
2341                                               "struct._image3d_t",
2342                                               "struct._sampler_t" };
2343 
2344   Type *Ty = arg->getType();
2345   auto *PTy = dyn_cast<PointerType>(Ty);
2346 
2347   if (!PTy)
2348     return false;
2349 
2350   if (!context)
2351     return false;
2352 
2353   auto *STy = dyn_cast<StructType>(PTy->getElementType());
2354   if (!STy || STy->isLiteral())
2355     return false;
2356 
2357   return std::find(std::begin(specialTypes), std::end(specialTypes),
2358                    STy->getName()) != std::end(specialTypes);
2359 }
2360 
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2361 SDValue NVPTXTargetLowering::LowerFormalArguments(
2362     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2363     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2364     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2365   MachineFunction &MF = DAG.getMachineFunction();
2366   const DataLayout &DL = DAG.getDataLayout();
2367   auto PtrVT = getPointerTy(DAG.getDataLayout());
2368 
2369   const Function *F = &MF.getFunction();
2370   const AttributeList &PAL = F->getAttributes();
2371   const TargetLowering *TLI = STI.getTargetLowering();
2372 
2373   SDValue Root = DAG.getRoot();
2374   std::vector<SDValue> OutChains;
2375 
2376   bool isABI = (STI.getSmVersion() >= 20);
2377   assert(isABI && "Non-ABI compilation is not supported");
2378   if (!isABI)
2379     return Chain;
2380 
2381   std::vector<Type *> argTypes;
2382   std::vector<const Argument *> theArgs;
2383   for (const Argument &I : F->args()) {
2384     theArgs.push_back(&I);
2385     argTypes.push_back(I.getType());
2386   }
2387   // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2388   // Ins.size() will be larger
2389   //   * if there is an aggregate argument with multiple fields (each field
2390   //     showing up separately in Ins)
2391   //   * if there is a vector argument with more than typical vector-length
2392   //     elements (generally if more than 4) where each vector element is
2393   //     individually present in Ins.
2394   // So a different index should be used for indexing into Ins.
2395   // See similar issue in LowerCall.
2396   unsigned InsIdx = 0;
2397 
2398   int idx = 0;
2399   for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2400     Type *Ty = argTypes[i];
2401 
2402     // If the kernel argument is image*_t or sampler_t, convert it to
2403     // a i32 constant holding the parameter position. This can later
2404     // matched in the AsmPrinter to output the correct mangled name.
2405     if (isImageOrSamplerVal(
2406             theArgs[i],
2407             (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2408                                      : nullptr))) {
2409       assert(isKernelFunction(*F) &&
2410              "Only kernels can have image/sampler params");
2411       InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2412       continue;
2413     }
2414 
2415     if (theArgs[i]->use_empty()) {
2416       // argument is dead
2417       if (Ty->isAggregateType() || Ty->isIntegerTy(128)) {
2418         SmallVector<EVT, 16> vtparts;
2419 
2420         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2421         assert(vtparts.size() > 0 && "empty aggregate type not expected");
2422         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2423              ++parti) {
2424           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2425           ++InsIdx;
2426         }
2427         if (vtparts.size() > 0)
2428           --InsIdx;
2429         continue;
2430       }
2431       if (Ty->isVectorTy()) {
2432         EVT ObjectVT = getValueType(DL, Ty);
2433         unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2434         for (unsigned parti = 0; parti < NumRegs; ++parti) {
2435           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2436           ++InsIdx;
2437         }
2438         if (NumRegs > 0)
2439           --InsIdx;
2440         continue;
2441       }
2442       InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2443       continue;
2444     }
2445 
2446     // In the following cases, assign a node order of "idx+1"
2447     // to newly created nodes. The SDNodes for params have to
2448     // appear in the same order as their order of appearance
2449     // in the original function. "idx+1" holds that order.
2450     if (!PAL.hasParamAttribute(i, Attribute::ByVal)) {
2451       bool aggregateIsPacked = false;
2452       if (StructType *STy = dyn_cast<StructType>(Ty))
2453         aggregateIsPacked = STy->isPacked();
2454 
2455       SmallVector<EVT, 16> VTs;
2456       SmallVector<uint64_t, 16> Offsets;
2457       ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets, 0);
2458       assert(VTs.size() > 0 && "Unexpected empty type.");
2459       auto VectorInfo =
2460           VectorizePTXValueVTs(VTs, Offsets, DL.getABITypeAlignment(Ty));
2461 
2462       SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2463       int VecIdx = -1; // Index of the first element of the current vector.
2464       for (unsigned parti = 0, parte = VTs.size(); parti != parte; ++parti) {
2465         if (VectorInfo[parti] & PVF_FIRST) {
2466           assert(VecIdx == -1 && "Orphaned vector.");
2467           VecIdx = parti;
2468         }
2469 
2470         // That's the last element of this store op.
2471         if (VectorInfo[parti] & PVF_LAST) {
2472           unsigned NumElts = parti - VecIdx + 1;
2473           EVT EltVT = VTs[parti];
2474           // i1 is loaded/stored as i8.
2475           EVT LoadVT = EltVT;
2476           if (EltVT == MVT::i1)
2477             LoadVT = MVT::i8;
2478           else if (EltVT == MVT::v2f16)
2479             // getLoad needs a vector type, but it can't handle
2480             // vectors which contain v2f16 elements. So we must load
2481             // using i32 here and then bitcast back.
2482             LoadVT = MVT::i32;
2483 
2484           EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts);
2485           SDValue VecAddr =
2486               DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2487                           DAG.getConstant(Offsets[VecIdx], dl, PtrVT));
2488           Value *srcValue = Constant::getNullValue(PointerType::get(
2489               EltVT.getTypeForEVT(F->getContext()), ADDRESS_SPACE_PARAM));
2490           SDValue P =
2491               DAG.getLoad(VecVT, dl, Root, VecAddr,
2492                           MachinePointerInfo(srcValue), aggregateIsPacked,
2493                           MachineMemOperand::MODereferenceable |
2494                               MachineMemOperand::MOInvariant);
2495           if (P.getNode())
2496             P.getNode()->setIROrder(idx + 1);
2497           for (unsigned j = 0; j < NumElts; ++j) {
2498             SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P,
2499                                       DAG.getIntPtrConstant(j, dl));
2500             // We've loaded i1 as an i8 and now must truncate it back to i1
2501             if (EltVT == MVT::i1)
2502               Elt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Elt);
2503             // v2f16 was loaded as an i32. Now we must bitcast it back.
2504             else if (EltVT == MVT::v2f16)
2505               Elt = DAG.getNode(ISD::BITCAST, dl, MVT::v2f16, Elt);
2506             // Extend the element if necessary (e.g. an i8 is loaded
2507             // into an i16 register)
2508             if (Ins[InsIdx].VT.isInteger() &&
2509                 Ins[InsIdx].VT.getSizeInBits() > LoadVT.getSizeInBits()) {
2510               unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
2511                                                            : ISD::ZERO_EXTEND;
2512               Elt = DAG.getNode(Extend, dl, Ins[InsIdx].VT, Elt);
2513             }
2514             InVals.push_back(Elt);
2515           }
2516 
2517           // Reset vector tracking state.
2518           VecIdx = -1;
2519         }
2520         ++InsIdx;
2521       }
2522       if (VTs.size() > 0)
2523         --InsIdx;
2524       continue;
2525     }
2526 
2527     // Param has ByVal attribute
2528     // Return MoveParam(param symbol).
2529     // Ideally, the param symbol can be returned directly,
2530     // but when SDNode builder decides to use it in a CopyToReg(),
2531     // machine instruction fails because TargetExternalSymbol
2532     // (not lowered) is target dependent, and CopyToReg assumes
2533     // the source is lowered.
2534     EVT ObjectVT = getValueType(DL, Ty);
2535     assert(ObjectVT == Ins[InsIdx].VT &&
2536            "Ins type did not match function type");
2537     SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2538     SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2539     if (p.getNode())
2540       p.getNode()->setIROrder(idx + 1);
2541     InVals.push_back(p);
2542   }
2543 
2544   // Clang will check explicit VarArg and issue error if any. However, Clang
2545   // will let code with
2546   // implicit var arg like f() pass. See bug 617733.
2547   // We treat this case as if the arg list is empty.
2548   // if (F.isVarArg()) {
2549   // assert(0 && "VarArg not supported yet!");
2550   //}
2551 
2552   if (!OutChains.empty())
2553     DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2554 
2555   return Chain;
2556 }
2557 
2558 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & dl,SelectionDAG & DAG) const2559 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2560                                  bool isVarArg,
2561                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
2562                                  const SmallVectorImpl<SDValue> &OutVals,
2563                                  const SDLoc &dl, SelectionDAG &DAG) const {
2564   MachineFunction &MF = DAG.getMachineFunction();
2565   Type *RetTy = MF.getFunction().getReturnType();
2566 
2567   bool isABI = (STI.getSmVersion() >= 20);
2568   assert(isABI && "Non-ABI compilation is not supported");
2569   if (!isABI)
2570     return Chain;
2571 
2572   const DataLayout DL = DAG.getDataLayout();
2573   SmallVector<EVT, 16> VTs;
2574   SmallVector<uint64_t, 16> Offsets;
2575   ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets);
2576   assert(VTs.size() == OutVals.size() && "Bad return value decomposition");
2577 
2578   auto VectorInfo = VectorizePTXValueVTs(
2579       VTs, Offsets, RetTy->isSized() ? DL.getABITypeAlignment(RetTy) : 1);
2580 
2581   // PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
2582   // 32-bits are sign extended or zero extended, depending on whether
2583   // they are signed or unsigned types.
2584   bool ExtendIntegerRetVal =
2585       RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
2586 
2587   SmallVector<SDValue, 6> StoreOperands;
2588   for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2589     // New load/store. Record chain and offset operands.
2590     if (VectorInfo[i] & PVF_FIRST) {
2591       assert(StoreOperands.empty() && "Orphaned operand list.");
2592       StoreOperands.push_back(Chain);
2593       StoreOperands.push_back(DAG.getConstant(Offsets[i], dl, MVT::i32));
2594     }
2595 
2596     SDValue RetVal = OutVals[i];
2597     if (ExtendIntegerRetVal) {
2598       RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND
2599                                                   : ISD::ZERO_EXTEND,
2600                            dl, MVT::i32, RetVal);
2601     } else if (RetVal.getValueSizeInBits() < 16) {
2602       // Use 16-bit registers for small load-stores as it's the
2603       // smallest general purpose register size supported by NVPTX.
2604       RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal);
2605     }
2606 
2607     // Record the value to return.
2608     StoreOperands.push_back(RetVal);
2609 
2610     // That's the last element of this store op.
2611     if (VectorInfo[i] & PVF_LAST) {
2612       NVPTXISD::NodeType Op;
2613       unsigned NumElts = StoreOperands.size() - 2;
2614       switch (NumElts) {
2615       case 1:
2616         Op = NVPTXISD::StoreRetval;
2617         break;
2618       case 2:
2619         Op = NVPTXISD::StoreRetvalV2;
2620         break;
2621       case 4:
2622         Op = NVPTXISD::StoreRetvalV4;
2623         break;
2624       default:
2625         llvm_unreachable("Invalid vector info.");
2626       }
2627 
2628       // Adjust type of load/store op if we've extended the scalar
2629       // return value.
2630       EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
2631       Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
2632                                       StoreOperands, TheStoreType,
2633                                       MachinePointerInfo(), /* Align */ 1,
2634                                       MachineMemOperand::MOStore);
2635       // Cleanup vector state.
2636       StoreOperands.clear();
2637     }
2638   }
2639 
2640   return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2641 }
2642 
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const2643 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2644     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2645     SelectionDAG &DAG) const {
2646   if (Constraint.length() > 1)
2647     return;
2648   else
2649     TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2650 }
2651 
getOpcForTextureInstr(unsigned Intrinsic)2652 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2653   switch (Intrinsic) {
2654   default:
2655     return 0;
2656 
2657   case Intrinsic::nvvm_tex_1d_v4f32_s32:
2658     return NVPTXISD::Tex1DFloatS32;
2659   case Intrinsic::nvvm_tex_1d_v4f32_f32:
2660     return NVPTXISD::Tex1DFloatFloat;
2661   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2662     return NVPTXISD::Tex1DFloatFloatLevel;
2663   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2664     return NVPTXISD::Tex1DFloatFloatGrad;
2665   case Intrinsic::nvvm_tex_1d_v4s32_s32:
2666     return NVPTXISD::Tex1DS32S32;
2667   case Intrinsic::nvvm_tex_1d_v4s32_f32:
2668     return NVPTXISD::Tex1DS32Float;
2669   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2670     return NVPTXISD::Tex1DS32FloatLevel;
2671   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2672     return NVPTXISD::Tex1DS32FloatGrad;
2673   case Intrinsic::nvvm_tex_1d_v4u32_s32:
2674     return NVPTXISD::Tex1DU32S32;
2675   case Intrinsic::nvvm_tex_1d_v4u32_f32:
2676     return NVPTXISD::Tex1DU32Float;
2677   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2678     return NVPTXISD::Tex1DU32FloatLevel;
2679   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2680     return NVPTXISD::Tex1DU32FloatGrad;
2681 
2682   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2683     return NVPTXISD::Tex1DArrayFloatS32;
2684   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2685     return NVPTXISD::Tex1DArrayFloatFloat;
2686   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2687     return NVPTXISD::Tex1DArrayFloatFloatLevel;
2688   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2689     return NVPTXISD::Tex1DArrayFloatFloatGrad;
2690   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2691     return NVPTXISD::Tex1DArrayS32S32;
2692   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2693     return NVPTXISD::Tex1DArrayS32Float;
2694   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2695     return NVPTXISD::Tex1DArrayS32FloatLevel;
2696   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2697     return NVPTXISD::Tex1DArrayS32FloatGrad;
2698   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2699     return NVPTXISD::Tex1DArrayU32S32;
2700   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2701     return NVPTXISD::Tex1DArrayU32Float;
2702   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2703     return NVPTXISD::Tex1DArrayU32FloatLevel;
2704   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2705     return NVPTXISD::Tex1DArrayU32FloatGrad;
2706 
2707   case Intrinsic::nvvm_tex_2d_v4f32_s32:
2708     return NVPTXISD::Tex2DFloatS32;
2709   case Intrinsic::nvvm_tex_2d_v4f32_f32:
2710     return NVPTXISD::Tex2DFloatFloat;
2711   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2712     return NVPTXISD::Tex2DFloatFloatLevel;
2713   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2714     return NVPTXISD::Tex2DFloatFloatGrad;
2715   case Intrinsic::nvvm_tex_2d_v4s32_s32:
2716     return NVPTXISD::Tex2DS32S32;
2717   case Intrinsic::nvvm_tex_2d_v4s32_f32:
2718     return NVPTXISD::Tex2DS32Float;
2719   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2720     return NVPTXISD::Tex2DS32FloatLevel;
2721   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2722     return NVPTXISD::Tex2DS32FloatGrad;
2723   case Intrinsic::nvvm_tex_2d_v4u32_s32:
2724     return NVPTXISD::Tex2DU32S32;
2725   case Intrinsic::nvvm_tex_2d_v4u32_f32:
2726     return NVPTXISD::Tex2DU32Float;
2727   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2728     return NVPTXISD::Tex2DU32FloatLevel;
2729   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2730     return NVPTXISD::Tex2DU32FloatGrad;
2731 
2732   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2733     return NVPTXISD::Tex2DArrayFloatS32;
2734   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2735     return NVPTXISD::Tex2DArrayFloatFloat;
2736   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2737     return NVPTXISD::Tex2DArrayFloatFloatLevel;
2738   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2739     return NVPTXISD::Tex2DArrayFloatFloatGrad;
2740   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2741     return NVPTXISD::Tex2DArrayS32S32;
2742   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2743     return NVPTXISD::Tex2DArrayS32Float;
2744   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2745     return NVPTXISD::Tex2DArrayS32FloatLevel;
2746   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2747     return NVPTXISD::Tex2DArrayS32FloatGrad;
2748   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2749     return NVPTXISD::Tex2DArrayU32S32;
2750   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2751     return NVPTXISD::Tex2DArrayU32Float;
2752   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2753     return NVPTXISD::Tex2DArrayU32FloatLevel;
2754   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2755     return NVPTXISD::Tex2DArrayU32FloatGrad;
2756 
2757   case Intrinsic::nvvm_tex_3d_v4f32_s32:
2758     return NVPTXISD::Tex3DFloatS32;
2759   case Intrinsic::nvvm_tex_3d_v4f32_f32:
2760     return NVPTXISD::Tex3DFloatFloat;
2761   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2762     return NVPTXISD::Tex3DFloatFloatLevel;
2763   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2764     return NVPTXISD::Tex3DFloatFloatGrad;
2765   case Intrinsic::nvvm_tex_3d_v4s32_s32:
2766     return NVPTXISD::Tex3DS32S32;
2767   case Intrinsic::nvvm_tex_3d_v4s32_f32:
2768     return NVPTXISD::Tex3DS32Float;
2769   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2770     return NVPTXISD::Tex3DS32FloatLevel;
2771   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2772     return NVPTXISD::Tex3DS32FloatGrad;
2773   case Intrinsic::nvvm_tex_3d_v4u32_s32:
2774     return NVPTXISD::Tex3DU32S32;
2775   case Intrinsic::nvvm_tex_3d_v4u32_f32:
2776     return NVPTXISD::Tex3DU32Float;
2777   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2778     return NVPTXISD::Tex3DU32FloatLevel;
2779   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2780     return NVPTXISD::Tex3DU32FloatGrad;
2781 
2782   case Intrinsic::nvvm_tex_cube_v4f32_f32:
2783     return NVPTXISD::TexCubeFloatFloat;
2784   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2785     return NVPTXISD::TexCubeFloatFloatLevel;
2786   case Intrinsic::nvvm_tex_cube_v4s32_f32:
2787     return NVPTXISD::TexCubeS32Float;
2788   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2789     return NVPTXISD::TexCubeS32FloatLevel;
2790   case Intrinsic::nvvm_tex_cube_v4u32_f32:
2791     return NVPTXISD::TexCubeU32Float;
2792   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2793     return NVPTXISD::TexCubeU32FloatLevel;
2794 
2795   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2796     return NVPTXISD::TexCubeArrayFloatFloat;
2797   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2798     return NVPTXISD::TexCubeArrayFloatFloatLevel;
2799   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2800     return NVPTXISD::TexCubeArrayS32Float;
2801   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2802     return NVPTXISD::TexCubeArrayS32FloatLevel;
2803   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2804     return NVPTXISD::TexCubeArrayU32Float;
2805   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2806     return NVPTXISD::TexCubeArrayU32FloatLevel;
2807 
2808   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2809     return NVPTXISD::Tld4R2DFloatFloat;
2810   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2811     return NVPTXISD::Tld4G2DFloatFloat;
2812   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2813     return NVPTXISD::Tld4B2DFloatFloat;
2814   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2815     return NVPTXISD::Tld4A2DFloatFloat;
2816   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2817     return NVPTXISD::Tld4R2DS64Float;
2818   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2819     return NVPTXISD::Tld4G2DS64Float;
2820   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2821     return NVPTXISD::Tld4B2DS64Float;
2822   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2823     return NVPTXISD::Tld4A2DS64Float;
2824   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2825     return NVPTXISD::Tld4R2DU64Float;
2826   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2827     return NVPTXISD::Tld4G2DU64Float;
2828   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2829     return NVPTXISD::Tld4B2DU64Float;
2830   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2831     return NVPTXISD::Tld4A2DU64Float;
2832 
2833   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2834     return NVPTXISD::TexUnified1DFloatS32;
2835   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2836     return NVPTXISD::TexUnified1DFloatFloat;
2837   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2838     return NVPTXISD::TexUnified1DFloatFloatLevel;
2839   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2840     return NVPTXISD::TexUnified1DFloatFloatGrad;
2841   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2842     return NVPTXISD::TexUnified1DS32S32;
2843   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2844     return NVPTXISD::TexUnified1DS32Float;
2845   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2846     return NVPTXISD::TexUnified1DS32FloatLevel;
2847   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2848     return NVPTXISD::TexUnified1DS32FloatGrad;
2849   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2850     return NVPTXISD::TexUnified1DU32S32;
2851   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2852     return NVPTXISD::TexUnified1DU32Float;
2853   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2854     return NVPTXISD::TexUnified1DU32FloatLevel;
2855   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2856     return NVPTXISD::TexUnified1DU32FloatGrad;
2857 
2858   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2859     return NVPTXISD::TexUnified1DArrayFloatS32;
2860   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2861     return NVPTXISD::TexUnified1DArrayFloatFloat;
2862   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2863     return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2864   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2865     return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2866   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2867     return NVPTXISD::TexUnified1DArrayS32S32;
2868   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2869     return NVPTXISD::TexUnified1DArrayS32Float;
2870   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2871     return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2872   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2873     return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2874   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2875     return NVPTXISD::TexUnified1DArrayU32S32;
2876   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2877     return NVPTXISD::TexUnified1DArrayU32Float;
2878   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2879     return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2880   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2881     return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2882 
2883   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2884     return NVPTXISD::TexUnified2DFloatS32;
2885   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2886     return NVPTXISD::TexUnified2DFloatFloat;
2887   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2888     return NVPTXISD::TexUnified2DFloatFloatLevel;
2889   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2890     return NVPTXISD::TexUnified2DFloatFloatGrad;
2891   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2892     return NVPTXISD::TexUnified2DS32S32;
2893   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2894     return NVPTXISD::TexUnified2DS32Float;
2895   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2896     return NVPTXISD::TexUnified2DS32FloatLevel;
2897   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2898     return NVPTXISD::TexUnified2DS32FloatGrad;
2899   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2900     return NVPTXISD::TexUnified2DU32S32;
2901   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2902     return NVPTXISD::TexUnified2DU32Float;
2903   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2904     return NVPTXISD::TexUnified2DU32FloatLevel;
2905   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2906     return NVPTXISD::TexUnified2DU32FloatGrad;
2907 
2908   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2909     return NVPTXISD::TexUnified2DArrayFloatS32;
2910   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2911     return NVPTXISD::TexUnified2DArrayFloatFloat;
2912   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2913     return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2914   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2915     return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2916   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2917     return NVPTXISD::TexUnified2DArrayS32S32;
2918   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2919     return NVPTXISD::TexUnified2DArrayS32Float;
2920   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2921     return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2922   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2923     return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2924   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2925     return NVPTXISD::TexUnified2DArrayU32S32;
2926   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2927     return NVPTXISD::TexUnified2DArrayU32Float;
2928   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2929     return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2930   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2931     return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2932 
2933   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2934     return NVPTXISD::TexUnified3DFloatS32;
2935   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2936     return NVPTXISD::TexUnified3DFloatFloat;
2937   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2938     return NVPTXISD::TexUnified3DFloatFloatLevel;
2939   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2940     return NVPTXISD::TexUnified3DFloatFloatGrad;
2941   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2942     return NVPTXISD::TexUnified3DS32S32;
2943   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2944     return NVPTXISD::TexUnified3DS32Float;
2945   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2946     return NVPTXISD::TexUnified3DS32FloatLevel;
2947   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2948     return NVPTXISD::TexUnified3DS32FloatGrad;
2949   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2950     return NVPTXISD::TexUnified3DU32S32;
2951   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2952     return NVPTXISD::TexUnified3DU32Float;
2953   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2954     return NVPTXISD::TexUnified3DU32FloatLevel;
2955   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2956     return NVPTXISD::TexUnified3DU32FloatGrad;
2957 
2958   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2959     return NVPTXISD::TexUnifiedCubeFloatFloat;
2960   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2961     return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2962   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2963     return NVPTXISD::TexUnifiedCubeS32Float;
2964   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2965     return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2966   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2967     return NVPTXISD::TexUnifiedCubeU32Float;
2968   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2969     return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2970 
2971   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2972     return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2973   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2974     return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2975   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2976     return NVPTXISD::TexUnifiedCubeArrayS32Float;
2977   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2978     return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2979   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2980     return NVPTXISD::TexUnifiedCubeArrayU32Float;
2981   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2982     return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2983 
2984   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2985     return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2986   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2987     return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2988   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2989     return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2990   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2991     return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2992   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2993     return NVPTXISD::Tld4UnifiedR2DS64Float;
2994   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2995     return NVPTXISD::Tld4UnifiedG2DS64Float;
2996   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2997     return NVPTXISD::Tld4UnifiedB2DS64Float;
2998   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2999     return NVPTXISD::Tld4UnifiedA2DS64Float;
3000   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3001     return NVPTXISD::Tld4UnifiedR2DU64Float;
3002   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3003     return NVPTXISD::Tld4UnifiedG2DU64Float;
3004   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3005     return NVPTXISD::Tld4UnifiedB2DU64Float;
3006   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3007     return NVPTXISD::Tld4UnifiedA2DU64Float;
3008   }
3009 }
3010 
getOpcForSurfaceInstr(unsigned Intrinsic)3011 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
3012   switch (Intrinsic) {
3013   default:
3014     return 0;
3015   case Intrinsic::nvvm_suld_1d_i8_clamp:
3016     return NVPTXISD::Suld1DI8Clamp;
3017   case Intrinsic::nvvm_suld_1d_i16_clamp:
3018     return NVPTXISD::Suld1DI16Clamp;
3019   case Intrinsic::nvvm_suld_1d_i32_clamp:
3020     return NVPTXISD::Suld1DI32Clamp;
3021   case Intrinsic::nvvm_suld_1d_i64_clamp:
3022     return NVPTXISD::Suld1DI64Clamp;
3023   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3024     return NVPTXISD::Suld1DV2I8Clamp;
3025   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3026     return NVPTXISD::Suld1DV2I16Clamp;
3027   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3028     return NVPTXISD::Suld1DV2I32Clamp;
3029   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3030     return NVPTXISD::Suld1DV2I64Clamp;
3031   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3032     return NVPTXISD::Suld1DV4I8Clamp;
3033   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3034     return NVPTXISD::Suld1DV4I16Clamp;
3035   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3036     return NVPTXISD::Suld1DV4I32Clamp;
3037   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3038     return NVPTXISD::Suld1DArrayI8Clamp;
3039   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3040     return NVPTXISD::Suld1DArrayI16Clamp;
3041   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3042     return NVPTXISD::Suld1DArrayI32Clamp;
3043   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3044     return NVPTXISD::Suld1DArrayI64Clamp;
3045   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3046     return NVPTXISD::Suld1DArrayV2I8Clamp;
3047   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3048     return NVPTXISD::Suld1DArrayV2I16Clamp;
3049   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3050     return NVPTXISD::Suld1DArrayV2I32Clamp;
3051   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3052     return NVPTXISD::Suld1DArrayV2I64Clamp;
3053   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3054     return NVPTXISD::Suld1DArrayV4I8Clamp;
3055   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3056     return NVPTXISD::Suld1DArrayV4I16Clamp;
3057   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3058     return NVPTXISD::Suld1DArrayV4I32Clamp;
3059   case Intrinsic::nvvm_suld_2d_i8_clamp:
3060     return NVPTXISD::Suld2DI8Clamp;
3061   case Intrinsic::nvvm_suld_2d_i16_clamp:
3062     return NVPTXISD::Suld2DI16Clamp;
3063   case Intrinsic::nvvm_suld_2d_i32_clamp:
3064     return NVPTXISD::Suld2DI32Clamp;
3065   case Intrinsic::nvvm_suld_2d_i64_clamp:
3066     return NVPTXISD::Suld2DI64Clamp;
3067   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3068     return NVPTXISD::Suld2DV2I8Clamp;
3069   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3070     return NVPTXISD::Suld2DV2I16Clamp;
3071   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3072     return NVPTXISD::Suld2DV2I32Clamp;
3073   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3074     return NVPTXISD::Suld2DV2I64Clamp;
3075   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3076     return NVPTXISD::Suld2DV4I8Clamp;
3077   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3078     return NVPTXISD::Suld2DV4I16Clamp;
3079   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3080     return NVPTXISD::Suld2DV4I32Clamp;
3081   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3082     return NVPTXISD::Suld2DArrayI8Clamp;
3083   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3084     return NVPTXISD::Suld2DArrayI16Clamp;
3085   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3086     return NVPTXISD::Suld2DArrayI32Clamp;
3087   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3088     return NVPTXISD::Suld2DArrayI64Clamp;
3089   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3090     return NVPTXISD::Suld2DArrayV2I8Clamp;
3091   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3092     return NVPTXISD::Suld2DArrayV2I16Clamp;
3093   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3094     return NVPTXISD::Suld2DArrayV2I32Clamp;
3095   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3096     return NVPTXISD::Suld2DArrayV2I64Clamp;
3097   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3098     return NVPTXISD::Suld2DArrayV4I8Clamp;
3099   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3100     return NVPTXISD::Suld2DArrayV4I16Clamp;
3101   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3102     return NVPTXISD::Suld2DArrayV4I32Clamp;
3103   case Intrinsic::nvvm_suld_3d_i8_clamp:
3104     return NVPTXISD::Suld3DI8Clamp;
3105   case Intrinsic::nvvm_suld_3d_i16_clamp:
3106     return NVPTXISD::Suld3DI16Clamp;
3107   case Intrinsic::nvvm_suld_3d_i32_clamp:
3108     return NVPTXISD::Suld3DI32Clamp;
3109   case Intrinsic::nvvm_suld_3d_i64_clamp:
3110     return NVPTXISD::Suld3DI64Clamp;
3111   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3112     return NVPTXISD::Suld3DV2I8Clamp;
3113   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3114     return NVPTXISD::Suld3DV2I16Clamp;
3115   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3116     return NVPTXISD::Suld3DV2I32Clamp;
3117   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3118     return NVPTXISD::Suld3DV2I64Clamp;
3119   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3120     return NVPTXISD::Suld3DV4I8Clamp;
3121   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3122     return NVPTXISD::Suld3DV4I16Clamp;
3123   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3124     return NVPTXISD::Suld3DV4I32Clamp;
3125   case Intrinsic::nvvm_suld_1d_i8_trap:
3126     return NVPTXISD::Suld1DI8Trap;
3127   case Intrinsic::nvvm_suld_1d_i16_trap:
3128     return NVPTXISD::Suld1DI16Trap;
3129   case Intrinsic::nvvm_suld_1d_i32_trap:
3130     return NVPTXISD::Suld1DI32Trap;
3131   case Intrinsic::nvvm_suld_1d_i64_trap:
3132     return NVPTXISD::Suld1DI64Trap;
3133   case Intrinsic::nvvm_suld_1d_v2i8_trap:
3134     return NVPTXISD::Suld1DV2I8Trap;
3135   case Intrinsic::nvvm_suld_1d_v2i16_trap:
3136     return NVPTXISD::Suld1DV2I16Trap;
3137   case Intrinsic::nvvm_suld_1d_v2i32_trap:
3138     return NVPTXISD::Suld1DV2I32Trap;
3139   case Intrinsic::nvvm_suld_1d_v2i64_trap:
3140     return NVPTXISD::Suld1DV2I64Trap;
3141   case Intrinsic::nvvm_suld_1d_v4i8_trap:
3142     return NVPTXISD::Suld1DV4I8Trap;
3143   case Intrinsic::nvvm_suld_1d_v4i16_trap:
3144     return NVPTXISD::Suld1DV4I16Trap;
3145   case Intrinsic::nvvm_suld_1d_v4i32_trap:
3146     return NVPTXISD::Suld1DV4I32Trap;
3147   case Intrinsic::nvvm_suld_1d_array_i8_trap:
3148     return NVPTXISD::Suld1DArrayI8Trap;
3149   case Intrinsic::nvvm_suld_1d_array_i16_trap:
3150     return NVPTXISD::Suld1DArrayI16Trap;
3151   case Intrinsic::nvvm_suld_1d_array_i32_trap:
3152     return NVPTXISD::Suld1DArrayI32Trap;
3153   case Intrinsic::nvvm_suld_1d_array_i64_trap:
3154     return NVPTXISD::Suld1DArrayI64Trap;
3155   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3156     return NVPTXISD::Suld1DArrayV2I8Trap;
3157   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3158     return NVPTXISD::Suld1DArrayV2I16Trap;
3159   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3160     return NVPTXISD::Suld1DArrayV2I32Trap;
3161   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3162     return NVPTXISD::Suld1DArrayV2I64Trap;
3163   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3164     return NVPTXISD::Suld1DArrayV4I8Trap;
3165   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3166     return NVPTXISD::Suld1DArrayV4I16Trap;
3167   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3168     return NVPTXISD::Suld1DArrayV4I32Trap;
3169   case Intrinsic::nvvm_suld_2d_i8_trap:
3170     return NVPTXISD::Suld2DI8Trap;
3171   case Intrinsic::nvvm_suld_2d_i16_trap:
3172     return NVPTXISD::Suld2DI16Trap;
3173   case Intrinsic::nvvm_suld_2d_i32_trap:
3174     return NVPTXISD::Suld2DI32Trap;
3175   case Intrinsic::nvvm_suld_2d_i64_trap:
3176     return NVPTXISD::Suld2DI64Trap;
3177   case Intrinsic::nvvm_suld_2d_v2i8_trap:
3178     return NVPTXISD::Suld2DV2I8Trap;
3179   case Intrinsic::nvvm_suld_2d_v2i16_trap:
3180     return NVPTXISD::Suld2DV2I16Trap;
3181   case Intrinsic::nvvm_suld_2d_v2i32_trap:
3182     return NVPTXISD::Suld2DV2I32Trap;
3183   case Intrinsic::nvvm_suld_2d_v2i64_trap:
3184     return NVPTXISD::Suld2DV2I64Trap;
3185   case Intrinsic::nvvm_suld_2d_v4i8_trap:
3186     return NVPTXISD::Suld2DV4I8Trap;
3187   case Intrinsic::nvvm_suld_2d_v4i16_trap:
3188     return NVPTXISD::Suld2DV4I16Trap;
3189   case Intrinsic::nvvm_suld_2d_v4i32_trap:
3190     return NVPTXISD::Suld2DV4I32Trap;
3191   case Intrinsic::nvvm_suld_2d_array_i8_trap:
3192     return NVPTXISD::Suld2DArrayI8Trap;
3193   case Intrinsic::nvvm_suld_2d_array_i16_trap:
3194     return NVPTXISD::Suld2DArrayI16Trap;
3195   case Intrinsic::nvvm_suld_2d_array_i32_trap:
3196     return NVPTXISD::Suld2DArrayI32Trap;
3197   case Intrinsic::nvvm_suld_2d_array_i64_trap:
3198     return NVPTXISD::Suld2DArrayI64Trap;
3199   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3200     return NVPTXISD::Suld2DArrayV2I8Trap;
3201   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3202     return NVPTXISD::Suld2DArrayV2I16Trap;
3203   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3204     return NVPTXISD::Suld2DArrayV2I32Trap;
3205   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3206     return NVPTXISD::Suld2DArrayV2I64Trap;
3207   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3208     return NVPTXISD::Suld2DArrayV4I8Trap;
3209   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3210     return NVPTXISD::Suld2DArrayV4I16Trap;
3211   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3212     return NVPTXISD::Suld2DArrayV4I32Trap;
3213   case Intrinsic::nvvm_suld_3d_i8_trap:
3214     return NVPTXISD::Suld3DI8Trap;
3215   case Intrinsic::nvvm_suld_3d_i16_trap:
3216     return NVPTXISD::Suld3DI16Trap;
3217   case Intrinsic::nvvm_suld_3d_i32_trap:
3218     return NVPTXISD::Suld3DI32Trap;
3219   case Intrinsic::nvvm_suld_3d_i64_trap:
3220     return NVPTXISD::Suld3DI64Trap;
3221   case Intrinsic::nvvm_suld_3d_v2i8_trap:
3222     return NVPTXISD::Suld3DV2I8Trap;
3223   case Intrinsic::nvvm_suld_3d_v2i16_trap:
3224     return NVPTXISD::Suld3DV2I16Trap;
3225   case Intrinsic::nvvm_suld_3d_v2i32_trap:
3226     return NVPTXISD::Suld3DV2I32Trap;
3227   case Intrinsic::nvvm_suld_3d_v2i64_trap:
3228     return NVPTXISD::Suld3DV2I64Trap;
3229   case Intrinsic::nvvm_suld_3d_v4i8_trap:
3230     return NVPTXISD::Suld3DV4I8Trap;
3231   case Intrinsic::nvvm_suld_3d_v4i16_trap:
3232     return NVPTXISD::Suld3DV4I16Trap;
3233   case Intrinsic::nvvm_suld_3d_v4i32_trap:
3234     return NVPTXISD::Suld3DV4I32Trap;
3235   case Intrinsic::nvvm_suld_1d_i8_zero:
3236     return NVPTXISD::Suld1DI8Zero;
3237   case Intrinsic::nvvm_suld_1d_i16_zero:
3238     return NVPTXISD::Suld1DI16Zero;
3239   case Intrinsic::nvvm_suld_1d_i32_zero:
3240     return NVPTXISD::Suld1DI32Zero;
3241   case Intrinsic::nvvm_suld_1d_i64_zero:
3242     return NVPTXISD::Suld1DI64Zero;
3243   case Intrinsic::nvvm_suld_1d_v2i8_zero:
3244     return NVPTXISD::Suld1DV2I8Zero;
3245   case Intrinsic::nvvm_suld_1d_v2i16_zero:
3246     return NVPTXISD::Suld1DV2I16Zero;
3247   case Intrinsic::nvvm_suld_1d_v2i32_zero:
3248     return NVPTXISD::Suld1DV2I32Zero;
3249   case Intrinsic::nvvm_suld_1d_v2i64_zero:
3250     return NVPTXISD::Suld1DV2I64Zero;
3251   case Intrinsic::nvvm_suld_1d_v4i8_zero:
3252     return NVPTXISD::Suld1DV4I8Zero;
3253   case Intrinsic::nvvm_suld_1d_v4i16_zero:
3254     return NVPTXISD::Suld1DV4I16Zero;
3255   case Intrinsic::nvvm_suld_1d_v4i32_zero:
3256     return NVPTXISD::Suld1DV4I32Zero;
3257   case Intrinsic::nvvm_suld_1d_array_i8_zero:
3258     return NVPTXISD::Suld1DArrayI8Zero;
3259   case Intrinsic::nvvm_suld_1d_array_i16_zero:
3260     return NVPTXISD::Suld1DArrayI16Zero;
3261   case Intrinsic::nvvm_suld_1d_array_i32_zero:
3262     return NVPTXISD::Suld1DArrayI32Zero;
3263   case Intrinsic::nvvm_suld_1d_array_i64_zero:
3264     return NVPTXISD::Suld1DArrayI64Zero;
3265   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3266     return NVPTXISD::Suld1DArrayV2I8Zero;
3267   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3268     return NVPTXISD::Suld1DArrayV2I16Zero;
3269   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3270     return NVPTXISD::Suld1DArrayV2I32Zero;
3271   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3272     return NVPTXISD::Suld1DArrayV2I64Zero;
3273   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3274     return NVPTXISD::Suld1DArrayV4I8Zero;
3275   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3276     return NVPTXISD::Suld1DArrayV4I16Zero;
3277   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3278     return NVPTXISD::Suld1DArrayV4I32Zero;
3279   case Intrinsic::nvvm_suld_2d_i8_zero:
3280     return NVPTXISD::Suld2DI8Zero;
3281   case Intrinsic::nvvm_suld_2d_i16_zero:
3282     return NVPTXISD::Suld2DI16Zero;
3283   case Intrinsic::nvvm_suld_2d_i32_zero:
3284     return NVPTXISD::Suld2DI32Zero;
3285   case Intrinsic::nvvm_suld_2d_i64_zero:
3286     return NVPTXISD::Suld2DI64Zero;
3287   case Intrinsic::nvvm_suld_2d_v2i8_zero:
3288     return NVPTXISD::Suld2DV2I8Zero;
3289   case Intrinsic::nvvm_suld_2d_v2i16_zero:
3290     return NVPTXISD::Suld2DV2I16Zero;
3291   case Intrinsic::nvvm_suld_2d_v2i32_zero:
3292     return NVPTXISD::Suld2DV2I32Zero;
3293   case Intrinsic::nvvm_suld_2d_v2i64_zero:
3294     return NVPTXISD::Suld2DV2I64Zero;
3295   case Intrinsic::nvvm_suld_2d_v4i8_zero:
3296     return NVPTXISD::Suld2DV4I8Zero;
3297   case Intrinsic::nvvm_suld_2d_v4i16_zero:
3298     return NVPTXISD::Suld2DV4I16Zero;
3299   case Intrinsic::nvvm_suld_2d_v4i32_zero:
3300     return NVPTXISD::Suld2DV4I32Zero;
3301   case Intrinsic::nvvm_suld_2d_array_i8_zero:
3302     return NVPTXISD::Suld2DArrayI8Zero;
3303   case Intrinsic::nvvm_suld_2d_array_i16_zero:
3304     return NVPTXISD::Suld2DArrayI16Zero;
3305   case Intrinsic::nvvm_suld_2d_array_i32_zero:
3306     return NVPTXISD::Suld2DArrayI32Zero;
3307   case Intrinsic::nvvm_suld_2d_array_i64_zero:
3308     return NVPTXISD::Suld2DArrayI64Zero;
3309   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3310     return NVPTXISD::Suld2DArrayV2I8Zero;
3311   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3312     return NVPTXISD::Suld2DArrayV2I16Zero;
3313   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3314     return NVPTXISD::Suld2DArrayV2I32Zero;
3315   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3316     return NVPTXISD::Suld2DArrayV2I64Zero;
3317   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3318     return NVPTXISD::Suld2DArrayV4I8Zero;
3319   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3320     return NVPTXISD::Suld2DArrayV4I16Zero;
3321   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3322     return NVPTXISD::Suld2DArrayV4I32Zero;
3323   case Intrinsic::nvvm_suld_3d_i8_zero:
3324     return NVPTXISD::Suld3DI8Zero;
3325   case Intrinsic::nvvm_suld_3d_i16_zero:
3326     return NVPTXISD::Suld3DI16Zero;
3327   case Intrinsic::nvvm_suld_3d_i32_zero:
3328     return NVPTXISD::Suld3DI32Zero;
3329   case Intrinsic::nvvm_suld_3d_i64_zero:
3330     return NVPTXISD::Suld3DI64Zero;
3331   case Intrinsic::nvvm_suld_3d_v2i8_zero:
3332     return NVPTXISD::Suld3DV2I8Zero;
3333   case Intrinsic::nvvm_suld_3d_v2i16_zero:
3334     return NVPTXISD::Suld3DV2I16Zero;
3335   case Intrinsic::nvvm_suld_3d_v2i32_zero:
3336     return NVPTXISD::Suld3DV2I32Zero;
3337   case Intrinsic::nvvm_suld_3d_v2i64_zero:
3338     return NVPTXISD::Suld3DV2I64Zero;
3339   case Intrinsic::nvvm_suld_3d_v4i8_zero:
3340     return NVPTXISD::Suld3DV4I8Zero;
3341   case Intrinsic::nvvm_suld_3d_v4i16_zero:
3342     return NVPTXISD::Suld3DV4I16Zero;
3343   case Intrinsic::nvvm_suld_3d_v4i32_zero:
3344     return NVPTXISD::Suld3DV4I32Zero;
3345   }
3346 }
3347 
3348 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3349 // TgtMemIntrinsic
3350 // because we need the information that is only available in the "Value" type
3351 // of destination
3352 // pointer. In particular, the address space information.
getTgtMemIntrinsic(IntrinsicInfo & Info,const CallInst & I,MachineFunction & MF,unsigned Intrinsic) const3353 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3354     IntrinsicInfo &Info, const CallInst &I,
3355     MachineFunction &MF, unsigned Intrinsic) const {
3356   switch (Intrinsic) {
3357   default:
3358     return false;
3359   case Intrinsic::nvvm_match_all_sync_i32p:
3360   case Intrinsic::nvvm_match_all_sync_i64p:
3361     Info.opc = ISD::INTRINSIC_W_CHAIN;
3362     // memVT is bogus. These intrinsics have IntrInaccessibleMemOnly attribute
3363     // in order to model data exchange with other threads, but perform no real
3364     // memory accesses.
3365     Info.memVT = MVT::i1;
3366 
3367     // Our result depends on both our and other thread's arguments.
3368     Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
3369     return true;
3370   case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col:
3371   case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row:
3372   case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col_stride:
3373   case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row_stride:
3374   case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col:
3375   case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row:
3376   case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col_stride:
3377   case Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row_stride:
3378   case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_col:
3379   case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_row:
3380   case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_col_stride:
3381   case Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_row_stride:
3382   case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_col:
3383   case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_row:
3384   case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_col_stride:
3385   case Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_row_stride:
3386   case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_col:
3387   case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_row:
3388   case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_col_stride:
3389   case Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_row_stride:
3390   case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_col:
3391   case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_row:
3392   case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_col_stride:
3393   case Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_row_stride: {
3394     Info.opc = ISD::INTRINSIC_W_CHAIN;
3395     Info.memVT = MVT::v8f16;
3396     Info.ptrVal = I.getArgOperand(0);
3397     Info.offset = 0;
3398     Info.flags = MachineMemOperand::MOLoad;
3399     Info.align = 16;
3400     return true;
3401   }
3402 
3403   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col:
3404   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row:
3405   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col_stride:
3406   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row_stride:
3407   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_col:
3408   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_row:
3409   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_col_stride:
3410   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_row_stride:
3411   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_col:
3412   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_row:
3413   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_col_stride:
3414   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_row_stride: {
3415     Info.opc = ISD::INTRINSIC_W_CHAIN;
3416     Info.memVT = MVT::v4f16;
3417     Info.ptrVal = I.getArgOperand(0);
3418     Info.offset = 0;
3419     Info.flags = MachineMemOperand::MOLoad;
3420     Info.align = 16;
3421     return true;
3422   }
3423 
3424   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col:
3425   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row:
3426   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col_stride:
3427   case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row_stride:
3428   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_col:
3429   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_row:
3430   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_col_stride:
3431   case Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_row_stride:
3432   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_col:
3433   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_row:
3434   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_col_stride:
3435   case Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_row_stride: {
3436     Info.opc = ISD::INTRINSIC_W_CHAIN;
3437     Info.memVT = MVT::v8f32;
3438     Info.ptrVal = I.getArgOperand(0);
3439     Info.offset = 0;
3440     Info.flags = MachineMemOperand::MOLoad;
3441     Info.align = 16;
3442     return true;
3443   }
3444 
3445   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col:
3446   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row:
3447   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col_stride:
3448   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row_stride:
3449   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_col:
3450   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_row:
3451   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_col_stride:
3452   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_row_stride:
3453   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_col:
3454   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_row:
3455   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_col_stride:
3456   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_row_stride: {
3457     Info.opc = ISD::INTRINSIC_VOID;
3458     Info.memVT = MVT::v4f16;
3459     Info.ptrVal = I.getArgOperand(0);
3460     Info.offset = 0;
3461     Info.flags = MachineMemOperand::MOStore;
3462     Info.align = 16;
3463     return true;
3464   }
3465 
3466   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col:
3467   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row:
3468   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col_stride:
3469   case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row_stride:
3470   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_col:
3471   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_row:
3472   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_col_stride:
3473   case Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_row_stride:
3474   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_col:
3475   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_row:
3476   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_col_stride:
3477   case Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_row_stride: {
3478     Info.opc = ISD::INTRINSIC_VOID;
3479     Info.memVT = MVT::v8f32;
3480     Info.ptrVal = I.getArgOperand(0);
3481     Info.offset = 0;
3482     Info.flags = MachineMemOperand::MOStore;
3483     Info.align = 16;
3484     return true;
3485   }
3486 
3487   case Intrinsic::nvvm_atomic_load_add_f32:
3488   case Intrinsic::nvvm_atomic_load_add_f64:
3489   case Intrinsic::nvvm_atomic_load_inc_32:
3490   case Intrinsic::nvvm_atomic_load_dec_32:
3491 
3492   case Intrinsic::nvvm_atomic_add_gen_f_cta:
3493   case Intrinsic::nvvm_atomic_add_gen_f_sys:
3494   case Intrinsic::nvvm_atomic_add_gen_i_cta:
3495   case Intrinsic::nvvm_atomic_add_gen_i_sys:
3496   case Intrinsic::nvvm_atomic_and_gen_i_cta:
3497   case Intrinsic::nvvm_atomic_and_gen_i_sys:
3498   case Intrinsic::nvvm_atomic_cas_gen_i_cta:
3499   case Intrinsic::nvvm_atomic_cas_gen_i_sys:
3500   case Intrinsic::nvvm_atomic_dec_gen_i_cta:
3501   case Intrinsic::nvvm_atomic_dec_gen_i_sys:
3502   case Intrinsic::nvvm_atomic_inc_gen_i_cta:
3503   case Intrinsic::nvvm_atomic_inc_gen_i_sys:
3504   case Intrinsic::nvvm_atomic_max_gen_i_cta:
3505   case Intrinsic::nvvm_atomic_max_gen_i_sys:
3506   case Intrinsic::nvvm_atomic_min_gen_i_cta:
3507   case Intrinsic::nvvm_atomic_min_gen_i_sys:
3508   case Intrinsic::nvvm_atomic_or_gen_i_cta:
3509   case Intrinsic::nvvm_atomic_or_gen_i_sys:
3510   case Intrinsic::nvvm_atomic_exch_gen_i_cta:
3511   case Intrinsic::nvvm_atomic_exch_gen_i_sys:
3512   case Intrinsic::nvvm_atomic_xor_gen_i_cta:
3513   case Intrinsic::nvvm_atomic_xor_gen_i_sys: {
3514     auto &DL = I.getModule()->getDataLayout();
3515     Info.opc = ISD::INTRINSIC_W_CHAIN;
3516     Info.memVT = getValueType(DL, I.getType());
3517     Info.ptrVal = I.getArgOperand(0);
3518     Info.offset = 0;
3519     Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
3520     Info.align = 0;
3521     return true;
3522   }
3523 
3524   case Intrinsic::nvvm_ldu_global_i:
3525   case Intrinsic::nvvm_ldu_global_f:
3526   case Intrinsic::nvvm_ldu_global_p: {
3527     auto &DL = I.getModule()->getDataLayout();
3528     Info.opc = ISD::INTRINSIC_W_CHAIN;
3529     if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3530       Info.memVT = getValueType(DL, I.getType());
3531     else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3532       Info.memVT = getPointerTy(DL);
3533     else
3534       Info.memVT = getValueType(DL, I.getType());
3535     Info.ptrVal = I.getArgOperand(0);
3536     Info.offset = 0;
3537     Info.flags = MachineMemOperand::MOLoad;
3538     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3539 
3540     return true;
3541   }
3542   case Intrinsic::nvvm_ldg_global_i:
3543   case Intrinsic::nvvm_ldg_global_f:
3544   case Intrinsic::nvvm_ldg_global_p: {
3545     auto &DL = I.getModule()->getDataLayout();
3546 
3547     Info.opc = ISD::INTRINSIC_W_CHAIN;
3548     if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3549       Info.memVT = getValueType(DL, I.getType());
3550     else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3551       Info.memVT = getPointerTy(DL);
3552     else
3553       Info.memVT = getValueType(DL, I.getType());
3554     Info.ptrVal = I.getArgOperand(0);
3555     Info.offset = 0;
3556     Info.flags = MachineMemOperand::MOLoad;
3557     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3558 
3559     return true;
3560   }
3561 
3562   case Intrinsic::nvvm_tex_1d_v4f32_s32:
3563   case Intrinsic::nvvm_tex_1d_v4f32_f32:
3564   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3565   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3566   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3567   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3568   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3569   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3570   case Intrinsic::nvvm_tex_2d_v4f32_s32:
3571   case Intrinsic::nvvm_tex_2d_v4f32_f32:
3572   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3573   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3574   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3575   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3576   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3577   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3578   case Intrinsic::nvvm_tex_3d_v4f32_s32:
3579   case Intrinsic::nvvm_tex_3d_v4f32_f32:
3580   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3581   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3582   case Intrinsic::nvvm_tex_cube_v4f32_f32:
3583   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3584   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3585   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3586   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3587   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3588   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3589   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3590   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3591   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3592   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3593   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3594   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3595   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3596   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3597   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3598   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3599   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3600   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3601   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3602   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3603   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3604   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3605   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3606   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3607   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3608   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3609   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3610   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3611   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3612   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3613   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3614   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3615   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3616   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3617   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3618     Info.opc = getOpcForTextureInstr(Intrinsic);
3619     Info.memVT = MVT::v4f32;
3620     Info.ptrVal = nullptr;
3621     Info.offset = 0;
3622     Info.flags = MachineMemOperand::MOLoad;
3623     Info.align = 16;
3624     return true;
3625 
3626   case Intrinsic::nvvm_tex_1d_v4s32_s32:
3627   case Intrinsic::nvvm_tex_1d_v4s32_f32:
3628   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3629   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3630   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3631   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3632   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3633   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3634   case Intrinsic::nvvm_tex_2d_v4s32_s32:
3635   case Intrinsic::nvvm_tex_2d_v4s32_f32:
3636   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3637   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3638   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3639   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3640   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3641   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3642   case Intrinsic::nvvm_tex_3d_v4s32_s32:
3643   case Intrinsic::nvvm_tex_3d_v4s32_f32:
3644   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3645   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3646   case Intrinsic::nvvm_tex_cube_v4s32_f32:
3647   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3648   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3649   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3650   case Intrinsic::nvvm_tex_cube_v4u32_f32:
3651   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3652   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3653   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3654   case Intrinsic::nvvm_tex_1d_v4u32_s32:
3655   case Intrinsic::nvvm_tex_1d_v4u32_f32:
3656   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3657   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3658   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3659   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3660   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3661   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3662   case Intrinsic::nvvm_tex_2d_v4u32_s32:
3663   case Intrinsic::nvvm_tex_2d_v4u32_f32:
3664   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3665   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3666   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3667   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3668   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3669   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3670   case Intrinsic::nvvm_tex_3d_v4u32_s32:
3671   case Intrinsic::nvvm_tex_3d_v4u32_f32:
3672   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3673   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3674   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3675   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3676   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3677   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3678   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3679   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3680   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3681   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3682   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3683   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3684   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3685   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3686   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3687   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3688   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3689   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3690   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3691   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3692   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3693   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3694   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3695   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3696   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3697   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3698   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3699   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3700   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3701   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3702   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3703   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3704   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3705   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3706   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3707   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3708   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3709   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3710   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3711   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3712   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3713   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3714   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3715   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3716   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3717   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3718   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3719   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3720   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3721   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3722   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3723   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3724   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3725   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3726   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3727   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3728   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3729   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3730   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3731   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3732   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3733   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3734   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3735   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3736   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3737   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3738     Info.opc = getOpcForTextureInstr(Intrinsic);
3739     Info.memVT = MVT::v4i32;
3740     Info.ptrVal = nullptr;
3741     Info.offset = 0;
3742     Info.flags = MachineMemOperand::MOLoad;
3743     Info.align = 16;
3744     return true;
3745 
3746   case Intrinsic::nvvm_suld_1d_i8_clamp:
3747   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3748   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3749   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3750   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3751   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3752   case Intrinsic::nvvm_suld_2d_i8_clamp:
3753   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3754   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3755   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3756   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3757   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3758   case Intrinsic::nvvm_suld_3d_i8_clamp:
3759   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3760   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3761   case Intrinsic::nvvm_suld_1d_i8_trap:
3762   case Intrinsic::nvvm_suld_1d_v2i8_trap:
3763   case Intrinsic::nvvm_suld_1d_v4i8_trap:
3764   case Intrinsic::nvvm_suld_1d_array_i8_trap:
3765   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3766   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3767   case Intrinsic::nvvm_suld_2d_i8_trap:
3768   case Intrinsic::nvvm_suld_2d_v2i8_trap:
3769   case Intrinsic::nvvm_suld_2d_v4i8_trap:
3770   case Intrinsic::nvvm_suld_2d_array_i8_trap:
3771   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3772   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3773   case Intrinsic::nvvm_suld_3d_i8_trap:
3774   case Intrinsic::nvvm_suld_3d_v2i8_trap:
3775   case Intrinsic::nvvm_suld_3d_v4i8_trap:
3776   case Intrinsic::nvvm_suld_1d_i8_zero:
3777   case Intrinsic::nvvm_suld_1d_v2i8_zero:
3778   case Intrinsic::nvvm_suld_1d_v4i8_zero:
3779   case Intrinsic::nvvm_suld_1d_array_i8_zero:
3780   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3781   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3782   case Intrinsic::nvvm_suld_2d_i8_zero:
3783   case Intrinsic::nvvm_suld_2d_v2i8_zero:
3784   case Intrinsic::nvvm_suld_2d_v4i8_zero:
3785   case Intrinsic::nvvm_suld_2d_array_i8_zero:
3786   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3787   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3788   case Intrinsic::nvvm_suld_3d_i8_zero:
3789   case Intrinsic::nvvm_suld_3d_v2i8_zero:
3790   case Intrinsic::nvvm_suld_3d_v4i8_zero:
3791     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3792     Info.memVT = MVT::i8;
3793     Info.ptrVal = nullptr;
3794     Info.offset = 0;
3795     Info.flags = MachineMemOperand::MOLoad;
3796     Info.align = 16;
3797     return true;
3798 
3799   case Intrinsic::nvvm_suld_1d_i16_clamp:
3800   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3801   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3802   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3803   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3804   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3805   case Intrinsic::nvvm_suld_2d_i16_clamp:
3806   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3807   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3808   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3809   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3810   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3811   case Intrinsic::nvvm_suld_3d_i16_clamp:
3812   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3813   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3814   case Intrinsic::nvvm_suld_1d_i16_trap:
3815   case Intrinsic::nvvm_suld_1d_v2i16_trap:
3816   case Intrinsic::nvvm_suld_1d_v4i16_trap:
3817   case Intrinsic::nvvm_suld_1d_array_i16_trap:
3818   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3819   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3820   case Intrinsic::nvvm_suld_2d_i16_trap:
3821   case Intrinsic::nvvm_suld_2d_v2i16_trap:
3822   case Intrinsic::nvvm_suld_2d_v4i16_trap:
3823   case Intrinsic::nvvm_suld_2d_array_i16_trap:
3824   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3825   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3826   case Intrinsic::nvvm_suld_3d_i16_trap:
3827   case Intrinsic::nvvm_suld_3d_v2i16_trap:
3828   case Intrinsic::nvvm_suld_3d_v4i16_trap:
3829   case Intrinsic::nvvm_suld_1d_i16_zero:
3830   case Intrinsic::nvvm_suld_1d_v2i16_zero:
3831   case Intrinsic::nvvm_suld_1d_v4i16_zero:
3832   case Intrinsic::nvvm_suld_1d_array_i16_zero:
3833   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3834   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3835   case Intrinsic::nvvm_suld_2d_i16_zero:
3836   case Intrinsic::nvvm_suld_2d_v2i16_zero:
3837   case Intrinsic::nvvm_suld_2d_v4i16_zero:
3838   case Intrinsic::nvvm_suld_2d_array_i16_zero:
3839   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3840   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3841   case Intrinsic::nvvm_suld_3d_i16_zero:
3842   case Intrinsic::nvvm_suld_3d_v2i16_zero:
3843   case Intrinsic::nvvm_suld_3d_v4i16_zero:
3844     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3845     Info.memVT = MVT::i16;
3846     Info.ptrVal = nullptr;
3847     Info.offset = 0;
3848     Info.flags = MachineMemOperand::MOLoad;
3849     Info.align = 16;
3850     return true;
3851 
3852   case Intrinsic::nvvm_suld_1d_i32_clamp:
3853   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3854   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3855   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3856   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3857   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3858   case Intrinsic::nvvm_suld_2d_i32_clamp:
3859   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3860   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3861   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3862   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3863   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3864   case Intrinsic::nvvm_suld_3d_i32_clamp:
3865   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3866   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3867   case Intrinsic::nvvm_suld_1d_i32_trap:
3868   case Intrinsic::nvvm_suld_1d_v2i32_trap:
3869   case Intrinsic::nvvm_suld_1d_v4i32_trap:
3870   case Intrinsic::nvvm_suld_1d_array_i32_trap:
3871   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3872   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3873   case Intrinsic::nvvm_suld_2d_i32_trap:
3874   case Intrinsic::nvvm_suld_2d_v2i32_trap:
3875   case Intrinsic::nvvm_suld_2d_v4i32_trap:
3876   case Intrinsic::nvvm_suld_2d_array_i32_trap:
3877   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3878   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3879   case Intrinsic::nvvm_suld_3d_i32_trap:
3880   case Intrinsic::nvvm_suld_3d_v2i32_trap:
3881   case Intrinsic::nvvm_suld_3d_v4i32_trap:
3882   case Intrinsic::nvvm_suld_1d_i32_zero:
3883   case Intrinsic::nvvm_suld_1d_v2i32_zero:
3884   case Intrinsic::nvvm_suld_1d_v4i32_zero:
3885   case Intrinsic::nvvm_suld_1d_array_i32_zero:
3886   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3887   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3888   case Intrinsic::nvvm_suld_2d_i32_zero:
3889   case Intrinsic::nvvm_suld_2d_v2i32_zero:
3890   case Intrinsic::nvvm_suld_2d_v4i32_zero:
3891   case Intrinsic::nvvm_suld_2d_array_i32_zero:
3892   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3893   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3894   case Intrinsic::nvvm_suld_3d_i32_zero:
3895   case Intrinsic::nvvm_suld_3d_v2i32_zero:
3896   case Intrinsic::nvvm_suld_3d_v4i32_zero:
3897     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3898     Info.memVT = MVT::i32;
3899     Info.ptrVal = nullptr;
3900     Info.offset = 0;
3901     Info.flags = MachineMemOperand::MOLoad;
3902     Info.align = 16;
3903     return true;
3904 
3905   case Intrinsic::nvvm_suld_1d_i64_clamp:
3906   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3907   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3908   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3909   case Intrinsic::nvvm_suld_2d_i64_clamp:
3910   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3911   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3912   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3913   case Intrinsic::nvvm_suld_3d_i64_clamp:
3914   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3915   case Intrinsic::nvvm_suld_1d_i64_trap:
3916   case Intrinsic::nvvm_suld_1d_v2i64_trap:
3917   case Intrinsic::nvvm_suld_1d_array_i64_trap:
3918   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3919   case Intrinsic::nvvm_suld_2d_i64_trap:
3920   case Intrinsic::nvvm_suld_2d_v2i64_trap:
3921   case Intrinsic::nvvm_suld_2d_array_i64_trap:
3922   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3923   case Intrinsic::nvvm_suld_3d_i64_trap:
3924   case Intrinsic::nvvm_suld_3d_v2i64_trap:
3925   case Intrinsic::nvvm_suld_1d_i64_zero:
3926   case Intrinsic::nvvm_suld_1d_v2i64_zero:
3927   case Intrinsic::nvvm_suld_1d_array_i64_zero:
3928   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3929   case Intrinsic::nvvm_suld_2d_i64_zero:
3930   case Intrinsic::nvvm_suld_2d_v2i64_zero:
3931   case Intrinsic::nvvm_suld_2d_array_i64_zero:
3932   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3933   case Intrinsic::nvvm_suld_3d_i64_zero:
3934   case Intrinsic::nvvm_suld_3d_v2i64_zero:
3935     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3936     Info.memVT = MVT::i64;
3937     Info.ptrVal = nullptr;
3938     Info.offset = 0;
3939     Info.flags = MachineMemOperand::MOLoad;
3940     Info.align = 16;
3941     return true;
3942   }
3943   return false;
3944 }
3945 
3946 /// isLegalAddressingMode - Return true if the addressing mode represented
3947 /// by AM is legal for this target, for a load/store of the specified type.
3948 /// Used to guide target specific optimizations, like loop strength reduction
3949 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3950 /// (CodeGenPrepare.cpp)
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS,Instruction * I) const3951 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3952                                                 const AddrMode &AM, Type *Ty,
3953                                                 unsigned AS, Instruction *I) const {
3954   // AddrMode - This represents an addressing mode of:
3955   //    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3956   //
3957   // The legal address modes are
3958   // - [avar]
3959   // - [areg]
3960   // - [areg+immoff]
3961   // - [immAddr]
3962 
3963   if (AM.BaseGV) {
3964     return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3965   }
3966 
3967   switch (AM.Scale) {
3968   case 0: // "r", "r+i" or "i" is allowed
3969     break;
3970   case 1:
3971     if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3972       return false;
3973     // Otherwise we have r+i.
3974     break;
3975   default:
3976     // No scale > 1 is allowed
3977     return false;
3978   }
3979   return true;
3980 }
3981 
3982 //===----------------------------------------------------------------------===//
3983 //                         NVPTX Inline Assembly Support
3984 //===----------------------------------------------------------------------===//
3985 
3986 /// getConstraintType - Given a constraint letter, return the type of
3987 /// constraint it is for this target.
3988 NVPTXTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const3989 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3990   if (Constraint.size() == 1) {
3991     switch (Constraint[0]) {
3992     default:
3993       break;
3994     case 'b':
3995     case 'r':
3996     case 'h':
3997     case 'c':
3998     case 'l':
3999     case 'f':
4000     case 'd':
4001     case '0':
4002     case 'N':
4003       return C_RegisterClass;
4004     }
4005   }
4006   return TargetLowering::getConstraintType(Constraint);
4007 }
4008 
4009 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const4010 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4011                                                   StringRef Constraint,
4012                                                   MVT VT) const {
4013   if (Constraint.size() == 1) {
4014     switch (Constraint[0]) {
4015     case 'b':
4016       return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
4017     case 'c':
4018       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
4019     case 'h':
4020       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
4021     case 'r':
4022       return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
4023     case 'l':
4024     case 'N':
4025       return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
4026     case 'f':
4027       return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
4028     case 'd':
4029       return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
4030     }
4031   }
4032   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4033 }
4034 
4035 //===----------------------------------------------------------------------===//
4036 //                         NVPTX DAG Combining
4037 //===----------------------------------------------------------------------===//
4038 
allowFMA(MachineFunction & MF,CodeGenOpt::Level OptLevel) const4039 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
4040                                    CodeGenOpt::Level OptLevel) const {
4041   // Always honor command-line argument
4042   if (FMAContractLevelOpt.getNumOccurrences() > 0)
4043     return FMAContractLevelOpt > 0;
4044 
4045   // Do not contract if we're not optimizing the code.
4046   if (OptLevel == 0)
4047     return false;
4048 
4049   // Honor TargetOptions flags that explicitly say fusion is okay.
4050   if (MF.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast)
4051     return true;
4052 
4053   return allowUnsafeFPMath(MF);
4054 }
4055 
allowUnsafeFPMath(MachineFunction & MF) const4056 bool NVPTXTargetLowering::allowUnsafeFPMath(MachineFunction &MF) const {
4057   // Honor TargetOptions flags that explicitly say unsafe math is okay.
4058   if (MF.getTarget().Options.UnsafeFPMath)
4059     return true;
4060 
4061   // Allow unsafe math if unsafe-fp-math attribute explicitly says so.
4062   const Function &F = MF.getFunction();
4063   if (F.hasFnAttribute("unsafe-fp-math")) {
4064     Attribute Attr = F.getFnAttribute("unsafe-fp-math");
4065     StringRef Val = Attr.getValueAsString();
4066     if (Val == "true")
4067       return true;
4068   }
4069 
4070   return false;
4071 }
4072 
4073 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4074 /// operands N0 and N1.  This is a helper for PerformADDCombine that is
4075 /// called with the default operands, and if that fails, with commuted
4076 /// operands.
PerformADDCombineWithOperands(SDNode * N,SDValue N0,SDValue N1,TargetLowering::DAGCombinerInfo & DCI,const NVPTXSubtarget & Subtarget,CodeGenOpt::Level OptLevel)4077 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4078                                            TargetLowering::DAGCombinerInfo &DCI,
4079                                              const NVPTXSubtarget &Subtarget,
4080                                              CodeGenOpt::Level OptLevel) {
4081   SelectionDAG  &DAG = DCI.DAG;
4082   // Skip non-integer, non-scalar case
4083   EVT VT=N0.getValueType();
4084   if (VT.isVector())
4085     return SDValue();
4086 
4087   // fold (add (mul a, b), c) -> (mad a, b, c)
4088   //
4089   if (N0.getOpcode() == ISD::MUL) {
4090     assert (VT.isInteger());
4091     // For integer:
4092     // Since integer multiply-add costs the same as integer multiply
4093     // but is more costly than integer add, do the fusion only when
4094     // the mul is only used in the add.
4095     if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
4096         !N0.getNode()->hasOneUse())
4097       return SDValue();
4098 
4099     // Do the folding
4100     return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
4101                        N0.getOperand(0), N0.getOperand(1), N1);
4102   }
4103   else if (N0.getOpcode() == ISD::FMUL) {
4104     if (VT == MVT::f32 || VT == MVT::f64) {
4105       const auto *TLI = static_cast<const NVPTXTargetLowering *>(
4106           &DAG.getTargetLoweringInfo());
4107       if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
4108         return SDValue();
4109 
4110       // For floating point:
4111       // Do the fusion only when the mul has less than 5 uses and all
4112       // are add.
4113       // The heuristic is that if a use is not an add, then that use
4114       // cannot be fused into fma, therefore mul is still needed anyway.
4115       // If there are more than 4 uses, even if they are all add, fusing
4116       // them will increase register pressue.
4117       //
4118       int numUses = 0;
4119       int nonAddCount = 0;
4120       for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4121            UE = N0.getNode()->use_end();
4122            UI != UE; ++UI) {
4123         numUses++;
4124         SDNode *User = *UI;
4125         if (User->getOpcode() != ISD::FADD)
4126           ++nonAddCount;
4127       }
4128       if (numUses >= 5)
4129         return SDValue();
4130       if (nonAddCount) {
4131         int orderNo = N->getIROrder();
4132         int orderNo2 = N0.getNode()->getIROrder();
4133         // simple heuristics here for considering potential register
4134         // pressure, the logics here is that the differnce are used
4135         // to measure the distance between def and use, the longer distance
4136         // more likely cause register pressure.
4137         if (orderNo - orderNo2 < 500)
4138           return SDValue();
4139 
4140         // Now, check if at least one of the FMUL's operands is live beyond the node N,
4141         // which guarantees that the FMA will not increase register pressure at node N.
4142         bool opIsLive = false;
4143         const SDNode *left = N0.getOperand(0).getNode();
4144         const SDNode *right = N0.getOperand(1).getNode();
4145 
4146         if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
4147           opIsLive = true;
4148 
4149         if (!opIsLive)
4150           for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
4151             SDNode *User = *UI;
4152             int orderNo3 = User->getIROrder();
4153             if (orderNo3 > orderNo) {
4154               opIsLive = true;
4155               break;
4156             }
4157           }
4158 
4159         if (!opIsLive)
4160           for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
4161             SDNode *User = *UI;
4162             int orderNo3 = User->getIROrder();
4163             if (orderNo3 > orderNo) {
4164               opIsLive = true;
4165               break;
4166             }
4167           }
4168 
4169         if (!opIsLive)
4170           return SDValue();
4171       }
4172 
4173       return DAG.getNode(ISD::FMA, SDLoc(N), VT,
4174                          N0.getOperand(0), N0.getOperand(1), N1);
4175     }
4176   }
4177 
4178   return SDValue();
4179 }
4180 
4181 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4182 ///
PerformADDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const NVPTXSubtarget & Subtarget,CodeGenOpt::Level OptLevel)4183 static SDValue PerformADDCombine(SDNode *N,
4184                                  TargetLowering::DAGCombinerInfo &DCI,
4185                                  const NVPTXSubtarget &Subtarget,
4186                                  CodeGenOpt::Level OptLevel) {
4187   SDValue N0 = N->getOperand(0);
4188   SDValue N1 = N->getOperand(1);
4189 
4190   // First try with the default operand order.
4191   if (SDValue Result =
4192           PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel))
4193     return Result;
4194 
4195   // If that didn't work, try again with the operands commuted.
4196   return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
4197 }
4198 
PerformANDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI)4199 static SDValue PerformANDCombine(SDNode *N,
4200                                  TargetLowering::DAGCombinerInfo &DCI) {
4201   // The type legalizer turns a vector load of i8 values into a zextload to i16
4202   // registers, optionally ANY_EXTENDs it (if target type is integer),
4203   // and ANDs off the high 8 bits. Since we turn this load into a
4204   // target-specific DAG node, the DAG combiner fails to eliminate these AND
4205   // nodes. Do that here.
4206   SDValue Val = N->getOperand(0);
4207   SDValue Mask = N->getOperand(1);
4208 
4209   if (isa<ConstantSDNode>(Val)) {
4210     std::swap(Val, Mask);
4211   }
4212 
4213   SDValue AExt;
4214   // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4215   if (Val.getOpcode() == ISD::ANY_EXTEND) {
4216     AExt = Val;
4217     Val = Val->getOperand(0);
4218   }
4219 
4220   if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4221     Val = Val->getOperand(0);
4222   }
4223 
4224   if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4225       Val->getOpcode() == NVPTXISD::LoadV4) {
4226     ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
4227     if (!MaskCnst) {
4228       // Not an AND with a constant
4229       return SDValue();
4230     }
4231 
4232     uint64_t MaskVal = MaskCnst->getZExtValue();
4233     if (MaskVal != 0xff) {
4234       // Not an AND that chops off top 8 bits
4235       return SDValue();
4236     }
4237 
4238     MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4239     if (!Mem) {
4240       // Not a MemSDNode?!?
4241       return SDValue();
4242     }
4243 
4244     EVT MemVT = Mem->getMemoryVT();
4245     if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4246       // We only handle the i8 case
4247       return SDValue();
4248     }
4249 
4250     unsigned ExtType =
4251       cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4252         getZExtValue();
4253     if (ExtType == ISD::SEXTLOAD) {
4254       // If for some reason the load is a sextload, the and is needed to zero
4255       // out the high 8 bits
4256       return SDValue();
4257     }
4258 
4259     bool AddTo = false;
4260     if (AExt.getNode() != nullptr) {
4261       // Re-insert the ext as a zext.
4262       Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4263                             AExt.getValueType(), Val);
4264       AddTo = true;
4265     }
4266 
4267     // If we get here, the AND is unnecessary.  Just replace it with the load
4268     DCI.CombineTo(N, Val, AddTo);
4269   }
4270 
4271   return SDValue();
4272 }
4273 
PerformREMCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,CodeGenOpt::Level OptLevel)4274 static SDValue PerformREMCombine(SDNode *N,
4275                                  TargetLowering::DAGCombinerInfo &DCI,
4276                                  CodeGenOpt::Level OptLevel) {
4277   assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4278 
4279   // Don't do anything at less than -O2.
4280   if (OptLevel < CodeGenOpt::Default)
4281     return SDValue();
4282 
4283   SelectionDAG &DAG = DCI.DAG;
4284   SDLoc DL(N);
4285   EVT VT = N->getValueType(0);
4286   bool IsSigned = N->getOpcode() == ISD::SREM;
4287   unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
4288 
4289   const SDValue &Num = N->getOperand(0);
4290   const SDValue &Den = N->getOperand(1);
4291 
4292   for (const SDNode *U : Num->uses()) {
4293     if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4294         U->getOperand(1) == Den) {
4295       // Num % Den -> Num - (Num / Den) * Den
4296       return DAG.getNode(ISD::SUB, DL, VT, Num,
4297                          DAG.getNode(ISD::MUL, DL, VT,
4298                                      DAG.getNode(DivOpc, DL, VT, Num, Den),
4299                                      Den));
4300     }
4301   }
4302   return SDValue();
4303 }
4304 
4305 enum OperandSignedness {
4306   Signed = 0,
4307   Unsigned,
4308   Unknown
4309 };
4310 
4311 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4312 /// that can be demoted to \p OptSize bits without loss of information. The
4313 /// signedness of the operand, if determinable, is placed in \p S.
IsMulWideOperandDemotable(SDValue Op,unsigned OptSize,OperandSignedness & S)4314 static bool IsMulWideOperandDemotable(SDValue Op,
4315                                       unsigned OptSize,
4316                                       OperandSignedness &S) {
4317   S = Unknown;
4318 
4319   if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4320       Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4321     EVT OrigVT = Op.getOperand(0).getValueType();
4322     if (OrigVT.getSizeInBits() <= OptSize) {
4323       S = Signed;
4324       return true;
4325     }
4326   } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4327     EVT OrigVT = Op.getOperand(0).getValueType();
4328     if (OrigVT.getSizeInBits() <= OptSize) {
4329       S = Unsigned;
4330       return true;
4331     }
4332   }
4333 
4334   return false;
4335 }
4336 
4337 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4338 /// be demoted to \p OptSize bits without loss of information. If the operands
4339 /// contain a constant, it should appear as the RHS operand. The signedness of
4340 /// the operands is placed in \p IsSigned.
AreMulWideOperandsDemotable(SDValue LHS,SDValue RHS,unsigned OptSize,bool & IsSigned)4341 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4342                                         unsigned OptSize,
4343                                         bool &IsSigned) {
4344   OperandSignedness LHSSign;
4345 
4346   // The LHS operand must be a demotable op
4347   if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4348     return false;
4349 
4350   // We should have been able to determine the signedness from the LHS
4351   if (LHSSign == Unknown)
4352     return false;
4353 
4354   IsSigned = (LHSSign == Signed);
4355 
4356   // The RHS can be a demotable op or a constant
4357   if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4358     const APInt &Val = CI->getAPIntValue();
4359     if (LHSSign == Unsigned) {
4360       return Val.isIntN(OptSize);
4361     } else {
4362       return Val.isSignedIntN(OptSize);
4363     }
4364   } else {
4365     OperandSignedness RHSSign;
4366     if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4367       return false;
4368 
4369     return LHSSign == RHSSign;
4370   }
4371 }
4372 
4373 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4374 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4375 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4376 /// amount.
TryMULWIDECombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI)4377 static SDValue TryMULWIDECombine(SDNode *N,
4378                                  TargetLowering::DAGCombinerInfo &DCI) {
4379   EVT MulType = N->getValueType(0);
4380   if (MulType != MVT::i32 && MulType != MVT::i64) {
4381     return SDValue();
4382   }
4383 
4384   SDLoc DL(N);
4385   unsigned OptSize = MulType.getSizeInBits() >> 1;
4386   SDValue LHS = N->getOperand(0);
4387   SDValue RHS = N->getOperand(1);
4388 
4389   // Canonicalize the multiply so the constant (if any) is on the right
4390   if (N->getOpcode() == ISD::MUL) {
4391     if (isa<ConstantSDNode>(LHS)) {
4392       std::swap(LHS, RHS);
4393     }
4394   }
4395 
4396   // If we have a SHL, determine the actual multiply amount
4397   if (N->getOpcode() == ISD::SHL) {
4398     ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4399     if (!ShlRHS) {
4400       return SDValue();
4401     }
4402 
4403     APInt ShiftAmt = ShlRHS->getAPIntValue();
4404     unsigned BitWidth = MulType.getSizeInBits();
4405     if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4406       APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4407       RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4408     } else {
4409       return SDValue();
4410     }
4411   }
4412 
4413   bool Signed;
4414   // Verify that our operands are demotable
4415   if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4416     return SDValue();
4417   }
4418 
4419   EVT DemotedVT;
4420   if (MulType == MVT::i32) {
4421     DemotedVT = MVT::i16;
4422   } else {
4423     DemotedVT = MVT::i32;
4424   }
4425 
4426   // Truncate the operands to the correct size. Note that these are just for
4427   // type consistency and will (likely) be eliminated in later phases.
4428   SDValue TruncLHS =
4429     DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4430   SDValue TruncRHS =
4431     DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4432 
4433   unsigned Opc;
4434   if (Signed) {
4435     Opc = NVPTXISD::MUL_WIDE_SIGNED;
4436   } else {
4437     Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4438   }
4439 
4440   return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4441 }
4442 
4443 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
PerformMULCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,CodeGenOpt::Level OptLevel)4444 static SDValue PerformMULCombine(SDNode *N,
4445                                  TargetLowering::DAGCombinerInfo &DCI,
4446                                  CodeGenOpt::Level OptLevel) {
4447   if (OptLevel > 0) {
4448     // Try mul.wide combining at OptLevel > 0
4449     if (SDValue Ret = TryMULWIDECombine(N, DCI))
4450       return Ret;
4451   }
4452 
4453   return SDValue();
4454 }
4455 
4456 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
PerformSHLCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,CodeGenOpt::Level OptLevel)4457 static SDValue PerformSHLCombine(SDNode *N,
4458                                  TargetLowering::DAGCombinerInfo &DCI,
4459                                  CodeGenOpt::Level OptLevel) {
4460   if (OptLevel > 0) {
4461     // Try mul.wide combining at OptLevel > 0
4462     if (SDValue Ret = TryMULWIDECombine(N, DCI))
4463       return Ret;
4464   }
4465 
4466   return SDValue();
4467 }
4468 
PerformSETCCCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI)4469 static SDValue PerformSETCCCombine(SDNode *N,
4470                                    TargetLowering::DAGCombinerInfo &DCI) {
4471   EVT CCType = N->getValueType(0);
4472   SDValue A = N->getOperand(0);
4473   SDValue B = N->getOperand(1);
4474 
4475   if (CCType != MVT::v2i1 || A.getValueType() != MVT::v2f16)
4476     return SDValue();
4477 
4478   SDLoc DL(N);
4479   // setp.f16x2 returns two scalar predicates, which we need to
4480   // convert back to v2i1. The returned result will be scalarized by
4481   // the legalizer, but the comparison will remain a single vector
4482   // instruction.
4483   SDValue CCNode = DCI.DAG.getNode(NVPTXISD::SETP_F16X2, DL,
4484                                    DCI.DAG.getVTList(MVT::i1, MVT::i1),
4485                                    {A, B, N->getOperand(2)});
4486   return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0),
4487                          CCNode.getValue(1));
4488 }
4489 
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const4490 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4491                                                DAGCombinerInfo &DCI) const {
4492   CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4493   switch (N->getOpcode()) {
4494     default: break;
4495     case ISD::ADD:
4496     case ISD::FADD:
4497       return PerformADDCombine(N, DCI, STI, OptLevel);
4498     case ISD::MUL:
4499       return PerformMULCombine(N, DCI, OptLevel);
4500     case ISD::SHL:
4501       return PerformSHLCombine(N, DCI, OptLevel);
4502     case ISD::AND:
4503       return PerformANDCombine(N, DCI);
4504     case ISD::UREM:
4505     case ISD::SREM:
4506       return PerformREMCombine(N, DCI, OptLevel);
4507     case ISD::SETCC:
4508       return PerformSETCCCombine(N, DCI);
4509   }
4510   return SDValue();
4511 }
4512 
4513 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
ReplaceLoadVector(SDNode * N,SelectionDAG & DAG,SmallVectorImpl<SDValue> & Results)4514 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4515                               SmallVectorImpl<SDValue> &Results) {
4516   EVT ResVT = N->getValueType(0);
4517   SDLoc DL(N);
4518 
4519   assert(ResVT.isVector() && "Vector load must have vector type");
4520 
4521   // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4522   // legal.  We can (and should) split that into 2 loads of <2 x double> here
4523   // but I'm leaving that as a TODO for now.
4524   assert(ResVT.isSimple() && "Can only handle simple types");
4525   switch (ResVT.getSimpleVT().SimpleTy) {
4526   default:
4527     return;
4528   case MVT::v2i8:
4529   case MVT::v2i16:
4530   case MVT::v2i32:
4531   case MVT::v2i64:
4532   case MVT::v2f16:
4533   case MVT::v2f32:
4534   case MVT::v2f64:
4535   case MVT::v4i8:
4536   case MVT::v4i16:
4537   case MVT::v4i32:
4538   case MVT::v4f16:
4539   case MVT::v4f32:
4540   case MVT::v8f16: // <4 x f16x2>
4541     // This is a "native" vector type
4542     break;
4543   }
4544 
4545   LoadSDNode *LD = cast<LoadSDNode>(N);
4546 
4547   unsigned Align = LD->getAlignment();
4548   auto &TD = DAG.getDataLayout();
4549   unsigned PrefAlign =
4550       TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4551   if (Align < PrefAlign) {
4552     // This load is not sufficiently aligned, so bail out and let this vector
4553     // load be scalarized.  Note that we may still be able to emit smaller
4554     // vector loads.  For example, if we are loading a <4 x float> with an
4555     // alignment of 8, this check will fail but the legalizer will try again
4556     // with 2 x <2 x float>, which will succeed with an alignment of 8.
4557     return;
4558   }
4559 
4560   EVT EltVT = ResVT.getVectorElementType();
4561   unsigned NumElts = ResVT.getVectorNumElements();
4562 
4563   // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4564   // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
4565   // loaded type to i16 and propagate the "real" type as the memory type.
4566   bool NeedTrunc = false;
4567   if (EltVT.getSizeInBits() < 16) {
4568     EltVT = MVT::i16;
4569     NeedTrunc = true;
4570   }
4571 
4572   unsigned Opcode = 0;
4573   SDVTList LdResVTs;
4574   bool LoadF16x2 = false;
4575 
4576   switch (NumElts) {
4577   default:
4578     return;
4579   case 2:
4580     Opcode = NVPTXISD::LoadV2;
4581     LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4582     break;
4583   case 4: {
4584     Opcode = NVPTXISD::LoadV4;
4585     EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4586     LdResVTs = DAG.getVTList(ListVTs);
4587     break;
4588   }
4589   case 8: {
4590     // v8f16 is a special case. PTX doesn't have ld.v8.f16
4591     // instruction. Instead, we split the vector into v2f16 chunks and
4592     // load them with ld.v4.b32.
4593     assert(EltVT == MVT::f16 && "Unsupported v8 vector type.");
4594     LoadF16x2 = true;
4595     Opcode = NVPTXISD::LoadV4;
4596     EVT ListVTs[] = {MVT::v2f16, MVT::v2f16, MVT::v2f16, MVT::v2f16,
4597                      MVT::Other};
4598     LdResVTs = DAG.getVTList(ListVTs);
4599     break;
4600   }
4601   }
4602 
4603   // Copy regular operands
4604   SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4605 
4606   // The select routine does not have access to the LoadSDNode instance, so
4607   // pass along the extension information
4608   OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4609 
4610   SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4611                                           LD->getMemoryVT(),
4612                                           LD->getMemOperand());
4613 
4614   SmallVector<SDValue, 8> ScalarRes;
4615   if (LoadF16x2) {
4616     // Split v2f16 subvectors back into individual elements.
4617     NumElts /= 2;
4618     for (unsigned i = 0; i < NumElts; ++i) {
4619       SDValue SubVector = NewLD.getValue(i);
4620       SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector,
4621                                DAG.getIntPtrConstant(0, DL));
4622       SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector,
4623                                DAG.getIntPtrConstant(1, DL));
4624       ScalarRes.push_back(E0);
4625       ScalarRes.push_back(E1);
4626     }
4627   } else {
4628     for (unsigned i = 0; i < NumElts; ++i) {
4629       SDValue Res = NewLD.getValue(i);
4630       if (NeedTrunc)
4631         Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4632       ScalarRes.push_back(Res);
4633     }
4634   }
4635 
4636   SDValue LoadChain = NewLD.getValue(NumElts);
4637 
4638   SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes);
4639 
4640   Results.push_back(BuildVec);
4641   Results.push_back(LoadChain);
4642 }
4643 
ReplaceINTRINSIC_W_CHAIN(SDNode * N,SelectionDAG & DAG,SmallVectorImpl<SDValue> & Results)4644 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4645                                      SmallVectorImpl<SDValue> &Results) {
4646   SDValue Chain = N->getOperand(0);
4647   SDValue Intrin = N->getOperand(1);
4648   SDLoc DL(N);
4649 
4650   // Get the intrinsic ID
4651   unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4652   switch (IntrinNo) {
4653   default:
4654     return;
4655   case Intrinsic::nvvm_ldg_global_i:
4656   case Intrinsic::nvvm_ldg_global_f:
4657   case Intrinsic::nvvm_ldg_global_p:
4658   case Intrinsic::nvvm_ldu_global_i:
4659   case Intrinsic::nvvm_ldu_global_f:
4660   case Intrinsic::nvvm_ldu_global_p: {
4661     EVT ResVT = N->getValueType(0);
4662 
4663     if (ResVT.isVector()) {
4664       // Vector LDG/LDU
4665 
4666       unsigned NumElts = ResVT.getVectorNumElements();
4667       EVT EltVT = ResVT.getVectorElementType();
4668 
4669       // Since LDU/LDG are target nodes, we cannot rely on DAG type
4670       // legalization.
4671       // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
4672       // loaded type to i16 and propagate the "real" type as the memory type.
4673       bool NeedTrunc = false;
4674       if (EltVT.getSizeInBits() < 16) {
4675         EltVT = MVT::i16;
4676         NeedTrunc = true;
4677       }
4678 
4679       unsigned Opcode = 0;
4680       SDVTList LdResVTs;
4681 
4682       switch (NumElts) {
4683       default:
4684         return;
4685       case 2:
4686         switch (IntrinNo) {
4687         default:
4688           return;
4689         case Intrinsic::nvvm_ldg_global_i:
4690         case Intrinsic::nvvm_ldg_global_f:
4691         case Intrinsic::nvvm_ldg_global_p:
4692           Opcode = NVPTXISD::LDGV2;
4693           break;
4694         case Intrinsic::nvvm_ldu_global_i:
4695         case Intrinsic::nvvm_ldu_global_f:
4696         case Intrinsic::nvvm_ldu_global_p:
4697           Opcode = NVPTXISD::LDUV2;
4698           break;
4699         }
4700         LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4701         break;
4702       case 4: {
4703         switch (IntrinNo) {
4704         default:
4705           return;
4706         case Intrinsic::nvvm_ldg_global_i:
4707         case Intrinsic::nvvm_ldg_global_f:
4708         case Intrinsic::nvvm_ldg_global_p:
4709           Opcode = NVPTXISD::LDGV4;
4710           break;
4711         case Intrinsic::nvvm_ldu_global_i:
4712         case Intrinsic::nvvm_ldu_global_f:
4713         case Intrinsic::nvvm_ldu_global_p:
4714           Opcode = NVPTXISD::LDUV4;
4715           break;
4716         }
4717         EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4718         LdResVTs = DAG.getVTList(ListVTs);
4719         break;
4720       }
4721       }
4722 
4723       SmallVector<SDValue, 8> OtherOps;
4724 
4725       // Copy regular operands
4726 
4727       OtherOps.push_back(Chain); // Chain
4728                                  // Skip operand 1 (intrinsic ID)
4729       // Others
4730       OtherOps.append(N->op_begin() + 2, N->op_end());
4731 
4732       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4733 
4734       SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4735                                               MemSD->getMemoryVT(),
4736                                               MemSD->getMemOperand());
4737 
4738       SmallVector<SDValue, 4> ScalarRes;
4739 
4740       for (unsigned i = 0; i < NumElts; ++i) {
4741         SDValue Res = NewLD.getValue(i);
4742         if (NeedTrunc)
4743           Res =
4744               DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4745         ScalarRes.push_back(Res);
4746       }
4747 
4748       SDValue LoadChain = NewLD.getValue(NumElts);
4749 
4750       SDValue BuildVec =
4751           DAG.getBuildVector(ResVT, DL, ScalarRes);
4752 
4753       Results.push_back(BuildVec);
4754       Results.push_back(LoadChain);
4755     } else {
4756       // i8 LDG/LDU
4757       assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4758              "Custom handling of non-i8 ldu/ldg?");
4759 
4760       // Just copy all operands as-is
4761       SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4762 
4763       // Force output to i16
4764       SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4765 
4766       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4767 
4768       // We make sure the memory type is i8, which will be used during isel
4769       // to select the proper instruction.
4770       SDValue NewLD =
4771           DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4772                                   MVT::i8, MemSD->getMemOperand());
4773 
4774       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4775                                     NewLD.getValue(0)));
4776       Results.push_back(NewLD.getValue(1));
4777     }
4778   }
4779   }
4780 }
4781 
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const4782 void NVPTXTargetLowering::ReplaceNodeResults(
4783     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4784   switch (N->getOpcode()) {
4785   default:
4786     report_fatal_error("Unhandled custom legalization");
4787   case ISD::LOAD:
4788     ReplaceLoadVector(N, DAG, Results);
4789     return;
4790   case ISD::INTRINSIC_W_CHAIN:
4791     ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4792     return;
4793   }
4794 }
4795 
4796 // Pin NVPTXTargetObjectFile's vtables to this file.
~NVPTXTargetObjectFile()4797 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {}
4798 
SelectSectionForGlobal(const GlobalObject * GO,SectionKind Kind,const TargetMachine & TM) const4799 MCSection *NVPTXTargetObjectFile::SelectSectionForGlobal(
4800     const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
4801   return getDataSection();
4802 }
4803