1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; Test that we generate an unaligned vector store for a spill when a function 4; has an alloca. Also, make sure the addressing mode for unaligned store does 5; is not a base+offset with a non-zero offset that is not a multiple of 128. 6 7; CHECK: vmemu(r{{[0-9]+}}+#0) 8 9%s.0 = type { [5 x [4 x i8]], i32, i32, i32, i32 } 10 11; Function Attrs: nounwind 12define i32 @f0(i8* nocapture readonly %a0, i8* nocapture %a1, i8* nocapture readonly %a2, i8* nocapture readonly %a3, i32 %a4, i32 %a5, i32 %a6, %s.0* nocapture readonly %a7) #0 { 13b0: 14 %v0 = alloca i8, i32 %a4, align 128 15 br i1 undef, label %b1, label %b5 16 17b1: ; preds = %b0 18 %v1 = icmp sgt i32 %a5, 2 19 br label %b2 20 21b2: ; preds = %b3, %b2, %b1 22 br i1 undef, label %b3, label %b2 23 24b3: ; preds = %b2 25 call void @f1(i8* undef, i8* undef, i8* nonnull %v0, i32 %a4, i32 %a5, %s.0* %a7) 26 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B() #2 27 br i1 %v1, label %b4, label %b2 28 29b4: ; preds = %b4, %b3 30 %v3 = phi <32 x i32> [ %v5, %b4 ], [ undef, %b3 ] 31 %v4 = tail call <32 x i32> @llvm.hexagon.V6.vsubhnq.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3) #2 32 %v5 = tail call <32 x i32> @llvm.hexagon.V6.vavguh.128B(<32 x i32> %v3, <32 x i32> %v2) #2 33 br label %b4 34 35b5: ; preds = %b0 36 ret i32 0 37} 38 39; Function Attrs: nounwind 40declare void @f1(i8* nocapture readonly, i8* nocapture readonly, i8* nocapture, i32, i32, %s.0* nocapture readonly) #0 41 42; Function Attrs: nounwind readnone 43declare <32 x i32> @llvm.hexagon.V6.vd0.128B() #1 44 45; Function Attrs: nounwind readnone 46declare <32 x i32> @llvm.hexagon.V6.vsubhnq.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1 47 48; Function Attrs: nounwind readnone 49declare <32 x i32> @llvm.hexagon.V6.vavguh.128B(<32 x i32>, <32 x i32>) #1 50 51attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } 52attributes #1 = { nounwind readnone } 53attributes #2 = { nounwind } 54