1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 20 namespace llvm { 21 22 class GCNTargetMachine; 23 class LLVMContext; 24 class GCNSubtarget; 25 26 /// This class provides the information for the target register banks. 27 class AMDGPULegalizerInfo : public LegalizerInfo { 28 const GCNSubtarget &ST; 29 30 public: 31 AMDGPULegalizerInfo(const GCNSubtarget &ST, 32 const GCNTargetMachine &TM); 33 34 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, 35 MachineIRBuilder &MIRBuilder, 36 GISelChangeObserver &Observer) const override; 37 38 Register getSegmentAperture(unsigned AddrSpace, 39 MachineRegisterInfo &MRI, 40 MachineIRBuilder &MIRBuilder) const; 41 42 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 43 MachineIRBuilder &MIRBuilder) const; 44 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 45 MachineIRBuilder &MIRBuilder) const; 46 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 47 MachineIRBuilder &MIRBuilder) const; 48 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 49 MachineIRBuilder &MIRBuilder) const; 50 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 51 MachineIRBuilder &MIRBuilder, bool Signed) const; 52 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI, 53 MachineIRBuilder &MIRBuilder) const; 54 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 55 MachineIRBuilder &MIRBuilder) const; 56 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 57 MachineIRBuilder &MIRBuilder) const; 58 59 Register getLiveInRegister(MachineRegisterInfo &MRI, 60 Register Reg, LLT Ty) const; 61 62 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 63 const ArgDescriptor *Arg) const; 64 bool legalizePreloadedArgIntrin( 65 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 66 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 67 68 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 69 MachineIRBuilder &B) const; 70 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 71 MachineIRBuilder &MIRBuilder) const override; 72 73 }; 74 } // End llvm namespace. 75 #endif 76