1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Helpers 11//===----------------------------------------------------------------------===// 12 13class getSubRegs<int size> { 14 list<SubRegIndex> ret2 = [sub0, sub1]; 15 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 16 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 17 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 18 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 19 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 20 sub4, sub5, sub6, sub7, 21 sub8, sub9, sub10, sub11, 22 sub12, sub13, sub14, sub15]; 23 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 24 sub4, sub5, sub6, sub7, 25 sub8, sub9, sub10, sub11, 26 sub12, sub13, sub14, sub15, 27 sub16, sub17, sub18, sub19, 28 sub20, sub21, sub22, sub23, 29 sub24, sub25, sub26, sub27, 30 sub28, sub29, sub30, sub31]; 31 32 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 33 !if(!eq(size, 3), ret3, 34 !if(!eq(size, 4), ret4, 35 !if(!eq(size, 5), ret5, 36 !if(!eq(size, 8), ret8, 37 !if(!eq(size, 16), ret16, ret32)))))); 38} 39 40let Namespace = "AMDGPU" in { 41defset list<RegAltNameIndex> AllRegAltNameIndices = { 42 def Reg32 : RegAltNameIndex; 43 def Reg64 : RegAltNameIndex; 44 def Reg96 : RegAltNameIndex; 45 def Reg128 : RegAltNameIndex; 46 def Reg160 : RegAltNameIndex; 47 def Reg256 : RegAltNameIndex; 48 def Reg512 : RegAltNameIndex; 49 def Reg1024 : RegAltNameIndex; 50} 51} 52 53//===----------------------------------------------------------------------===// 54// Declarations that describe the SI registers 55//===----------------------------------------------------------------------===// 56class SIReg <string n, bits<16> regIdx = 0, string prefix = "", 57 int regNo = !cast<int>(regIdx)> : 58 Register<n, !if(!eq(prefix, ""), 59 [ n, n, n, n, n, n, n, n ], 60 [ prefix # regNo, 61 prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]", 62 prefix # "[" # regNo # ":" # !and(!add(regNo, 2), 255) # "]", 63 prefix # "[" # regNo # ":" # !and(!add(regNo, 3), 255) # "]", 64 prefix # "[" # regNo # ":" # !and(!add(regNo, 4), 255) # "]", 65 prefix # "[" # regNo # ":" # !and(!add(regNo, 7), 255) # "]", 66 prefix # "[" # regNo # ":" # !and(!add(regNo, 15), 255) # "]", 67 prefix # "[" # regNo # ":" # !and(!add(regNo, 31), 255) # "]", 68 ])>, 69 DwarfRegNum<[!cast<int>(HWEncoding)]> { 70 let Namespace = "AMDGPU"; 71 let RegAltNameIndices = AllRegAltNameIndices; 72 73 // This is the not yet the complete register encoding. An additional 74 // bit is set for VGPRs. 75 let HWEncoding = regIdx; 76} 77 78class SIRegisterWithSubRegs<string n, list<Register> subregs> : 79 RegisterWithSubRegs<n, subregs> { 80 let RegAltNameIndices = AllRegAltNameIndices; 81 let AltNames = [ n, n, n, n, n, n, n, n ]; 82} 83 84// Special Registers 85def VCC_LO : SIReg<"vcc_lo", 106>; 86def VCC_HI : SIReg<"vcc_hi", 107>; 87 88// Pseudo-registers: Used as placeholders during isel and immediately 89// replaced, never seeing the verifier. 90def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 91def FP_REG : SIReg<"fp", 0>; 92def SP_REG : SIReg<"sp", 0>; 93def SCRATCH_WAVE_OFFSET_REG : SIReg<"scratch_wave_offset", 0>; 94 95// VCC for 64-bit instructions 96def VCC : SIRegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>, 97 DwarfRegAlias<VCC_LO> { 98 let Namespace = "AMDGPU"; 99 let SubRegIndices = [sub0, sub1]; 100 let HWEncoding = 106; 101} 102 103def EXEC_LO : SIReg<"exec_lo", 126>; 104def EXEC_HI : SIReg<"exec_hi", 127>; 105 106def EXEC : SIRegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, 107 DwarfRegAlias<EXEC_LO> { 108 let Namespace = "AMDGPU"; 109 let SubRegIndices = [sub0, sub1]; 110 let HWEncoding = 126; 111} 112 113// 32-bit real registers, for MC only. 114// May be used with both 32-bit and 64-bit operands. 115def SRC_VCCZ : SIReg<"src_vccz", 251>; 116def SRC_EXECZ : SIReg<"src_execz", 252>; 117def SRC_SCC : SIReg<"src_scc", 253>; 118 119// 1-bit pseudo register, for codegen only. 120// Should never be emitted. 121def SCC : SIReg<"scc">; 122 123def M0 : SIReg <"m0", 124>; 124def SGPR_NULL : SIReg<"null", 125>; 125 126def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>; 127def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>; 128def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>; 129def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>; 130def SRC_POPS_EXITING_WAVE_ID : SIReg<"src_pops_exiting_wave_id", 239>; 131 132def LDS_DIRECT : SIReg <"src_lds_direct", 254>; 133 134def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>; 135def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>; 136 137def XNACK_MASK : SIRegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>, 138 DwarfRegAlias<XNACK_MASK_LO> { 139 let Namespace = "AMDGPU"; 140 let SubRegIndices = [sub0, sub1]; 141 let HWEncoding = 104; 142} 143 144// Trap handler registers 145def TBA_LO : SIReg<"tba_lo", 108>; 146def TBA_HI : SIReg<"tba_hi", 109>; 147 148def TBA : SIRegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>, 149 DwarfRegAlias<TBA_LO> { 150 let Namespace = "AMDGPU"; 151 let SubRegIndices = [sub0, sub1]; 152 let HWEncoding = 108; 153} 154 155def TMA_LO : SIReg<"tma_lo", 110>; 156def TMA_HI : SIReg<"tma_hi", 111>; 157 158def TMA : SIRegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>, 159 DwarfRegAlias<TMA_LO> { 160 let Namespace = "AMDGPU"; 161 let SubRegIndices = [sub0, sub1]; 162 let HWEncoding = 110; 163} 164 165foreach Index = 0-15 in { 166 def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>; 167 def TTMP#Index#_gfx9_gfx10 : SIReg<"ttmp"#Index, !add(108, Index)>; 168 def TTMP#Index : SIReg<"ttmp"#Index, 0>; 169} 170 171multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { 172 def _ci : SIReg<n, ci_e>; 173 def _vi : SIReg<n, vi_e>; 174 def "" : SIReg<n, 0>; 175} 176 177class FlatReg <Register lo, Register hi, bits<16> encoding> : 178 SIRegisterWithSubRegs<"flat_scratch", [lo, hi]>, 179 DwarfRegAlias<lo> { 180 let Namespace = "AMDGPU"; 181 let SubRegIndices = [sub0, sub1]; 182 let HWEncoding = encoding; 183} 184 185defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 186defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 187 188def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 189def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 190def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 191 192// SGPR registers 193foreach Index = 0-105 in { 194 def SGPR#Index : SIReg <"SGPR"#Index, Index, "s">; 195} 196 197// VGPR registers 198foreach Index = 0-255 in { 199 def VGPR#Index : SIReg <"VGPR"#Index, Index, "v"> { 200 let HWEncoding{8} = 1; 201 } 202} 203 204// AccVGPR registers 205foreach Index = 0-255 in { 206 def AGPR#Index : SIReg <"AGPR"#Index, Index, "a"> { 207 let HWEncoding{8} = 1; 208 } 209} 210 211//===----------------------------------------------------------------------===// 212// Groupings using register classes and tuples 213//===----------------------------------------------------------------------===// 214 215def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 216 let CopyCost = -1; 217 let isAllocatable = 0; 218} 219 220def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> { 221 let CopyCost = 1; 222 let isAllocatable = 0; 223} 224 225// TODO: Do we need to set DwarfRegAlias on register tuples? 226 227// SGPR 32-bit registers 228def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 229 (add (sequence "SGPR%u", 0, 105)), Reg32> { 230 // Give all SGPR classes higher priority than VGPR classes, because 231 // we want to spill SGPRs to VGPRs. 232 let AllocationPriority = 9; 233} 234 235// SGPR 64-bit registers 236def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret, 237 [(add (decimate SGPR_32, 2)), 238 (add (decimate (shl SGPR_32, 1), 2))]>; 239 240// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 241def SGPR_96Regs : RegisterTuples<getSubRegs<3>.ret, 242 [(add (decimate SGPR_32, 3)), 243 (add (decimate (shl SGPR_32, 1), 3)), 244 (add (decimate (shl SGPR_32, 2), 3))]>; 245 246// SGPR 128-bit registers 247def SGPR_128Regs : RegisterTuples<getSubRegs<4>.ret, 248 [(add (decimate SGPR_32, 4)), 249 (add (decimate (shl SGPR_32, 1), 4)), 250 (add (decimate (shl SGPR_32, 2), 4)), 251 (add (decimate (shl SGPR_32, 3), 4))]>; 252 253// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 254def SGPR_160Regs : RegisterTuples<getSubRegs<5>.ret, 255 [(add (decimate SGPR_32, 4)), 256 (add (decimate (shl SGPR_32, 1), 4)), 257 (add (decimate (shl SGPR_32, 2), 4)), 258 (add (decimate (shl SGPR_32, 3), 4)), 259 (add (decimate (shl SGPR_32, 4), 4))]>; 260 261// SGPR 256-bit registers 262def SGPR_256Regs : RegisterTuples<getSubRegs<8>.ret, 263 [(add (decimate SGPR_32, 4)), 264 (add (decimate (shl SGPR_32, 1), 4)), 265 (add (decimate (shl SGPR_32, 2), 4)), 266 (add (decimate (shl SGPR_32, 3), 4)), 267 (add (decimate (shl SGPR_32, 4), 4)), 268 (add (decimate (shl SGPR_32, 5), 4)), 269 (add (decimate (shl SGPR_32, 6), 4)), 270 (add (decimate (shl SGPR_32, 7), 4))]>; 271 272// SGPR 512-bit registers 273def SGPR_512Regs : RegisterTuples<getSubRegs<16>.ret, 274 [(add (decimate SGPR_32, 4)), 275 (add (decimate (shl SGPR_32, 1), 4)), 276 (add (decimate (shl SGPR_32, 2), 4)), 277 (add (decimate (shl SGPR_32, 3), 4)), 278 (add (decimate (shl SGPR_32, 4), 4)), 279 (add (decimate (shl SGPR_32, 5), 4)), 280 (add (decimate (shl SGPR_32, 6), 4)), 281 (add (decimate (shl SGPR_32, 7), 4)), 282 (add (decimate (shl SGPR_32, 8), 4)), 283 (add (decimate (shl SGPR_32, 9), 4)), 284 (add (decimate (shl SGPR_32, 10), 4)), 285 (add (decimate (shl SGPR_32, 11), 4)), 286 (add (decimate (shl SGPR_32, 12), 4)), 287 (add (decimate (shl SGPR_32, 13), 4)), 288 (add (decimate (shl SGPR_32, 14), 4)), 289 (add (decimate (shl SGPR_32, 15), 4))]>; 290 291// SGPR 1024-bit registers 292def SGPR_1024Regs : RegisterTuples<getSubRegs<32>.ret, 293 [(add (decimate SGPR_32, 4)), 294 (add (decimate (shl SGPR_32, 1), 4)), 295 (add (decimate (shl SGPR_32, 2), 4)), 296 (add (decimate (shl SGPR_32, 3), 4)), 297 (add (decimate (shl SGPR_32, 4), 4)), 298 (add (decimate (shl SGPR_32, 5), 4)), 299 (add (decimate (shl SGPR_32, 6), 4)), 300 (add (decimate (shl SGPR_32, 7), 4)), 301 (add (decimate (shl SGPR_32, 8), 4)), 302 (add (decimate (shl SGPR_32, 9), 4)), 303 (add (decimate (shl SGPR_32, 10), 4)), 304 (add (decimate (shl SGPR_32, 11), 4)), 305 (add (decimate (shl SGPR_32, 12), 4)), 306 (add (decimate (shl SGPR_32, 13), 4)), 307 (add (decimate (shl SGPR_32, 14), 4)), 308 (add (decimate (shl SGPR_32, 15), 4)), 309 (add (decimate (shl SGPR_32, 16), 4)), 310 (add (decimate (shl SGPR_32, 17), 4)), 311 (add (decimate (shl SGPR_32, 18), 4)), 312 (add (decimate (shl SGPR_32, 19), 4)), 313 (add (decimate (shl SGPR_32, 20), 4)), 314 (add (decimate (shl SGPR_32, 21), 4)), 315 (add (decimate (shl SGPR_32, 22), 4)), 316 (add (decimate (shl SGPR_32, 23), 4)), 317 (add (decimate (shl SGPR_32, 24), 4)), 318 (add (decimate (shl SGPR_32, 25), 4)), 319 (add (decimate (shl SGPR_32, 26), 4)), 320 (add (decimate (shl SGPR_32, 27), 4)), 321 (add (decimate (shl SGPR_32, 28), 4)), 322 (add (decimate (shl SGPR_32, 29), 4)), 323 (add (decimate (shl SGPR_32, 30), 4)), 324 (add (decimate (shl SGPR_32, 31), 4))]>; 325 326// Trap handler TMP 32-bit registers 327def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 328 (add (sequence "TTMP%u", 0, 15))> { 329 let isAllocatable = 0; 330} 331 332// Trap handler TMP 64-bit registers 333def TTMP_64Regs : RegisterTuples<getSubRegs<2>.ret, 334 [(add (decimate TTMP_32, 2)), 335 (add (decimate (shl TTMP_32, 1), 2))]>; 336 337// Trap handler TMP 128-bit registers 338def TTMP_128Regs : RegisterTuples<getSubRegs<4>.ret, 339 [(add (decimate TTMP_32, 4)), 340 (add (decimate (shl TTMP_32, 1), 4)), 341 (add (decimate (shl TTMP_32, 2), 4)), 342 (add (decimate (shl TTMP_32, 3), 4))]>; 343 344def TTMP_256Regs : RegisterTuples<getSubRegs<8>.ret, 345 [(add (decimate TTMP_32, 4)), 346 (add (decimate (shl TTMP_32, 1), 4)), 347 (add (decimate (shl TTMP_32, 2), 4)), 348 (add (decimate (shl TTMP_32, 3), 4)), 349 (add (decimate (shl TTMP_32, 4), 4)), 350 (add (decimate (shl TTMP_32, 5), 4)), 351 (add (decimate (shl TTMP_32, 6), 4)), 352 (add (decimate (shl TTMP_32, 7), 4))]>; 353 354def TTMP_512Regs : RegisterTuples<getSubRegs<16>.ret, 355 [(add (decimate TTMP_32, 4)), 356 (add (decimate (shl TTMP_32, 1), 4)), 357 (add (decimate (shl TTMP_32, 2), 4)), 358 (add (decimate (shl TTMP_32, 3), 4)), 359 (add (decimate (shl TTMP_32, 4), 4)), 360 (add (decimate (shl TTMP_32, 5), 4)), 361 (add (decimate (shl TTMP_32, 6), 4)), 362 (add (decimate (shl TTMP_32, 7), 4)), 363 (add (decimate (shl TTMP_32, 8), 4)), 364 (add (decimate (shl TTMP_32, 9), 4)), 365 (add (decimate (shl TTMP_32, 10), 4)), 366 (add (decimate (shl TTMP_32, 11), 4)), 367 (add (decimate (shl TTMP_32, 12), 4)), 368 (add (decimate (shl TTMP_32, 13), 4)), 369 (add (decimate (shl TTMP_32, 14), 4)), 370 (add (decimate (shl TTMP_32, 15), 4))]>; 371 372class TmpRegTuplesBase<int index, int size, 373 list<Register> subRegs, 374 list<SubRegIndex> indices = getSubRegs<size>.ret, 375 int index1 = !add(index, !add(size, -1)), 376 string name = "ttmp["#index#":"#index1#"]"> : 377 SIRegisterWithSubRegs<name, subRegs> { 378 let HWEncoding = subRegs[0].HWEncoding; 379 let SubRegIndices = indices; 380} 381 382class TmpRegTuples<string tgt, 383 int size, 384 int index0, 385 int index1 = !add(index0, 1), 386 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 387 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 388 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 389 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 390 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 391 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 392 Register r0 = !cast<Register>("TTMP"#index0#tgt), 393 Register r1 = !cast<Register>("TTMP"#index1#tgt), 394 Register r2 = !cast<Register>("TTMP"#index2#tgt), 395 Register r3 = !cast<Register>("TTMP"#index3#tgt), 396 Register r4 = !cast<Register>("TTMP"#index4#tgt), 397 Register r5 = !cast<Register>("TTMP"#index5#tgt), 398 Register r6 = !cast<Register>("TTMP"#index6#tgt), 399 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 400 TmpRegTuplesBase<index0, size, 401 !if(!eq(size, 2), [r0, r1], 402 !if(!eq(size, 4), [r0, r1, r2, r3], 403 [r0, r1, r2, r3, r4, r5, r6, r7])), 404 getSubRegs<size>.ret>; 405 406foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 407 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 408 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 2, Index>; 409} 410 411foreach Index = {0, 4, 8, 12} in { 412 def TTMP#Index#_TTMP#!add(Index,1)# 413 _TTMP#!add(Index,2)# 414 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 415 def TTMP#Index#_TTMP#!add(Index,1)# 416 _TTMP#!add(Index,2)# 417 _TTMP#!add(Index,3)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 4, Index>; 418} 419 420foreach Index = {0, 4, 8} in { 421 def TTMP#Index#_TTMP#!add(Index,1)# 422 _TTMP#!add(Index,2)# 423 _TTMP#!add(Index,3)# 424 _TTMP#!add(Index,4)# 425 _TTMP#!add(Index,5)# 426 _TTMP#!add(Index,6)# 427 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 428 def TTMP#Index#_TTMP#!add(Index,1)# 429 _TTMP#!add(Index,2)# 430 _TTMP#!add(Index,3)# 431 _TTMP#!add(Index,4)# 432 _TTMP#!add(Index,5)# 433 _TTMP#!add(Index,6)# 434 _TTMP#!add(Index,7)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 8, Index>; 435} 436 437def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 438 TmpRegTuplesBase<0, 16, 439 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 440 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 441 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 442 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 443 444def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9_gfx10 : 445 TmpRegTuplesBase<0, 16, 446 [TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10, 447 TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10, 448 TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10, 449 TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>; 450 451// VGPR 32-bit registers 452// i16/f16 only on VI+ 453def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 454 (add (sequence "VGPR%u", 0, 255)), Reg32> { 455 let AllocationPriority = 1; 456 let Size = 32; 457} 458 459// VGPR 64-bit registers 460def VGPR_64 : RegisterTuples<getSubRegs<2>.ret, 461 [(add (trunc VGPR_32, 255)), 462 (add (shl VGPR_32, 1))]>; 463 464// VGPR 96-bit registers 465def VGPR_96 : RegisterTuples<getSubRegs<3>.ret, 466 [(add (trunc VGPR_32, 254)), 467 (add (shl VGPR_32, 1)), 468 (add (shl VGPR_32, 2))]>; 469 470// VGPR 128-bit registers 471def VGPR_128 : RegisterTuples<getSubRegs<4>.ret, 472 [(add (trunc VGPR_32, 253)), 473 (add (shl VGPR_32, 1)), 474 (add (shl VGPR_32, 2)), 475 (add (shl VGPR_32, 3))]>; 476 477// VGPR 160-bit registers 478def VGPR_160 : RegisterTuples<getSubRegs<5>.ret, 479 [(add (trunc VGPR_32, 252)), 480 (add (shl VGPR_32, 1)), 481 (add (shl VGPR_32, 2)), 482 (add (shl VGPR_32, 3)), 483 (add (shl VGPR_32, 4))]>; 484 485// VGPR 256-bit registers 486def VGPR_256 : RegisterTuples<getSubRegs<8>.ret, 487 [(add (trunc VGPR_32, 249)), 488 (add (shl VGPR_32, 1)), 489 (add (shl VGPR_32, 2)), 490 (add (shl VGPR_32, 3)), 491 (add (shl VGPR_32, 4)), 492 (add (shl VGPR_32, 5)), 493 (add (shl VGPR_32, 6)), 494 (add (shl VGPR_32, 7))]>; 495 496// VGPR 512-bit registers 497def VGPR_512 : RegisterTuples<getSubRegs<16>.ret, 498 [(add (trunc VGPR_32, 241)), 499 (add (shl VGPR_32, 1)), 500 (add (shl VGPR_32, 2)), 501 (add (shl VGPR_32, 3)), 502 (add (shl VGPR_32, 4)), 503 (add (shl VGPR_32, 5)), 504 (add (shl VGPR_32, 6)), 505 (add (shl VGPR_32, 7)), 506 (add (shl VGPR_32, 8)), 507 (add (shl VGPR_32, 9)), 508 (add (shl VGPR_32, 10)), 509 (add (shl VGPR_32, 11)), 510 (add (shl VGPR_32, 12)), 511 (add (shl VGPR_32, 13)), 512 (add (shl VGPR_32, 14)), 513 (add (shl VGPR_32, 15))]>; 514 515// VGPR 1024-bit registers 516def VGPR_1024 : RegisterTuples<getSubRegs<32>.ret, 517 [(add (trunc VGPR_32, 225)), 518 (add (shl VGPR_32, 1)), 519 (add (shl VGPR_32, 2)), 520 (add (shl VGPR_32, 3)), 521 (add (shl VGPR_32, 4)), 522 (add (shl VGPR_32, 5)), 523 (add (shl VGPR_32, 6)), 524 (add (shl VGPR_32, 7)), 525 (add (shl VGPR_32, 8)), 526 (add (shl VGPR_32, 9)), 527 (add (shl VGPR_32, 10)), 528 (add (shl VGPR_32, 11)), 529 (add (shl VGPR_32, 12)), 530 (add (shl VGPR_32, 13)), 531 (add (shl VGPR_32, 14)), 532 (add (shl VGPR_32, 15)), 533 (add (shl VGPR_32, 16)), 534 (add (shl VGPR_32, 17)), 535 (add (shl VGPR_32, 18)), 536 (add (shl VGPR_32, 19)), 537 (add (shl VGPR_32, 20)), 538 (add (shl VGPR_32, 21)), 539 (add (shl VGPR_32, 22)), 540 (add (shl VGPR_32, 23)), 541 (add (shl VGPR_32, 24)), 542 (add (shl VGPR_32, 25)), 543 (add (shl VGPR_32, 26)), 544 (add (shl VGPR_32, 27)), 545 (add (shl VGPR_32, 28)), 546 (add (shl VGPR_32, 29)), 547 (add (shl VGPR_32, 30)), 548 (add (shl VGPR_32, 31))]>; 549 550// AccVGPR 32-bit registers 551def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 552 (add (sequence "AGPR%u", 0, 255)), Reg32> { 553 let AllocationPriority = 1; 554 let Size = 32; 555} 556 557// AGPR 64-bit registers 558def AGPR_64 : RegisterTuples<getSubRegs<2>.ret, 559 [(add (trunc AGPR_32, 255)), 560 (add (shl AGPR_32, 1))]>; 561 562// AGPR 128-bit registers 563def AGPR_128 : RegisterTuples<getSubRegs<4>.ret, 564 [(add (trunc AGPR_32, 253)), 565 (add (shl AGPR_32, 1)), 566 (add (shl AGPR_32, 2)), 567 (add (shl AGPR_32, 3))]>; 568 569// AGPR 512-bit registers 570def AGPR_512 : RegisterTuples<getSubRegs<16>.ret, 571 [(add (trunc AGPR_32, 241)), 572 (add (shl AGPR_32, 1)), 573 (add (shl AGPR_32, 2)), 574 (add (shl AGPR_32, 3)), 575 (add (shl AGPR_32, 4)), 576 (add (shl AGPR_32, 5)), 577 (add (shl AGPR_32, 6)), 578 (add (shl AGPR_32, 7)), 579 (add (shl AGPR_32, 8)), 580 (add (shl AGPR_32, 9)), 581 (add (shl AGPR_32, 10)), 582 (add (shl AGPR_32, 11)), 583 (add (shl AGPR_32, 12)), 584 (add (shl AGPR_32, 13)), 585 (add (shl AGPR_32, 14)), 586 (add (shl AGPR_32, 15))]>; 587 588// AGPR 1024-bit registers 589def AGPR_1024 : RegisterTuples<getSubRegs<32>.ret, 590 [(add (trunc AGPR_32, 225)), 591 (add (shl AGPR_32, 1)), 592 (add (shl AGPR_32, 2)), 593 (add (shl AGPR_32, 3)), 594 (add (shl AGPR_32, 4)), 595 (add (shl AGPR_32, 5)), 596 (add (shl AGPR_32, 6)), 597 (add (shl AGPR_32, 7)), 598 (add (shl AGPR_32, 8)), 599 (add (shl AGPR_32, 9)), 600 (add (shl AGPR_32, 10)), 601 (add (shl AGPR_32, 11)), 602 (add (shl AGPR_32, 12)), 603 (add (shl AGPR_32, 13)), 604 (add (shl AGPR_32, 14)), 605 (add (shl AGPR_32, 15)), 606 (add (shl AGPR_32, 16)), 607 (add (shl AGPR_32, 17)), 608 (add (shl AGPR_32, 18)), 609 (add (shl AGPR_32, 19)), 610 (add (shl AGPR_32, 20)), 611 (add (shl AGPR_32, 21)), 612 (add (shl AGPR_32, 22)), 613 (add (shl AGPR_32, 23)), 614 (add (shl AGPR_32, 24)), 615 (add (shl AGPR_32, 25)), 616 (add (shl AGPR_32, 26)), 617 (add (shl AGPR_32, 27)), 618 (add (shl AGPR_32, 28)), 619 (add (shl AGPR_32, 29)), 620 (add (shl AGPR_32, 30)), 621 (add (shl AGPR_32, 31))]>; 622 623//===----------------------------------------------------------------------===// 624// Register classes used as source and destination 625//===----------------------------------------------------------------------===// 626 627def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 628 (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG), Reg32> { 629 let isAllocatable = 0; 630 let CopyCost = -1; 631} 632 633def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, 634 (add PRIVATE_RSRC_REG), Reg128> { 635 let isAllocatable = 0; 636 let CopyCost = -1; 637} 638 639def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 640 (add LDS_DIRECT), Reg32> { 641 let isAllocatable = 0; 642 let CopyCost = -1; 643} 644 645// Subset of SReg_32 without M0 for SMRD instructions and alike. 646// See comments in SIInstructions.td for more info. 647def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 648 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 649 SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT, 650 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID, 651 SRC_VCCZ, SRC_EXECZ, SRC_SCC), Reg32> { 652 let AllocationPriority = 10; 653} 654 655def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 656 (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS), Reg32> { 657 let AllocationPriority = 10; 658} 659 660def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 661 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI), Reg32> { 662 let AllocationPriority = 10; 663} 664 665// Register class for all scalar registers (SGPRs + Special Registers) 666def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 667 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI), Reg32> { 668 let AllocationPriority = 10; 669} 670 671def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 672 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS), 673 Reg32> { 674 let isAllocatable = 0; 675} 676 677def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, 678 (add SGPR_64Regs), Reg64> { 679 let CopyCost = 1; 680 let AllocationPriority = 11; 681} 682 683// CCR (call clobbered registers) SGPR 64-bit registers 684def CCR_SGPR_64 : RegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 685 (add (trunc SGPR_64, 16)), Reg64> { 686 let CopyCost = SGPR_64.CopyCost; 687 let AllocationPriority = SGPR_64.AllocationPriority; 688} 689 690def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, 691 (add TTMP_64Regs)> { 692 let isAllocatable = 0; 693} 694 695def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 696 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA), Reg64> { 697 let CopyCost = 1; 698 let AllocationPriority = 13; 699} 700 701def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 702 (add SReg_64_XEXEC, EXEC), Reg64> { 703 let CopyCost = 1; 704 let AllocationPriority = 13; 705} 706 707def SReg_1_XEXEC : RegisterClass<"AMDGPU", [i1], 32, 708 (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> { 709 let CopyCost = 1; 710 let isAllocatable = 0; 711} 712 713def SReg_1 : RegisterClass<"AMDGPU", [i1], 32, 714 (add SReg_1_XEXEC, EXEC, EXEC_LO)> { 715 let CopyCost = 1; 716 let isAllocatable = 0; 717} 718 719// Requires 2 s_mov_b64 to copy 720let CopyCost = 2 in { 721 722// There are no 3-component scalar instructions, but this is needed 723// for symmetry with VGPRs. 724def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, 725 (add SGPR_96Regs), Reg96> { 726 let AllocationPriority = 14; 727} 728 729def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, 730 (add SGPR_96), Reg96> { 731 let AllocationPriority = 14; 732} 733 734def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, 735 (add SGPR_128Regs), Reg128> { 736 let AllocationPriority = 15; 737} 738 739def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, 740 (add TTMP_128Regs)> { 741 let isAllocatable = 0; 742} 743 744def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 745 (add SGPR_128, TTMP_128), Reg128> { 746 let AllocationPriority = 15; 747} 748 749} // End CopyCost = 2 750 751// There are no 5-component scalar instructions, but this is needed 752// for symmetry with VGPRs. 753def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 754 (add SGPR_160Regs), Reg160> { 755 let AllocationPriority = 16; 756} 757 758def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 759 (add SGPR_160), Reg160> { 760 let AllocationPriority = 16; 761} 762 763def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs), 764 Reg256> { 765 let AllocationPriority = 17; 766} 767 768def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> { 769 let isAllocatable = 0; 770} 771 772def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, 773 (add SGPR_256, TTMP_256), Reg256> { 774 // Requires 4 s_mov_b64 to copy 775 let CopyCost = 4; 776 let AllocationPriority = 17; 777} 778 779def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 780 (add SGPR_512Regs), Reg512> { 781 let AllocationPriority = 18; 782} 783 784def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 785 (add TTMP_512Regs)> { 786 let isAllocatable = 0; 787} 788 789def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 790 (add SGPR_512, TTMP_512), Reg512> { 791 // Requires 8 s_mov_b64 to copy 792 let CopyCost = 8; 793 let AllocationPriority = 18; 794} 795 796def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 797 (add VGPR_32, LDS_DIRECT_CLASS), Reg32> { 798 let isAllocatable = 0; 799} 800 801def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 802 (add SGPR_1024Regs), Reg1024> { 803 let AllocationPriority = 19; 804} 805 806def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 807 (add SGPR_1024), Reg1024> { 808 let CopyCost = 16; 809 let AllocationPriority = 19; 810} 811 812// Register class for all vector registers (VGPRs + Interploation Registers) 813def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, 814 (add VGPR_64), Reg64> { 815 let Size = 64; 816 817 // Requires 2 v_mov_b32 to copy 818 let CopyCost = 2; 819 let AllocationPriority = 2; 820} 821 822def VReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, (add VGPR_96), Reg96> { 823 let Size = 96; 824 825 // Requires 3 v_mov_b32 to copy 826 let CopyCost = 3; 827 let AllocationPriority = 3; 828} 829 830def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 831 (add VGPR_128), Reg128> { 832 let Size = 128; 833 834 // Requires 4 v_mov_b32 to copy 835 let CopyCost = 4; 836 let AllocationPriority = 4; 837} 838 839def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 840 (add VGPR_160), Reg160> { 841 let Size = 160; 842 843 // Requires 5 v_mov_b32 to copy 844 let CopyCost = 5; 845 let AllocationPriority = 5; 846} 847 848def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, 849 (add VGPR_256), Reg256> { 850 let Size = 256; 851 let CopyCost = 8; 852 let AllocationPriority = 6; 853} 854 855def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 856 (add VGPR_512), Reg512> { 857 let Size = 512; 858 let CopyCost = 16; 859 let AllocationPriority = 7; 860} 861 862def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 863 (add VGPR_1024), Reg1024> { 864 let Size = 1024; 865 let CopyCost = 32; 866 let AllocationPriority = 8; 867} 868 869def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, 870 (add AGPR_64), Reg64> { 871 let Size = 64; 872 873 let CopyCost = 5; 874 let AllocationPriority = 2; 875} 876 877def AReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 878 (add AGPR_128), Reg128> { 879 let Size = 128; 880 881 // Requires 4 v_accvgpr_write and 4 v_accvgpr_read to copy + burn 1 vgpr 882 let CopyCost = 9; 883 let AllocationPriority = 4; 884} 885 886def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 887 (add AGPR_512), Reg512> { 888 let Size = 512; 889 let CopyCost = 33; 890 let AllocationPriority = 7; 891} 892 893def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 894 (add AGPR_1024), Reg1024> { 895 let Size = 1024; 896 let CopyCost = 65; 897 let AllocationPriority = 8; 898} 899 900def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32), Reg32> { 901 let Size = 32; 902} 903 904def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 905 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS), Reg32> { 906 let isAllocatable = 0; 907} 908 909def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64), 910 Reg64> { 911 let isAllocatable = 0; 912} 913 914def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 915 (add AGPR_32, VGPR_32), Reg32> { 916 let isAllocatable = 0; 917} 918 919def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32, 920 (add AReg_64, VReg_64), Reg64> { 921 let isAllocatable = 0; 922} 923 924//===----------------------------------------------------------------------===// 925// Register operands 926//===----------------------------------------------------------------------===// 927 928class RegImmMatcher<string name> : AsmOperandClass { 929 let Name = name; 930 let RenderMethod = "addRegOrImmOperands"; 931} 932 933multiclass SIRegOperand32 <string rc, string MatchName, string opType, 934 string rc_suffix = "_32"> { 935 let OperandNamespace = "AMDGPU" in { 936 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 937 let OperandType = opType#"_INT16"; 938 let ParserMatchClass = RegImmMatcher<MatchName#"B16">; 939 let DecoderMethod = "decodeOperand_VSrc16"; 940 } 941 942 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 943 let OperandType = opType#"_FP16"; 944 let ParserMatchClass = RegImmMatcher<MatchName#"F16">; 945 let DecoderMethod = "decodeOperand_" # rc # "_16"; 946 } 947 948 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 949 let OperandType = opType#"_INT32"; 950 let ParserMatchClass = RegImmMatcher<MatchName#"B32">; 951 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 952 } 953 954 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 955 let OperandType = opType#"_FP32"; 956 let ParserMatchClass = RegImmMatcher<MatchName#"F32">; 957 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 958 } 959 960 def _v2b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 961 let OperandType = opType#"_V2INT16"; 962 let ParserMatchClass = RegImmMatcher<MatchName#"V2B16">; 963 let DecoderMethod = "decodeOperand_VSrcV216"; 964 } 965 966 def _v2f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 967 let OperandType = opType#"_V2FP16"; 968 let ParserMatchClass = RegImmMatcher<MatchName#"V2F16">; 969 let DecoderMethod = "decodeOperand_VSrcV216"; 970 } 971 } 972} 973 974multiclass SIRegOperand <string rc, string MatchName, string opType> : 975 SIRegOperand32<rc, MatchName, opType> { 976 let OperandNamespace = "AMDGPU" in { 977 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> { 978 let OperandType = opType#"_INT64"; 979 let ParserMatchClass = RegImmMatcher<MatchName#"B64">; 980 } 981 982 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> { 983 let OperandType = opType#"_FP64"; 984 let ParserMatchClass = RegImmMatcher<MatchName#"F64">; 985 } 986 } 987} 988 989// FIXME: 64-bit sources can sometimes use 32-bit constants. 990multiclass RegImmOperand <string rc, string MatchName> 991 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">; 992 993multiclass RegInlineOperand <string rc, string MatchName> 994 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">; 995 996multiclass RegInlineOperand32 <string rc, string MatchName, 997 string rc_suffix = "_32"> 998 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 999 1000multiclass RegInlineOperandAC <string rc, string MatchName, 1001 string rc_suffix = "_32"> 1002 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix>; 1003 1004//===----------------------------------------------------------------------===// 1005// SSrc_* Operands with an SGPR or a 32-bit immediate 1006//===----------------------------------------------------------------------===// 1007 1008defm SSrc : RegImmOperand<"SReg", "SSrc">; 1009 1010def SSrcOrLds_b32 : RegisterOperand<SRegOrLds_32> { 1011 let OperandNamespace = "AMDGPU"; 1012 let OperandType = "OPERAND_REG_IMM_INT32"; 1013 let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">; 1014} 1015 1016//===----------------------------------------------------------------------===// 1017// SCSrc_* Operands with an SGPR or a inline constant 1018//===----------------------------------------------------------------------===// 1019 1020defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ; 1021 1022//===----------------------------------------------------------------------===// 1023// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 1024//===----------------------------------------------------------------------===// 1025 1026defm VSrc : RegImmOperand<"VS", "VSrc">; 1027 1028def VSrc_128 : RegisterOperand<VReg_128> { 1029 let DecoderMethod = "DecodeVS_128RegisterClass"; 1030} 1031 1032//===----------------------------------------------------------------------===// 1033// VSrc_* Operands with an VGPR 1034//===----------------------------------------------------------------------===// 1035 1036// This is for operands with the enum(9), VSrc encoding restriction, 1037// but only allows VGPRs. 1038def VRegSrc_32 : RegisterOperand<VGPR_32> { 1039 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; 1040 let DecoderMethod = "DecodeVS_32RegisterClass"; 1041} 1042 1043//===----------------------------------------------------------------------===// 1044// ASrc_* Operands with an AccVGPR 1045//===----------------------------------------------------------------------===// 1046 1047def ARegSrc_32 : RegisterOperand<AGPR_32> { 1048 let DecoderMethod = "DecodeAGPR_32RegisterClass"; 1049 let EncoderMethod = "getAVOperandEncoding"; 1050} 1051 1052//===----------------------------------------------------------------------===// 1053// VCSrc_* Operands with an SGPR, VGPR or an inline constant 1054//===----------------------------------------------------------------------===// 1055 1056defm VCSrc : RegInlineOperand<"VS", "VCSrc">; 1057 1058//===----------------------------------------------------------------------===// 1059// VISrc_* Operands with a VGPR or an inline constant 1060//===----------------------------------------------------------------------===// 1061 1062defm VISrc : RegInlineOperand32<"VGPR", "VISrc">; 1063 1064//===----------------------------------------------------------------------===// 1065// AVSrc_* Operands with an AGPR or VGPR 1066//===----------------------------------------------------------------------===// 1067 1068def AVSrc_32 : RegisterOperand<AV_32> { 1069 let DecoderMethod = "DecodeAV_32RegisterClass"; 1070 let EncoderMethod = "getAVOperandEncoding"; 1071} 1072 1073def AVSrc_64 : RegisterOperand<AV_64> { 1074 let DecoderMethod = "DecodeAV_64RegisterClass"; 1075 let EncoderMethod = "getAVOperandEncoding"; 1076} 1077 1078//===----------------------------------------------------------------------===// 1079// ACSrc_* Operands with an AGPR or an inline constant 1080//===----------------------------------------------------------------------===// 1081 1082defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; 1083defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; 1084defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; 1085defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; 1086