1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2013 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "output.h"
33 #include "insn-attr.h"
34 #include "flags.h"
35 #include "recog.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "optabs.h"
39 #include "diagnostic-core.h"
40 #include "c-family/c-pragma.h" /* ??? */
41 #include "tm_p.h"
42 #include "tm-constrs.h"
43 #include "ggc.h"
44 #include "target.h"
45 #include "target-def.h"
46 #include "df.h"
47
48 /* Classifies a h8300_src_operand or h8300_dst_operand.
49
50 H8OP_IMMEDIATE
51 A constant operand of some sort.
52
53 H8OP_REGISTER
54 An ordinary register.
55
56 H8OP_MEM_ABSOLUTE
57 A memory reference with a constant address.
58
59 H8OP_MEM_BASE
60 A memory reference with a register as its address.
61
62 H8OP_MEM_COMPLEX
63 Some other kind of memory reference. */
64 enum h8300_operand_class
65 {
66 H8OP_IMMEDIATE,
67 H8OP_REGISTER,
68 H8OP_MEM_ABSOLUTE,
69 H8OP_MEM_BASE,
70 H8OP_MEM_COMPLEX,
71 NUM_H8OPS
72 };
73
74 /* For a general two-operand instruction, element [X][Y] gives
75 the length of the opcode fields when the first operand has class
76 (X + 1) and the second has class Y. */
77 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
78
79 /* Forward declarations. */
80 static const char *byte_reg (rtx, int);
81 static int h8300_interrupt_function_p (tree);
82 static int h8300_saveall_function_p (tree);
83 static int h8300_monitor_function_p (tree);
84 static int h8300_os_task_function_p (tree);
85 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
86 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
87 static unsigned int compute_saved_regs (void);
88 static const char *cond_string (enum rtx_code);
89 static unsigned int h8300_asm_insn_count (const char *);
90 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
91 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
92 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
93 static void h8300_print_operand_address (FILE *, rtx);
94 static void h8300_print_operand (FILE *, rtx, int);
95 static bool h8300_print_operand_punct_valid_p (unsigned char code);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree);
98 #endif
99 static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
100 static int h8300_and_costs (rtx);
101 static int h8300_shift_costs (rtx);
102 static void h8300_push_pop (int, int, bool, bool);
103 static int h8300_stack_offset_p (rtx, int);
104 static int h8300_ldm_stm_regno (rtx, int, int, int);
105 static void h8300_reorg (void);
106 static unsigned int h8300_constant_length (rtx);
107 static unsigned int h8300_displacement_length (rtx, int);
108 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
109 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
110 static unsigned int h8300_unary_length (rtx);
111 static unsigned int h8300_short_immediate_length (rtx);
112 static unsigned int h8300_bitfield_length (rtx, rtx);
113 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
114 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
115 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
116 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
118
119 /* CPU_TYPE, says what cpu we're compiling for. */
120 int cpu_type;
121
122 /* True if a #pragma interrupt has been seen for the current function. */
123 static int pragma_interrupt;
124
125 /* True if a #pragma saveall has been seen for the current function. */
126 static int pragma_saveall;
127
128 static const char *const names_big[] =
129 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
130
131 static const char *const names_extended[] =
132 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
133
134 static const char *const names_upper_extended[] =
135 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
136
137 /* Points to one of the above. */
138 /* ??? The above could be put in an array indexed by CPU_TYPE. */
139 const char * const *h8_reg_names;
140
141 /* Various operations needed by the following, indexed by CPU_TYPE. */
142
143 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
144
145 /* Value of MOVE_RATIO. */
146 int h8300_move_ratio;
147
148 /* See below where shifts are handled for explanation of this enum. */
149
150 enum shift_alg
151 {
152 SHIFT_INLINE,
153 SHIFT_ROT_AND,
154 SHIFT_SPECIAL,
155 SHIFT_LOOP
156 };
157
158 /* Symbols of the various shifts which can be used as indices. */
159
160 enum shift_type
161 {
162 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
163 };
164
165 /* Macros to keep the shift algorithm tables small. */
166 #define INL SHIFT_INLINE
167 #define ROT SHIFT_ROT_AND
168 #define LOP SHIFT_LOOP
169 #define SPC SHIFT_SPECIAL
170
171 /* The shift algorithms for each machine, mode, shift type, and shift
172 count are defined below. The three tables below correspond to
173 QImode, HImode, and SImode, respectively. Each table is organized
174 by, in the order of indices, machine, shift type, and shift count. */
175
176 static enum shift_alg shift_alg_qi[3][3][8] = {
177 {
178 /* TARGET_H8300 */
179 /* 0 1 2 3 4 5 6 7 */
180 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
181 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
182 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
183 },
184 {
185 /* TARGET_H8300H */
186 /* 0 1 2 3 4 5 6 7 */
187 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
188 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
189 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
190 },
191 {
192 /* TARGET_H8300S */
193 /* 0 1 2 3 4 5 6 7 */
194 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
195 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
196 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
197 }
198 };
199
200 static enum shift_alg shift_alg_hi[3][3][16] = {
201 {
202 /* TARGET_H8300 */
203 /* 0 1 2 3 4 5 6 7 */
204 /* 8 9 10 11 12 13 14 15 */
205 { INL, INL, INL, INL, INL, INL, INL, SPC,
206 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
207 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
209 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
211 },
212 {
213 /* TARGET_H8300H */
214 /* 0 1 2 3 4 5 6 7 */
215 /* 8 9 10 11 12 13 14 15 */
216 { INL, INL, INL, INL, INL, INL, INL, SPC,
217 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
218 { INL, INL, INL, INL, INL, INL, INL, SPC,
219 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
220 { INL, INL, INL, INL, INL, INL, INL, SPC,
221 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
222 },
223 {
224 /* TARGET_H8300S */
225 /* 0 1 2 3 4 5 6 7 */
226 /* 8 9 10 11 12 13 14 15 */
227 { INL, INL, INL, INL, INL, INL, INL, INL,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
229 { INL, INL, INL, INL, INL, INL, INL, INL,
230 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
231 { INL, INL, INL, INL, INL, INL, INL, INL,
232 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
233 }
234 };
235
236 static enum shift_alg shift_alg_si[3][3][32] = {
237 {
238 /* TARGET_H8300 */
239 /* 0 1 2 3 4 5 6 7 */
240 /* 8 9 10 11 12 13 14 15 */
241 /* 16 17 18 19 20 21 22 23 */
242 /* 24 25 26 27 28 29 30 31 */
243 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
244 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
246 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
247 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
248 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
249 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
251 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
252 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
255 },
256 {
257 /* TARGET_H8300H */
258 /* 0 1 2 3 4 5 6 7 */
259 /* 8 9 10 11 12 13 14 15 */
260 /* 16 17 18 19 20 21 22 23 */
261 /* 24 25 26 27 28 29 30 31 */
262 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
263 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
264 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
265 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
266 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
268 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
270 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
272 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
274 },
275 {
276 /* TARGET_H8300S */
277 /* 0 1 2 3 4 5 6 7 */
278 /* 8 9 10 11 12 13 14 15 */
279 /* 16 17 18 19 20 21 22 23 */
280 /* 24 25 26 27 28 29 30 31 */
281 { INL, INL, INL, INL, INL, INL, INL, INL,
282 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
283 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
284 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
285 { INL, INL, INL, INL, INL, INL, INL, INL,
286 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
287 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
288 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
289 { INL, INL, INL, INL, INL, INL, INL, INL,
290 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
291 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
292 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
293 }
294 };
295
296 #undef INL
297 #undef ROT
298 #undef LOP
299 #undef SPC
300
301 enum h8_cpu
302 {
303 H8_300,
304 H8_300H,
305 H8_S
306 };
307
308 /* Initialize various cpu specific globals at start up. */
309
310 static void
h8300_option_override(void)311 h8300_option_override (void)
312 {
313 static const char *const h8_push_ops[2] = { "push" , "push.l" };
314 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
315 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
316
317 #ifndef OBJECT_FORMAT_ELF
318 if (TARGET_H8300SX)
319 {
320 error ("-msx is not supported in coff");
321 target_flags |= MASK_H8300S;
322 }
323 #endif
324
325 if (TARGET_H8300)
326 {
327 cpu_type = (int) CPU_H8300;
328 h8_reg_names = names_big;
329 }
330 else
331 {
332 /* For this we treat the H8/300H and H8S the same. */
333 cpu_type = (int) CPU_H8300H;
334 h8_reg_names = names_extended;
335 }
336 h8_push_op = h8_push_ops[cpu_type];
337 h8_pop_op = h8_pop_ops[cpu_type];
338 h8_mov_op = h8_mov_ops[cpu_type];
339
340 if (!TARGET_H8300S && TARGET_MAC)
341 {
342 error ("-ms2600 is used without -ms");
343 target_flags |= MASK_H8300S_1;
344 }
345
346 if (TARGET_H8300 && TARGET_NORMAL_MODE)
347 {
348 error ("-mn is used without -mh or -ms or -msx");
349 target_flags ^= MASK_NORMAL_MODE;
350 }
351
352 if (! TARGET_H8300S && TARGET_EXR)
353 {
354 error ("-mexr is used without -ms");
355 target_flags |= MASK_H8300S_1;
356 }
357
358 if (TARGET_H8300 && TARGET_INT32)
359 {
360 error ("-mint32 is not supported for H8300 and H8300L targets");
361 target_flags ^= MASK_INT32;
362 }
363
364 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
365 {
366 error ("-mexr is used without -ms or -msx");
367 target_flags |= MASK_H8300S_1;
368 }
369
370 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
371 {
372 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
373 - Option ignored!");
374 }
375
376 /* Some of the shifts are optimized for speed by default.
377 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
378 If optimizing for size, change shift_alg for those shift to
379 SHIFT_LOOP. */
380 if (optimize_size)
381 {
382 /* H8/300 */
383 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
384 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
385 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
386 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
387
388 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
389 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
390
391 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
392 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
393
394 /* H8/300H */
395 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
396 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
397
398 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
399 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
400
401 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
402 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
403 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
404 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
405
406 /* H8S */
407 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
408 }
409
410 /* Work out a value for MOVE_RATIO. */
411 if (!TARGET_H8300SX)
412 {
413 /* Memory-memory moves are quite expensive without the
414 h8sx instructions. */
415 h8300_move_ratio = 3;
416 }
417 else if (flag_omit_frame_pointer)
418 {
419 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
420 sometimes be as short as two individual memory-to-memory moves,
421 but since they use all the call-saved registers, it seems better
422 to allow up to three moves here. */
423 h8300_move_ratio = 4;
424 }
425 else if (optimize_size)
426 {
427 /* In this case we don't use movmd sequences since they tend
428 to be longer than calls to memcpy(). Memory-to-memory
429 moves are cheaper than for !TARGET_H8300SX, so it makes
430 sense to have a slightly higher threshold. */
431 h8300_move_ratio = 4;
432 }
433 else
434 {
435 /* We use movmd sequences for some moves since it can be quicker
436 than calling memcpy(). The sequences will need to save and
437 restore er6 though, so bump up the cost. */
438 h8300_move_ratio = 6;
439 }
440
441 /* This target defaults to strict volatile bitfields. */
442 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
443 flag_strict_volatile_bitfields = 1;
444 }
445
446 /* Return the byte register name for a register rtx X. B should be 0
447 if you want a lower byte register. B should be 1 if you want an
448 upper byte register. */
449
450 static const char *
byte_reg(rtx x,int b)451 byte_reg (rtx x, int b)
452 {
453 static const char *const names_small[] = {
454 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
455 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
456 };
457
458 gcc_assert (REG_P (x));
459
460 return names_small[REGNO (x) * 2 + b];
461 }
462
463 /* REGNO must be saved/restored across calls if this macro is true. */
464
465 #define WORD_REG_USED(regno) \
466 (regno < SP_REG \
467 /* No need to save registers if this function will not return. */ \
468 && ! TREE_THIS_VOLATILE (current_function_decl) \
469 && (h8300_saveall_function_p (current_function_decl) \
470 /* Save any call saved register that was used. */ \
471 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
472 /* Save the frame pointer if it was used. */ \
473 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
474 /* Save any register used in an interrupt handler. */ \
475 || (h8300_current_function_interrupt_function_p () \
476 && df_regs_ever_live_p (regno)) \
477 /* Save call clobbered registers in non-leaf interrupt \
478 handlers. */ \
479 || (h8300_current_function_interrupt_function_p () \
480 && call_used_regs[regno] \
481 && !crtl->is_leaf)))
482
483 /* We use this to wrap all emitted insns in the prologue. */
484 static rtx
F(rtx x,bool set_it)485 F (rtx x, bool set_it)
486 {
487 if (set_it)
488 RTX_FRAME_RELATED_P (x) = 1;
489 return x;
490 }
491
492 /* Mark all the subexpressions of the PARALLEL rtx PAR as
493 frame-related. Return PAR.
494
495 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
496 PARALLEL rtx other than the first if they do not have the
497 FRAME_RELATED flag set on them. */
498 static rtx
Fpa(rtx par)499 Fpa (rtx par)
500 {
501 int len = XVECLEN (par, 0);
502 int i;
503
504 for (i = 0; i < len; i++)
505 F (XVECEXP (par, 0, i), true);
506
507 return par;
508 }
509
510 /* Output assembly language to FILE for the operation OP with operand size
511 SIZE to adjust the stack pointer. */
512
513 static void
h8300_emit_stack_adjustment(int sign,HOST_WIDE_INT size,bool in_prologue)514 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
515 {
516 /* If the frame size is 0, we don't have anything to do. */
517 if (size == 0)
518 return;
519
520 /* H8/300 cannot add/subtract a large constant with a single
521 instruction. If a temporary register is available, load the
522 constant to it and then do the addition. */
523 if (TARGET_H8300
524 && size > 4
525 && !h8300_current_function_interrupt_function_p ()
526 && !(cfun->static_chain_decl != NULL && sign < 0))
527 {
528 rtx r3 = gen_rtx_REG (Pmode, 3);
529 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
530 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
531 stack_pointer_rtx, r3)), in_prologue);
532 }
533 else
534 {
535 /* The stack adjustment made here is further optimized by the
536 splitter. In case of H8/300, the splitter always splits the
537 addition emitted here to make the adjustment interrupt-safe.
538 FIXME: We don't always tag those, because we don't know what
539 the splitter will do. */
540 if (Pmode == HImode)
541 {
542 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
543 stack_pointer_rtx, GEN_INT (sign * size)));
544 if (size < 4)
545 F (x, in_prologue);
546 }
547 else
548 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
549 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
550 }
551 }
552
553 /* Round up frame size SIZE. */
554
555 static HOST_WIDE_INT
round_frame_size(HOST_WIDE_INT size)556 round_frame_size (HOST_WIDE_INT size)
557 {
558 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
559 & -STACK_BOUNDARY / BITS_PER_UNIT);
560 }
561
562 /* Compute which registers to push/pop.
563 Return a bit vector of registers. */
564
565 static unsigned int
compute_saved_regs(void)566 compute_saved_regs (void)
567 {
568 unsigned int saved_regs = 0;
569 int regno;
570
571 /* Construct a bit vector of registers to be pushed/popped. */
572 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
573 {
574 if (WORD_REG_USED (regno))
575 saved_regs |= 1 << regno;
576 }
577
578 /* Don't push/pop the frame pointer as it is treated separately. */
579 if (frame_pointer_needed)
580 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
581
582 return saved_regs;
583 }
584
585 /* Emit an insn to push register RN. */
586
587 static rtx
push(int rn)588 push (int rn)
589 {
590 rtx reg = gen_rtx_REG (word_mode, rn);
591 rtx x;
592
593 if (TARGET_H8300)
594 x = gen_push_h8300 (reg);
595 else if (!TARGET_NORMAL_MODE)
596 x = gen_push_h8300hs_advanced (reg);
597 else
598 x = gen_push_h8300hs_normal (reg);
599 x = F (emit_insn (x), true);
600 add_reg_note (x, REG_INC, stack_pointer_rtx);
601 return x;
602 }
603
604 /* Emit an insn to pop register RN. */
605
606 static rtx
pop(int rn)607 pop (int rn)
608 {
609 rtx reg = gen_rtx_REG (word_mode, rn);
610 rtx x;
611
612 if (TARGET_H8300)
613 x = gen_pop_h8300 (reg);
614 else if (!TARGET_NORMAL_MODE)
615 x = gen_pop_h8300hs_advanced (reg);
616 else
617 x = gen_pop_h8300hs_normal (reg);
618 x = emit_insn (x);
619 add_reg_note (x, REG_INC, stack_pointer_rtx);
620 return x;
621 }
622
623 /* Emit an instruction to push or pop NREGS consecutive registers
624 starting at register REGNO. POP_P selects a pop rather than a
625 push and RETURN_P is true if the instruction should return.
626
627 It must be possible to do the requested operation in a single
628 instruction. If NREGS == 1 && !RETURN_P, use a normal push
629 or pop insn. Otherwise emit a parallel of the form:
630
631 (parallel
632 [(return) ;; if RETURN_P
633 (save or restore REGNO)
634 (save or restore REGNO + 1)
635 ...
636 (save or restore REGNO + NREGS - 1)
637 (set sp (plus sp (const_int adjust)))] */
638
639 static void
h8300_push_pop(int regno,int nregs,bool pop_p,bool return_p)640 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
641 {
642 int i, j;
643 rtvec vec;
644 rtx sp, offset, x;
645
646 /* See whether we can use a simple push or pop. */
647 if (!return_p && nregs == 1)
648 {
649 if (pop_p)
650 pop (regno);
651 else
652 push (regno);
653 return;
654 }
655
656 /* We need one element for the return insn, if present, one for each
657 register, and one for stack adjustment. */
658 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
659 sp = stack_pointer_rtx;
660 i = 0;
661
662 /* Add the return instruction. */
663 if (return_p)
664 {
665 RTVEC_ELT (vec, i) = ret_rtx;
666 i++;
667 }
668
669 /* Add the register moves. */
670 for (j = 0; j < nregs; j++)
671 {
672 rtx lhs, rhs;
673
674 if (pop_p)
675 {
676 /* Register REGNO + NREGS - 1 is popped first. Before the
677 stack adjustment, its slot is at address @sp. */
678 lhs = gen_rtx_REG (SImode, regno + j);
679 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
680 (nregs - j - 1) * 4));
681 }
682 else
683 {
684 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
685 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
686 rhs = gen_rtx_REG (SImode, regno + j);
687 }
688 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
689 }
690
691 /* Add the stack adjustment. */
692 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
693 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
694 gen_rtx_PLUS (Pmode, sp, offset));
695
696 x = gen_rtx_PARALLEL (VOIDmode, vec);
697 if (!pop_p)
698 x = Fpa (x);
699
700 if (return_p)
701 emit_jump_insn (x);
702 else
703 emit_insn (x);
704 }
705
706 /* Return true if X has the value sp + OFFSET. */
707
708 static int
h8300_stack_offset_p(rtx x,int offset)709 h8300_stack_offset_p (rtx x, int offset)
710 {
711 if (offset == 0)
712 return x == stack_pointer_rtx;
713
714 return (GET_CODE (x) == PLUS
715 && XEXP (x, 0) == stack_pointer_rtx
716 && GET_CODE (XEXP (x, 1)) == CONST_INT
717 && INTVAL (XEXP (x, 1)) == offset);
718 }
719
720 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
721 something that may be an ldm or stm instruction. If it fits
722 the required template, return the register it loads or stores,
723 otherwise return -1.
724
725 LOAD_P is true if X should be a load, false if it should be a store.
726 NREGS is the number of registers that the whole instruction is expected
727 to load or store. INDEX is the index of the register that X should
728 load or store, relative to the lowest-numbered register. */
729
730 static int
h8300_ldm_stm_regno(rtx x,int load_p,int index,int nregs)731 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
732 {
733 int regindex, memindex, offset;
734
735 if (load_p)
736 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
737 else
738 memindex = 0, regindex = 1, offset = (index + 1) * -4;
739
740 if (GET_CODE (x) == SET
741 && GET_CODE (XEXP (x, regindex)) == REG
742 && GET_CODE (XEXP (x, memindex)) == MEM
743 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
744 return REGNO (XEXP (x, regindex));
745
746 return -1;
747 }
748
749 /* Return true if the elements of VEC starting at FIRST describe an
750 ldm or stm instruction (LOAD_P says which). */
751
752 int
h8300_ldm_stm_parallel(rtvec vec,int load_p,int first)753 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
754 {
755 rtx last;
756 int nregs, i, regno, adjust;
757
758 /* There must be a stack adjustment, a register move, and at least one
759 other operation (a return or another register move). */
760 if (GET_NUM_ELEM (vec) < 3)
761 return false;
762
763 /* Get the range of registers to be pushed or popped. */
764 nregs = GET_NUM_ELEM (vec) - first - 1;
765 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
766
767 /* Check that the call to h8300_ldm_stm_regno succeeded and
768 that we're only dealing with GPRs. */
769 if (regno < 0 || regno + nregs > 8)
770 return false;
771
772 /* 2-register h8s instructions must start with an even-numbered register.
773 3- and 4-register instructions must start with er0 or er4. */
774 if (!TARGET_H8300SX)
775 {
776 if ((regno & 1) != 0)
777 return false;
778 if (nregs > 2 && (regno & 3) != 0)
779 return false;
780 }
781
782 /* Check the other loads or stores. */
783 for (i = 1; i < nregs; i++)
784 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
785 != regno + i)
786 return false;
787
788 /* Check the stack adjustment. */
789 last = RTVEC_ELT (vec, first + nregs);
790 adjust = (load_p ? nregs : -nregs) * 4;
791 return (GET_CODE (last) == SET
792 && SET_DEST (last) == stack_pointer_rtx
793 && h8300_stack_offset_p (SET_SRC (last), adjust));
794 }
795
796 /* This is what the stack looks like after the prolog of
797 a function with a frame has been set up:
798
799 <args>
800 PC
801 FP <- fp
802 <locals>
803 <saved registers> <- sp
804
805 This is what the stack looks like after the prolog of
806 a function which doesn't have a frame:
807
808 <args>
809 PC
810 <locals>
811 <saved registers> <- sp
812 */
813
814 /* Generate RTL code for the function prologue. */
815
816 void
h8300_expand_prologue(void)817 h8300_expand_prologue (void)
818 {
819 int regno;
820 int saved_regs;
821 int n_regs;
822
823 /* If the current function has the OS_Task attribute set, then
824 we have a naked prologue. */
825 if (h8300_os_task_function_p (current_function_decl))
826 return;
827
828 if (h8300_monitor_function_p (current_function_decl))
829 /* The monitor function act as normal functions, which means it
830 can accept parameters and return values. In addition to this,
831 interrupts are masked in prologue and return with "rte" in epilogue. */
832 emit_insn (gen_monitor_prologue ());
833
834 if (frame_pointer_needed)
835 {
836 /* Push fp. */
837 push (HARD_FRAME_POINTER_REGNUM);
838 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
839 }
840
841 /* Push the rest of the registers in ascending order. */
842 saved_regs = compute_saved_regs ();
843 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
844 {
845 n_regs = 1;
846 if (saved_regs & (1 << regno))
847 {
848 if (TARGET_H8300S)
849 {
850 /* See how many registers we can push at the same time. */
851 if ((!TARGET_H8300SX || (regno & 3) == 0)
852 && ((saved_regs >> regno) & 0x0f) == 0x0f)
853 n_regs = 4;
854
855 else if ((!TARGET_H8300SX || (regno & 3) == 0)
856 && ((saved_regs >> regno) & 0x07) == 0x07)
857 n_regs = 3;
858
859 else if ((!TARGET_H8300SX || (regno & 1) == 0)
860 && ((saved_regs >> regno) & 0x03) == 0x03)
861 n_regs = 2;
862 }
863
864 h8300_push_pop (regno, n_regs, false, false);
865 }
866 }
867
868 /* Leave room for locals. */
869 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
870 }
871
872 /* Return nonzero if we can use "rts" for the function currently being
873 compiled. */
874
875 int
h8300_can_use_return_insn_p(void)876 h8300_can_use_return_insn_p (void)
877 {
878 return (reload_completed
879 && !frame_pointer_needed
880 && get_frame_size () == 0
881 && compute_saved_regs () == 0);
882 }
883
884 /* Generate RTL code for the function epilogue. */
885
886 void
h8300_expand_epilogue(void)887 h8300_expand_epilogue (void)
888 {
889 int regno;
890 int saved_regs;
891 int n_regs;
892 HOST_WIDE_INT frame_size;
893 bool returned_p;
894
895 if (h8300_os_task_function_p (current_function_decl))
896 /* OS_Task epilogues are nearly naked -- they just have an
897 rts instruction. */
898 return;
899
900 frame_size = round_frame_size (get_frame_size ());
901 returned_p = false;
902
903 /* Deallocate locals. */
904 h8300_emit_stack_adjustment (1, frame_size, false);
905
906 /* Pop the saved registers in descending order. */
907 saved_regs = compute_saved_regs ();
908 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
909 {
910 n_regs = 1;
911 if (saved_regs & (1 << regno))
912 {
913 if (TARGET_H8300S)
914 {
915 /* See how many registers we can pop at the same time. */
916 if ((TARGET_H8300SX || (regno & 3) == 3)
917 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
918 n_regs = 4;
919
920 else if ((TARGET_H8300SX || (regno & 3) == 2)
921 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
922 n_regs = 3;
923
924 else if ((TARGET_H8300SX || (regno & 1) == 1)
925 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
926 n_regs = 2;
927 }
928
929 /* See if this pop would be the last insn before the return.
930 If so, use rte/l or rts/l instead of pop or ldm.l. */
931 if (TARGET_H8300SX
932 && !frame_pointer_needed
933 && frame_size == 0
934 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
935 returned_p = true;
936
937 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
938 }
939 }
940
941 /* Pop frame pointer if we had one. */
942 if (frame_pointer_needed)
943 {
944 if (TARGET_H8300SX)
945 returned_p = true;
946 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
947 }
948
949 if (!returned_p)
950 emit_jump_insn (ret_rtx);
951 }
952
953 /* Return nonzero if the current function is an interrupt
954 function. */
955
956 int
h8300_current_function_interrupt_function_p(void)957 h8300_current_function_interrupt_function_p (void)
958 {
959 return (h8300_interrupt_function_p (current_function_decl));
960 }
961
962 int
h8300_current_function_monitor_function_p()963 h8300_current_function_monitor_function_p ()
964 {
965 return (h8300_monitor_function_p (current_function_decl));
966 }
967
968 /* Output assembly code for the start of the file. */
969
970 static void
h8300_file_start(void)971 h8300_file_start (void)
972 {
973 default_file_start ();
974
975 if (TARGET_H8300H)
976 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
977 else if (TARGET_H8300SX)
978 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
979 else if (TARGET_H8300S)
980 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
981 }
982
983 /* Output assembly language code for the end of file. */
984
985 static void
h8300_file_end(void)986 h8300_file_end (void)
987 {
988 fputs ("\t.end\n", asm_out_file);
989 }
990
991 /* Split an add of a small constant into two adds/subs insns.
992
993 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
994 instead of adds/subs. */
995
996 void
split_adds_subs(enum machine_mode mode,rtx * operands)997 split_adds_subs (enum machine_mode mode, rtx *operands)
998 {
999 HOST_WIDE_INT val = INTVAL (operands[1]);
1000 rtx reg = operands[0];
1001 HOST_WIDE_INT sign = 1;
1002 HOST_WIDE_INT amount;
1003 rtx (*gen_add) (rtx, rtx, rtx);
1004
1005 /* Force VAL to be positive so that we do not have to consider the
1006 sign. */
1007 if (val < 0)
1008 {
1009 val = -val;
1010 sign = -1;
1011 }
1012
1013 switch (mode)
1014 {
1015 case HImode:
1016 gen_add = gen_addhi3;
1017 break;
1018
1019 case SImode:
1020 gen_add = gen_addsi3;
1021 break;
1022
1023 default:
1024 gcc_unreachable ();
1025 }
1026
1027 /* Try different amounts in descending order. */
1028 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1029 amount > 0;
1030 amount /= 2)
1031 {
1032 for (; val >= amount; val -= amount)
1033 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1034 }
1035
1036 return;
1037 }
1038
1039 /* Handle machine specific pragmas for compatibility with existing
1040 compilers for the H8/300.
1041
1042 pragma saveall generates prologue/epilogue code which saves and
1043 restores all the registers on function entry.
1044
1045 pragma interrupt saves and restores all registers, and exits with
1046 an rte instruction rather than an rts. A pointer to a function
1047 with this attribute may be safely used in an interrupt vector. */
1048
1049 void
h8300_pr_interrupt(struct cpp_reader * pfile ATTRIBUTE_UNUSED)1050 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1051 {
1052 pragma_interrupt = 1;
1053 }
1054
1055 void
h8300_pr_saveall(struct cpp_reader * pfile ATTRIBUTE_UNUSED)1056 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1057 {
1058 pragma_saveall = 1;
1059 }
1060
1061 /* If the next function argument with MODE and TYPE is to be passed in
1062 a register, return a reg RTX for the hard register in which to pass
1063 the argument. CUM represents the state after the last argument.
1064 If the argument is to be pushed, NULL_RTX is returned.
1065
1066 On the H8/300 all normal args are pushed, unless -mquickcall in which
1067 case the first 3 arguments are passed in registers. */
1068
1069 static rtx
h8300_function_arg(cumulative_args_t cum_v,enum machine_mode mode,const_tree type,bool named)1070 h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
1071 const_tree type, bool named)
1072 {
1073 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1074
1075 static const char *const hand_list[] = {
1076 "__main",
1077 "__cmpsi2",
1078 "__divhi3",
1079 "__modhi3",
1080 "__udivhi3",
1081 "__umodhi3",
1082 "__divsi3",
1083 "__modsi3",
1084 "__udivsi3",
1085 "__umodsi3",
1086 "__mulhi3",
1087 "__mulsi3",
1088 "__reg_memcpy",
1089 "__reg_memset",
1090 "__ucmpsi2",
1091 0,
1092 };
1093
1094 rtx result = NULL_RTX;
1095 const char *fname;
1096 int regpass = 0;
1097
1098 /* Never pass unnamed arguments in registers. */
1099 if (!named)
1100 return NULL_RTX;
1101
1102 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1103 if (TARGET_QUICKCALL)
1104 regpass = 3;
1105
1106 /* If calling hand written assembler, use 4 regs of args. */
1107 if (cum->libcall)
1108 {
1109 const char * const *p;
1110
1111 fname = XSTR (cum->libcall, 0);
1112
1113 /* See if this libcall is one of the hand coded ones. */
1114 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1115 ;
1116
1117 if (*p)
1118 regpass = 4;
1119 }
1120
1121 if (regpass)
1122 {
1123 int size;
1124
1125 if (mode == BLKmode)
1126 size = int_size_in_bytes (type);
1127 else
1128 size = GET_MODE_SIZE (mode);
1129
1130 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1131 && cum->nbytes / UNITS_PER_WORD <= 3)
1132 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1133 }
1134
1135 return result;
1136 }
1137
1138 /* Update the data in CUM to advance over an argument
1139 of mode MODE and data type TYPE.
1140 (TYPE is null for libcalls where that information may not be available.) */
1141
1142 static void
h8300_function_arg_advance(cumulative_args_t cum_v,enum machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)1143 h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1144 const_tree type, bool named ATTRIBUTE_UNUSED)
1145 {
1146 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1147
1148 cum->nbytes += (mode != BLKmode
1149 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1150 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1151 }
1152
1153
1154 /* Implements TARGET_REGISTER_MOVE_COST.
1155
1156 Any SI register-to-register move may need to be reloaded,
1157 so inmplement h8300_register_move_cost to return > 2 so that reload never
1158 shortcuts. */
1159
1160 static int
h8300_register_move_cost(enum machine_mode mode ATTRIBUTE_UNUSED,reg_class_t from,reg_class_t to)1161 h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1162 reg_class_t from, reg_class_t to)
1163 {
1164 if (from == MAC_REGS || to == MAC_REG)
1165 return 6;
1166 else
1167 return 3;
1168 }
1169
1170 /* Compute the cost of an and insn. */
1171
1172 static int
h8300_and_costs(rtx x)1173 h8300_and_costs (rtx x)
1174 {
1175 rtx operands[4];
1176
1177 if (GET_MODE (x) == QImode)
1178 return 1;
1179
1180 if (GET_MODE (x) != HImode
1181 && GET_MODE (x) != SImode)
1182 return 100;
1183
1184 operands[0] = NULL;
1185 operands[1] = XEXP (x, 0);
1186 operands[2] = XEXP (x, 1);
1187 operands[3] = x;
1188 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1189 }
1190
1191 /* Compute the cost of a shift insn. */
1192
1193 static int
h8300_shift_costs(rtx x)1194 h8300_shift_costs (rtx x)
1195 {
1196 rtx operands[4];
1197
1198 if (GET_MODE (x) != QImode
1199 && GET_MODE (x) != HImode
1200 && GET_MODE (x) != SImode)
1201 return 100;
1202
1203 operands[0] = NULL;
1204 operands[1] = NULL;
1205 operands[2] = XEXP (x, 1);
1206 operands[3] = x;
1207 return compute_a_shift_length (NULL, operands) / 2;
1208 }
1209
1210 /* Worker function for TARGET_RTX_COSTS. */
1211
1212 static bool
h8300_rtx_costs(rtx x,int code,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed)1213 h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1214 int *total, bool speed)
1215 {
1216 if (TARGET_H8300SX && outer_code == MEM)
1217 {
1218 /* Estimate the number of execution states needed to calculate
1219 the address. */
1220 if (register_operand (x, VOIDmode)
1221 || GET_CODE (x) == POST_INC
1222 || GET_CODE (x) == POST_DEC
1223 || CONSTANT_P (x))
1224 *total = 0;
1225 else
1226 *total = COSTS_N_INSNS (1);
1227 return true;
1228 }
1229
1230 switch (code)
1231 {
1232 case CONST_INT:
1233 {
1234 HOST_WIDE_INT n = INTVAL (x);
1235
1236 if (TARGET_H8300SX)
1237 {
1238 /* Constant operands need the same number of processor
1239 states as register operands. Although we could try to
1240 use a size-based cost for !speed, the lack of
1241 of a mode makes the results very unpredictable. */
1242 *total = 0;
1243 return true;
1244 }
1245 if (-4 <= n && n <= 4)
1246 {
1247 switch ((int) n)
1248 {
1249 case 0:
1250 *total = 0;
1251 return true;
1252 case 1:
1253 case 2:
1254 case -1:
1255 case -2:
1256 *total = 0 + (outer_code == SET);
1257 return true;
1258 case 4:
1259 case -4:
1260 if (TARGET_H8300H || TARGET_H8300S)
1261 *total = 0 + (outer_code == SET);
1262 else
1263 *total = 1;
1264 return true;
1265 }
1266 }
1267 *total = 1;
1268 return true;
1269 }
1270
1271 case CONST:
1272 case LABEL_REF:
1273 case SYMBOL_REF:
1274 if (TARGET_H8300SX)
1275 {
1276 /* See comment for CONST_INT. */
1277 *total = 0;
1278 return true;
1279 }
1280 *total = 3;
1281 return true;
1282
1283 case CONST_DOUBLE:
1284 *total = 20;
1285 return true;
1286
1287 case COMPARE:
1288 if (XEXP (x, 1) == const0_rtx)
1289 *total = 0;
1290 return false;
1291
1292 case AND:
1293 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1294 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1295 return false;
1296 *total = COSTS_N_INSNS (h8300_and_costs (x));
1297 return true;
1298
1299 /* We say that MOD and DIV are so expensive because otherwise we'll
1300 generate some really horrible code for division of a power of two. */
1301 case MOD:
1302 case DIV:
1303 case UMOD:
1304 case UDIV:
1305 if (TARGET_H8300SX)
1306 switch (GET_MODE (x))
1307 {
1308 case QImode:
1309 case HImode:
1310 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1311 return false;
1312
1313 case SImode:
1314 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1315 return false;
1316
1317 default:
1318 break;
1319 }
1320 *total = COSTS_N_INSNS (12);
1321 return true;
1322
1323 case MULT:
1324 if (TARGET_H8300SX)
1325 switch (GET_MODE (x))
1326 {
1327 case QImode:
1328 case HImode:
1329 *total = COSTS_N_INSNS (2);
1330 return false;
1331
1332 case SImode:
1333 *total = COSTS_N_INSNS (5);
1334 return false;
1335
1336 default:
1337 break;
1338 }
1339 *total = COSTS_N_INSNS (4);
1340 return true;
1341
1342 case ASHIFT:
1343 case ASHIFTRT:
1344 case LSHIFTRT:
1345 if (h8sx_binary_shift_operator (x, VOIDmode))
1346 {
1347 *total = COSTS_N_INSNS (2);
1348 return false;
1349 }
1350 else if (h8sx_unary_shift_operator (x, VOIDmode))
1351 {
1352 *total = COSTS_N_INSNS (1);
1353 return false;
1354 }
1355 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1356 return true;
1357
1358 case ROTATE:
1359 case ROTATERT:
1360 if (GET_MODE (x) == HImode)
1361 *total = 2;
1362 else
1363 *total = 8;
1364 return true;
1365
1366 default:
1367 *total = COSTS_N_INSNS (1);
1368 return false;
1369 }
1370 }
1371
1372 /* Documentation for the machine specific operand escapes:
1373
1374 'E' like s but negative.
1375 'F' like t but negative.
1376 'G' constant just the negative
1377 'R' print operand as a byte:8 address if appropriate, else fall back to
1378 'X' handling.
1379 'S' print operand as a long word
1380 'T' print operand as a word
1381 'V' find the set bit, and print its number.
1382 'W' find the clear bit, and print its number.
1383 'X' print operand as a byte
1384 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1385 If this operand isn't a register, fall back to 'R' handling.
1386 'Z' print int & 7.
1387 'c' print the opcode corresponding to rtl
1388 'e' first word of 32-bit value - if reg, then least reg. if mem
1389 then least. if const then most sig word
1390 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1391 then +2. if const then least sig word
1392 'j' print operand as condition code.
1393 'k' print operand as reverse condition code.
1394 'm' convert an integer operand to a size suffix (.b, .w or .l)
1395 'o' print an integer without a leading '#'
1396 's' print as low byte of 16-bit value
1397 't' print as high byte of 16-bit value
1398 'w' print as low byte of 32-bit value
1399 'x' print as 2nd byte of 32-bit value
1400 'y' print as 3rd byte of 32-bit value
1401 'z' print as msb of 32-bit value
1402 */
1403
1404 /* Return assembly language string which identifies a comparison type. */
1405
1406 static const char *
cond_string(enum rtx_code code)1407 cond_string (enum rtx_code code)
1408 {
1409 switch (code)
1410 {
1411 case NE:
1412 return "ne";
1413 case EQ:
1414 return "eq";
1415 case GE:
1416 return "ge";
1417 case GT:
1418 return "gt";
1419 case LE:
1420 return "le";
1421 case LT:
1422 return "lt";
1423 case GEU:
1424 return "hs";
1425 case GTU:
1426 return "hi";
1427 case LEU:
1428 return "ls";
1429 case LTU:
1430 return "lo";
1431 default:
1432 gcc_unreachable ();
1433 }
1434 }
1435
1436 /* Print operand X using operand code CODE to assembly language output file
1437 FILE. */
1438
1439 static void
h8300_print_operand(FILE * file,rtx x,int code)1440 h8300_print_operand (FILE *file, rtx x, int code)
1441 {
1442 /* This is used for communication between codes V,W,Z and Y. */
1443 static int bitint;
1444
1445 switch (code)
1446 {
1447 case 'C':
1448 if (h8300_constant_length (x) == 2)
1449 fprintf (file, ":16");
1450 else
1451 fprintf (file, ":32");
1452 return;
1453 case 'E':
1454 switch (GET_CODE (x))
1455 {
1456 case REG:
1457 fprintf (file, "%sl", names_big[REGNO (x)]);
1458 break;
1459 case CONST_INT:
1460 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1461 break;
1462 default:
1463 gcc_unreachable ();
1464 }
1465 break;
1466 case 'F':
1467 switch (GET_CODE (x))
1468 {
1469 case REG:
1470 fprintf (file, "%sh", names_big[REGNO (x)]);
1471 break;
1472 case CONST_INT:
1473 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1474 break;
1475 default:
1476 gcc_unreachable ();
1477 }
1478 break;
1479 case 'G':
1480 gcc_assert (GET_CODE (x) == CONST_INT);
1481 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1482 break;
1483 case 'S':
1484 if (GET_CODE (x) == REG)
1485 fprintf (file, "%s", names_extended[REGNO (x)]);
1486 else
1487 goto def;
1488 break;
1489 case 'T':
1490 if (GET_CODE (x) == REG)
1491 fprintf (file, "%s", names_big[REGNO (x)]);
1492 else
1493 goto def;
1494 break;
1495 case 'V':
1496 bitint = (INTVAL (x) & 0xffff);
1497 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1498 bitint = exact_log2 (bitint & 0xff);
1499 else
1500 bitint = exact_log2 ((bitint >> 8) & 0xff);
1501 gcc_assert (bitint >= 0);
1502 fprintf (file, "#%d", bitint);
1503 break;
1504 case 'W':
1505 bitint = ((~INTVAL (x)) & 0xffff);
1506 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1507 bitint = exact_log2 (bitint & 0xff);
1508 else
1509 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1510 gcc_assert (bitint >= 0);
1511 fprintf (file, "#%d", bitint);
1512 break;
1513 case 'R':
1514 case 'X':
1515 if (GET_CODE (x) == REG)
1516 fprintf (file, "%s", byte_reg (x, 0));
1517 else
1518 goto def;
1519 break;
1520 case 'Y':
1521 gcc_assert (bitint >= 0);
1522 if (GET_CODE (x) == REG)
1523 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1524 else
1525 h8300_print_operand (file, x, 'R');
1526 bitint = -1;
1527 break;
1528 case 'Z':
1529 bitint = INTVAL (x);
1530 fprintf (file, "#%d", bitint & 7);
1531 break;
1532 case 'c':
1533 switch (GET_CODE (x))
1534 {
1535 case IOR:
1536 fprintf (file, "or");
1537 break;
1538 case XOR:
1539 fprintf (file, "xor");
1540 break;
1541 case AND:
1542 fprintf (file, "and");
1543 break;
1544 default:
1545 break;
1546 }
1547 break;
1548 case 'e':
1549 switch (GET_CODE (x))
1550 {
1551 case REG:
1552 if (TARGET_H8300)
1553 fprintf (file, "%s", names_big[REGNO (x)]);
1554 else
1555 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1556 break;
1557 case MEM:
1558 h8300_print_operand (file, x, 0);
1559 break;
1560 case CONST_INT:
1561 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1562 break;
1563 case CONST_DOUBLE:
1564 {
1565 long val;
1566 REAL_VALUE_TYPE rv;
1567 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1568 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1569 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1570 break;
1571 }
1572 default:
1573 gcc_unreachable ();
1574 break;
1575 }
1576 break;
1577 case 'f':
1578 switch (GET_CODE (x))
1579 {
1580 case REG:
1581 if (TARGET_H8300)
1582 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1583 else
1584 fprintf (file, "%s", names_big[REGNO (x)]);
1585 break;
1586 case MEM:
1587 x = adjust_address (x, HImode, 2);
1588 h8300_print_operand (file, x, 0);
1589 break;
1590 case CONST_INT:
1591 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1592 break;
1593 case CONST_DOUBLE:
1594 {
1595 long val;
1596 REAL_VALUE_TYPE rv;
1597 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1598 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1599 fprintf (file, "#%ld", (val & 0xffff));
1600 break;
1601 }
1602 default:
1603 gcc_unreachable ();
1604 }
1605 break;
1606 case 'j':
1607 fputs (cond_string (GET_CODE (x)), file);
1608 break;
1609 case 'k':
1610 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1611 break;
1612 case 'm':
1613 gcc_assert (GET_CODE (x) == CONST_INT);
1614 switch (INTVAL (x))
1615 {
1616 case 1:
1617 fputs (".b", file);
1618 break;
1619
1620 case 2:
1621 fputs (".w", file);
1622 break;
1623
1624 case 4:
1625 fputs (".l", file);
1626 break;
1627
1628 default:
1629 gcc_unreachable ();
1630 }
1631 break;
1632 case 'o':
1633 h8300_print_operand_address (file, x);
1634 break;
1635 case 's':
1636 if (GET_CODE (x) == CONST_INT)
1637 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1638 else
1639 fprintf (file, "%s", byte_reg (x, 0));
1640 break;
1641 case 't':
1642 if (GET_CODE (x) == CONST_INT)
1643 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1644 else
1645 fprintf (file, "%s", byte_reg (x, 1));
1646 break;
1647 case 'w':
1648 if (GET_CODE (x) == CONST_INT)
1649 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1650 else
1651 fprintf (file, "%s",
1652 byte_reg (x, TARGET_H8300 ? 2 : 0));
1653 break;
1654 case 'x':
1655 if (GET_CODE (x) == CONST_INT)
1656 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1657 else
1658 fprintf (file, "%s",
1659 byte_reg (x, TARGET_H8300 ? 3 : 1));
1660 break;
1661 case 'y':
1662 if (GET_CODE (x) == CONST_INT)
1663 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1664 else
1665 fprintf (file, "%s", byte_reg (x, 0));
1666 break;
1667 case 'z':
1668 if (GET_CODE (x) == CONST_INT)
1669 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1670 else
1671 fprintf (file, "%s", byte_reg (x, 1));
1672 break;
1673
1674 default:
1675 def:
1676 switch (GET_CODE (x))
1677 {
1678 case REG:
1679 switch (GET_MODE (x))
1680 {
1681 case QImode:
1682 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1683 fprintf (file, "%s", byte_reg (x, 0));
1684 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1685 fprintf (file, "%s", names_big[REGNO (x)]);
1686 #endif
1687 break;
1688 case HImode:
1689 fprintf (file, "%s", names_big[REGNO (x)]);
1690 break;
1691 case SImode:
1692 case SFmode:
1693 fprintf (file, "%s", names_extended[REGNO (x)]);
1694 break;
1695 default:
1696 gcc_unreachable ();
1697 }
1698 break;
1699
1700 case MEM:
1701 {
1702 rtx addr = XEXP (x, 0);
1703
1704 fprintf (file, "@");
1705 output_address (addr);
1706
1707 /* Add a length suffix to constant addresses. Although this
1708 is often unnecessary, it helps to avoid ambiguity in the
1709 syntax of mova. If we wrote an insn like:
1710
1711 mova/w.l @(1,@foo.b),er0
1712
1713 then .b would be considered part of the symbol name.
1714 Adding a length after foo will avoid this. */
1715 if (CONSTANT_P (addr))
1716 switch (code)
1717 {
1718 case 'R':
1719 /* Used for mov.b and bit operations. */
1720 if (h8300_eightbit_constant_address_p (addr))
1721 {
1722 fprintf (file, ":8");
1723 break;
1724 }
1725
1726 /* Fall through. We should not get here if we are
1727 processing bit operations on H8/300 or H8/300H
1728 because 'U' constraint does not allow bit
1729 operations on the tiny area on these machines. */
1730
1731 case 'X':
1732 case 'T':
1733 case 'S':
1734 if (h8300_constant_length (addr) == 2)
1735 fprintf (file, ":16");
1736 else
1737 fprintf (file, ":32");
1738 break;
1739 default:
1740 break;
1741 }
1742 }
1743 break;
1744
1745 case CONST_INT:
1746 case SYMBOL_REF:
1747 case CONST:
1748 case LABEL_REF:
1749 fprintf (file, "#");
1750 h8300_print_operand_address (file, x);
1751 break;
1752 case CONST_DOUBLE:
1753 {
1754 long val;
1755 REAL_VALUE_TYPE rv;
1756 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1757 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1758 fprintf (file, "#%ld", val);
1759 break;
1760 }
1761 default:
1762 break;
1763 }
1764 }
1765 }
1766
1767 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1768
1769 static bool
h8300_print_operand_punct_valid_p(unsigned char code)1770 h8300_print_operand_punct_valid_p (unsigned char code)
1771 {
1772 return (code == '#');
1773 }
1774
1775 /* Output assembly language output for the address ADDR to FILE. */
1776
1777 static void
h8300_print_operand_address(FILE * file,rtx addr)1778 h8300_print_operand_address (FILE *file, rtx addr)
1779 {
1780 rtx index;
1781 int size;
1782
1783 switch (GET_CODE (addr))
1784 {
1785 case REG:
1786 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1787 break;
1788
1789 case PRE_DEC:
1790 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1791 break;
1792
1793 case POST_INC:
1794 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1795 break;
1796
1797 case PRE_INC:
1798 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1799 break;
1800
1801 case POST_DEC:
1802 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1803 break;
1804
1805 case PLUS:
1806 fprintf (file, "(");
1807
1808 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1809 if (GET_CODE (index) == REG)
1810 {
1811 /* reg,foo */
1812 h8300_print_operand_address (file, XEXP (addr, 1));
1813 fprintf (file, ",");
1814 switch (size)
1815 {
1816 case 0:
1817 h8300_print_operand_address (file, index);
1818 break;
1819
1820 case 1:
1821 h8300_print_operand (file, index, 'X');
1822 fputs (".b", file);
1823 break;
1824
1825 case 2:
1826 h8300_print_operand (file, index, 'T');
1827 fputs (".w", file);
1828 break;
1829
1830 case 4:
1831 h8300_print_operand (file, index, 'S');
1832 fputs (".l", file);
1833 break;
1834 }
1835 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1836 }
1837 else
1838 {
1839 /* foo+k */
1840 h8300_print_operand_address (file, XEXP (addr, 0));
1841 fprintf (file, "+");
1842 h8300_print_operand_address (file, XEXP (addr, 1));
1843 }
1844 fprintf (file, ")");
1845 break;
1846
1847 case CONST_INT:
1848 {
1849 /* Since the H8/300 only has 16-bit pointers, negative values are also
1850 those >= 32768. This happens for example with pointer minus a
1851 constant. We don't want to turn (char *p - 2) into
1852 (char *p + 65534) because loop unrolling can build upon this
1853 (IE: char *p + 131068). */
1854 int n = INTVAL (addr);
1855 if (TARGET_H8300)
1856 n = (int) (short) n;
1857 fprintf (file, "%d", n);
1858 break;
1859 }
1860
1861 default:
1862 output_addr_const (file, addr);
1863 break;
1864 }
1865 }
1866
1867 /* Output all insn addresses and their sizes into the assembly language
1868 output file. This is helpful for debugging whether the length attributes
1869 in the md file are correct. This is not meant to be a user selectable
1870 option. */
1871
1872 void
final_prescan_insn(rtx insn,rtx * operand ATTRIBUTE_UNUSED,int num_operands ATTRIBUTE_UNUSED)1873 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1874 int num_operands ATTRIBUTE_UNUSED)
1875 {
1876 /* This holds the last insn address. */
1877 static int last_insn_address = 0;
1878
1879 const int uid = INSN_UID (insn);
1880
1881 if (TARGET_ADDRESSES)
1882 {
1883 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1884 INSN_ADDRESSES (uid) - last_insn_address);
1885 last_insn_address = INSN_ADDRESSES (uid);
1886 }
1887 }
1888
1889 /* Prepare for an SI sized move. */
1890
1891 int
h8300_expand_movsi(rtx operands[])1892 h8300_expand_movsi (rtx operands[])
1893 {
1894 rtx src = operands[1];
1895 rtx dst = operands[0];
1896 if (!reload_in_progress && !reload_completed)
1897 {
1898 if (!register_operand (dst, GET_MODE (dst)))
1899 {
1900 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1901 emit_move_insn (tmp, src);
1902 operands[1] = tmp;
1903 }
1904 }
1905 return 0;
1906 }
1907
1908 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1909 Frame pointer elimination is automatically handled.
1910
1911 For the h8300, if frame pointer elimination is being done, we would like to
1912 convert ap and rp into sp, not fp.
1913
1914 All other eliminations are valid. */
1915
1916 static bool
h8300_can_eliminate(const int from ATTRIBUTE_UNUSED,const int to)1917 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1918 {
1919 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1920 }
1921
1922 /* Conditionally modify register usage based on target flags. */
1923
1924 static void
h8300_conditional_register_usage(void)1925 h8300_conditional_register_usage (void)
1926 {
1927 if (!TARGET_MAC)
1928 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1929 }
1930
1931 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1932 Define the offset between two registers, one to be eliminated, and
1933 the other its replacement, at the start of a routine. */
1934
1935 int
h8300_initial_elimination_offset(int from,int to)1936 h8300_initial_elimination_offset (int from, int to)
1937 {
1938 /* The number of bytes that the return address takes on the stack. */
1939 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1940
1941 /* The number of bytes that the saved frame pointer takes on the stack. */
1942 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1943
1944 /* The number of bytes that the saved registers, excluding the frame
1945 pointer, take on the stack. */
1946 int saved_regs_size = 0;
1947
1948 /* The number of bytes that the locals takes on the stack. */
1949 int frame_size = round_frame_size (get_frame_size ());
1950
1951 int regno;
1952
1953 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1954 if (WORD_REG_USED (regno))
1955 saved_regs_size += UNITS_PER_WORD;
1956
1957 /* Adjust saved_regs_size because the above loop took the frame
1958 pointer int account. */
1959 saved_regs_size -= fp_size;
1960
1961 switch (to)
1962 {
1963 case HARD_FRAME_POINTER_REGNUM:
1964 switch (from)
1965 {
1966 case ARG_POINTER_REGNUM:
1967 return pc_size + fp_size;
1968 case RETURN_ADDRESS_POINTER_REGNUM:
1969 return fp_size;
1970 case FRAME_POINTER_REGNUM:
1971 return -saved_regs_size;
1972 default:
1973 gcc_unreachable ();
1974 }
1975 break;
1976 case STACK_POINTER_REGNUM:
1977 switch (from)
1978 {
1979 case ARG_POINTER_REGNUM:
1980 return pc_size + saved_regs_size + frame_size;
1981 case RETURN_ADDRESS_POINTER_REGNUM:
1982 return saved_regs_size + frame_size;
1983 case FRAME_POINTER_REGNUM:
1984 return frame_size;
1985 default:
1986 gcc_unreachable ();
1987 }
1988 break;
1989 default:
1990 gcc_unreachable ();
1991 }
1992 gcc_unreachable ();
1993 }
1994
1995 /* Worker function for RETURN_ADDR_RTX. */
1996
1997 rtx
h8300_return_addr_rtx(int count,rtx frame)1998 h8300_return_addr_rtx (int count, rtx frame)
1999 {
2000 rtx ret;
2001
2002 if (count == 0)
2003 ret = gen_rtx_MEM (Pmode,
2004 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2005 else if (flag_omit_frame_pointer)
2006 return (rtx) 0;
2007 else
2008 ret = gen_rtx_MEM (Pmode,
2009 memory_address (Pmode,
2010 plus_constant (Pmode, frame,
2011 UNITS_PER_WORD)));
2012 set_mem_alias_set (ret, get_frame_alias_set ());
2013 return ret;
2014 }
2015
2016 /* Update the condition code from the insn. */
2017
2018 void
notice_update_cc(rtx body,rtx insn)2019 notice_update_cc (rtx body, rtx insn)
2020 {
2021 rtx set;
2022
2023 switch (get_attr_cc (insn))
2024 {
2025 case CC_NONE:
2026 /* Insn does not affect CC at all. */
2027 break;
2028
2029 case CC_NONE_0HIT:
2030 /* Insn does not change CC, but the 0'th operand has been changed. */
2031 if (cc_status.value1 != 0
2032 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2033 cc_status.value1 = 0;
2034 if (cc_status.value2 != 0
2035 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2036 cc_status.value2 = 0;
2037 break;
2038
2039 case CC_SET_ZN:
2040 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2041 The V flag is unusable. The C flag may or may not be known but
2042 that's ok because alter_cond will change tests to use EQ/NE. */
2043 CC_STATUS_INIT;
2044 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2045 set = single_set (insn);
2046 cc_status.value1 = SET_SRC (set);
2047 if (SET_DEST (set) != cc0_rtx)
2048 cc_status.value2 = SET_DEST (set);
2049 break;
2050
2051 case CC_SET_ZNV:
2052 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2053 The C flag may or may not be known but that's ok because
2054 alter_cond will change tests to use EQ/NE. */
2055 CC_STATUS_INIT;
2056 cc_status.flags |= CC_NO_CARRY;
2057 set = single_set (insn);
2058 cc_status.value1 = SET_SRC (set);
2059 if (SET_DEST (set) != cc0_rtx)
2060 {
2061 /* If the destination is STRICT_LOW_PART, strip off
2062 STRICT_LOW_PART. */
2063 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2064 cc_status.value2 = XEXP (SET_DEST (set), 0);
2065 else
2066 cc_status.value2 = SET_DEST (set);
2067 }
2068 break;
2069
2070 case CC_COMPARE:
2071 /* The insn is a compare instruction. */
2072 CC_STATUS_INIT;
2073 cc_status.value1 = SET_SRC (body);
2074 break;
2075
2076 case CC_CLOBBER:
2077 /* Insn doesn't leave CC in a usable state. */
2078 CC_STATUS_INIT;
2079 break;
2080 }
2081 }
2082
2083 /* Given that X occurs in an address of the form (plus X constant),
2084 return the part of X that is expected to be a register. There are
2085 four kinds of addressing mode to recognize:
2086
2087 @(dd,Rn)
2088 @(dd,RnL.b)
2089 @(dd,Rn.w)
2090 @(dd,ERn.l)
2091
2092 If SIZE is nonnull, and the address is one of the last three forms,
2093 set *SIZE to the index multiplication factor. Set it to 0 for
2094 plain @(dd,Rn) addresses.
2095
2096 MODE is the mode of the value being accessed. It can be VOIDmode
2097 if the address is known to be valid, but its mode is unknown. */
2098
2099 static rtx
h8300_get_index(rtx x,enum machine_mode mode,int * size)2100 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2101 {
2102 int dummy, factor;
2103
2104 if (size == 0)
2105 size = &dummy;
2106
2107 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2108 if (TARGET_H8300SX
2109 && factor <= 4
2110 && (mode == VOIDmode
2111 || GET_MODE_CLASS (mode) == MODE_INT
2112 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2113 {
2114 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2115 {
2116 /* When accessing byte-sized values, the index can be
2117 a zero-extended QImode or HImode register. */
2118 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2119 return XEXP (x, 0);
2120 }
2121 else
2122 {
2123 /* We're looking for addresses of the form:
2124
2125 (mult X I)
2126 or (mult (zero_extend X) I)
2127
2128 where I is the size of the operand being accessed.
2129 The canonical form of the second expression is:
2130
2131 (and (mult (subreg X) I) J)
2132
2133 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2134 rtx index;
2135
2136 if (GET_CODE (x) == AND
2137 && GET_CODE (XEXP (x, 1)) == CONST_INT
2138 && (factor == 0
2139 || INTVAL (XEXP (x, 1)) == 0xff * factor
2140 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2141 {
2142 index = XEXP (x, 0);
2143 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2144 }
2145 else
2146 {
2147 index = x;
2148 *size = 4;
2149 }
2150
2151 if (GET_CODE (index) == MULT
2152 && GET_CODE (XEXP (index, 1)) == CONST_INT
2153 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2154 return XEXP (index, 0);
2155 }
2156 }
2157 *size = 0;
2158 return x;
2159 }
2160
2161 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2162
2163 On the H8/300, the predecrement and postincrement address depend thus
2164 (the amount of decrement or increment being the length of the operand). */
2165
2166 static bool
h8300_mode_dependent_address_p(const_rtx addr,addr_space_t as ATTRIBUTE_UNUSED)2167 h8300_mode_dependent_address_p (const_rtx addr,
2168 addr_space_t as ATTRIBUTE_UNUSED)
2169 {
2170 if (GET_CODE (addr) == PLUS
2171 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2172 return true;
2173
2174 return false;
2175 }
2176
2177 static const h8300_length_table addb_length_table =
2178 {
2179 /* #xx Rs @aa @Rs @xx */
2180 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2181 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2182 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2183 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2184 };
2185
2186 static const h8300_length_table addw_length_table =
2187 {
2188 /* #xx Rs @aa @Rs @xx */
2189 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2190 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2191 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2192 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2193 };
2194
2195 static const h8300_length_table addl_length_table =
2196 {
2197 /* #xx Rs @aa @Rs @xx */
2198 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2199 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2200 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2201 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2202 };
2203
2204 #define logicb_length_table addb_length_table
2205 #define logicw_length_table addw_length_table
2206
2207 static const h8300_length_table logicl_length_table =
2208 {
2209 /* #xx Rs @aa @Rs @xx */
2210 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2211 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2212 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2213 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2214 };
2215
2216 static const h8300_length_table movb_length_table =
2217 {
2218 /* #xx Rs @aa @Rs @xx */
2219 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2220 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2221 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2222 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2223 };
2224
2225 #define movw_length_table movb_length_table
2226
2227 static const h8300_length_table movl_length_table =
2228 {
2229 /* #xx Rs @aa @Rs @xx */
2230 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2231 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2232 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2233 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2234 };
2235
2236 /* Return the size of the given address or displacement constant. */
2237
2238 static unsigned int
h8300_constant_length(rtx constant)2239 h8300_constant_length (rtx constant)
2240 {
2241 /* Check for (@d:16,Reg). */
2242 if (GET_CODE (constant) == CONST_INT
2243 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2244 return 2;
2245
2246 /* Check for (@d:16,Reg) in cases where the displacement is
2247 an absolute address. */
2248 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2249 return 2;
2250
2251 return 4;
2252 }
2253
2254 /* Return the size of a displacement field in address ADDR, which should
2255 have the form (plus X constant). SIZE is the number of bytes being
2256 accessed. */
2257
2258 static unsigned int
h8300_displacement_length(rtx addr,int size)2259 h8300_displacement_length (rtx addr, int size)
2260 {
2261 rtx offset;
2262
2263 offset = XEXP (addr, 1);
2264
2265 /* Check for @(d:2,Reg). */
2266 if (register_operand (XEXP (addr, 0), VOIDmode)
2267 && GET_CODE (offset) == CONST_INT
2268 && (INTVAL (offset) == size
2269 || INTVAL (offset) == size * 2
2270 || INTVAL (offset) == size * 3))
2271 return 0;
2272
2273 return h8300_constant_length (offset);
2274 }
2275
2276 /* Store the class of operand OP in *OPCLASS and return the length of any
2277 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2278 can be null if only the length is needed. */
2279
2280 static unsigned int
h8300_classify_operand(rtx op,int size,enum h8300_operand_class * opclass)2281 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2282 {
2283 enum h8300_operand_class dummy;
2284
2285 if (opclass == 0)
2286 opclass = &dummy;
2287
2288 if (CONSTANT_P (op))
2289 {
2290 *opclass = H8OP_IMMEDIATE;
2291
2292 /* Byte-sized immediates are stored in the opcode fields. */
2293 if (size == 1)
2294 return 0;
2295
2296 /* If this is a 32-bit instruction, see whether the constant
2297 will fit into a 16-bit immediate field. */
2298 if (TARGET_H8300SX
2299 && size == 4
2300 && GET_CODE (op) == CONST_INT
2301 && IN_RANGE (INTVAL (op), 0, 0xffff))
2302 return 2;
2303
2304 return size;
2305 }
2306 else if (GET_CODE (op) == MEM)
2307 {
2308 op = XEXP (op, 0);
2309 if (CONSTANT_P (op))
2310 {
2311 *opclass = H8OP_MEM_ABSOLUTE;
2312 return h8300_constant_length (op);
2313 }
2314 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2315 {
2316 *opclass = H8OP_MEM_COMPLEX;
2317 return h8300_displacement_length (op, size);
2318 }
2319 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2320 {
2321 *opclass = H8OP_MEM_COMPLEX;
2322 return 0;
2323 }
2324 else if (register_operand (op, VOIDmode))
2325 {
2326 *opclass = H8OP_MEM_BASE;
2327 return 0;
2328 }
2329 }
2330 gcc_assert (register_operand (op, VOIDmode));
2331 *opclass = H8OP_REGISTER;
2332 return 0;
2333 }
2334
2335 /* Return the length of the instruction described by TABLE given that
2336 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2337 and OP2 must be an h8300_src_operand. */
2338
2339 static unsigned int
h8300_length_from_table(rtx op1,rtx op2,const h8300_length_table * table)2340 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2341 {
2342 enum h8300_operand_class op1_class, op2_class;
2343 unsigned int size, immediate_length;
2344
2345 size = GET_MODE_SIZE (GET_MODE (op1));
2346 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2347 + h8300_classify_operand (op2, size, &op2_class));
2348 return immediate_length + (*table)[op1_class - 1][op2_class];
2349 }
2350
2351 /* Return the length of a unary instruction such as neg or not given that
2352 its operand is OP. */
2353
2354 unsigned int
h8300_unary_length(rtx op)2355 h8300_unary_length (rtx op)
2356 {
2357 enum h8300_operand_class opclass;
2358 unsigned int size, operand_length;
2359
2360 size = GET_MODE_SIZE (GET_MODE (op));
2361 operand_length = h8300_classify_operand (op, size, &opclass);
2362 switch (opclass)
2363 {
2364 case H8OP_REGISTER:
2365 return 2;
2366
2367 case H8OP_MEM_BASE:
2368 return (size == 4 ? 6 : 4);
2369
2370 case H8OP_MEM_ABSOLUTE:
2371 return operand_length + (size == 4 ? 6 : 4);
2372
2373 case H8OP_MEM_COMPLEX:
2374 return operand_length + 6;
2375
2376 default:
2377 gcc_unreachable ();
2378 }
2379 }
2380
2381 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2382
2383 static unsigned int
h8300_short_immediate_length(rtx op)2384 h8300_short_immediate_length (rtx op)
2385 {
2386 enum h8300_operand_class opclass;
2387 unsigned int size, operand_length;
2388
2389 size = GET_MODE_SIZE (GET_MODE (op));
2390 operand_length = h8300_classify_operand (op, size, &opclass);
2391
2392 switch (opclass)
2393 {
2394 case H8OP_REGISTER:
2395 return 2;
2396
2397 case H8OP_MEM_BASE:
2398 case H8OP_MEM_ABSOLUTE:
2399 case H8OP_MEM_COMPLEX:
2400 return 4 + operand_length;
2401
2402 default:
2403 gcc_unreachable ();
2404 }
2405 }
2406
2407 /* Likewise bitfield load and store instructions. */
2408
2409 static unsigned int
h8300_bitfield_length(rtx op,rtx op2)2410 h8300_bitfield_length (rtx op, rtx op2)
2411 {
2412 enum h8300_operand_class opclass;
2413 unsigned int size, operand_length;
2414
2415 if (GET_CODE (op) == REG)
2416 op = op2;
2417 gcc_assert (GET_CODE (op) != REG);
2418
2419 size = GET_MODE_SIZE (GET_MODE (op));
2420 operand_length = h8300_classify_operand (op, size, &opclass);
2421
2422 switch (opclass)
2423 {
2424 case H8OP_MEM_BASE:
2425 case H8OP_MEM_ABSOLUTE:
2426 case H8OP_MEM_COMPLEX:
2427 return 4 + operand_length;
2428
2429 default:
2430 gcc_unreachable ();
2431 }
2432 }
2433
2434 /* Calculate the length of general binary instruction INSN using TABLE. */
2435
2436 static unsigned int
h8300_binary_length(rtx insn,const h8300_length_table * table)2437 h8300_binary_length (rtx insn, const h8300_length_table *table)
2438 {
2439 rtx set;
2440
2441 set = single_set (insn);
2442 gcc_assert (set);
2443
2444 if (BINARY_P (SET_SRC (set)))
2445 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2446 XEXP (SET_SRC (set), 1), table);
2447 else
2448 {
2449 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2450 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2451 XEXP (XEXP (SET_SRC (set), 1), 1),
2452 table);
2453 }
2454 }
2455
2456 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2457 memory reference and either (1) it has the form @(d:16,Rn) or
2458 (2) its address has the code given by INC_CODE. */
2459
2460 static bool
h8300_short_move_mem_p(rtx op,enum rtx_code inc_code)2461 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2462 {
2463 rtx addr;
2464 unsigned int size;
2465
2466 if (GET_CODE (op) != MEM)
2467 return false;
2468
2469 addr = XEXP (op, 0);
2470 size = GET_MODE_SIZE (GET_MODE (op));
2471 if (size != 1 && size != 2)
2472 return false;
2473
2474 return (GET_CODE (addr) == inc_code
2475 || (GET_CODE (addr) == PLUS
2476 && GET_CODE (XEXP (addr, 0)) == REG
2477 && h8300_displacement_length (addr, size) == 2));
2478 }
2479
2480 /* Calculate the length of move instruction INSN using the given length
2481 table. Although the tables are correct for most cases, there is some
2482 irregularity in the length of mov.b and mov.w. The following forms:
2483
2484 mov @ERs+, Rd
2485 mov @(d:16,ERs), Rd
2486 mov Rs, @-ERd
2487 mov Rs, @(d:16,ERd)
2488
2489 are two bytes shorter than most other "mov Rs, @complex" or
2490 "mov @complex,Rd" combinations. */
2491
2492 static unsigned int
h8300_move_length(rtx * operands,const h8300_length_table * table)2493 h8300_move_length (rtx *operands, const h8300_length_table *table)
2494 {
2495 unsigned int size;
2496
2497 size = h8300_length_from_table (operands[0], operands[1], table);
2498 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2499 size -= 2;
2500 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2501 size -= 2;
2502 return size;
2503 }
2504
2505 /* Return the length of a mova instruction with the given operands.
2506 DEST is the register destination, SRC is the source address and
2507 OFFSET is the 16-bit or 32-bit displacement. */
2508
2509 static unsigned int
h8300_mova_length(rtx dest,rtx src,rtx offset)2510 h8300_mova_length (rtx dest, rtx src, rtx offset)
2511 {
2512 unsigned int size;
2513
2514 size = (2
2515 + h8300_constant_length (offset)
2516 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2517 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2518 size += 2;
2519 return size;
2520 }
2521
2522 /* Compute the length of INSN based on its length_table attribute.
2523 OPERANDS is the array of its operands. */
2524
2525 unsigned int
h8300_insn_length_from_table(rtx insn,rtx * operands)2526 h8300_insn_length_from_table (rtx insn, rtx * operands)
2527 {
2528 switch (get_attr_length_table (insn))
2529 {
2530 case LENGTH_TABLE_NONE:
2531 gcc_unreachable ();
2532
2533 case LENGTH_TABLE_ADDB:
2534 return h8300_binary_length (insn, &addb_length_table);
2535
2536 case LENGTH_TABLE_ADDW:
2537 return h8300_binary_length (insn, &addw_length_table);
2538
2539 case LENGTH_TABLE_ADDL:
2540 return h8300_binary_length (insn, &addl_length_table);
2541
2542 case LENGTH_TABLE_LOGICB:
2543 return h8300_binary_length (insn, &logicb_length_table);
2544
2545 case LENGTH_TABLE_MOVB:
2546 return h8300_move_length (operands, &movb_length_table);
2547
2548 case LENGTH_TABLE_MOVW:
2549 return h8300_move_length (operands, &movw_length_table);
2550
2551 case LENGTH_TABLE_MOVL:
2552 return h8300_move_length (operands, &movl_length_table);
2553
2554 case LENGTH_TABLE_MOVA:
2555 return h8300_mova_length (operands[0], operands[1], operands[2]);
2556
2557 case LENGTH_TABLE_MOVA_ZERO:
2558 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2559
2560 case LENGTH_TABLE_UNARY:
2561 return h8300_unary_length (operands[0]);
2562
2563 case LENGTH_TABLE_MOV_IMM4:
2564 return 2 + h8300_classify_operand (operands[0], 0, 0);
2565
2566 case LENGTH_TABLE_SHORT_IMMEDIATE:
2567 return h8300_short_immediate_length (operands[0]);
2568
2569 case LENGTH_TABLE_BITFIELD:
2570 return h8300_bitfield_length (operands[0], operands[1]);
2571
2572 case LENGTH_TABLE_BITBRANCH:
2573 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2574
2575 default:
2576 gcc_unreachable ();
2577 }
2578 }
2579
2580 /* Return true if LHS and RHS are memory references that can be mapped
2581 to the same h8sx assembly operand. LHS appears as the destination of
2582 an instruction and RHS appears as a source.
2583
2584 Three cases are allowed:
2585
2586 - RHS is @+Rn or @-Rn, LHS is @Rn
2587 - RHS is @Rn, LHS is @Rn+ or @Rn-
2588 - RHS and LHS have the same address and neither has side effects. */
2589
2590 bool
h8sx_mergeable_memrefs_p(rtx lhs,rtx rhs)2591 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2592 {
2593 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2594 {
2595 rhs = XEXP (rhs, 0);
2596 lhs = XEXP (lhs, 0);
2597
2598 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2599 return rtx_equal_p (XEXP (rhs, 0), lhs);
2600
2601 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2602 return rtx_equal_p (rhs, XEXP (lhs, 0));
2603
2604 if (rtx_equal_p (rhs, lhs))
2605 return true;
2606 }
2607 return false;
2608 }
2609
2610 /* Return true if OPERANDS[1] can be mapped to the same assembly
2611 operand as OPERANDS[0]. */
2612
2613 bool
h8300_operands_match_p(rtx * operands)2614 h8300_operands_match_p (rtx *operands)
2615 {
2616 if (register_operand (operands[0], VOIDmode)
2617 && register_operand (operands[1], VOIDmode))
2618 return true;
2619
2620 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2621 return true;
2622
2623 return false;
2624 }
2625
2626 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2627 region DEST. The two regions do not overlap and have the common
2628 alignment given by ALIGNMENT. Return true on success.
2629
2630 Using movmd for variable-length moves seems to involve some
2631 complex trade-offs. For instance:
2632
2633 - Preparing for a movmd instruction is similar to preparing
2634 for a memcpy. The main difference is that the arguments
2635 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2636
2637 - Since movmd clobbers the frame pointer, we need to save
2638 and restore it somehow when frame_pointer_needed. This can
2639 sometimes make movmd sequences longer than calls to memcpy().
2640
2641 - The counter register is 16 bits, so the instruction is only
2642 suitable for variable-length moves when sizeof (size_t) == 2.
2643 That's only true in normal mode.
2644
2645 - We will often lack static alignment information. Falling back
2646 on movmd.b would likely be slower than calling memcpy(), at least
2647 for big moves.
2648
2649 This function therefore only uses movmd when the length is a
2650 known constant, and only then if -fomit-frame-pointer is in
2651 effect or if we're not optimizing for size.
2652
2653 At the moment the function uses movmd for all in-range constants,
2654 but it might be better to fall back on memcpy() for large moves
2655 if ALIGNMENT == 1. */
2656
2657 bool
h8sx_emit_movmd(rtx dest,rtx src,rtx length,HOST_WIDE_INT alignment)2658 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2659 HOST_WIDE_INT alignment)
2660 {
2661 if (!flag_omit_frame_pointer && optimize_size)
2662 return false;
2663
2664 if (GET_CODE (length) == CONST_INT)
2665 {
2666 rtx dest_reg, src_reg, first_dest, first_src;
2667 HOST_WIDE_INT n;
2668 int factor;
2669
2670 /* Use movmd.l if the alignment allows it, otherwise fall back
2671 on movmd.b. */
2672 factor = (alignment >= 2 ? 4 : 1);
2673
2674 /* Make sure the length is within range. We can handle counter
2675 values up to 65536, although HImode truncation will make
2676 the count appear negative in rtl dumps. */
2677 n = INTVAL (length);
2678 if (n <= 0 || n / factor > 65536)
2679 return false;
2680
2681 /* Create temporary registers for the source and destination
2682 pointers. Initialize them to the start of each region. */
2683 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2684 src_reg = copy_addr_to_reg (XEXP (src, 0));
2685
2686 /* Create references to the movmd source and destination blocks. */
2687 first_dest = replace_equiv_address (dest, dest_reg);
2688 first_src = replace_equiv_address (src, src_reg);
2689
2690 set_mem_size (first_dest, n & -factor);
2691 set_mem_size (first_src, n & -factor);
2692
2693 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2694 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2695
2696 if ((n & -factor) != n)
2697 {
2698 /* Move SRC and DEST past the region we just copied.
2699 This is done to update the memory attributes. */
2700 dest = adjust_address (dest, BLKmode, n & -factor);
2701 src = adjust_address (src, BLKmode, n & -factor);
2702
2703 /* Replace the addresses with the source and destination
2704 registers, which movmd has left with the right values. */
2705 dest = replace_equiv_address (dest, dest_reg);
2706 src = replace_equiv_address (src, src_reg);
2707
2708 /* Mop up the left-over bytes. */
2709 if (n & 2)
2710 emit_move_insn (adjust_address (dest, HImode, 0),
2711 adjust_address (src, HImode, 0));
2712 if (n & 1)
2713 emit_move_insn (adjust_address (dest, QImode, n & 2),
2714 adjust_address (src, QImode, n & 2));
2715 }
2716 return true;
2717 }
2718 return false;
2719 }
2720
2721 /* Move ADDR into er6 after pushing its old value onto the stack. */
2722
2723 void
h8300_swap_into_er6(rtx addr)2724 h8300_swap_into_er6 (rtx addr)
2725 {
2726 rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2727 if (frame_pointer_needed)
2728 add_reg_note (insn, REG_CFA_DEF_CFA,
2729 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
2730 2 * UNITS_PER_WORD));
2731 else
2732 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2733 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2734 plus_constant (Pmode, stack_pointer_rtx, 4)));
2735
2736 emit_move_insn (hard_frame_pointer_rtx, addr);
2737 if (REGNO (addr) == SP_REG)
2738 emit_move_insn (hard_frame_pointer_rtx,
2739 plus_constant (Pmode, hard_frame_pointer_rtx,
2740 GET_MODE_SIZE (word_mode)));
2741 }
2742
2743 /* Move the current value of er6 into ADDR and pop its old value
2744 from the stack. */
2745
2746 void
h8300_swap_out_of_er6(rtx addr)2747 h8300_swap_out_of_er6 (rtx addr)
2748 {
2749 rtx insn;
2750
2751 if (REGNO (addr) != SP_REG)
2752 emit_move_insn (addr, hard_frame_pointer_rtx);
2753
2754 insn = pop (HARD_FRAME_POINTER_REGNUM);
2755 RTX_FRAME_RELATED_P (insn) = 1;
2756 if (frame_pointer_needed)
2757 add_reg_note (insn, REG_CFA_DEF_CFA,
2758 plus_constant (Pmode, hard_frame_pointer_rtx,
2759 2 * UNITS_PER_WORD));
2760 else
2761 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2762 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2763 plus_constant (Pmode, stack_pointer_rtx, -4)));
2764 }
2765
2766 /* Return the length of mov instruction. */
2767
2768 unsigned int
compute_mov_length(rtx * operands)2769 compute_mov_length (rtx *operands)
2770 {
2771 /* If the mov instruction involves a memory operand, we compute the
2772 length, assuming the largest addressing mode is used, and then
2773 adjust later in the function. Otherwise, we compute and return
2774 the exact length in one step. */
2775 enum machine_mode mode = GET_MODE (operands[0]);
2776 rtx dest = operands[0];
2777 rtx src = operands[1];
2778 rtx addr;
2779
2780 if (GET_CODE (src) == MEM)
2781 addr = XEXP (src, 0);
2782 else if (GET_CODE (dest) == MEM)
2783 addr = XEXP (dest, 0);
2784 else
2785 addr = NULL_RTX;
2786
2787 if (TARGET_H8300)
2788 {
2789 unsigned int base_length;
2790
2791 switch (mode)
2792 {
2793 case QImode:
2794 if (addr == NULL_RTX)
2795 return 2;
2796
2797 /* The eightbit addressing is available only in QImode, so
2798 go ahead and take care of it. */
2799 if (h8300_eightbit_constant_address_p (addr))
2800 return 2;
2801
2802 base_length = 4;
2803 break;
2804
2805 case HImode:
2806 if (addr == NULL_RTX)
2807 {
2808 if (REG_P (src))
2809 return 2;
2810
2811 if (src == const0_rtx)
2812 return 2;
2813
2814 return 4;
2815 }
2816
2817 base_length = 4;
2818 break;
2819
2820 case SImode:
2821 if (addr == NULL_RTX)
2822 {
2823 if (REG_P (src))
2824 return 4;
2825
2826 if (GET_CODE (src) == CONST_INT)
2827 {
2828 if (src == const0_rtx)
2829 return 4;
2830
2831 if ((INTVAL (src) & 0xffff) == 0)
2832 return 6;
2833
2834 if ((INTVAL (src) & 0xffff) == 0)
2835 return 6;
2836
2837 if ((INTVAL (src) & 0xffff)
2838 == ((INTVAL (src) >> 16) & 0xffff))
2839 return 6;
2840 }
2841 return 8;
2842 }
2843
2844 base_length = 8;
2845 break;
2846
2847 case SFmode:
2848 if (addr == NULL_RTX)
2849 {
2850 if (REG_P (src))
2851 return 4;
2852
2853 if (satisfies_constraint_G (src))
2854 return 4;
2855
2856 return 8;
2857 }
2858
2859 base_length = 8;
2860 break;
2861
2862 default:
2863 gcc_unreachable ();
2864 }
2865
2866 /* Adjust the length based on the addressing mode used.
2867 Specifically, we subtract the difference between the actual
2868 length and the longest one, which is @(d:16,Rs). For SImode
2869 and SFmode, we double the adjustment because two mov.w are
2870 used to do the job. */
2871
2872 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2873 if (GET_CODE (addr) == PRE_DEC
2874 || GET_CODE (addr) == POST_INC)
2875 {
2876 if (mode == QImode || mode == HImode)
2877 return base_length - 2;
2878 else
2879 /* In SImode and SFmode, we use two mov.w instructions, so
2880 double the adjustment. */
2881 return base_length - 4;
2882 }
2883
2884 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2885 in SImode and SFmode, the second mov.w involves an address
2886 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2887 only 2 bytes. */
2888 if (GET_CODE (addr) == REG)
2889 return base_length - 2;
2890
2891 return base_length;
2892 }
2893 else
2894 {
2895 unsigned int base_length;
2896
2897 switch (mode)
2898 {
2899 case QImode:
2900 if (addr == NULL_RTX)
2901 return 2;
2902
2903 /* The eightbit addressing is available only in QImode, so
2904 go ahead and take care of it. */
2905 if (h8300_eightbit_constant_address_p (addr))
2906 return 2;
2907
2908 base_length = 8;
2909 break;
2910
2911 case HImode:
2912 if (addr == NULL_RTX)
2913 {
2914 if (REG_P (src))
2915 return 2;
2916
2917 if (src == const0_rtx)
2918 return 2;
2919
2920 return 4;
2921 }
2922
2923 base_length = 8;
2924 break;
2925
2926 case SImode:
2927 if (addr == NULL_RTX)
2928 {
2929 if (REG_P (src))
2930 {
2931 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2932 return 4;
2933 else
2934 return 2;
2935 }
2936
2937 if (GET_CODE (src) == CONST_INT)
2938 {
2939 int val = INTVAL (src);
2940
2941 if (val == 0)
2942 return 2;
2943
2944 if (val == (val & 0x00ff) || val == (val & 0xff00))
2945 return 4;
2946
2947 switch (val & 0xffffffff)
2948 {
2949 case 0xffffffff:
2950 case 0xfffffffe:
2951 case 0xfffffffc:
2952 case 0x0000ffff:
2953 case 0x0000fffe:
2954 case 0xffff0000:
2955 case 0xfffe0000:
2956 case 0x00010000:
2957 case 0x00020000:
2958 return 4;
2959 }
2960 }
2961 return 6;
2962 }
2963
2964 base_length = 10;
2965 break;
2966
2967 case SFmode:
2968 if (addr == NULL_RTX)
2969 {
2970 if (REG_P (src))
2971 return 2;
2972
2973 if (satisfies_constraint_G (src))
2974 return 2;
2975
2976 return 6;
2977 }
2978
2979 base_length = 10;
2980 break;
2981
2982 default:
2983 gcc_unreachable ();
2984 }
2985
2986 /* Adjust the length based on the addressing mode used.
2987 Specifically, we subtract the difference between the actual
2988 length and the longest one, which is @(d:24,ERs). */
2989
2990 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2991 if (GET_CODE (addr) == PRE_DEC
2992 || GET_CODE (addr) == POST_INC)
2993 return base_length - 6;
2994
2995 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2996 if (GET_CODE (addr) == REG)
2997 return base_length - 6;
2998
2999 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3000 longest. */
3001 if (GET_CODE (addr) == PLUS
3002 && GET_CODE (XEXP (addr, 0)) == REG
3003 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3004 && INTVAL (XEXP (addr, 1)) > -32768
3005 && INTVAL (XEXP (addr, 1)) < 32767)
3006 return base_length - 4;
3007
3008 /* @aa:16 is 4 bytes shorter than the longest. */
3009 if (h8300_tiny_constant_address_p (addr))
3010 return base_length - 4;
3011
3012 /* @aa:24 is 2 bytes shorter than the longest. */
3013 if (CONSTANT_P (addr))
3014 return base_length - 2;
3015
3016 return base_length;
3017 }
3018 }
3019
3020 /* Output an addition insn. */
3021
3022 const char *
output_plussi(rtx * operands)3023 output_plussi (rtx *operands)
3024 {
3025 enum machine_mode mode = GET_MODE (operands[0]);
3026
3027 gcc_assert (mode == SImode);
3028
3029 if (TARGET_H8300)
3030 {
3031 if (GET_CODE (operands[2]) == REG)
3032 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3033
3034 if (GET_CODE (operands[2]) == CONST_INT)
3035 {
3036 HOST_WIDE_INT n = INTVAL (operands[2]);
3037
3038 if ((n & 0xffffff) == 0)
3039 return "add\t%z2,%z0";
3040 if ((n & 0xffff) == 0)
3041 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3042 if ((n & 0xff) == 0)
3043 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3044 }
3045
3046 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3047 }
3048 else
3049 {
3050 if (GET_CODE (operands[2]) == CONST_INT
3051 && register_operand (operands[1], VOIDmode))
3052 {
3053 HOST_WIDE_INT intval = INTVAL (operands[2]);
3054
3055 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3056 return "add.l\t%S2,%S0";
3057 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3058 return "sub.l\t%G2,%S0";
3059
3060 /* See if we can finish with 2 bytes. */
3061
3062 switch ((unsigned int) intval & 0xffffffff)
3063 {
3064 case 0x00000001:
3065 case 0x00000002:
3066 case 0x00000004:
3067 return "adds\t%2,%S0";
3068
3069 case 0xffffffff:
3070 case 0xfffffffe:
3071 case 0xfffffffc:
3072 return "subs\t%G2,%S0";
3073
3074 case 0x00010000:
3075 case 0x00020000:
3076 operands[2] = GEN_INT (intval >> 16);
3077 return "inc.w\t%2,%e0";
3078
3079 case 0xffff0000:
3080 case 0xfffe0000:
3081 operands[2] = GEN_INT (intval >> 16);
3082 return "dec.w\t%G2,%e0";
3083 }
3084
3085 /* See if we can finish with 4 bytes. */
3086 if ((intval & 0xffff) == 0)
3087 {
3088 operands[2] = GEN_INT (intval >> 16);
3089 return "add.w\t%2,%e0";
3090 }
3091 }
3092
3093 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3094 {
3095 operands[2] = GEN_INT (-INTVAL (operands[2]));
3096 return "sub.l\t%S2,%S0";
3097 }
3098 return "add.l\t%S2,%S0";
3099 }
3100 }
3101
3102 /* ??? It would be much easier to add the h8sx stuff if a single function
3103 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3104 /* Compute the length of an addition insn. */
3105
3106 unsigned int
compute_plussi_length(rtx * operands)3107 compute_plussi_length (rtx *operands)
3108 {
3109 enum machine_mode mode = GET_MODE (operands[0]);
3110
3111 gcc_assert (mode == SImode);
3112
3113 if (TARGET_H8300)
3114 {
3115 if (GET_CODE (operands[2]) == REG)
3116 return 6;
3117
3118 if (GET_CODE (operands[2]) == CONST_INT)
3119 {
3120 HOST_WIDE_INT n = INTVAL (operands[2]);
3121
3122 if ((n & 0xffffff) == 0)
3123 return 2;
3124 if ((n & 0xffff) == 0)
3125 return 4;
3126 if ((n & 0xff) == 0)
3127 return 6;
3128 }
3129
3130 return 8;
3131 }
3132 else
3133 {
3134 if (GET_CODE (operands[2]) == CONST_INT
3135 && register_operand (operands[1], VOIDmode))
3136 {
3137 HOST_WIDE_INT intval = INTVAL (operands[2]);
3138
3139 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3140 return 2;
3141 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3142 return 2;
3143
3144 /* See if we can finish with 2 bytes. */
3145
3146 switch ((unsigned int) intval & 0xffffffff)
3147 {
3148 case 0x00000001:
3149 case 0x00000002:
3150 case 0x00000004:
3151 return 2;
3152
3153 case 0xffffffff:
3154 case 0xfffffffe:
3155 case 0xfffffffc:
3156 return 2;
3157
3158 case 0x00010000:
3159 case 0x00020000:
3160 return 2;
3161
3162 case 0xffff0000:
3163 case 0xfffe0000:
3164 return 2;
3165 }
3166
3167 /* See if we can finish with 4 bytes. */
3168 if ((intval & 0xffff) == 0)
3169 return 4;
3170 }
3171
3172 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3173 return h8300_length_from_table (operands[0],
3174 GEN_INT (-INTVAL (operands[2])),
3175 &addl_length_table);
3176 else
3177 return h8300_length_from_table (operands[0], operands[2],
3178 &addl_length_table);
3179 return 6;
3180 }
3181 }
3182
3183 /* Compute which flag bits are valid after an addition insn. */
3184
3185 enum attr_cc
compute_plussi_cc(rtx * operands)3186 compute_plussi_cc (rtx *operands)
3187 {
3188 enum machine_mode mode = GET_MODE (operands[0]);
3189
3190 gcc_assert (mode == SImode);
3191
3192 if (TARGET_H8300)
3193 {
3194 return CC_CLOBBER;
3195 }
3196 else
3197 {
3198 if (GET_CODE (operands[2]) == CONST_INT
3199 && register_operand (operands[1], VOIDmode))
3200 {
3201 HOST_WIDE_INT intval = INTVAL (operands[2]);
3202
3203 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3204 return CC_SET_ZN;
3205 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3206 return CC_SET_ZN;
3207
3208 /* See if we can finish with 2 bytes. */
3209
3210 switch ((unsigned int) intval & 0xffffffff)
3211 {
3212 case 0x00000001:
3213 case 0x00000002:
3214 case 0x00000004:
3215 return CC_NONE_0HIT;
3216
3217 case 0xffffffff:
3218 case 0xfffffffe:
3219 case 0xfffffffc:
3220 return CC_NONE_0HIT;
3221
3222 case 0x00010000:
3223 case 0x00020000:
3224 return CC_CLOBBER;
3225
3226 case 0xffff0000:
3227 case 0xfffe0000:
3228 return CC_CLOBBER;
3229 }
3230
3231 /* See if we can finish with 4 bytes. */
3232 if ((intval & 0xffff) == 0)
3233 return CC_CLOBBER;
3234 }
3235
3236 return CC_SET_ZN;
3237 }
3238 }
3239
3240 /* Output a logical insn. */
3241
3242 const char *
output_logical_op(enum machine_mode mode,rtx * operands)3243 output_logical_op (enum machine_mode mode, rtx *operands)
3244 {
3245 /* Figure out the logical op that we need to perform. */
3246 enum rtx_code code = GET_CODE (operands[3]);
3247 /* Pretend that every byte is affected if both operands are registers. */
3248 const unsigned HOST_WIDE_INT intval =
3249 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3250 /* Always use the full instruction if the
3251 first operand is in memory. It is better
3252 to use define_splits to generate the shorter
3253 sequence where valid. */
3254 && register_operand (operands[1], VOIDmode)
3255 ? INTVAL (operands[2]) : 0x55555555);
3256 /* The determinant of the algorithm. If we perform an AND, 0
3257 affects a bit. Otherwise, 1 affects a bit. */
3258 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3259 /* Break up DET into pieces. */
3260 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3261 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3262 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3263 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3264 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3265 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3266 int lower_half_easy_p = 0;
3267 int upper_half_easy_p = 0;
3268 /* The name of an insn. */
3269 const char *opname;
3270 char insn_buf[100];
3271
3272 switch (code)
3273 {
3274 case AND:
3275 opname = "and";
3276 break;
3277 case IOR:
3278 opname = "or";
3279 break;
3280 case XOR:
3281 opname = "xor";
3282 break;
3283 default:
3284 gcc_unreachable ();
3285 }
3286
3287 switch (mode)
3288 {
3289 case HImode:
3290 /* First, see if we can finish with one insn. */
3291 if ((TARGET_H8300H || TARGET_H8300S)
3292 && b0 != 0
3293 && b1 != 0)
3294 {
3295 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3296 output_asm_insn (insn_buf, operands);
3297 }
3298 else
3299 {
3300 /* Take care of the lower byte. */
3301 if (b0 != 0)
3302 {
3303 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3304 output_asm_insn (insn_buf, operands);
3305 }
3306 /* Take care of the upper byte. */
3307 if (b1 != 0)
3308 {
3309 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3310 output_asm_insn (insn_buf, operands);
3311 }
3312 }
3313 break;
3314 case SImode:
3315 if (TARGET_H8300H || TARGET_H8300S)
3316 {
3317 /* Determine if the lower half can be taken care of in no more
3318 than two bytes. */
3319 lower_half_easy_p = (b0 == 0
3320 || b1 == 0
3321 || (code != IOR && w0 == 0xffff));
3322
3323 /* Determine if the upper half can be taken care of in no more
3324 than two bytes. */
3325 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3326 || (code == AND && w1 == 0xff00));
3327 }
3328
3329 /* Check if doing everything with one insn is no worse than
3330 using multiple insns. */
3331 if ((TARGET_H8300H || TARGET_H8300S)
3332 && w0 != 0 && w1 != 0
3333 && !(lower_half_easy_p && upper_half_easy_p)
3334 && !(code == IOR && w1 == 0xffff
3335 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3336 {
3337 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3338 output_asm_insn (insn_buf, operands);
3339 }
3340 else
3341 {
3342 /* Take care of the lower and upper words individually. For
3343 each word, we try different methods in the order of
3344
3345 1) the special insn (in case of AND or XOR),
3346 2) the word-wise insn, and
3347 3) The byte-wise insn. */
3348 if (w0 == 0xffff
3349 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3350 output_asm_insn ((code == AND)
3351 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3352 operands);
3353 else if ((TARGET_H8300H || TARGET_H8300S)
3354 && (b0 != 0)
3355 && (b1 != 0))
3356 {
3357 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3358 output_asm_insn (insn_buf, operands);
3359 }
3360 else
3361 {
3362 if (b0 != 0)
3363 {
3364 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3365 output_asm_insn (insn_buf, operands);
3366 }
3367 if (b1 != 0)
3368 {
3369 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3370 output_asm_insn (insn_buf, operands);
3371 }
3372 }
3373
3374 if ((w1 == 0xffff)
3375 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3376 output_asm_insn ((code == AND)
3377 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3378 operands);
3379 else if ((TARGET_H8300H || TARGET_H8300S)
3380 && code == IOR
3381 && w1 == 0xffff
3382 && (w0 & 0x8000) != 0)
3383 {
3384 output_asm_insn ("exts.l\t%S0", operands);
3385 }
3386 else if ((TARGET_H8300H || TARGET_H8300S)
3387 && code == AND
3388 && w1 == 0xff00)
3389 {
3390 output_asm_insn ("extu.w\t%e0", operands);
3391 }
3392 else if (TARGET_H8300H || TARGET_H8300S)
3393 {
3394 if (w1 != 0)
3395 {
3396 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3397 output_asm_insn (insn_buf, operands);
3398 }
3399 }
3400 else
3401 {
3402 if (b2 != 0)
3403 {
3404 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3405 output_asm_insn (insn_buf, operands);
3406 }
3407 if (b3 != 0)
3408 {
3409 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3410 output_asm_insn (insn_buf, operands);
3411 }
3412 }
3413 }
3414 break;
3415 default:
3416 gcc_unreachable ();
3417 }
3418 return "";
3419 }
3420
3421 /* Compute the length of a logical insn. */
3422
3423 unsigned int
compute_logical_op_length(enum machine_mode mode,rtx * operands)3424 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3425 {
3426 /* Figure out the logical op that we need to perform. */
3427 enum rtx_code code = GET_CODE (operands[3]);
3428 /* Pretend that every byte is affected if both operands are registers. */
3429 const unsigned HOST_WIDE_INT intval =
3430 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3431 /* Always use the full instruction if the
3432 first operand is in memory. It is better
3433 to use define_splits to generate the shorter
3434 sequence where valid. */
3435 && register_operand (operands[1], VOIDmode)
3436 ? INTVAL (operands[2]) : 0x55555555);
3437 /* The determinant of the algorithm. If we perform an AND, 0
3438 affects a bit. Otherwise, 1 affects a bit. */
3439 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3440 /* Break up DET into pieces. */
3441 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3442 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3443 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3444 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3445 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3446 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3447 int lower_half_easy_p = 0;
3448 int upper_half_easy_p = 0;
3449 /* Insn length. */
3450 unsigned int length = 0;
3451
3452 switch (mode)
3453 {
3454 case HImode:
3455 /* First, see if we can finish with one insn. */
3456 if ((TARGET_H8300H || TARGET_H8300S)
3457 && b0 != 0
3458 && b1 != 0)
3459 {
3460 length = h8300_length_from_table (operands[1], operands[2],
3461 &logicw_length_table);
3462 }
3463 else
3464 {
3465 /* Take care of the lower byte. */
3466 if (b0 != 0)
3467 length += 2;
3468
3469 /* Take care of the upper byte. */
3470 if (b1 != 0)
3471 length += 2;
3472 }
3473 break;
3474 case SImode:
3475 if (TARGET_H8300H || TARGET_H8300S)
3476 {
3477 /* Determine if the lower half can be taken care of in no more
3478 than two bytes. */
3479 lower_half_easy_p = (b0 == 0
3480 || b1 == 0
3481 || (code != IOR && w0 == 0xffff));
3482
3483 /* Determine if the upper half can be taken care of in no more
3484 than two bytes. */
3485 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3486 || (code == AND && w1 == 0xff00));
3487 }
3488
3489 /* Check if doing everything with one insn is no worse than
3490 using multiple insns. */
3491 if ((TARGET_H8300H || TARGET_H8300S)
3492 && w0 != 0 && w1 != 0
3493 && !(lower_half_easy_p && upper_half_easy_p)
3494 && !(code == IOR && w1 == 0xffff
3495 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3496 {
3497 length = h8300_length_from_table (operands[1], operands[2],
3498 &logicl_length_table);
3499 }
3500 else
3501 {
3502 /* Take care of the lower and upper words individually. For
3503 each word, we try different methods in the order of
3504
3505 1) the special insn (in case of AND or XOR),
3506 2) the word-wise insn, and
3507 3) The byte-wise insn. */
3508 if (w0 == 0xffff
3509 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3510 {
3511 length += 2;
3512 }
3513 else if ((TARGET_H8300H || TARGET_H8300S)
3514 && (b0 != 0)
3515 && (b1 != 0))
3516 {
3517 length += 4;
3518 }
3519 else
3520 {
3521 if (b0 != 0)
3522 length += 2;
3523
3524 if (b1 != 0)
3525 length += 2;
3526 }
3527
3528 if (w1 == 0xffff
3529 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3530 {
3531 length += 2;
3532 }
3533 else if ((TARGET_H8300H || TARGET_H8300S)
3534 && code == IOR
3535 && w1 == 0xffff
3536 && (w0 & 0x8000) != 0)
3537 {
3538 length += 2;
3539 }
3540 else if ((TARGET_H8300H || TARGET_H8300S)
3541 && code == AND
3542 && w1 == 0xff00)
3543 {
3544 length += 2;
3545 }
3546 else if (TARGET_H8300H || TARGET_H8300S)
3547 {
3548 if (w1 != 0)
3549 length += 4;
3550 }
3551 else
3552 {
3553 if (b2 != 0)
3554 length += 2;
3555
3556 if (b3 != 0)
3557 length += 2;
3558 }
3559 }
3560 break;
3561 default:
3562 gcc_unreachable ();
3563 }
3564 return length;
3565 }
3566
3567 /* Compute which flag bits are valid after a logical insn. */
3568
3569 enum attr_cc
compute_logical_op_cc(enum machine_mode mode,rtx * operands)3570 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3571 {
3572 /* Figure out the logical op that we need to perform. */
3573 enum rtx_code code = GET_CODE (operands[3]);
3574 /* Pretend that every byte is affected if both operands are registers. */
3575 const unsigned HOST_WIDE_INT intval =
3576 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3577 /* Always use the full instruction if the
3578 first operand is in memory. It is better
3579 to use define_splits to generate the shorter
3580 sequence where valid. */
3581 && register_operand (operands[1], VOIDmode)
3582 ? INTVAL (operands[2]) : 0x55555555);
3583 /* The determinant of the algorithm. If we perform an AND, 0
3584 affects a bit. Otherwise, 1 affects a bit. */
3585 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3586 /* Break up DET into pieces. */
3587 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3588 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3589 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3590 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3591 int lower_half_easy_p = 0;
3592 int upper_half_easy_p = 0;
3593 /* Condition code. */
3594 enum attr_cc cc = CC_CLOBBER;
3595
3596 switch (mode)
3597 {
3598 case HImode:
3599 /* First, see if we can finish with one insn. */
3600 if ((TARGET_H8300H || TARGET_H8300S)
3601 && b0 != 0
3602 && b1 != 0)
3603 {
3604 cc = CC_SET_ZNV;
3605 }
3606 break;
3607 case SImode:
3608 if (TARGET_H8300H || TARGET_H8300S)
3609 {
3610 /* Determine if the lower half can be taken care of in no more
3611 than two bytes. */
3612 lower_half_easy_p = (b0 == 0
3613 || b1 == 0
3614 || (code != IOR && w0 == 0xffff));
3615
3616 /* Determine if the upper half can be taken care of in no more
3617 than two bytes. */
3618 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3619 || (code == AND && w1 == 0xff00));
3620 }
3621
3622 /* Check if doing everything with one insn is no worse than
3623 using multiple insns. */
3624 if ((TARGET_H8300H || TARGET_H8300S)
3625 && w0 != 0 && w1 != 0
3626 && !(lower_half_easy_p && upper_half_easy_p)
3627 && !(code == IOR && w1 == 0xffff
3628 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3629 {
3630 cc = CC_SET_ZNV;
3631 }
3632 else
3633 {
3634 if ((TARGET_H8300H || TARGET_H8300S)
3635 && code == IOR
3636 && w1 == 0xffff
3637 && (w0 & 0x8000) != 0)
3638 {
3639 cc = CC_SET_ZNV;
3640 }
3641 }
3642 break;
3643 default:
3644 gcc_unreachable ();
3645 }
3646 return cc;
3647 }
3648
3649 /* Expand a conditional branch. */
3650
3651 void
h8300_expand_branch(rtx operands[])3652 h8300_expand_branch (rtx operands[])
3653 {
3654 enum rtx_code code = GET_CODE (operands[0]);
3655 rtx op0 = operands[1];
3656 rtx op1 = operands[2];
3657 rtx label = operands[3];
3658 rtx tmp;
3659
3660 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3661 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3662
3663 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3664 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3665 gen_rtx_LABEL_REF (VOIDmode, label),
3666 pc_rtx);
3667 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3668 }
3669
3670
3671 /* Expand a conditional store. */
3672
3673 void
h8300_expand_store(rtx operands[])3674 h8300_expand_store (rtx operands[])
3675 {
3676 rtx dest = operands[0];
3677 enum rtx_code code = GET_CODE (operands[1]);
3678 rtx op0 = operands[2];
3679 rtx op1 = operands[3];
3680 rtx tmp;
3681
3682 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3683 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3684
3685 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3686 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3687 }
3688
3689 /* Shifts.
3690
3691 We devote a fair bit of code to getting efficient shifts since we
3692 can only shift one bit at a time on the H8/300 and H8/300H and only
3693 one or two bits at a time on the H8S.
3694
3695 All shift code falls into one of the following ways of
3696 implementation:
3697
3698 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3699 when a straight line shift is about the same size or smaller than
3700 a loop.
3701
3702 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3703 off the bits we don't need. This is used when only a few of the
3704 bits in the original value will survive in the shifted value.
3705
3706 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3707 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3708 shifts can be added if the shift count is slightly more than 8 or
3709 16. This case also includes other oddballs that are not worth
3710 explaining here.
3711
3712 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3713
3714 For each shift count, we try to use code that has no trade-off
3715 between code size and speed whenever possible.
3716
3717 If the trade-off is unavoidable, we try to be reasonable.
3718 Specifically, the fastest version is one instruction longer than
3719 the shortest version, we take the fastest version. We also provide
3720 the use a way to switch back to the shortest version with -Os.
3721
3722 For the details of the shift algorithms for various shift counts,
3723 refer to shift_alg_[qhs]i. */
3724
3725 /* Classify a shift with the given mode and code. OP is the shift amount. */
3726
3727 enum h8sx_shift_type
h8sx_classify_shift(enum machine_mode mode,enum rtx_code code,rtx op)3728 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3729 {
3730 if (!TARGET_H8300SX)
3731 return H8SX_SHIFT_NONE;
3732
3733 switch (code)
3734 {
3735 case ASHIFT:
3736 case LSHIFTRT:
3737 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3738 if (GET_CODE (op) != CONST_INT)
3739 return H8SX_SHIFT_BINARY;
3740
3741 /* Reject out-of-range shift amounts. */
3742 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3743 return H8SX_SHIFT_NONE;
3744
3745 /* Power-of-2 shifts are effectively unary operations. */
3746 if (exact_log2 (INTVAL (op)) >= 0)
3747 return H8SX_SHIFT_UNARY;
3748
3749 return H8SX_SHIFT_BINARY;
3750
3751 case ASHIFTRT:
3752 if (op == const1_rtx || op == const2_rtx)
3753 return H8SX_SHIFT_UNARY;
3754 return H8SX_SHIFT_NONE;
3755
3756 case ROTATE:
3757 if (GET_CODE (op) == CONST_INT
3758 && (INTVAL (op) == 1
3759 || INTVAL (op) == 2
3760 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3761 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3762 return H8SX_SHIFT_UNARY;
3763 return H8SX_SHIFT_NONE;
3764
3765 default:
3766 return H8SX_SHIFT_NONE;
3767 }
3768 }
3769
3770 /* Return the asm template for a single h8sx shift instruction.
3771 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3772 is the source and OPERANDS[3] is the shift. SUFFIX is the
3773 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3774 prefix for the destination operand. */
3775
3776 const char *
output_h8sx_shift(rtx * operands,int suffix,int optype)3777 output_h8sx_shift (rtx *operands, int suffix, int optype)
3778 {
3779 static char buffer[16];
3780 const char *stem;
3781
3782 switch (GET_CODE (operands[3]))
3783 {
3784 case ASHIFT:
3785 stem = "shll";
3786 break;
3787
3788 case ASHIFTRT:
3789 stem = "shar";
3790 break;
3791
3792 case LSHIFTRT:
3793 stem = "shlr";
3794 break;
3795
3796 case ROTATE:
3797 stem = "rotl";
3798 if (INTVAL (operands[2]) > 2)
3799 {
3800 /* This is really a right rotate. */
3801 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3802 - INTVAL (operands[2]));
3803 stem = "rotr";
3804 }
3805 break;
3806
3807 default:
3808 gcc_unreachable ();
3809 }
3810 if (operands[2] == const1_rtx)
3811 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3812 else
3813 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3814 return buffer;
3815 }
3816
3817 /* Emit code to do shifts. */
3818
3819 bool
expand_a_shift(enum machine_mode mode,enum rtx_code code,rtx operands[])3820 expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
3821 {
3822 switch (h8sx_classify_shift (mode, code, operands[2]))
3823 {
3824 case H8SX_SHIFT_BINARY:
3825 operands[1] = force_reg (mode, operands[1]);
3826 return false;
3827
3828 case H8SX_SHIFT_UNARY:
3829 return false;
3830
3831 case H8SX_SHIFT_NONE:
3832 break;
3833 }
3834
3835 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3836
3837 /* Need a loop to get all the bits we want - we generate the
3838 code at emit time, but need to allocate a scratch reg now. */
3839
3840 emit_insn (gen_rtx_PARALLEL
3841 (VOIDmode,
3842 gen_rtvec (2,
3843 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3844 gen_rtx_fmt_ee (code, mode,
3845 copy_rtx (operands[0]), operands[2])),
3846 gen_rtx_CLOBBER (VOIDmode,
3847 gen_rtx_SCRATCH (QImode)))));
3848 return true;
3849 }
3850
3851 /* Symbols of the various modes which can be used as indices. */
3852
3853 enum shift_mode
3854 {
3855 QIshift, HIshift, SIshift
3856 };
3857
3858 /* For single bit shift insns, record assembler and what bits of the
3859 condition code are valid afterwards (represented as various CC_FOO
3860 bits, 0 means CC isn't left in a usable state). */
3861
3862 struct shift_insn
3863 {
3864 const char *const assembler;
3865 const enum attr_cc cc_valid;
3866 };
3867
3868 /* Assembler instruction shift table.
3869
3870 These tables are used to look up the basic shifts.
3871 They are indexed by cpu, shift_type, and mode. */
3872
3873 static const struct shift_insn shift_one[2][3][3] =
3874 {
3875 /* H8/300 */
3876 {
3877 /* SHIFT_ASHIFT */
3878 {
3879 { "shll\t%X0", CC_SET_ZNV },
3880 { "add.w\t%T0,%T0", CC_SET_ZN },
3881 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3882 },
3883 /* SHIFT_LSHIFTRT */
3884 {
3885 { "shlr\t%X0", CC_SET_ZNV },
3886 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3887 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3888 },
3889 /* SHIFT_ASHIFTRT */
3890 {
3891 { "shar\t%X0", CC_SET_ZNV },
3892 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3893 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3894 }
3895 },
3896 /* H8/300H */
3897 {
3898 /* SHIFT_ASHIFT */
3899 {
3900 { "shll.b\t%X0", CC_SET_ZNV },
3901 { "shll.w\t%T0", CC_SET_ZNV },
3902 { "shll.l\t%S0", CC_SET_ZNV }
3903 },
3904 /* SHIFT_LSHIFTRT */
3905 {
3906 { "shlr.b\t%X0", CC_SET_ZNV },
3907 { "shlr.w\t%T0", CC_SET_ZNV },
3908 { "shlr.l\t%S0", CC_SET_ZNV }
3909 },
3910 /* SHIFT_ASHIFTRT */
3911 {
3912 { "shar.b\t%X0", CC_SET_ZNV },
3913 { "shar.w\t%T0", CC_SET_ZNV },
3914 { "shar.l\t%S0", CC_SET_ZNV }
3915 }
3916 }
3917 };
3918
3919 static const struct shift_insn shift_two[3][3] =
3920 {
3921 /* SHIFT_ASHIFT */
3922 {
3923 { "shll.b\t#2,%X0", CC_SET_ZNV },
3924 { "shll.w\t#2,%T0", CC_SET_ZNV },
3925 { "shll.l\t#2,%S0", CC_SET_ZNV }
3926 },
3927 /* SHIFT_LSHIFTRT */
3928 {
3929 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3930 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3931 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3932 },
3933 /* SHIFT_ASHIFTRT */
3934 {
3935 { "shar.b\t#2,%X0", CC_SET_ZNV },
3936 { "shar.w\t#2,%T0", CC_SET_ZNV },
3937 { "shar.l\t#2,%S0", CC_SET_ZNV }
3938 }
3939 };
3940
3941 /* Rotates are organized by which shift they'll be used in implementing.
3942 There's no need to record whether the cc is valid afterwards because
3943 it is the AND insn that will decide this. */
3944
3945 static const char *const rotate_one[2][3][3] =
3946 {
3947 /* H8/300 */
3948 {
3949 /* SHIFT_ASHIFT */
3950 {
3951 "rotr\t%X0",
3952 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3953 0
3954 },
3955 /* SHIFT_LSHIFTRT */
3956 {
3957 "rotl\t%X0",
3958 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3959 0
3960 },
3961 /* SHIFT_ASHIFTRT */
3962 {
3963 "rotl\t%X0",
3964 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3965 0
3966 }
3967 },
3968 /* H8/300H */
3969 {
3970 /* SHIFT_ASHIFT */
3971 {
3972 "rotr.b\t%X0",
3973 "rotr.w\t%T0",
3974 "rotr.l\t%S0"
3975 },
3976 /* SHIFT_LSHIFTRT */
3977 {
3978 "rotl.b\t%X0",
3979 "rotl.w\t%T0",
3980 "rotl.l\t%S0"
3981 },
3982 /* SHIFT_ASHIFTRT */
3983 {
3984 "rotl.b\t%X0",
3985 "rotl.w\t%T0",
3986 "rotl.l\t%S0"
3987 }
3988 }
3989 };
3990
3991 static const char *const rotate_two[3][3] =
3992 {
3993 /* SHIFT_ASHIFT */
3994 {
3995 "rotr.b\t#2,%X0",
3996 "rotr.w\t#2,%T0",
3997 "rotr.l\t#2,%S0"
3998 },
3999 /* SHIFT_LSHIFTRT */
4000 {
4001 "rotl.b\t#2,%X0",
4002 "rotl.w\t#2,%T0",
4003 "rotl.l\t#2,%S0"
4004 },
4005 /* SHIFT_ASHIFTRT */
4006 {
4007 "rotl.b\t#2,%X0",
4008 "rotl.w\t#2,%T0",
4009 "rotl.l\t#2,%S0"
4010 }
4011 };
4012
4013 struct shift_info {
4014 /* Shift algorithm. */
4015 enum shift_alg alg;
4016
4017 /* The number of bits to be shifted by shift1 and shift2. Valid
4018 when ALG is SHIFT_SPECIAL. */
4019 unsigned int remainder;
4020
4021 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4022 const char *special;
4023
4024 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4025 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4026 const char *shift1;
4027
4028 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4029 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4030 const char *shift2;
4031
4032 /* CC status for SHIFT_INLINE. */
4033 enum attr_cc cc_inline;
4034
4035 /* CC status for SHIFT_SPECIAL. */
4036 enum attr_cc cc_special;
4037 };
4038
4039 static void get_shift_alg (enum shift_type,
4040 enum shift_mode, unsigned int,
4041 struct shift_info *);
4042
4043 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4044 best algorithm for doing the shift. The assembler code is stored
4045 in the pointers in INFO. We achieve the maximum efficiency in most
4046 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4047 SImode in particular have a lot of room to optimize.
4048
4049 We first determine the strategy of the shift algorithm by a table
4050 lookup. If that tells us to use a hand crafted assembly code, we
4051 go into the big switch statement to find what that is. Otherwise,
4052 we resort to a generic way, such as inlining. In either case, the
4053 result is returned through INFO. */
4054
4055 static void
get_shift_alg(enum shift_type shift_type,enum shift_mode shift_mode,unsigned int count,struct shift_info * info)4056 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4057 unsigned int count, struct shift_info *info)
4058 {
4059 enum h8_cpu cpu;
4060
4061 /* Find the target CPU. */
4062 if (TARGET_H8300)
4063 cpu = H8_300;
4064 else if (TARGET_H8300H)
4065 cpu = H8_300H;
4066 else
4067 cpu = H8_S;
4068
4069 /* Find the shift algorithm. */
4070 info->alg = SHIFT_LOOP;
4071 switch (shift_mode)
4072 {
4073 case QIshift:
4074 if (count < GET_MODE_BITSIZE (QImode))
4075 info->alg = shift_alg_qi[cpu][shift_type][count];
4076 break;
4077
4078 case HIshift:
4079 if (count < GET_MODE_BITSIZE (HImode))
4080 info->alg = shift_alg_hi[cpu][shift_type][count];
4081 break;
4082
4083 case SIshift:
4084 if (count < GET_MODE_BITSIZE (SImode))
4085 info->alg = shift_alg_si[cpu][shift_type][count];
4086 break;
4087
4088 default:
4089 gcc_unreachable ();
4090 }
4091
4092 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4093 switch (info->alg)
4094 {
4095 case SHIFT_INLINE:
4096 info->remainder = count;
4097 /* Fall through. */
4098
4099 case SHIFT_LOOP:
4100 /* It is up to the caller to know that looping clobbers cc. */
4101 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4102 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4103 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4104 goto end;
4105
4106 case SHIFT_ROT_AND:
4107 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4108 info->shift2 = rotate_two[shift_type][shift_mode];
4109 info->cc_inline = CC_CLOBBER;
4110 goto end;
4111
4112 case SHIFT_SPECIAL:
4113 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4114 info->remainder = 0;
4115 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4116 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4117 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4118 info->cc_special = CC_CLOBBER;
4119 break;
4120 }
4121
4122 /* Here we only deal with SHIFT_SPECIAL. */
4123 switch (shift_mode)
4124 {
4125 case QIshift:
4126 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4127 through the entire value. */
4128 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4129 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4130 goto end;
4131
4132 case HIshift:
4133 if (count == 7)
4134 {
4135 switch (shift_type)
4136 {
4137 case SHIFT_ASHIFT:
4138 if (TARGET_H8300)
4139 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4140 else
4141 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4142 goto end;
4143 case SHIFT_LSHIFTRT:
4144 if (TARGET_H8300)
4145 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4146 else
4147 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4148 goto end;
4149 case SHIFT_ASHIFTRT:
4150 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4151 goto end;
4152 }
4153 }
4154 else if ((8 <= count && count <= 13)
4155 || (TARGET_H8300S && count == 14))
4156 {
4157 info->remainder = count - 8;
4158
4159 switch (shift_type)
4160 {
4161 case SHIFT_ASHIFT:
4162 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4163 goto end;
4164 case SHIFT_LSHIFTRT:
4165 if (TARGET_H8300)
4166 {
4167 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4168 info->shift1 = "shlr.b\t%s0";
4169 info->cc_inline = CC_SET_ZNV;
4170 }
4171 else
4172 {
4173 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4174 info->cc_special = CC_SET_ZNV;
4175 }
4176 goto end;
4177 case SHIFT_ASHIFTRT:
4178 if (TARGET_H8300)
4179 {
4180 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4181 info->shift1 = "shar.b\t%s0";
4182 }
4183 else
4184 {
4185 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4186 info->cc_special = CC_SET_ZNV;
4187 }
4188 goto end;
4189 }
4190 }
4191 else if (count == 14)
4192 {
4193 switch (shift_type)
4194 {
4195 case SHIFT_ASHIFT:
4196 if (TARGET_H8300)
4197 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4198 goto end;
4199 case SHIFT_LSHIFTRT:
4200 if (TARGET_H8300)
4201 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4202 goto end;
4203 case SHIFT_ASHIFTRT:
4204 if (TARGET_H8300)
4205 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4206 else if (TARGET_H8300H)
4207 {
4208 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4209 info->cc_special = CC_SET_ZNV;
4210 }
4211 else /* TARGET_H8300S */
4212 gcc_unreachable ();
4213 goto end;
4214 }
4215 }
4216 else if (count == 15)
4217 {
4218 switch (shift_type)
4219 {
4220 case SHIFT_ASHIFT:
4221 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4222 goto end;
4223 case SHIFT_LSHIFTRT:
4224 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4225 goto end;
4226 case SHIFT_ASHIFTRT:
4227 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4228 goto end;
4229 }
4230 }
4231 gcc_unreachable ();
4232
4233 case SIshift:
4234 if (TARGET_H8300 && 8 <= count && count <= 9)
4235 {
4236 info->remainder = count - 8;
4237
4238 switch (shift_type)
4239 {
4240 case SHIFT_ASHIFT:
4241 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4242 goto end;
4243 case SHIFT_LSHIFTRT:
4244 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4245 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4246 goto end;
4247 case SHIFT_ASHIFTRT:
4248 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4249 goto end;
4250 }
4251 }
4252 else if (count == 8 && !TARGET_H8300)
4253 {
4254 switch (shift_type)
4255 {
4256 case SHIFT_ASHIFT:
4257 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4258 goto end;
4259 case SHIFT_LSHIFTRT:
4260 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4261 goto end;
4262 case SHIFT_ASHIFTRT:
4263 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4264 goto end;
4265 }
4266 }
4267 else if (count == 15 && TARGET_H8300)
4268 {
4269 switch (shift_type)
4270 {
4271 case SHIFT_ASHIFT:
4272 gcc_unreachable ();
4273 case SHIFT_LSHIFTRT:
4274 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4275 goto end;
4276 case SHIFT_ASHIFTRT:
4277 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4278 goto end;
4279 }
4280 }
4281 else if (count == 15 && !TARGET_H8300)
4282 {
4283 switch (shift_type)
4284 {
4285 case SHIFT_ASHIFT:
4286 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4287 info->cc_special = CC_SET_ZNV;
4288 goto end;
4289 case SHIFT_LSHIFTRT:
4290 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4291 info->cc_special = CC_SET_ZNV;
4292 goto end;
4293 case SHIFT_ASHIFTRT:
4294 gcc_unreachable ();
4295 }
4296 }
4297 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4298 || (TARGET_H8300H && 16 <= count && count <= 19)
4299 || (TARGET_H8300S && 16 <= count && count <= 21))
4300 {
4301 info->remainder = count - 16;
4302
4303 switch (shift_type)
4304 {
4305 case SHIFT_ASHIFT:
4306 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4307 if (TARGET_H8300)
4308 info->shift1 = "add.w\t%e0,%e0";
4309 goto end;
4310 case SHIFT_LSHIFTRT:
4311 if (TARGET_H8300)
4312 {
4313 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4314 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4315 }
4316 else
4317 {
4318 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4319 info->cc_special = CC_SET_ZNV;
4320 }
4321 goto end;
4322 case SHIFT_ASHIFTRT:
4323 if (TARGET_H8300)
4324 {
4325 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4326 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4327 }
4328 else
4329 {
4330 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4331 info->cc_special = CC_SET_ZNV;
4332 }
4333 goto end;
4334 }
4335 }
4336 else if (TARGET_H8300 && 24 <= count && count <= 28)
4337 {
4338 info->remainder = count - 24;
4339
4340 switch (shift_type)
4341 {
4342 case SHIFT_ASHIFT:
4343 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4344 info->shift1 = "shll.b\t%z0";
4345 info->cc_inline = CC_SET_ZNV;
4346 goto end;
4347 case SHIFT_LSHIFTRT:
4348 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4349 info->shift1 = "shlr.b\t%w0";
4350 info->cc_inline = CC_SET_ZNV;
4351 goto end;
4352 case SHIFT_ASHIFTRT:
4353 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4354 info->shift1 = "shar.b\t%w0";
4355 info->cc_inline = CC_SET_ZNV;
4356 goto end;
4357 }
4358 }
4359 else if ((TARGET_H8300H && count == 24)
4360 || (TARGET_H8300S && 24 <= count && count <= 25))
4361 {
4362 info->remainder = count - 24;
4363
4364 switch (shift_type)
4365 {
4366 case SHIFT_ASHIFT:
4367 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4368 goto end;
4369 case SHIFT_LSHIFTRT:
4370 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4371 info->cc_special = CC_SET_ZNV;
4372 goto end;
4373 case SHIFT_ASHIFTRT:
4374 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4375 info->cc_special = CC_SET_ZNV;
4376 goto end;
4377 }
4378 }
4379 else if (!TARGET_H8300 && count == 28)
4380 {
4381 switch (shift_type)
4382 {
4383 case SHIFT_ASHIFT:
4384 if (TARGET_H8300H)
4385 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4386 else
4387 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4388 goto end;
4389 case SHIFT_LSHIFTRT:
4390 if (TARGET_H8300H)
4391 {
4392 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4393 info->cc_special = CC_SET_ZNV;
4394 }
4395 else
4396 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4397 goto end;
4398 case SHIFT_ASHIFTRT:
4399 gcc_unreachable ();
4400 }
4401 }
4402 else if (!TARGET_H8300 && count == 29)
4403 {
4404 switch (shift_type)
4405 {
4406 case SHIFT_ASHIFT:
4407 if (TARGET_H8300H)
4408 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4409 else
4410 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4411 goto end;
4412 case SHIFT_LSHIFTRT:
4413 if (TARGET_H8300H)
4414 {
4415 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4416 info->cc_special = CC_SET_ZNV;
4417 }
4418 else
4419 {
4420 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4421 info->cc_special = CC_SET_ZNV;
4422 }
4423 goto end;
4424 case SHIFT_ASHIFTRT:
4425 gcc_unreachable ();
4426 }
4427 }
4428 else if (!TARGET_H8300 && count == 30)
4429 {
4430 switch (shift_type)
4431 {
4432 case SHIFT_ASHIFT:
4433 if (TARGET_H8300H)
4434 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4435 else
4436 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4437 goto end;
4438 case SHIFT_LSHIFTRT:
4439 if (TARGET_H8300H)
4440 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4441 else
4442 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4443 goto end;
4444 case SHIFT_ASHIFTRT:
4445 gcc_unreachable ();
4446 }
4447 }
4448 else if (count == 31)
4449 {
4450 if (TARGET_H8300)
4451 {
4452 switch (shift_type)
4453 {
4454 case SHIFT_ASHIFT:
4455 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4456 goto end;
4457 case SHIFT_LSHIFTRT:
4458 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4459 goto end;
4460 case SHIFT_ASHIFTRT:
4461 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4462 goto end;
4463 }
4464 }
4465 else
4466 {
4467 switch (shift_type)
4468 {
4469 case SHIFT_ASHIFT:
4470 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4471 info->cc_special = CC_SET_ZNV;
4472 goto end;
4473 case SHIFT_LSHIFTRT:
4474 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4475 info->cc_special = CC_SET_ZNV;
4476 goto end;
4477 case SHIFT_ASHIFTRT:
4478 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4479 info->cc_special = CC_SET_ZNV;
4480 goto end;
4481 }
4482 }
4483 }
4484 gcc_unreachable ();
4485
4486 default:
4487 gcc_unreachable ();
4488 }
4489
4490 end:
4491 if (!TARGET_H8300S)
4492 info->shift2 = NULL;
4493 }
4494
4495 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4496 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4497
4498 int
h8300_shift_needs_scratch_p(int count,enum machine_mode mode)4499 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4500 {
4501 enum h8_cpu cpu;
4502 int a, lr, ar;
4503
4504 if (GET_MODE_BITSIZE (mode) <= count)
4505 return 1;
4506
4507 /* Find out the target CPU. */
4508 if (TARGET_H8300)
4509 cpu = H8_300;
4510 else if (TARGET_H8300H)
4511 cpu = H8_300H;
4512 else
4513 cpu = H8_S;
4514
4515 /* Find the shift algorithm. */
4516 switch (mode)
4517 {
4518 case QImode:
4519 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4520 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4521 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4522 break;
4523
4524 case HImode:
4525 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4526 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4527 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4528 break;
4529
4530 case SImode:
4531 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4532 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4533 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4534 break;
4535
4536 default:
4537 gcc_unreachable ();
4538 }
4539
4540 /* On H8/300H, count == 8 uses a scratch register. */
4541 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4542 || (TARGET_H8300H && mode == SImode && count == 8));
4543 }
4544
4545 /* Output the assembler code for doing shifts. */
4546
4547 const char *
output_a_shift(rtx * operands)4548 output_a_shift (rtx *operands)
4549 {
4550 static int loopend_lab;
4551 rtx shift = operands[3];
4552 enum machine_mode mode = GET_MODE (shift);
4553 enum rtx_code code = GET_CODE (shift);
4554 enum shift_type shift_type;
4555 enum shift_mode shift_mode;
4556 struct shift_info info;
4557 int n;
4558
4559 loopend_lab++;
4560
4561 switch (mode)
4562 {
4563 case QImode:
4564 shift_mode = QIshift;
4565 break;
4566 case HImode:
4567 shift_mode = HIshift;
4568 break;
4569 case SImode:
4570 shift_mode = SIshift;
4571 break;
4572 default:
4573 gcc_unreachable ();
4574 }
4575
4576 switch (code)
4577 {
4578 case ASHIFTRT:
4579 shift_type = SHIFT_ASHIFTRT;
4580 break;
4581 case LSHIFTRT:
4582 shift_type = SHIFT_LSHIFTRT;
4583 break;
4584 case ASHIFT:
4585 shift_type = SHIFT_ASHIFT;
4586 break;
4587 default:
4588 gcc_unreachable ();
4589 }
4590
4591 /* This case must be taken care of by one of the two splitters
4592 that convert a variable shift into a loop. */
4593 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4594
4595 n = INTVAL (operands[2]);
4596
4597 /* If the count is negative, make it 0. */
4598 if (n < 0)
4599 n = 0;
4600 /* If the count is too big, truncate it.
4601 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4602 do the intuitive thing. */
4603 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4604 n = GET_MODE_BITSIZE (mode);
4605
4606 get_shift_alg (shift_type, shift_mode, n, &info);
4607
4608 switch (info.alg)
4609 {
4610 case SHIFT_SPECIAL:
4611 output_asm_insn (info.special, operands);
4612 /* Fall through. */
4613
4614 case SHIFT_INLINE:
4615 n = info.remainder;
4616
4617 /* Emit two bit shifts first. */
4618 if (info.shift2 != NULL)
4619 {
4620 for (; n > 1; n -= 2)
4621 output_asm_insn (info.shift2, operands);
4622 }
4623
4624 /* Now emit one bit shifts for any residual. */
4625 for (; n > 0; n--)
4626 output_asm_insn (info.shift1, operands);
4627 return "";
4628
4629 case SHIFT_ROT_AND:
4630 {
4631 int m = GET_MODE_BITSIZE (mode) - n;
4632 const int mask = (shift_type == SHIFT_ASHIFT
4633 ? ((1 << m) - 1) << n
4634 : (1 << m) - 1);
4635 char insn_buf[200];
4636
4637 /* Not all possibilities of rotate are supported. They shouldn't
4638 be generated, but let's watch for 'em. */
4639 gcc_assert (info.shift1);
4640
4641 /* Emit two bit rotates first. */
4642 if (info.shift2 != NULL)
4643 {
4644 for (; m > 1; m -= 2)
4645 output_asm_insn (info.shift2, operands);
4646 }
4647
4648 /* Now single bit rotates for any residual. */
4649 for (; m > 0; m--)
4650 output_asm_insn (info.shift1, operands);
4651
4652 /* Now mask off the high bits. */
4653 switch (mode)
4654 {
4655 case QImode:
4656 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4657 break;
4658
4659 case HImode:
4660 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4661 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4662 break;
4663
4664 default:
4665 gcc_unreachable ();
4666 }
4667
4668 output_asm_insn (insn_buf, operands);
4669 return "";
4670 }
4671
4672 case SHIFT_LOOP:
4673 /* A loop to shift by a "large" constant value.
4674 If we have shift-by-2 insns, use them. */
4675 if (info.shift2 != NULL)
4676 {
4677 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4678 names_big[REGNO (operands[4])]);
4679 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4680 output_asm_insn (info.shift2, operands);
4681 output_asm_insn ("add #0xff,%X4", operands);
4682 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4683 if (n % 2)
4684 output_asm_insn (info.shift1, operands);
4685 }
4686 else
4687 {
4688 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4689 names_big[REGNO (operands[4])]);
4690 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4691 output_asm_insn (info.shift1, operands);
4692 output_asm_insn ("add #0xff,%X4", operands);
4693 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4694 }
4695 return "";
4696
4697 default:
4698 gcc_unreachable ();
4699 }
4700 }
4701
4702 /* Count the number of assembly instructions in a string TEMPL. */
4703
4704 static unsigned int
h8300_asm_insn_count(const char * templ)4705 h8300_asm_insn_count (const char *templ)
4706 {
4707 unsigned int count = 1;
4708
4709 for (; *templ; templ++)
4710 if (*templ == '\n')
4711 count++;
4712
4713 return count;
4714 }
4715
4716 /* Compute the length of a shift insn. */
4717
4718 unsigned int
compute_a_shift_length(rtx insn ATTRIBUTE_UNUSED,rtx * operands)4719 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4720 {
4721 rtx shift = operands[3];
4722 enum machine_mode mode = GET_MODE (shift);
4723 enum rtx_code code = GET_CODE (shift);
4724 enum shift_type shift_type;
4725 enum shift_mode shift_mode;
4726 struct shift_info info;
4727 unsigned int wlength = 0;
4728
4729 switch (mode)
4730 {
4731 case QImode:
4732 shift_mode = QIshift;
4733 break;
4734 case HImode:
4735 shift_mode = HIshift;
4736 break;
4737 case SImode:
4738 shift_mode = SIshift;
4739 break;
4740 default:
4741 gcc_unreachable ();
4742 }
4743
4744 switch (code)
4745 {
4746 case ASHIFTRT:
4747 shift_type = SHIFT_ASHIFTRT;
4748 break;
4749 case LSHIFTRT:
4750 shift_type = SHIFT_LSHIFTRT;
4751 break;
4752 case ASHIFT:
4753 shift_type = SHIFT_ASHIFT;
4754 break;
4755 default:
4756 gcc_unreachable ();
4757 }
4758
4759 if (GET_CODE (operands[2]) != CONST_INT)
4760 {
4761 /* Get the assembler code to do one shift. */
4762 get_shift_alg (shift_type, shift_mode, 1, &info);
4763
4764 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4765 }
4766 else
4767 {
4768 int n = INTVAL (operands[2]);
4769
4770 /* If the count is negative, make it 0. */
4771 if (n < 0)
4772 n = 0;
4773 /* If the count is too big, truncate it.
4774 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4775 do the intuitive thing. */
4776 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4777 n = GET_MODE_BITSIZE (mode);
4778
4779 get_shift_alg (shift_type, shift_mode, n, &info);
4780
4781 switch (info.alg)
4782 {
4783 case SHIFT_SPECIAL:
4784 wlength += h8300_asm_insn_count (info.special);
4785
4786 /* Every assembly instruction used in SHIFT_SPECIAL case
4787 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4788 see xor.l, we just pretend that xor.l counts as two insns
4789 so that the insn length will be computed correctly. */
4790 if (strstr (info.special, "xor.l") != NULL)
4791 wlength++;
4792
4793 /* Fall through. */
4794
4795 case SHIFT_INLINE:
4796 n = info.remainder;
4797
4798 if (info.shift2 != NULL)
4799 {
4800 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4801 n = n % 2;
4802 }
4803
4804 wlength += h8300_asm_insn_count (info.shift1) * n;
4805
4806 return 2 * wlength;
4807
4808 case SHIFT_ROT_AND:
4809 {
4810 int m = GET_MODE_BITSIZE (mode) - n;
4811
4812 /* Not all possibilities of rotate are supported. They shouldn't
4813 be generated, but let's watch for 'em. */
4814 gcc_assert (info.shift1);
4815
4816 if (info.shift2 != NULL)
4817 {
4818 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4819 m = m % 2;
4820 }
4821
4822 wlength += h8300_asm_insn_count (info.shift1) * m;
4823
4824 /* Now mask off the high bits. */
4825 switch (mode)
4826 {
4827 case QImode:
4828 wlength += 1;
4829 break;
4830 case HImode:
4831 wlength += 2;
4832 break;
4833 case SImode:
4834 gcc_assert (!TARGET_H8300);
4835 wlength += 3;
4836 break;
4837 default:
4838 gcc_unreachable ();
4839 }
4840 return 2 * wlength;
4841 }
4842
4843 case SHIFT_LOOP:
4844 /* A loop to shift by a "large" constant value.
4845 If we have shift-by-2 insns, use them. */
4846 if (info.shift2 != NULL)
4847 {
4848 wlength += 3 + h8300_asm_insn_count (info.shift2);
4849 if (n % 2)
4850 wlength += h8300_asm_insn_count (info.shift1);
4851 }
4852 else
4853 {
4854 wlength += 3 + h8300_asm_insn_count (info.shift1);
4855 }
4856 return 2 * wlength;
4857
4858 default:
4859 gcc_unreachable ();
4860 }
4861 }
4862 }
4863
4864 /* Compute which flag bits are valid after a shift insn. */
4865
4866 enum attr_cc
compute_a_shift_cc(rtx insn ATTRIBUTE_UNUSED,rtx * operands)4867 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4868 {
4869 rtx shift = operands[3];
4870 enum machine_mode mode = GET_MODE (shift);
4871 enum rtx_code code = GET_CODE (shift);
4872 enum shift_type shift_type;
4873 enum shift_mode shift_mode;
4874 struct shift_info info;
4875 int n;
4876
4877 switch (mode)
4878 {
4879 case QImode:
4880 shift_mode = QIshift;
4881 break;
4882 case HImode:
4883 shift_mode = HIshift;
4884 break;
4885 case SImode:
4886 shift_mode = SIshift;
4887 break;
4888 default:
4889 gcc_unreachable ();
4890 }
4891
4892 switch (code)
4893 {
4894 case ASHIFTRT:
4895 shift_type = SHIFT_ASHIFTRT;
4896 break;
4897 case LSHIFTRT:
4898 shift_type = SHIFT_LSHIFTRT;
4899 break;
4900 case ASHIFT:
4901 shift_type = SHIFT_ASHIFT;
4902 break;
4903 default:
4904 gcc_unreachable ();
4905 }
4906
4907 /* This case must be taken care of by one of the two splitters
4908 that convert a variable shift into a loop. */
4909 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4910
4911 n = INTVAL (operands[2]);
4912
4913 /* If the count is negative, make it 0. */
4914 if (n < 0)
4915 n = 0;
4916 /* If the count is too big, truncate it.
4917 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4918 do the intuitive thing. */
4919 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4920 n = GET_MODE_BITSIZE (mode);
4921
4922 get_shift_alg (shift_type, shift_mode, n, &info);
4923
4924 switch (info.alg)
4925 {
4926 case SHIFT_SPECIAL:
4927 if (info.remainder == 0)
4928 return info.cc_special;
4929
4930 /* Fall through. */
4931
4932 case SHIFT_INLINE:
4933 return info.cc_inline;
4934
4935 case SHIFT_ROT_AND:
4936 /* This case always ends with an and instruction. */
4937 return CC_SET_ZNV;
4938
4939 case SHIFT_LOOP:
4940 /* A loop to shift by a "large" constant value.
4941 If we have shift-by-2 insns, use them. */
4942 if (info.shift2 != NULL)
4943 {
4944 if (n % 2)
4945 return info.cc_inline;
4946 }
4947 return CC_CLOBBER;
4948
4949 default:
4950 gcc_unreachable ();
4951 }
4952 }
4953
4954 /* A rotation by a non-constant will cause a loop to be generated, in
4955 which a rotation by one bit is used. A rotation by a constant,
4956 including the one in the loop, will be taken care of by
4957 output_a_rotate () at the insn emit time. */
4958
4959 int
expand_a_rotate(rtx operands[])4960 expand_a_rotate (rtx operands[])
4961 {
4962 rtx dst = operands[0];
4963 rtx src = operands[1];
4964 rtx rotate_amount = operands[2];
4965 enum machine_mode mode = GET_MODE (dst);
4966
4967 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4968 return false;
4969
4970 /* We rotate in place. */
4971 emit_move_insn (dst, src);
4972
4973 if (GET_CODE (rotate_amount) != CONST_INT)
4974 {
4975 rtx counter = gen_reg_rtx (QImode);
4976 rtx start_label = gen_label_rtx ();
4977 rtx end_label = gen_label_rtx ();
4978
4979 /* If the rotate amount is less than or equal to 0,
4980 we go out of the loop. */
4981 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4982 QImode, 0, end_label);
4983
4984 /* Initialize the loop counter. */
4985 emit_move_insn (counter, rotate_amount);
4986
4987 emit_label (start_label);
4988
4989 /* Rotate by one bit. */
4990 switch (mode)
4991 {
4992 case QImode:
4993 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4994 break;
4995 case HImode:
4996 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4997 break;
4998 case SImode:
4999 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5000 break;
5001 default:
5002 gcc_unreachable ();
5003 }
5004
5005 /* Decrement the counter by 1. */
5006 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
5007
5008 /* If the loop counter is nonzero, we go back to the beginning
5009 of the loop. */
5010 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
5011 start_label);
5012
5013 emit_label (end_label);
5014 }
5015 else
5016 {
5017 /* Rotate by AMOUNT bits. */
5018 switch (mode)
5019 {
5020 case QImode:
5021 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5022 break;
5023 case HImode:
5024 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5025 break;
5026 case SImode:
5027 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5028 break;
5029 default:
5030 gcc_unreachable ();
5031 }
5032 }
5033
5034 return 1;
5035 }
5036
5037 /* Output a rotate insn. */
5038
5039 const char *
output_a_rotate(enum rtx_code code,rtx * operands)5040 output_a_rotate (enum rtx_code code, rtx *operands)
5041 {
5042 rtx dst = operands[0];
5043 rtx rotate_amount = operands[2];
5044 enum shift_mode rotate_mode;
5045 enum shift_type rotate_type;
5046 const char *insn_buf;
5047 int bits;
5048 int amount;
5049 enum machine_mode mode = GET_MODE (dst);
5050
5051 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5052
5053 switch (mode)
5054 {
5055 case QImode:
5056 rotate_mode = QIshift;
5057 break;
5058 case HImode:
5059 rotate_mode = HIshift;
5060 break;
5061 case SImode:
5062 rotate_mode = SIshift;
5063 break;
5064 default:
5065 gcc_unreachable ();
5066 }
5067
5068 switch (code)
5069 {
5070 case ROTATERT:
5071 rotate_type = SHIFT_ASHIFT;
5072 break;
5073 case ROTATE:
5074 rotate_type = SHIFT_LSHIFTRT;
5075 break;
5076 default:
5077 gcc_unreachable ();
5078 }
5079
5080 amount = INTVAL (rotate_amount);
5081
5082 /* Clean up AMOUNT. */
5083 if (amount < 0)
5084 amount = 0;
5085 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5086 amount = GET_MODE_BITSIZE (mode);
5087
5088 /* Determine the faster direction. After this phase, amount will be
5089 at most a half of GET_MODE_BITSIZE (mode). */
5090 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5091 {
5092 /* Flip the direction. */
5093 amount = GET_MODE_BITSIZE (mode) - amount;
5094 rotate_type =
5095 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5096 }
5097
5098 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5099 boost up the rotation. */
5100 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5101 || (mode == HImode && TARGET_H8300H && amount >= 6)
5102 || (mode == HImode && TARGET_H8300S && amount == 8)
5103 || (mode == SImode && TARGET_H8300H && amount >= 10)
5104 || (mode == SImode && TARGET_H8300S && amount >= 13))
5105 {
5106 switch (mode)
5107 {
5108 case HImode:
5109 /* This code works on any family. */
5110 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5111 output_asm_insn (insn_buf, operands);
5112 break;
5113
5114 case SImode:
5115 /* This code works on the H8/300H and H8S. */
5116 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5117 output_asm_insn (insn_buf, operands);
5118 break;
5119
5120 default:
5121 gcc_unreachable ();
5122 }
5123
5124 /* Adjust AMOUNT and flip the direction. */
5125 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5126 rotate_type =
5127 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5128 }
5129
5130 /* Output rotate insns. */
5131 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5132 {
5133 if (bits == 2)
5134 insn_buf = rotate_two[rotate_type][rotate_mode];
5135 else
5136 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5137
5138 for (; amount >= bits; amount -= bits)
5139 output_asm_insn (insn_buf, operands);
5140 }
5141
5142 return "";
5143 }
5144
5145 /* Compute the length of a rotate insn. */
5146
5147 unsigned int
compute_a_rotate_length(rtx * operands)5148 compute_a_rotate_length (rtx *operands)
5149 {
5150 rtx src = operands[1];
5151 rtx amount_rtx = operands[2];
5152 enum machine_mode mode = GET_MODE (src);
5153 int amount;
5154 unsigned int length = 0;
5155
5156 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5157
5158 amount = INTVAL (amount_rtx);
5159
5160 /* Clean up AMOUNT. */
5161 if (amount < 0)
5162 amount = 0;
5163 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5164 amount = GET_MODE_BITSIZE (mode);
5165
5166 /* Determine the faster direction. After this phase, amount
5167 will be at most a half of GET_MODE_BITSIZE (mode). */
5168 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5169 /* Flip the direction. */
5170 amount = GET_MODE_BITSIZE (mode) - amount;
5171
5172 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5173 boost up the rotation. */
5174 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5175 || (mode == HImode && TARGET_H8300H && amount >= 6)
5176 || (mode == HImode && TARGET_H8300S && amount == 8)
5177 || (mode == SImode && TARGET_H8300H && amount >= 10)
5178 || (mode == SImode && TARGET_H8300S && amount >= 13))
5179 {
5180 /* Adjust AMOUNT and flip the direction. */
5181 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5182 length += 6;
5183 }
5184
5185 /* We use 2-bit rotations on the H8S. */
5186 if (TARGET_H8300S)
5187 amount = amount / 2 + amount % 2;
5188
5189 /* The H8/300 uses three insns to rotate one bit, taking 6
5190 length. */
5191 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5192
5193 return length;
5194 }
5195
5196 /* Fix the operands of a gen_xxx so that it could become a bit
5197 operating insn. */
5198
5199 int
fix_bit_operand(rtx * operands,enum rtx_code code)5200 fix_bit_operand (rtx *operands, enum rtx_code code)
5201 {
5202 /* The bit_operand predicate accepts any memory during RTL generation, but
5203 only 'U' memory afterwards, so if this is a MEM operand, we must force
5204 it to be valid for 'U' by reloading the address. */
5205
5206 if (code == AND
5207 ? single_zero_operand (operands[2], QImode)
5208 : single_one_operand (operands[2], QImode))
5209 {
5210 /* OK to have a memory dest. */
5211 if (GET_CODE (operands[0]) == MEM
5212 && !satisfies_constraint_U (operands[0]))
5213 {
5214 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5215 copy_to_mode_reg (Pmode,
5216 XEXP (operands[0], 0)));
5217 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5218 operands[0] = mem;
5219 }
5220
5221 if (GET_CODE (operands[1]) == MEM
5222 && !satisfies_constraint_U (operands[1]))
5223 {
5224 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5225 copy_to_mode_reg (Pmode,
5226 XEXP (operands[1], 0)));
5227 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5228 operands[1] = mem;
5229 }
5230 return 0;
5231 }
5232
5233 /* Dest and src op must be register. */
5234
5235 operands[1] = force_reg (QImode, operands[1]);
5236 {
5237 rtx res = gen_reg_rtx (QImode);
5238 switch (code)
5239 {
5240 case AND:
5241 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5242 break;
5243 case IOR:
5244 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5245 break;
5246 case XOR:
5247 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5248 break;
5249 default:
5250 gcc_unreachable ();
5251 }
5252 emit_insn (gen_movqi (operands[0], res));
5253 }
5254 return 1;
5255 }
5256
5257 /* Return nonzero if FUNC is an interrupt function as specified
5258 by the "interrupt" attribute. */
5259
5260 static int
h8300_interrupt_function_p(tree func)5261 h8300_interrupt_function_p (tree func)
5262 {
5263 tree a;
5264
5265 if (TREE_CODE (func) != FUNCTION_DECL)
5266 return 0;
5267
5268 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5269 return a != NULL_TREE;
5270 }
5271
5272 /* Return nonzero if FUNC is a saveall function as specified by the
5273 "saveall" attribute. */
5274
5275 static int
h8300_saveall_function_p(tree func)5276 h8300_saveall_function_p (tree func)
5277 {
5278 tree a;
5279
5280 if (TREE_CODE (func) != FUNCTION_DECL)
5281 return 0;
5282
5283 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5284 return a != NULL_TREE;
5285 }
5286
5287 /* Return nonzero if FUNC is an OS_Task function as specified
5288 by the "OS_Task" attribute. */
5289
5290 static int
h8300_os_task_function_p(tree func)5291 h8300_os_task_function_p (tree func)
5292 {
5293 tree a;
5294
5295 if (TREE_CODE (func) != FUNCTION_DECL)
5296 return 0;
5297
5298 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5299 return a != NULL_TREE;
5300 }
5301
5302 /* Return nonzero if FUNC is a monitor function as specified
5303 by the "monitor" attribute. */
5304
5305 static int
h8300_monitor_function_p(tree func)5306 h8300_monitor_function_p (tree func)
5307 {
5308 tree a;
5309
5310 if (TREE_CODE (func) != FUNCTION_DECL)
5311 return 0;
5312
5313 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5314 return a != NULL_TREE;
5315 }
5316
5317 /* Return nonzero if FUNC is a function that should be called
5318 through the function vector. */
5319
5320 int
h8300_funcvec_function_p(tree func)5321 h8300_funcvec_function_p (tree func)
5322 {
5323 tree a;
5324
5325 if (TREE_CODE (func) != FUNCTION_DECL)
5326 return 0;
5327
5328 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5329 return a != NULL_TREE;
5330 }
5331
5332 /* Return nonzero if DECL is a variable that's in the eight bit
5333 data area. */
5334
5335 int
h8300_eightbit_data_p(tree decl)5336 h8300_eightbit_data_p (tree decl)
5337 {
5338 tree a;
5339
5340 if (TREE_CODE (decl) != VAR_DECL)
5341 return 0;
5342
5343 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5344 return a != NULL_TREE;
5345 }
5346
5347 /* Return nonzero if DECL is a variable that's in the tiny
5348 data area. */
5349
5350 int
h8300_tiny_data_p(tree decl)5351 h8300_tiny_data_p (tree decl)
5352 {
5353 tree a;
5354
5355 if (TREE_CODE (decl) != VAR_DECL)
5356 return 0;
5357
5358 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5359 return a != NULL_TREE;
5360 }
5361
5362 /* Generate an 'interrupt_handler' attribute for decls. We convert
5363 all the pragmas to corresponding attributes. */
5364
5365 static void
h8300_insert_attributes(tree node,tree * attributes)5366 h8300_insert_attributes (tree node, tree *attributes)
5367 {
5368 if (TREE_CODE (node) == FUNCTION_DECL)
5369 {
5370 if (pragma_interrupt)
5371 {
5372 pragma_interrupt = 0;
5373
5374 /* Add an 'interrupt_handler' attribute. */
5375 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5376 NULL, *attributes);
5377 }
5378
5379 if (pragma_saveall)
5380 {
5381 pragma_saveall = 0;
5382
5383 /* Add an 'saveall' attribute. */
5384 *attributes = tree_cons (get_identifier ("saveall"),
5385 NULL, *attributes);
5386 }
5387 }
5388 }
5389
5390 /* Supported attributes:
5391
5392 interrupt_handler: output a prologue and epilogue suitable for an
5393 interrupt handler.
5394
5395 saveall: output a prologue and epilogue that saves and restores
5396 all registers except the stack pointer.
5397
5398 function_vector: This function should be called through the
5399 function vector.
5400
5401 eightbit_data: This variable lives in the 8-bit data area and can
5402 be referenced with 8-bit absolute memory addresses.
5403
5404 tiny_data: This variable lives in the tiny data area and can be
5405 referenced with 16-bit absolute memory references. */
5406
5407 static const struct attribute_spec h8300_attribute_table[] =
5408 {
5409 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5410 affects_type_identity } */
5411 { "interrupt_handler", 0, 0, true, false, false,
5412 h8300_handle_fndecl_attribute, false },
5413 { "saveall", 0, 0, true, false, false,
5414 h8300_handle_fndecl_attribute, false },
5415 { "OS_Task", 0, 0, true, false, false,
5416 h8300_handle_fndecl_attribute, false },
5417 { "monitor", 0, 0, true, false, false,
5418 h8300_handle_fndecl_attribute, false },
5419 { "function_vector", 0, 0, true, false, false,
5420 h8300_handle_fndecl_attribute, false },
5421 { "eightbit_data", 0, 0, true, false, false,
5422 h8300_handle_eightbit_data_attribute, false },
5423 { "tiny_data", 0, 0, true, false, false,
5424 h8300_handle_tiny_data_attribute, false },
5425 { NULL, 0, 0, false, false, false, NULL, false }
5426 };
5427
5428
5429 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5430 struct attribute_spec.handler. */
5431 static tree
h8300_handle_fndecl_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)5432 h8300_handle_fndecl_attribute (tree *node, tree name,
5433 tree args ATTRIBUTE_UNUSED,
5434 int flags ATTRIBUTE_UNUSED,
5435 bool *no_add_attrs)
5436 {
5437 if (TREE_CODE (*node) != FUNCTION_DECL)
5438 {
5439 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5440 name);
5441 *no_add_attrs = true;
5442 }
5443
5444 return NULL_TREE;
5445 }
5446
5447 /* Handle an "eightbit_data" attribute; arguments as in
5448 struct attribute_spec.handler. */
5449 static tree
h8300_handle_eightbit_data_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)5450 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5451 tree args ATTRIBUTE_UNUSED,
5452 int flags ATTRIBUTE_UNUSED,
5453 bool *no_add_attrs)
5454 {
5455 tree decl = *node;
5456
5457 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5458 {
5459 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5460 }
5461 else
5462 {
5463 warning (OPT_Wattributes, "%qE attribute ignored",
5464 name);
5465 *no_add_attrs = true;
5466 }
5467
5468 return NULL_TREE;
5469 }
5470
5471 /* Handle an "tiny_data" attribute; arguments as in
5472 struct attribute_spec.handler. */
5473 static tree
h8300_handle_tiny_data_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)5474 h8300_handle_tiny_data_attribute (tree *node, tree name,
5475 tree args ATTRIBUTE_UNUSED,
5476 int flags ATTRIBUTE_UNUSED,
5477 bool *no_add_attrs)
5478 {
5479 tree decl = *node;
5480
5481 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5482 {
5483 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5484 }
5485 else
5486 {
5487 warning (OPT_Wattributes, "%qE attribute ignored",
5488 name);
5489 *no_add_attrs = true;
5490 }
5491
5492 return NULL_TREE;
5493 }
5494
5495 /* Mark function vectors, and various small data objects. */
5496
5497 static void
h8300_encode_section_info(tree decl,rtx rtl,int first)5498 h8300_encode_section_info (tree decl, rtx rtl, int first)
5499 {
5500 int extra_flags = 0;
5501
5502 default_encode_section_info (decl, rtl, first);
5503
5504 if (TREE_CODE (decl) == FUNCTION_DECL
5505 && h8300_funcvec_function_p (decl))
5506 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5507 else if (TREE_CODE (decl) == VAR_DECL
5508 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5509 {
5510 if (h8300_eightbit_data_p (decl))
5511 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5512 else if (first && h8300_tiny_data_p (decl))
5513 extra_flags = SYMBOL_FLAG_TINY_DATA;
5514 }
5515
5516 if (extra_flags)
5517 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5518 }
5519
5520 /* Output a single-bit extraction. */
5521
5522 const char *
output_simode_bld(int bild,rtx operands[])5523 output_simode_bld (int bild, rtx operands[])
5524 {
5525 if (TARGET_H8300)
5526 {
5527 /* Clear the destination register. */
5528 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5529
5530 /* Now output the bit load or bit inverse load, and store it in
5531 the destination. */
5532 if (bild)
5533 output_asm_insn ("bild\t%Z2,%Y1", operands);
5534 else
5535 output_asm_insn ("bld\t%Z2,%Y1", operands);
5536
5537 output_asm_insn ("bst\t#0,%w0", operands);
5538 }
5539 else
5540 {
5541 /* Determine if we can clear the destination first. */
5542 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5543 && REGNO (operands[0]) != REGNO (operands[1]));
5544
5545 if (clear_first)
5546 output_asm_insn ("sub.l\t%S0,%S0", operands);
5547
5548 /* Output the bit load or bit inverse load. */
5549 if (bild)
5550 output_asm_insn ("bild\t%Z2,%Y1", operands);
5551 else
5552 output_asm_insn ("bld\t%Z2,%Y1", operands);
5553
5554 if (!clear_first)
5555 output_asm_insn ("xor.l\t%S0,%S0", operands);
5556
5557 /* Perform the bit store. */
5558 output_asm_insn ("rotxl.l\t%S0", operands);
5559 }
5560
5561 /* All done. */
5562 return "";
5563 }
5564
5565 /* Delayed-branch scheduling is more effective if we have some idea
5566 how long each instruction will be. Use a shorten_branches pass
5567 to get an initial estimate. */
5568
5569 static void
h8300_reorg(void)5570 h8300_reorg (void)
5571 {
5572 if (flag_delayed_branch)
5573 shorten_branches (get_insns ());
5574 }
5575
5576 #ifndef OBJECT_FORMAT_ELF
5577 static void
h8300_asm_named_section(const char * name,unsigned int flags ATTRIBUTE_UNUSED,tree decl)5578 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5579 tree decl)
5580 {
5581 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5582 fprintf (asm_out_file, "\t.section %s\n", name);
5583 }
5584 #endif /* ! OBJECT_FORMAT_ELF */
5585
5586 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5587 which is a special case of the 'R' operand. */
5588
5589 int
h8300_eightbit_constant_address_p(rtx x)5590 h8300_eightbit_constant_address_p (rtx x)
5591 {
5592 /* The ranges of the 8-bit area. */
5593 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5594 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5595 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5596 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5597 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5598 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5599
5600 unsigned HOST_WIDE_INT addr;
5601
5602 /* We accept symbols declared with eightbit_data. */
5603 if (GET_CODE (x) == SYMBOL_REF)
5604 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5605
5606 if (GET_CODE (x) != CONST_INT)
5607 return 0;
5608
5609 addr = INTVAL (x);
5610
5611 return (0
5612 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5613 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5614 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5615 }
5616
5617 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5618 on H8/300H and H8S. */
5619
5620 int
h8300_tiny_constant_address_p(rtx x)5621 h8300_tiny_constant_address_p (rtx x)
5622 {
5623 /* The ranges of the 16-bit area. */
5624 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5625 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5626 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5627 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5628 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5629 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5630 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5631 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5632
5633 unsigned HOST_WIDE_INT addr;
5634
5635 switch (GET_CODE (x))
5636 {
5637 case SYMBOL_REF:
5638 /* In the normal mode, any symbol fits in the 16-bit absolute
5639 address range. We also accept symbols declared with
5640 tiny_data. */
5641 return (TARGET_NORMAL_MODE
5642 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5643
5644 case CONST_INT:
5645 addr = INTVAL (x);
5646 return (TARGET_NORMAL_MODE
5647 || (TARGET_H8300H
5648 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5649 || (TARGET_H8300S
5650 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5651
5652 case CONST:
5653 return TARGET_NORMAL_MODE;
5654
5655 default:
5656 return 0;
5657 }
5658
5659 }
5660
5661 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5662 locations that can be accessed as a 16-bit word. */
5663
5664 int
byte_accesses_mergeable_p(rtx addr1,rtx addr2)5665 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5666 {
5667 HOST_WIDE_INT offset1, offset2;
5668 rtx reg1, reg2;
5669
5670 if (REG_P (addr1))
5671 {
5672 reg1 = addr1;
5673 offset1 = 0;
5674 }
5675 else if (GET_CODE (addr1) == PLUS
5676 && REG_P (XEXP (addr1, 0))
5677 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5678 {
5679 reg1 = XEXP (addr1, 0);
5680 offset1 = INTVAL (XEXP (addr1, 1));
5681 }
5682 else
5683 return 0;
5684
5685 if (REG_P (addr2))
5686 {
5687 reg2 = addr2;
5688 offset2 = 0;
5689 }
5690 else if (GET_CODE (addr2) == PLUS
5691 && REG_P (XEXP (addr2, 0))
5692 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5693 {
5694 reg2 = XEXP (addr2, 0);
5695 offset2 = INTVAL (XEXP (addr2, 1));
5696 }
5697 else
5698 return 0;
5699
5700 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5701 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5702 && offset1 % 2 == 0
5703 && offset1 + 1 == offset2)
5704 return 1;
5705
5706 return 0;
5707 }
5708
5709 /* Return nonzero if we have the same comparison insn as I3 two insns
5710 before I3. I3 is assumed to be a comparison insn. */
5711
5712 int
same_cmp_preceding_p(rtx i3)5713 same_cmp_preceding_p (rtx i3)
5714 {
5715 rtx i1, i2;
5716
5717 /* Make sure we have a sequence of three insns. */
5718 i2 = prev_nonnote_insn (i3);
5719 if (i2 == NULL_RTX)
5720 return 0;
5721 i1 = prev_nonnote_insn (i2);
5722 if (i1 == NULL_RTX)
5723 return 0;
5724
5725 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5726 && any_condjump_p (i2) && onlyjump_p (i2));
5727 }
5728
5729 /* Return nonzero if we have the same comparison insn as I1 two insns
5730 after I1. I1 is assumed to be a comparison insn. */
5731
5732 int
same_cmp_following_p(rtx i1)5733 same_cmp_following_p (rtx i1)
5734 {
5735 rtx i2, i3;
5736
5737 /* Make sure we have a sequence of three insns. */
5738 i2 = next_nonnote_insn (i1);
5739 if (i2 == NULL_RTX)
5740 return 0;
5741 i3 = next_nonnote_insn (i2);
5742 if (i3 == NULL_RTX)
5743 return 0;
5744
5745 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5746 && any_condjump_p (i2) && onlyjump_p (i2));
5747 }
5748
5749 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5750 (or pops) N registers. OPERANDS are assumed to be an array of
5751 registers. */
5752
5753 int
h8300_regs_ok_for_stm(int n,rtx operands[])5754 h8300_regs_ok_for_stm (int n, rtx operands[])
5755 {
5756 switch (n)
5757 {
5758 case 2:
5759 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5760 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5761 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5762 case 3:
5763 return ((REGNO (operands[0]) == 0
5764 && REGNO (operands[1]) == 1
5765 && REGNO (operands[2]) == 2)
5766 || (REGNO (operands[0]) == 4
5767 && REGNO (operands[1]) == 5
5768 && REGNO (operands[2]) == 6));
5769
5770 case 4:
5771 return (REGNO (operands[0]) == 0
5772 && REGNO (operands[1]) == 1
5773 && REGNO (operands[2]) == 2
5774 && REGNO (operands[3]) == 3);
5775 default:
5776 gcc_unreachable ();
5777 }
5778 }
5779
5780 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5781
5782 int
h8300_hard_regno_rename_ok(unsigned int old_reg ATTRIBUTE_UNUSED,unsigned int new_reg)5783 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5784 unsigned int new_reg)
5785 {
5786 /* Interrupt functions can only use registers that have already been
5787 saved by the prologue, even if they would normally be
5788 call-clobbered. */
5789
5790 if (h8300_current_function_interrupt_function_p ()
5791 && !df_regs_ever_live_p (new_reg))
5792 return 0;
5793
5794 return 1;
5795 }
5796
5797 /* Returns true if register REGNO is safe to be allocated as a scratch
5798 register in the current function. */
5799
5800 static bool
h8300_hard_regno_scratch_ok(unsigned int regno)5801 h8300_hard_regno_scratch_ok (unsigned int regno)
5802 {
5803 if (h8300_current_function_interrupt_function_p ()
5804 && ! WORD_REG_USED (regno))
5805 return false;
5806
5807 return true;
5808 }
5809
5810
5811 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5812
5813 static int
h8300_rtx_ok_for_base_p(rtx x,int strict)5814 h8300_rtx_ok_for_base_p (rtx x, int strict)
5815 {
5816 /* Strip off SUBREG if any. */
5817 if (GET_CODE (x) == SUBREG)
5818 x = SUBREG_REG (x);
5819
5820 return (REG_P (x)
5821 && (strict
5822 ? REG_OK_FOR_BASE_STRICT_P (x)
5823 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5824 }
5825
5826 /* Return nozero if X is a legitimate address. On the H8/300, a
5827 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5828 CONSTANT_ADDRESS. */
5829
5830 static bool
h8300_legitimate_address_p(enum machine_mode mode,rtx x,bool strict)5831 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5832 {
5833 /* The register indirect addresses like @er0 is always valid. */
5834 if (h8300_rtx_ok_for_base_p (x, strict))
5835 return 1;
5836
5837 if (CONSTANT_ADDRESS_P (x))
5838 return 1;
5839
5840 if (TARGET_H8300SX
5841 && ( GET_CODE (x) == PRE_INC
5842 || GET_CODE (x) == PRE_DEC
5843 || GET_CODE (x) == POST_INC
5844 || GET_CODE (x) == POST_DEC)
5845 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5846 return 1;
5847
5848 if (GET_CODE (x) == PLUS
5849 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5850 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5851 mode, 0), strict))
5852 return 1;
5853
5854 return 0;
5855 }
5856
5857 /* Worker function for HARD_REGNO_NREGS.
5858
5859 We pretend the MAC register is 32bits -- we don't have any data
5860 types on the H8 series to handle more than 32bits. */
5861
5862 int
h8300_hard_regno_nregs(int regno ATTRIBUTE_UNUSED,enum machine_mode mode)5863 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5864 {
5865 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5866 }
5867
5868 /* Worker function for HARD_REGNO_MODE_OK. */
5869
5870 int
h8300_hard_regno_mode_ok(int regno,enum machine_mode mode)5871 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5872 {
5873 if (TARGET_H8300)
5874 /* If an even reg, then anything goes. Otherwise the mode must be
5875 QI or HI. */
5876 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5877 else
5878 /* MAC register can only be of SImode. Otherwise, anything
5879 goes. */
5880 return regno == MAC_REG ? mode == SImode : 1;
5881 }
5882
5883 /* Helper function for the move patterns. Make sure a move is legitimate. */
5884
5885 bool
h8300_move_ok(rtx dest,rtx src)5886 h8300_move_ok (rtx dest, rtx src)
5887 {
5888 rtx addr, other;
5889
5890 /* Validate that at least one operand is a register. */
5891 if (MEM_P (dest))
5892 {
5893 if (MEM_P (src) || CONSTANT_P (src))
5894 return false;
5895 addr = XEXP (dest, 0);
5896 other = src;
5897 }
5898 else if (MEM_P (src))
5899 {
5900 addr = XEXP (src, 0);
5901 other = dest;
5902 }
5903 else
5904 return true;
5905
5906 /* Validate that auto-inc doesn't affect OTHER. */
5907 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5908 return true;
5909 addr = XEXP (addr, 0);
5910
5911 if (addr == stack_pointer_rtx)
5912 return register_no_sp_elim_operand (other, VOIDmode);
5913 else
5914 return !reg_overlap_mentioned_p(other, addr);
5915 }
5916
5917 /* Perform target dependent optabs initialization. */
5918 static void
h8300_init_libfuncs(void)5919 h8300_init_libfuncs (void)
5920 {
5921 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5922 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5923 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5924 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5925 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5926 }
5927
5928 /* Worker function for TARGET_FUNCTION_VALUE.
5929
5930 On the H8 the return value is in R0/R1. */
5931
5932 static rtx
h8300_function_value(const_tree ret_type,const_tree fn_decl_or_type ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)5933 h8300_function_value (const_tree ret_type,
5934 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5935 bool outgoing ATTRIBUTE_UNUSED)
5936 {
5937 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5938 }
5939
5940 /* Worker function for TARGET_LIBCALL_VALUE.
5941
5942 On the H8 the return value is in R0/R1. */
5943
5944 static rtx
h8300_libcall_value(enum machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)5945 h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5946 {
5947 return gen_rtx_REG (mode, R0_REG);
5948 }
5949
5950 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5951
5952 On the H8, R0 is the only register thus used. */
5953
5954 static bool
h8300_function_value_regno_p(const unsigned int regno)5955 h8300_function_value_regno_p (const unsigned int regno)
5956 {
5957 return (regno == R0_REG);
5958 }
5959
5960 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5961
5962 static bool
h8300_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)5963 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5964 {
5965 return (TYPE_MODE (type) == BLKmode
5966 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5967 }
5968
5969 /* We emit the entire trampoline here. Depending on the pointer size,
5970 we use a different trampoline.
5971
5972 Pmode == HImode
5973 vvvv context
5974 1 0000 7903xxxx mov.w #0x1234,r3
5975 2 0004 5A00xxxx jmp @0x1234
5976 ^^^^ function
5977
5978 Pmode == SImode
5979 vvvvvvvv context
5980 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5981 3 0006 5Axxxxxx jmp @0x123456
5982 ^^^^^^ function
5983 */
5984
5985 static void
h8300_trampoline_init(rtx m_tramp,tree fndecl,rtx cxt)5986 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5987 {
5988 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5989 rtx mem;
5990
5991 if (Pmode == HImode)
5992 {
5993 mem = adjust_address (m_tramp, HImode, 0);
5994 emit_move_insn (mem, GEN_INT (0x7903));
5995 mem = adjust_address (m_tramp, Pmode, 2);
5996 emit_move_insn (mem, cxt);
5997 mem = adjust_address (m_tramp, HImode, 4);
5998 emit_move_insn (mem, GEN_INT (0x5a00));
5999 mem = adjust_address (m_tramp, Pmode, 6);
6000 emit_move_insn (mem, fnaddr);
6001 }
6002 else
6003 {
6004 rtx tem;
6005
6006 mem = adjust_address (m_tramp, HImode, 0);
6007 emit_move_insn (mem, GEN_INT (0x7a03));
6008 mem = adjust_address (m_tramp, Pmode, 2);
6009 emit_move_insn (mem, cxt);
6010
6011 tem = copy_to_reg (fnaddr);
6012 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6013 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6014 mem = adjust_address (m_tramp, SImode, 6);
6015 emit_move_insn (mem, tem);
6016 }
6017 }
6018
6019 /* Initialize the GCC target structure. */
6020 #undef TARGET_ATTRIBUTE_TABLE
6021 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6022
6023 #undef TARGET_ASM_ALIGNED_HI_OP
6024 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6025
6026 #undef TARGET_ASM_FILE_START
6027 #define TARGET_ASM_FILE_START h8300_file_start
6028 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6029 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6030
6031 #undef TARGET_ASM_FILE_END
6032 #define TARGET_ASM_FILE_END h8300_file_end
6033
6034 #undef TARGET_PRINT_OPERAND
6035 #define TARGET_PRINT_OPERAND h8300_print_operand
6036 #undef TARGET_PRINT_OPERAND_ADDRESS
6037 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6038 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6039 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6040
6041 #undef TARGET_ENCODE_SECTION_INFO
6042 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6043
6044 #undef TARGET_INSERT_ATTRIBUTES
6045 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6046
6047 #undef TARGET_REGISTER_MOVE_COST
6048 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6049
6050 #undef TARGET_RTX_COSTS
6051 #define TARGET_RTX_COSTS h8300_rtx_costs
6052
6053 #undef TARGET_INIT_LIBFUNCS
6054 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6055
6056 #undef TARGET_FUNCTION_VALUE
6057 #define TARGET_FUNCTION_VALUE h8300_function_value
6058
6059 #undef TARGET_LIBCALL_VALUE
6060 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6061
6062 #undef TARGET_FUNCTION_VALUE_REGNO_P
6063 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6064
6065 #undef TARGET_RETURN_IN_MEMORY
6066 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6067
6068 #undef TARGET_FUNCTION_ARG
6069 #define TARGET_FUNCTION_ARG h8300_function_arg
6070
6071 #undef TARGET_FUNCTION_ARG_ADVANCE
6072 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6073
6074 #undef TARGET_MACHINE_DEPENDENT_REORG
6075 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6076
6077 #undef TARGET_HARD_REGNO_SCRATCH_OK
6078 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6079
6080 #undef TARGET_LEGITIMATE_ADDRESS_P
6081 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6082
6083 #undef TARGET_CAN_ELIMINATE
6084 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6085
6086 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6087 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6088
6089 #undef TARGET_TRAMPOLINE_INIT
6090 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6091
6092 #undef TARGET_OPTION_OVERRIDE
6093 #define TARGET_OPTION_OVERRIDE h8300_option_override
6094
6095 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6096 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6097
6098 struct gcc_target targetm = TARGET_INITIALIZER;
6099