1 /* Definitions for Toshiba Media Processor 2 Copyright (C) 2001-2013 Free Software Foundation, Inc. 3 Contributed by Red Hat, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #undef CPP_SPEC 23 #define CPP_SPEC "\ 24 -D__MEP__ -D__MeP__ \ 25 -D__section(_x)=__attribute__((section(_x))) \ 26 -D__align(_x)=__attribute__((aligned(_x))) \ 27 -D__io(_x)=__attribute__((io(_x))) \ 28 -D__cb(_x)=__attribute__((cb(_x))) \ 29 -D__based=__attribute__((based)) \ 30 -D__tiny=__attribute__((tiny)) \ 31 -D__near=__attribute__((near)) \ 32 -D__far=__attribute__((far)) \ 33 -D__vliw=__attribute__((vliw)) \ 34 -D__interrupt=__attribute__((interrupt)) \ 35 -D__disinterrupt=__attribute__((disinterrupt)) \ 36 %{!meb:%{!mel:-D__BIG_ENDIAN__}} \ 37 %{meb:-U__LITTLE_ENDIAN__ -D__BIG_ENDIAN__} \ 38 %{mel:-U__BIG_ENDIAN__ -D__LITTLE_ENDIAN__} \ 39 %{mconfig=*:-D__MEP_CONFIG_%*} \ 40 %{mivc2:-D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64} \ 41 " 42 43 #undef CC1_SPEC 44 #define CC1_SPEC "%{!mlibrary:%(config_cc_spec)} \ 45 %{!.cc:%{O2:%{!funroll*:--param max-completely-peeled-insns=6 \ 46 --param max-unrolled-insns=6 -funroll-loops}}}" 47 48 #undef CC1PLUS_SPEC 49 #define CC1PLUS_SPEC "%{!mlibrary:%(config_cc_spec)}" 50 51 #undef ASM_SPEC 52 #define ASM_SPEC "%{mconfig=*} %{meb:-EB} %{mel:-EL} \ 53 %{mno-satur} %{msatur} %{mno-clip} %{mclip} %{mno-minmax} %{mminmax} \ 54 %{mno-absdiff} %{mabsdiff} %{mno-leadz} %{mleadz} %{mno-bitops} %{mbitops} \ 55 %{mno-div} %{mdiv} %{mno-mult} %{mmult} %{mno-average} %{maverage} \ 56 %{mcop32} %{mno-debug} %{mdebug} %{mlibrary}" 57 58 /* The MeP config tool will edit this spec. */ 59 #undef STARTFILE_SPEC 60 #define STARTFILE_SPEC "%{msdram:%{msim:simsdram-crt0.o%s}} \ 61 %{mno-sdram:%{msim:sim-crt0.o%s}} \ 62 %{msdram:%{!msim*:sdram-crt0.o%s}} \ 63 %{mno-sdram:%{!msim*:crt0.o%s}} \ 64 %(config_start_spec) \ 65 %{msimnovec:simnovec-crt0.o%s} \ 66 crtbegin.o%s" 67 68 #undef LIB_SPEC 69 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) %(config_link_spec)" 70 71 #undef LINK_SPEC 72 #define LINK_SPEC "%{meb:-EB} %{mel:-EL}" 73 74 #undef ENDFILE_SPEC 75 #define ENDFILE_SPEC "crtend.o%s %{msim*:sim-crtn.o%s}%{!msim*:crtn.o%s}" 76 77 /* The MeP config tool will edit this spec. */ 78 #define CONFIG_CC_SPEC "\ 79 %{mconfig=default: -mbitops -mleadz -mabsdiff -maverage -mminmax -mclip -msatur -mvl64 -mvliw -mcop64 -D__MEP_CONFIG_CP_DATA_BUS_WIDTH=64 -mivc2}\ 80 " 81 /* end-config-cc-spec */ 82 83 /* The MeP config tool will edit this spec. */ 84 #define CONFIG_LINK_SPEC "\ 85 %{mconfig=default: %{!T*:-Tdefault.ld}}\ 86 " 87 /* end-config-link-spec */ 88 89 /* The MeP config tool will edit this spec. */ 90 #define CONFIG_START_SPEC "\ 91 %{!msdram:%{!mno-sdram:%{!msim*:crt0.o%s}}} \ 92 %{!msdram:%{!mno-sdram:%{msim:sim-crt0.o%s}}} \ 93 " 94 /* end-config-start-spec */ 95 96 #define EXTRA_SPECS \ 97 { "config_cc_spec", CONFIG_CC_SPEC }, \ 98 { "config_link_spec", CONFIG_LINK_SPEC }, \ 99 { "config_start_spec", CONFIG_START_SPEC }, 100 101 102 #define TARGET_CPU_CPP_BUILTINS() \ 103 do \ 104 { \ 105 builtin_define_std ("mep"); \ 106 builtin_assert ("machine=mep"); \ 107 } \ 108 while (0) 109 110 /* Controlled by MeP-Integrator. */ 111 #define TARGET_H1 0 112 113 #define MEP_ALL_OPTS (MASK_OPT_AVERAGE \ 114 | MASK_OPT_MULT \ 115 | MASK_OPT_DIV \ 116 | MASK_OPT_BITOPS \ 117 | MASK_OPT_LEADZ \ 118 | MASK_OPT_ABSDIFF \ 119 | MASK_OPT_MINMAX \ 120 | MASK_OPT_CLIP \ 121 | MASK_OPT_SATUR ) 122 123 #define TARGET_DEFAULT (MASK_IO_VOLATILE | MASK_OPT_REPEAT | MEP_ALL_OPTS | MASK_LITTLE_ENDIAN) 124 125 #define TARGET_IO_NO_VOLATILE (! (target_flags & MASK_IO_VOLATILE)) 126 #define TARGET_OPT_NOREPEAT (! (target_flags & MASK_OPT_REPEAT)) 127 #define TARGET_32BIT_CR_REGS (! (target_flags & MASK_64BIT_CR_REGS)) 128 #define TARGET_BIG_ENDIAN (! (target_flags & MASK_LITTLE_ENDIAN)) 129 130 #define TARGET_COPRO_MULT 0 131 132 /* The MeP config tool will replace this as appropriate. */ 133 #define DEFAULT_ENDIAN_SPEC "%{!meb: -mel}" 134 135 /* The MeP config tool will replace this with an -mconfig= switch. */ 136 #define LIBRARY_CONFIG_SPEC "-mconfig=default" 137 138 /* Don't add an endian option when building the libraries. */ 139 #define DRIVER_SELF_SPECS \ 140 "%{!mlibrary:" DEFAULT_ENDIAN_SPEC "}", \ 141 "%{mlibrary: " LIBRARY_CONFIG_SPEC " %{!mel:-meb}}", \ 142 "%{mall-opts:-maverage -mmult -mdiv -mbitops -mleadz \ 143 -mabsdiff -mminmax -mclip -msatur -mdebug} %<mall-opts", \ 144 "%{mno-opts:-mno-average -mno-mult -mno-div -mno-bitops -mno-leadz \ 145 -mno-absdiff -mno-minmax -mno-clip -mno-satur -mno-debug} %<mno-opts", \ 146 "%{mfar:-ml -mtf -mc=far} %<mfar", \ 147 "%{mconfig=default:-mmult -mdiv -D__MEP_CONFIG_ISA=1}" 148 149 /* The MeP config tool will add COPROC_SELECTION_TABLE here. */ 150 /* start-coproc-selection-table */ 151 #define COPROC_SELECTION_TABLE \ 152 {"default", ISA_EXT1} 153 /* end-coproc-selection-table */ 154 155 156 #define BITS_BIG_ENDIAN 0 157 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1) 158 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN ? 0 : 1) 159 160 #define UNITS_PER_WORD 4 161 162 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 163 do \ 164 { \ 165 if (GET_MODE_CLASS (MODE) == MODE_INT \ 166 && GET_MODE_SIZE (MODE) < 4) \ 167 (MODE) = SImode; \ 168 } \ 169 while (0) 170 171 #define PARM_BOUNDARY 32 172 #define STACK_BOUNDARY 32 173 #define PREFERRED_STACK_BOUNDARY 64 174 #define FUNCTION_BOUNDARY 16 175 #define BIGGEST_ALIGNMENT 64 176 177 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 178 (TREE_CODE (TYPE) == ARRAY_TYPE \ 179 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 180 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 181 182 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 183 (TREE_CODE (EXP) == STRING_CST \ 184 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 185 186 #define STRICT_ALIGNMENT 1 187 188 #define PCC_BITFIELD_TYPE_MATTERS 1 189 190 #define DEFAULT_VTABLE_THUNKS 1 191 192 193 #define INT_TYPE_SIZE 32 194 #define SHORT_TYPE_SIZE 16 195 #define LONG_TYPE_SIZE 32 196 #define LONG_LONG_TYPE_SIZE 64 197 #define CHAR_TYPE_SIZE 8 198 #define FLOAT_TYPE_SIZE 32 199 #define DOUBLE_TYPE_SIZE 64 200 #define LONG_DOUBLE_TYPE_SIZE 64 201 #define DEFAULT_SIGNED_CHAR 1 202 203 #undef SIZE_TYPE 204 #define SIZE_TYPE "unsigned int" 205 206 #undef PTRDIFF_TYPE 207 #define PTRDIFF_TYPE "int" 208 209 #undef WCHAR_TYPE 210 #define WCHAR_TYPE "long int" 211 212 #undef WCHAR_TYPE_SIZE 213 #define WCHAR_TYPE_SIZE BITS_PER_WORD 214 215 /* Register numbers: 216 0..15 core registers 217 16..47 control registers 218 48..79 coprocessor registers 219 80..111 coprocessor control registers 220 112 virtual arg pointer register */ 221 222 #define FIRST_PSEUDO_REGISTER (LAST_SHADOW_REGISTER + 1) 223 224 /* R12 is optionally FP. R13 is TP, R14 is GP, R15 is SP. */ 225 /* hi and lo can be used as general registers. Others have 226 immutable bits. */ 227 /* A "1" here means the register is generally not available to gcc, 228 and is assumed to remain unchanged or unused throughout. */ 229 #define FIXED_REGISTERS { \ 230 /* core registers */ \ 231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 232 /* control registers */ \ 233 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ 234 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 235 /* coprocessor registers */ \ 236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 238 /* coprocessor control registers */ \ 239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 240 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 241 /* virtual arg pointer */ \ 242 1, FIXED_SHADOW_REGISTERS \ 243 } 244 245 /* This is a call-clobbered reg not used for args or return value, 246 that we use as a temp for saving control registers in the prolog 247 and restoring them in the epilog. */ 248 #define REGSAVE_CONTROL_TEMP 11 249 250 /* A "1" here means a register may be changed by a function without 251 needing to preserve its previous value. */ 252 #define CALL_USED_REGISTERS { \ 253 /* core registers */ \ 254 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, \ 255 /* control registers */ \ 256 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 257 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 258 /* coprocessor registers */ \ 259 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 261 /* coprocessor control registers */ \ 262 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 263 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 264 /* virtual arg pointer */ \ 265 1, CALL_USED_SHADOW_REGISTERS \ 266 } 267 268 #define REG_ALLOC_ORDER { \ 269 /* core registers */ \ 270 3, 2, 1, 0, 9, 10, 11, 12, 4, 5, 6, 7, 8, 13, 14, 15, \ 271 /* control registers */ \ 272 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 273 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 274 /* coprocessor registers */ \ 275 /* Prefer to use the non-loadable registers when looking for a \ 276 member of CR_REGS (as opposed to LOADABLE_CR_REGS). */ \ 277 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 48, 49, 50, 51, 52, 58, \ 278 59, 60, 61, 62, 63, 53, 54, 55, 56, 57, 74, 75, 76, 77, 78, 79, \ 279 /* coprocessor control registers */ \ 280 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 281 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, \ 282 /* virtual arg pointer */ \ 283 112, SHADOW_REG_ALLOC_ORDER \ 284 } 285 286 /* We must somehow disable register remapping for interrupt functions. */ 287 extern char mep_leaf_registers[]; 288 #define LEAF_REGISTERS mep_leaf_registers 289 #define LEAF_REG_REMAP(REG) (REG) 290 291 292 #define FIRST_GR_REGNO 0 293 #define FIRST_CONTROL_REGNO (FIRST_GR_REGNO + 16) 294 #define FIRST_CR_REGNO (FIRST_CONTROL_REGNO + 32) 295 #define FIRST_CCR_REGNO (FIRST_CR_REGNO + 32) 296 297 #define GR_REGNO_P(REGNO) \ 298 ((unsigned) ((REGNO) - FIRST_GR_REGNO) < 16) 299 300 #define CONTROL_REGNO_P(REGNO) \ 301 ((unsigned) ((REGNO) - FIRST_CONTROL_REGNO) < 32) 302 303 #define LOADABLE_CR_REGNO_P(REGNO) \ 304 ((unsigned) ((REGNO) - FIRST_CR_REGNO) < 16) 305 306 #define CR_REGNO_P(REGNO) \ 307 ((unsigned) ((REGNO) - FIRST_CR_REGNO) < 32) 308 309 #define CCR_REGNO_P(REGNO) \ 310 ((unsigned) ((REGNO) - FIRST_CCR_REGNO) < 32) 311 312 #define ANY_CONTROL_REGNO_P(REGNO) \ 313 (CONTROL_REGNO_P (REGNO) || CCR_REGNO_P (REGNO)) 314 315 #define HARD_REGNO_NREGS(REGNO, MODE) \ 316 ((CR_REGNO_P (REGNO) && TARGET_64BIT_CR_REGS) \ 317 ? (GET_MODE_SIZE (MODE) + 8 - 1) / 8 \ 318 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) 319 320 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 321 322 #define MODES_TIEABLE_P(MODE1, MODE2) 1 323 324 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 325 mep_cannot_change_mode_class (FROM, TO, CLASS) 326 327 enum reg_class 328 { 329 NO_REGS, 330 SP_REGS, 331 TP_REGS, 332 GP_REGS, 333 R0_REGS, 334 RPC_REGS, 335 HI_REGS, 336 LO_REGS, 337 HILO_REGS, 338 TPREL_REGS, 339 GENERAL_NOT_R0_REGS, 340 GENERAL_REGS, 341 CONTROL_REGS, 342 CONTROL_OR_GENERAL_REGS, 343 USER0_REGS, 344 USER1_REGS, 345 USER2_REGS, 346 USER3_REGS, 347 LOADABLE_CR_REGS, 348 CR_REGS, 349 CCR_REGS, 350 ALL_REGS, 351 LIM_REG_CLASSES 352 }; 353 354 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 355 356 #define REG_CLASS_NAMES { \ 357 "NO_REGS", \ 358 "SP_REGS", \ 359 "TP_REGS", \ 360 "GP_REGS", \ 361 "R0_REGS", \ 362 "RPC_REGS", \ 363 "HI_REGS", \ 364 "LO_REGS", \ 365 "HILO_REGS", \ 366 "TPREL_REGS", \ 367 "GENERAL_NOT_R0_REGS", \ 368 "GENERAL_REGS", \ 369 "CONTROL_REGS", \ 370 "CONTROL_OR_GENERAL_REGS", \ 371 "USER0_REGS", \ 372 "USER1_REGS", \ 373 "USER2_REGS", \ 374 "USER3_REGS", \ 375 "LOADABLE_CR_REGS", \ 376 "CR_REGS", \ 377 "CCR_REGS", \ 378 "ALL_REGS" } 379 380 #define REG_CLASS_CONTENTS { \ 381 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 382 { 0x00008000, 0x00000000, 0x00000000, 0x00000000 }, /* SP_REGS */ \ 383 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* TP_REGS */ \ 384 { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* GP_REGS */ \ 385 { 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* R0_REGS */ \ 386 { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* RPC_REGS */ \ 387 { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 388 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 389 { 0x01800000, 0x00000000, 0x00000000, 0x00000000 }, /* HILO_REGS */ \ 390 { 0x000000ff, 0x00000000, 0x00000000, 0x00000000 }, /* TPREL_REGS */ \ 391 { 0x0000fffe, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_NOT_R0_REGS */ \ 392 { 0x0000ffff, 0x00000000, 0x00000000, 0x00010000 }, /* GENERAL_REGS */ \ 393 { 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_REGS */ \ 394 { 0xffffffff, 0x0000ffff, 0x00000000, 0x00000000 }, /* CONTROL_OR_GENERAL_REGS */ \ 395 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER0_REGS */ \ 396 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER1_REGS */ \ 397 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER2_REGS */ \ 398 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* USER3_REGS */ \ 399 { 0x00000000, 0xffff0000, 0x00000000, 0x00000000 }, /* LOADABLE_CR_REGS */ \ 400 { 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* CR_REGS */ \ 401 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* CCR_REGS */ \ 402 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0001ffff }, /* ALL_REGS */ \ 403 } 404 405 #define REGNO_REG_CLASS(REGNO) (enum reg_class) mep_regno_reg_class (REGNO) 406 407 #define BASE_REG_CLASS GENERAL_REGS 408 #define INDEX_REG_CLASS GENERAL_REGS 409 410 #define REGNO_OK_FOR_BASE_P(NUM) (GR_REGNO_P (NUM) \ 411 || (NUM) == ARG_POINTER_REGNUM \ 412 || (NUM) >= FIRST_PSEUDO_REGISTER) 413 414 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) 415 416 #define PREFERRED_RELOAD_CLASS(X, CLASS) mep_preferred_reload_class (X, CLASS) 417 418 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 419 mep_secondary_input_reload_class (CLASS, MODE, X) 420 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 421 mep_secondary_output_reload_class (CLASS, MODE, X) 422 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 423 mep_secondary_memory_needed (CLASS1, CLASS2, MODE) 424 425 #define WANT_GCC_DECLARATIONS 426 #include "mep-intrin.h" 427 #undef WANT_GCC_DECLARATIONS 428 429 extern int mep_intrinsic_insn[]; 430 extern unsigned int mep_selected_isa; 431 432 /* True if intrinsic X is available. X is a mep_* value declared 433 in mep-intrin.h. */ 434 #define MEP_INTRINSIC_AVAILABLE_P(X) (mep_intrinsic_insn[X] >= 0) 435 436 /* Used to define CGEN_ENABLE_INTRINSIC_P in mep-intrin.h. */ 437 #define CGEN_CURRENT_ISAS mep_selected_isa 438 #define CGEN_CURRENT_GROUP \ 439 (mep_vliw_function_p (cfun->decl) ? GROUP_VLIW : GROUP_NORMAL) 440 441 442 443 #define STACK_GROWS_DOWNWARD 1 444 #define FRAME_GROWS_DOWNWARD 1 445 #define STARTING_FRAME_OFFSET 0 446 #define FIRST_PARM_OFFSET(FUNDECL) 0 447 #define INCOMING_FRAME_SP_OFFSET 0 448 449 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) mep_return_addr_rtx (COUNT) 450 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, LP_REGNO) 451 #define DWARF_FRAME_RETURN_COLUMN LP_REGNO 452 453 #define STACK_POINTER_REGNUM 15 454 #define FRAME_POINTER_REGNUM 8 455 #define ARG_POINTER_REGNUM 112 456 #define RETURN_ADDRESS_POINTER_REGNUM 17 457 #define STATIC_CHAIN_REGNUM 0 458 459 460 461 #define ELIMINABLE_REGS \ 462 { \ 463 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 464 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 465 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ 466 } 467 468 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 469 (OFFSET) = mep_elimination_offset (FROM, TO) 470 471 #define ACCUMULATE_OUTGOING_ARGS 1 472 473 474 475 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) 1 476 477 typedef struct 478 { 479 int nregs; 480 int vliw; 481 } CUMULATIVE_ARGS; 482 483 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 484 mep_init_cumulative_args (& (CUM), FNTYPE, LIBNAME, FNDECL) 485 486 #define FUNCTION_ARG_REGNO_P(REGNO) \ 487 (((REGNO) >= 1 && (REGNO) <= 4) \ 488 || ((REGNO) >= FIRST_CR_REGNO + 1 \ 489 && (REGNO) <= FIRST_CR_REGNO + 4 \ 490 && TARGET_COP)) 491 492 #define RETURN_VALUE_REGNUM 0 493 494 #define FUNCTION_VALUE(VALTYPE, FUNC) mep_function_value (VALTYPE, FUNC) 495 #define LIBCALL_VALUE(MODE) mep_libcall_value (MODE) 496 497 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 498 ((REGNO) == RETURN_VALUE_REGNUM) 499 500 #define DEFAULT_PCC_STRUCT_RETURN 0 501 502 #define STRUCT_VALUE 0 503 504 #define FUNCTION_OK_FOR_SIBCALL(DECL) mep_function_ok_for_sibcall(DECL) 505 506 /* Prologue and epilogues are all handled via RTL. */ 507 508 #define EXIT_IGNORE_STACK 1 509 510 #define EPILOGUE_USES(REGNO) mep_epilogue_uses (REGNO) 511 512 /* Profiling is supported. */ 513 514 #define FUNCTION_PROFILER(FILE, LABELNO) mep_function_profiler (FILE); 515 #undef TARGET_HAS_F_SETLKW 516 #define NO_PROFILE_COUNTERS 1 517 518 /* Trampolines are built at run-time. The cache is invalidated at 519 run-time also. */ 520 521 #define TRAMPOLINE_SIZE 20 522 523 524 #define MAX_REGS_PER_ADDRESS 1 525 526 #ifdef REG_OK_STRICT 527 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 528 if (mep_legitimate_address ((MODE), (X), 1)) goto LABEL 529 #else 530 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 531 if (mep_legitimate_address ((MODE), (X), 0)) goto LABEL 532 #endif 533 534 #ifdef REG_OK_STRICT 535 #define REG_OK_FOR_BASE_P(X) GR_REGNO_P (REGNO (X)) 536 #else 537 #define REG_OK_FOR_BASE_P(X) (GR_REGNO_P (REGNO (X)) \ 538 || REGNO (X) == ARG_POINTER_REGNUM \ 539 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 540 #endif 541 542 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 543 544 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 545 if (mep_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE), (IND_LEVELS))) \ 546 goto WIN 547 548 #define SELECT_CC_MODE(OP, X, Y) CCmode 549 550 551 /* Moves between control regs need a scratch. */ 552 #define REGISTER_MOVE_COST(MODE, FROM, TO) mep_register_move_cost (MODE, FROM, TO) 553 554 #define SLOW_BYTE_ACCESS 1 555 556 /* Define this macro if it is as good or better to call a constant function 557 address than to call an address kept in a register. */ 558 #define NO_FUNCTION_CSE 559 560 561 #define TEXT_SECTION_ASM_OP "\t.text\n\t.core" 562 #define DATA_SECTION_ASM_OP "\t.data" 563 #define BSS_SECTION_ASM_OP ".bss" 564 565 #define USE_SELECT_SECTION_FOR_FUNCTIONS 1 566 567 #define JUMP_TABLES_IN_TEXT_SECTION 1 568 569 #define TARGET_ASM_FILE_END mep_file_cleanups 570 571 #define ASM_APP_ON "#APP\n" 572 #define ASM_APP_OFF "#NO_APP\n" 573 574 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ 575 do \ 576 { \ 577 long l[2]; \ 578 \ 579 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ 580 fprintf (FILE, "\t.long\t0x%lx,0x%lx\n", l[0], l[1]); \ 581 } \ 582 while (0) 583 584 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ 585 do \ 586 { \ 587 long l; \ 588 \ 589 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 590 fprintf ((FILE), "\t.long\t0x%lx\n", l); \ 591 } \ 592 while (0) 593 594 #define ASM_OUTPUT_CHAR(FILE, VALUE) \ 595 do \ 596 { \ 597 fprintf (FILE, "\t.byte\t"); \ 598 output_addr_const (FILE, (VALUE)); \ 599 fprintf (FILE, "\n"); \ 600 } \ 601 while (0) 602 603 #define ASM_OUTPUT_SHORT(FILE, VALUE) \ 604 do \ 605 { \ 606 fprintf (FILE, "\t.hword\t"); \ 607 output_addr_const (FILE, (VALUE)); \ 608 fprintf (FILE, "\n"); \ 609 } \ 610 while (0) 611 612 #define ASM_OUTPUT_INT(FILE, VALUE) \ 613 do \ 614 { \ 615 fprintf (FILE, "\t.word\t"); \ 616 output_addr_const (FILE, (VALUE)); \ 617 fprintf (FILE, "\n"); \ 618 } \ 619 while (0) 620 621 /* Most of these are here to support based/tiny/far/io attributes. */ 622 623 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 624 mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) 625 626 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 627 mep_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) 628 629 #define ASM_OUTPUT_LABEL(STREAM, NAME) \ 630 do \ 631 { \ 632 assemble_name (STREAM, NAME); \ 633 fputs (":\n", STREAM); \ 634 } \ 635 while (0) 636 637 /* Globalizing directive for a label. */ 638 #define GLOBAL_ASM_OP "\t.globl " 639 640 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 641 asm_fprintf ((STREAM), "%U%s", mep_strip_name_encoding (NAME)) 642 643 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \ 644 do \ 645 { \ 646 (OUTVAR) = (char *) alloca (strlen ((NAME)) + 12); \ 647 sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER)); \ 648 } \ 649 while (0) 650 651 652 #define REGISTER_NAMES \ 653 { \ 654 /* Core registers. */ \ 655 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 656 "$8", "$9", "$10", "$11", "$12", "$tp", "$gp", "$sp", \ 657 /* Control registers. */ \ 658 "$pc", "$lp", "$sar", "3", "$rpb", "$rpe", "$rpc", "$hi", \ 659 "$lo", "9", "10", "11", "$mb0", "$me0", "$mb1", "$me1", \ 660 "$psw", "$id", "$tmp", "$epc", "$exc", "$cfg", "22", "$npc", \ 661 "$dbg", "$depc", "$opt", "$rcfg", "$ccfg", "29", "30", "31", \ 662 /* Coprocessor registers. */ \ 663 "$c0", "$c1", "$c2", "$c3", "$c4", "$c5", "$c6", "$c7", \ 664 "$c8", "$c9", "$c10", "$c11", "$c12", "$c13", "$c14", "$c15", \ 665 "$c16", "$c17", "$c18", "$c19", "$c20", "$c21", "$c22", "$c23", \ 666 "$c24", "$c25", "$c26", "$c27", "$c28", "$c29", "$c30", "$c31", \ 667 /* Coprocessor control registers. */ \ 668 "$ccr0", "$ccr1", "$ccr2", "$ccr3", "$ccr4", "$ccr5", "$ccr6", \ 669 "$ccr7", "$ccr8", "$ccr9", "$ccr10", "$ccr11", "$ccr12", "$ccr13", \ 670 "$ccr14", "$ccr15", "$ccr16", "$ccr17", "$ccr18", "$ccr19", "$ccr20", \ 671 "$ccr21", "$ccr22", "$ccr23", "$ccr24", "$ccr25", "$ccr26", "$ccr27", \ 672 "$ccr28", "$ccr29", "$ccr30", "$ccr31", \ 673 /* Virtual arg pointer. */ \ 674 "$argp", SHADOW_REGISTER_NAMES \ 675 } 676 677 /* We duplicate some of the above because we twiddle the above 678 according to *how* the registers are used. Likewise, we include 679 the standard names for coprocessor control registers so that 680 coprocessor options can rename them in the default table. Note 681 that these are compared to stripped names (see REGISTER_PREFIX 682 below). */ 683 #define ADDITIONAL_REGISTER_NAMES \ 684 { \ 685 { "8", 8 }, { "fp", 8 }, \ 686 { "13", 13 }, { "tp", 13 }, \ 687 { "14", 14 }, { "gp", 14 }, \ 688 { "15", 15 }, { "sp", 15 }, \ 689 { "ccr0", FIRST_CCR_REGNO + 0 }, \ 690 { "ccr1", FIRST_CCR_REGNO + 1 }, \ 691 { "ccr2", FIRST_CCR_REGNO + 2 }, \ 692 { "ccr3", FIRST_CCR_REGNO + 3 }, \ 693 { "ccr4", FIRST_CCR_REGNO + 4 }, \ 694 { "ccr5", FIRST_CCR_REGNO + 5 }, \ 695 { "ccr6", FIRST_CCR_REGNO + 6 }, \ 696 { "ccr7", FIRST_CCR_REGNO + 7 }, \ 697 { "ccr8", FIRST_CCR_REGNO + 8 }, \ 698 { "ccr9", FIRST_CCR_REGNO + 9 }, \ 699 { "ccr10", FIRST_CCR_REGNO + 10 }, \ 700 { "ccr11", FIRST_CCR_REGNO + 11 }, \ 701 { "ccr12", FIRST_CCR_REGNO + 12 }, \ 702 { "ccr13", FIRST_CCR_REGNO + 13 }, \ 703 { "ccr14", FIRST_CCR_REGNO + 14 }, \ 704 { "ccr15", FIRST_CCR_REGNO + 15 }, \ 705 { "ccr16", FIRST_CCR_REGNO + 16 }, \ 706 { "ccr17", FIRST_CCR_REGNO + 17 }, \ 707 { "ccr18", FIRST_CCR_REGNO + 18 }, \ 708 { "ccr19", FIRST_CCR_REGNO + 19 }, \ 709 { "ccr20", FIRST_CCR_REGNO + 20 }, \ 710 { "ccr21", FIRST_CCR_REGNO + 21 }, \ 711 { "ccr22", FIRST_CCR_REGNO + 22 }, \ 712 { "ccr23", FIRST_CCR_REGNO + 23 }, \ 713 { "ccr24", FIRST_CCR_REGNO + 24 }, \ 714 { "ccr25", FIRST_CCR_REGNO + 25 }, \ 715 { "ccr26", FIRST_CCR_REGNO + 26 }, \ 716 { "ccr27", FIRST_CCR_REGNO + 27 }, \ 717 { "ccr28", FIRST_CCR_REGNO + 28 }, \ 718 { "ccr29", FIRST_CCR_REGNO + 29 }, \ 719 { "ccr30", FIRST_CCR_REGNO + 30 }, \ 720 { "ccr31", FIRST_CCR_REGNO + 31 } \ 721 } 722 723 /* We watch for pipeline hazards with these */ 724 #define ASM_OUTPUT_OPCODE(STREAM, PTR) mep_asm_output_opcode (STREAM, PTR) 725 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) mep_final_prescan_insn (INSN, OPVEC, NOPERANDS) 726 727 #define PRINT_OPERAND(STREAM, X, CODE) mep_print_operand (STREAM, X, CODE) 728 729 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '!' || (CODE) == '<') 730 731 #define PRINT_OPERAND_ADDRESS(STREAM, X) mep_print_operand_address (STREAM, X) 732 733 #define REGISTER_PREFIX "$" 734 #define LOCAL_LABEL_PREFIX "." 735 #define USER_LABEL_PREFIX "" 736 #define IMMEDIATE_PREFIX "" 737 738 739 740 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 741 fprintf (STREAM, "\t.word .L%d\n", VALUE) 742 743 744 745 #undef PREFERRED_DEBUGGING_TYPE 746 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 747 #define DWARF2_DEBUGGING_INFO 1 748 #define DWARF2_UNWIND_INFO 1 749 750 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 10 : INVALID_REGNUM) 751 752 #define EH_RETURN_STACKADJ_RTX mep_return_stackadj_rtx () 753 #define EH_RETURN_HANDLER_RTX mep_return_handler_rtx () 754 755 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 756 757 758 759 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 760 fprintf ((STREAM), "\t.p2align %d\n", (POWER)) 761 762 763 764 #define CASE_VECTOR_MODE SImode 765 766 #define WORD_REGISTER_OPERATIONS 767 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND 768 769 #define SHORT_IMMEDIATES_SIGN_EXTEND 770 771 #define MOVE_MAX 4 772 773 #define SHIFT_COUNT_TRUNCATED 1 774 775 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 776 777 #define STORE_FLAG_VALUE 1 778 779 #define Pmode SImode 780 781 #define FUNCTION_MODE SImode 782 783 #define REGISTER_TARGET_PRAGMAS() mep_register_pragmas () 784 785 /* If defined, a C expression to determine the base term of address X. 786 This macro is used in only one place: `find_base_term' in alias.c. 787 788 It is always safe for this macro to not be defined. It exists so 789 that alias analysis can understand machine-dependent addresses. 790 791 The typical use of this macro is to handle addresses containing 792 a label_ref or symbol_ref within an UNSPEC. */ 793 #define FIND_BASE_TERM(X) mep_find_base_term (X) 794