1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2013 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 /* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29 #ifndef RS6000_OPTS_H 30 #include "config/rs6000/rs6000-opts.h" 31 #endif 32 33 /* Definitions for the object file format. These are set at 34 compile-time. */ 35 36 #define OBJECT_XCOFF 1 37 #define OBJECT_ELF 2 38 #define OBJECT_PEF 3 39 #define OBJECT_MACHO 4 40 41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 45 46 #ifndef TARGET_AIX 47 #define TARGET_AIX 0 48 #endif 49 50 #ifndef TARGET_AIX_OS 51 #define TARGET_AIX_OS 0 52 #endif 53 54 /* Control whether function entry points use a "dot" symbol when 55 ABI_AIX. */ 56 #define DOT_SYMBOLS 1 57 58 /* Default string to use for cpu if not specified. */ 59 #ifndef TARGET_CPU_DEFAULT 60 #define TARGET_CPU_DEFAULT ((char *)0) 61 #endif 62 63 /* If configured for PPC405, support PPC405CR Erratum77. */ 64 #ifdef CONFIG_PPC405CR 65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 66 #else 67 #define PPC405_ERRATUM77 0 68 #endif 69 70 #ifndef TARGET_PAIRED_FLOAT 71 #define TARGET_PAIRED_FLOAT 0 72 #endif 73 74 #ifdef HAVE_AS_POPCNTB 75 #define ASM_CPU_POWER5_SPEC "-mpower5" 76 #else 77 #define ASM_CPU_POWER5_SPEC "-mpower4" 78 #endif 79 80 #ifdef HAVE_AS_DFP 81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" 82 #else 83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" 84 #endif 85 86 #ifdef HAVE_AS_POPCNTD 87 #define ASM_CPU_POWER7_SPEC "-mpower7" 88 #else 89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" 90 #endif 91 92 #ifdef HAVE_AS_POWER8 93 #define ASM_CPU_POWER8_SPEC "-mpower8" 94 #else 95 #define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec" 96 #endif 97 98 #ifdef HAVE_AS_DCI 99 #define ASM_CPU_476_SPEC "-m476" 100 #else 101 #define ASM_CPU_476_SPEC "-mpower4" 102 #endif 103 104 /* Common ASM definitions used by ASM_SPEC among the various targets for 105 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 106 provide the default assembler options if the user uses -mcpu=native, so if 107 you make changes here, make them also there. */ 108 #define ASM_CPU_SPEC \ 109 "%{!mcpu*: \ 110 %{mpowerpc64*: -mppc64} \ 111 %{!mpowerpc64*: %(asm_default)}} \ 112 %{mcpu=native: %(asm_cpu_native)} \ 113 %{mcpu=cell: -mcell} \ 114 %{mcpu=power3: -mppc64} \ 115 %{mcpu=power4: -mpower4} \ 116 %{mcpu=power5: %(asm_cpu_power5)} \ 117 %{mcpu=power5+: %(asm_cpu_power5)} \ 118 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ 119 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ 120 %{mcpu=power7: %(asm_cpu_power7)} \ 121 %{mcpu=power8: %(asm_cpu_power8)} \ 122 %{mcpu=a2: -ma2} \ 123 %{mcpu=powerpc: -mppc} \ 124 %{mcpu=rs64a: -mppc64} \ 125 %{mcpu=401: -mppc} \ 126 %{mcpu=403: -m403} \ 127 %{mcpu=405: -m405} \ 128 %{mcpu=405fp: -m405} \ 129 %{mcpu=440: -m440} \ 130 %{mcpu=440fp: -m440} \ 131 %{mcpu=464: -m440} \ 132 %{mcpu=464fp: -m440} \ 133 %{mcpu=476: %(asm_cpu_476)} \ 134 %{mcpu=476fp: %(asm_cpu_476)} \ 135 %{mcpu=505: -mppc} \ 136 %{mcpu=601: -m601} \ 137 %{mcpu=602: -mppc} \ 138 %{mcpu=603: -mppc} \ 139 %{mcpu=603e: -mppc} \ 140 %{mcpu=ec603e: -mppc} \ 141 %{mcpu=604: -mppc} \ 142 %{mcpu=604e: -mppc} \ 143 %{mcpu=620: -mppc64} \ 144 %{mcpu=630: -mppc64} \ 145 %{mcpu=740: -mppc} \ 146 %{mcpu=750: -mppc} \ 147 %{mcpu=G3: -mppc} \ 148 %{mcpu=7400: -mppc -maltivec} \ 149 %{mcpu=7450: -mppc -maltivec} \ 150 %{mcpu=G4: -mppc -maltivec} \ 151 %{mcpu=801: -mppc} \ 152 %{mcpu=821: -mppc} \ 153 %{mcpu=823: -mppc} \ 154 %{mcpu=860: -mppc} \ 155 %{mcpu=970: -mpower4 -maltivec} \ 156 %{mcpu=G5: -mpower4 -maltivec} \ 157 %{mcpu=8540: -me500} \ 158 %{mcpu=8548: -me500} \ 159 %{mcpu=e300c2: -me300} \ 160 %{mcpu=e300c3: -me300} \ 161 %{mcpu=e500mc: -me500mc} \ 162 %{mcpu=e500mc64: -me500mc64} \ 163 %{mcpu=e5500: -me5500} \ 164 %{mcpu=e6500: -me6500} \ 165 %{maltivec: -maltivec} \ 166 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ 167 -many" 168 169 #define CPP_DEFAULT_SPEC "" 170 171 #define ASM_DEFAULT_SPEC "" 172 173 /* This macro defines names of additional specifications to put in the specs 174 that can be used in various specifications like CC1_SPEC. Its definition 175 is an initializer with a subgrouping for each command option. 176 177 Each subgrouping contains a string constant, that defines the 178 specification name, and a string constant that used by the GCC driver 179 program. 180 181 Do not define this macro if it does not need to do anything. */ 182 183 #define SUBTARGET_EXTRA_SPECS 184 185 #define EXTRA_SPECS \ 186 { "cpp_default", CPP_DEFAULT_SPEC }, \ 187 { "asm_cpu", ASM_CPU_SPEC }, \ 188 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 189 { "asm_default", ASM_DEFAULT_SPEC }, \ 190 { "cc1_cpu", CC1_CPU_SPEC }, \ 191 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ 192 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ 193 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ 194 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ 195 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ 196 SUBTARGET_EXTRA_SPECS 197 198 /* -mcpu=native handling only makes sense with compiler running on 199 an PowerPC chip. If changing this condition, also change 200 the condition in driver-rs6000.c. */ 201 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 202 /* In driver-rs6000.c. */ 203 extern const char *host_detect_local_cpu (int argc, const char **argv); 204 #define EXTRA_SPEC_FUNCTIONS \ 205 { "local_cpu_detect", host_detect_local_cpu }, 206 #define HAVE_LOCAL_CPU_DETECT 207 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 208 209 #else 210 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 211 #endif 212 213 #ifndef CC1_CPU_SPEC 214 #ifdef HAVE_LOCAL_CPU_DETECT 215 #define CC1_CPU_SPEC \ 216 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 217 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 218 #else 219 #define CC1_CPU_SPEC "" 220 #endif 221 #endif 222 223 /* Architecture type. */ 224 225 /* Define TARGET_MFCRF if the target assembler does not support the 226 optional field operand for mfcr. */ 227 228 #ifndef HAVE_AS_MFCRF 229 #undef TARGET_MFCRF 230 #define TARGET_MFCRF 0 231 #endif 232 233 /* Define TARGET_POPCNTB if the target assembler does not support the 234 popcount byte instruction. */ 235 236 #ifndef HAVE_AS_POPCNTB 237 #undef TARGET_POPCNTB 238 #define TARGET_POPCNTB 0 239 #endif 240 241 /* Define TARGET_FPRND if the target assembler does not support the 242 fp rounding instructions. */ 243 244 #ifndef HAVE_AS_FPRND 245 #undef TARGET_FPRND 246 #define TARGET_FPRND 0 247 #endif 248 249 /* Define TARGET_CMPB if the target assembler does not support the 250 cmpb instruction. */ 251 252 #ifndef HAVE_AS_CMPB 253 #undef TARGET_CMPB 254 #define TARGET_CMPB 0 255 #endif 256 257 /* Define TARGET_MFPGPR if the target assembler does not support the 258 mffpr and mftgpr instructions. */ 259 260 #ifndef HAVE_AS_MFPGPR 261 #undef TARGET_MFPGPR 262 #define TARGET_MFPGPR 0 263 #endif 264 265 /* Define TARGET_DFP if the target assembler does not support decimal 266 floating point instructions. */ 267 #ifndef HAVE_AS_DFP 268 #undef TARGET_DFP 269 #define TARGET_DFP 0 270 #endif 271 272 /* Define TARGET_POPCNTD if the target assembler does not support the 273 popcount word and double word instructions. */ 274 275 #ifndef HAVE_AS_POPCNTD 276 #undef TARGET_POPCNTD 277 #define TARGET_POPCNTD 0 278 #endif 279 280 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If 281 not, generate the lwsync code as an integer constant. */ 282 #ifdef HAVE_AS_LWSYNC 283 #define TARGET_LWSYNC_INSTRUCTION 1 284 #else 285 #define TARGET_LWSYNC_INSTRUCTION 0 286 #endif 287 288 /* Define TARGET_TLS_MARKERS if the target assembler does not support 289 arg markers for __tls_get_addr calls. */ 290 #ifndef HAVE_AS_TLS_MARKERS 291 #undef TARGET_TLS_MARKERS 292 #define TARGET_TLS_MARKERS 0 293 #else 294 #define TARGET_TLS_MARKERS tls_markers 295 #endif 296 297 #ifndef TARGET_SECURE_PLT 298 #define TARGET_SECURE_PLT 0 299 #endif 300 301 #ifndef TARGET_CMODEL 302 #define TARGET_CMODEL CMODEL_SMALL 303 #endif 304 305 #define TARGET_32BIT (! TARGET_64BIT) 306 307 #ifndef HAVE_AS_TLS 308 #define HAVE_AS_TLS 0 309 #endif 310 311 #ifndef TARGET_LINK_STACK 312 #define TARGET_LINK_STACK 0 313 #endif 314 315 #ifndef SET_TARGET_LINK_STACK 316 #define SET_TARGET_LINK_STACK(X) do { } while (0) 317 #endif 318 319 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 320 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 321 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 322 323 #ifdef IN_LIBGCC2 324 /* For libgcc2 we make sure this is a compile time constant */ 325 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 326 #undef TARGET_POWERPC64 327 #define TARGET_POWERPC64 1 328 #else 329 #undef TARGET_POWERPC64 330 #define TARGET_POWERPC64 0 331 #endif 332 #else 333 /* The option machinery will define this. */ 334 #endif 335 336 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) 337 338 /* FPU operations supported. 339 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must 340 also test TARGET_HARD_FLOAT. */ 341 #define TARGET_SINGLE_FLOAT 1 342 #define TARGET_DOUBLE_FLOAT 1 343 #define TARGET_SINGLE_FPU 0 344 #define TARGET_SIMPLE_FPU 0 345 #define TARGET_XILINX_FPU 0 346 347 /* Recast the processor type to the cpu attribute. */ 348 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 349 350 /* Define generic processor types based upon current deployment. */ 351 #define PROCESSOR_COMMON PROCESSOR_PPC601 352 #define PROCESSOR_POWERPC PROCESSOR_PPC604 353 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 354 355 /* Define the default processor. This is overridden by other tm.h files. */ 356 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 357 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 358 359 /* Specify the dialect of assembler to use. Only new mnemonics are supported 360 starting with GCC 4.8, i.e. just one dialect, but for backwards 361 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 362 defined. */ 363 #define ASSEMBLER_DIALECT 1 364 365 /* Debug support */ 366 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 367 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 368 #define MASK_DEBUG_REG 0x04 /* debug register handling */ 369 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 370 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 371 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 372 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 373 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 374 | MASK_DEBUG_ARG \ 375 | MASK_DEBUG_REG \ 376 | MASK_DEBUG_ADDR \ 377 | MASK_DEBUG_COST \ 378 | MASK_DEBUG_TARGET \ 379 | MASK_DEBUG_BUILTIN) 380 381 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 382 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 383 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 384 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 385 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 386 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 387 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 388 389 extern enum rs6000_vector rs6000_vector_unit[]; 390 391 #define VECTOR_UNIT_NONE_P(MODE) \ 392 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 393 394 #define VECTOR_UNIT_VSX_P(MODE) \ 395 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 396 397 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 398 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 399 400 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 401 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \ 402 || rs6000_vector_unit[(MODE)] == VECTOR_VSX) 403 404 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 405 same unit as the vector unit we are using, but we may want to migrate to 406 using VSX style loads even for types handled by altivec. */ 407 extern enum rs6000_vector rs6000_vector_mem[]; 408 409 #define VECTOR_MEM_NONE_P(MODE) \ 410 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 411 412 #define VECTOR_MEM_VSX_P(MODE) \ 413 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 414 415 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 416 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 417 418 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 419 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \ 420 || rs6000_vector_mem[(MODE)] == VECTOR_VSX) 421 422 /* Return the alignment of a given vector type, which is set based on the 423 vector unit use. VSX for instance can load 32 or 64 bit aligned words 424 without problems, while Altivec requires 128-bit aligned vectors. */ 425 extern int rs6000_vector_align[]; 426 427 #define VECTOR_ALIGN(MODE) \ 428 ((rs6000_vector_align[(MODE)] != 0) \ 429 ? rs6000_vector_align[(MODE)] \ 430 : (int)GET_MODE_BITSIZE ((MODE))) 431 432 /* Alignment options for fields in structures for sub-targets following 433 AIX-like ABI. 434 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 435 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 436 437 Override the macro definitions when compiling libobjc to avoid undefined 438 reference to rs6000_alignment_flags due to library's use of GCC alignment 439 macros which use the macros below. */ 440 441 #ifndef IN_TARGET_LIBS 442 #define MASK_ALIGN_POWER 0x00000000 443 #define MASK_ALIGN_NATURAL 0x00000001 444 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 445 #else 446 #define TARGET_ALIGN_NATURAL 0 447 #endif 448 449 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 450 #define TARGET_IEEEQUAD rs6000_ieeequad 451 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 452 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 453 454 #define TARGET_SPE_ABI 0 455 #define TARGET_SPE 0 456 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) 457 #define TARGET_FPRS 1 458 #define TARGET_E500_SINGLE 0 459 #define TARGET_E500_DOUBLE 0 460 #define CHECK_E500_OPTIONS do { } while (0) 461 462 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 463 Enable 32-bit fcfid's on any of the switches for newer ISA machines or 464 XILINX. */ 465 #define TARGET_FCFID (TARGET_POWERPC64 \ 466 || TARGET_PPC_GPOPT /* 970/power4 */ \ 467 || TARGET_POPCNTB /* ISA 2.02 */ \ 468 || TARGET_CMPB /* ISA 2.05 */ \ 469 || TARGET_POPCNTD /* ISA 2.06 */ \ 470 || TARGET_XILINX_FPU) 471 472 #define TARGET_FCTIDZ TARGET_FCFID 473 #define TARGET_STFIWX TARGET_PPC_GFXOPT 474 #define TARGET_LFIWAX TARGET_CMPB 475 #define TARGET_LFIWZX TARGET_POPCNTD 476 #define TARGET_FCFIDS TARGET_POPCNTD 477 #define TARGET_FCFIDU TARGET_POPCNTD 478 #define TARGET_FCFIDUS TARGET_POPCNTD 479 #define TARGET_FCTIDUZ TARGET_POPCNTD 480 #define TARGET_FCTIWUZ TARGET_POPCNTD 481 482 /* In switching from using target_flags to using rs6000_isa_flags, the options 483 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 484 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 485 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 486 #define MASK_CMPB OPTION_MASK_CMPB 487 #define MASK_DFP OPTION_MASK_DFP 488 #define MASK_DLMZB OPTION_MASK_DLMZB 489 #define MASK_EABI OPTION_MASK_EABI 490 #define MASK_FPRND OPTION_MASK_FPRND 491 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 492 #define MASK_ISEL OPTION_MASK_ISEL 493 #define MASK_MFCRF OPTION_MASK_MFCRF 494 #define MASK_MFPGPR OPTION_MASK_MFPGPR 495 #define MASK_MULHW OPTION_MASK_MULHW 496 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE 497 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 498 #define MASK_POPCNTB OPTION_MASK_POPCNTB 499 #define MASK_POPCNTD OPTION_MASK_POPCNTD 500 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 501 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 502 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 503 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 504 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 505 #define MASK_STRING OPTION_MASK_STRING 506 #define MASK_UPDATE OPTION_MASK_UPDATE 507 #define MASK_VSX OPTION_MASK_VSX 508 509 #ifndef IN_LIBGCC2 510 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 511 #endif 512 513 #ifdef TARGET_64BIT 514 #define MASK_64BIT OPTION_MASK_64BIT 515 #endif 516 517 #ifdef TARGET_RELOCATABLE 518 #define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE 519 #endif 520 521 #ifdef TARGET_LITTLE_ENDIAN 522 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 523 #endif 524 525 #ifdef TARGET_MINIMAL_TOC 526 #define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC 527 #endif 528 529 #ifdef TARGET_REGNAMES 530 #define MASK_REGNAMES OPTION_MASK_REGNAMES 531 #endif 532 533 #ifdef TARGET_PROTOTYPE 534 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 535 #endif 536 537 /* Explicit ISA options that were set. */ 538 #define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags 539 540 /* For power systems, we want to enable Altivec and VSX builtins even if the 541 user did not use -maltivec or -mvsx to allow the builtins to be used inside 542 of #pragma GCC target or the target attribute to change the code level for a 543 given system. The SPE and Paired builtins are only enabled if you configure 544 the compiler for those builtins, and those machines don't support altivec or 545 VSX. */ 546 547 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ 548 && ((TARGET_POWERPC64 \ 549 || TARGET_PPC_GPOPT /* 970/power4 */ \ 550 || TARGET_POPCNTB /* ISA 2.02 */ \ 551 || TARGET_CMPB /* ISA 2.05 */ \ 552 || TARGET_POPCNTD /* ISA 2.06 */ \ 553 || TARGET_ALTIVEC \ 554 || TARGET_VSX))) 555 556 /* E500 cores only support plain "sync", not lwsync. */ 557 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 558 || rs6000_cpu == PROCESSOR_PPC8548) 559 560 561 /* Which machine supports the various reciprocal estimate instructions. */ 562 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 563 && TARGET_FPRS && TARGET_SINGLE_FLOAT) 564 565 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ 566 && TARGET_DOUBLE_FLOAT \ 567 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 568 569 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 570 && TARGET_FPRS && TARGET_SINGLE_FLOAT) 571 572 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ 573 && TARGET_DOUBLE_FLOAT \ 574 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 575 576 /* Whether the various reciprocal divide/square root estimate instructions 577 exist, and whether we should automatically generate code for the instruction 578 by default. */ 579 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 580 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 581 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 582 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 583 584 extern unsigned char rs6000_recip_bits[]; 585 586 #define RS6000_RECIP_HAVE_RE_P(MODE) \ 587 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 588 589 #define RS6000_RECIP_AUTO_RE_P(MODE) \ 590 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 591 592 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 593 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 594 595 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 596 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 597 598 #define RS6000_RECIP_HIGH_PRECISION_P(MODE) \ 599 ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION) 600 601 /* The default CPU for TARGET_OPTION_OVERRIDE. */ 602 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 603 604 /* Target pragma. */ 605 #define REGISTER_TARGET_PRAGMAS() do { \ 606 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 607 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 608 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 609 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 610 } while (0) 611 612 /* Target #defines. */ 613 #define TARGET_CPU_CPP_BUILTINS() \ 614 rs6000_cpu_cpp_builtins (pfile) 615 616 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 617 we're compiling for. Some configurations may need to override it. */ 618 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 619 do \ 620 { \ 621 if (BYTES_BIG_ENDIAN) \ 622 { \ 623 builtin_define ("__BIG_ENDIAN__"); \ 624 builtin_define ("_BIG_ENDIAN"); \ 625 builtin_assert ("machine=bigendian"); \ 626 } \ 627 else \ 628 { \ 629 builtin_define ("__LITTLE_ENDIAN__"); \ 630 builtin_define ("_LITTLE_ENDIAN"); \ 631 builtin_assert ("machine=littleendian"); \ 632 } \ 633 } \ 634 while (0) 635 636 /* Target machine storage layout. */ 637 638 /* Define this macro if it is advisable to hold scalars in registers 639 in a wider mode than that declared by the program. In such cases, 640 the value is constrained to be within the bounds of the declared 641 type, but kept valid in the wider mode. The signedness of the 642 extension may differ from that of the type. */ 643 644 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 645 if (GET_MODE_CLASS (MODE) == MODE_INT \ 646 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 647 (MODE) = TARGET_32BIT ? SImode : DImode; 648 649 /* Define this if most significant bit is lowest numbered 650 in instructions that operate on numbered bit-fields. */ 651 /* That is true on RS/6000. */ 652 #define BITS_BIG_ENDIAN 1 653 654 /* Define this if most significant byte of a word is the lowest numbered. */ 655 /* That is true on RS/6000. */ 656 #define BYTES_BIG_ENDIAN 1 657 658 /* Define this if most significant word of a multiword number is lowest 659 numbered. 660 661 For RS/6000 we can decide arbitrarily since there are no machine 662 instructions for them. Might as well be consistent with bits and bytes. */ 663 #define WORDS_BIG_ENDIAN 1 664 665 #define MAX_BITS_PER_WORD 64 666 667 /* Width of a word, in units (bytes). */ 668 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 669 #ifdef IN_LIBGCC2 670 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 671 #else 672 #define MIN_UNITS_PER_WORD 4 673 #endif 674 #define UNITS_PER_FP_WORD 8 675 #define UNITS_PER_ALTIVEC_WORD 16 676 #define UNITS_PER_VSX_WORD 16 677 #define UNITS_PER_SPE_WORD 8 678 #define UNITS_PER_PAIRED_WORD 8 679 680 /* Type used for ptrdiff_t, as a string used in a declaration. */ 681 #define PTRDIFF_TYPE "int" 682 683 /* Type used for size_t, as a string used in a declaration. */ 684 #define SIZE_TYPE "long unsigned int" 685 686 /* Type used for wchar_t, as a string used in a declaration. */ 687 #define WCHAR_TYPE "short unsigned int" 688 689 /* Width of wchar_t in bits. */ 690 #define WCHAR_TYPE_SIZE 16 691 692 /* A C expression for the size in bits of the type `short' on the 693 target machine. If you don't define this, the default is half a 694 word. (If this would be less than one storage unit, it is 695 rounded up to one unit.) */ 696 #define SHORT_TYPE_SIZE 16 697 698 /* A C expression for the size in bits of the type `int' on the 699 target machine. If you don't define this, the default is one 700 word. */ 701 #define INT_TYPE_SIZE 32 702 703 /* A C expression for the size in bits of the type `long' on the 704 target machine. If you don't define this, the default is one 705 word. */ 706 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 707 708 /* A C expression for the size in bits of the type `long long' on the 709 target machine. If you don't define this, the default is two 710 words. */ 711 #define LONG_LONG_TYPE_SIZE 64 712 713 /* A C expression for the size in bits of the type `float' on the 714 target machine. If you don't define this, the default is one 715 word. */ 716 #define FLOAT_TYPE_SIZE 32 717 718 /* A C expression for the size in bits of the type `double' on the 719 target machine. If you don't define this, the default is two 720 words. */ 721 #define DOUBLE_TYPE_SIZE 64 722 723 /* A C expression for the size in bits of the type `long double' on 724 the target machine. If you don't define this, the default is two 725 words. */ 726 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 727 728 /* Define this to set long double type size to use in libgcc2.c, which can 729 not depend on target_flags. */ 730 #ifdef __LONG_DOUBLE_128__ 731 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 732 #else 733 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 734 #endif 735 736 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 737 #define WIDEST_HARDWARE_FP_SIZE 64 738 739 /* Width in bits of a pointer. 740 See also the macro `Pmode' defined below. */ 741 extern unsigned rs6000_pointer_size; 742 #define POINTER_SIZE rs6000_pointer_size 743 744 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 745 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 746 747 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 748 #define STACK_BOUNDARY \ 749 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 750 ? 64 : 128) 751 752 /* Allocation boundary (in *bits*) for the code of a function. */ 753 #define FUNCTION_BOUNDARY 32 754 755 /* No data type wants to be aligned rounder than this. */ 756 #define BIGGEST_ALIGNMENT 128 757 758 /* A C expression to compute the alignment for a variables in the 759 local store. TYPE is the data type, and ALIGN is the alignment 760 that the object would ordinarily have. */ 761 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 762 DATA_ALIGNMENT (TYPE, ALIGN) 763 764 /* Alignment of field after `int : 0' in a structure. */ 765 #define EMPTY_FIELD_BOUNDARY 32 766 767 /* Every structure's size must be a multiple of this. */ 768 #define STRUCTURE_SIZE_BOUNDARY 8 769 770 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 771 #define PCC_BITFIELD_TYPE_MATTERS 1 772 773 /* Make strings word-aligned so strcpy from constants will be faster. 774 Make vector constants quadword aligned. */ 775 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 776 (TREE_CODE (EXP) == STRING_CST \ 777 && (STRICT_ALIGNMENT || !optimize_size) \ 778 && (ALIGN) < BITS_PER_WORD \ 779 ? BITS_PER_WORD \ 780 : (ALIGN)) 781 782 /* Make arrays of chars word-aligned for the same reasons. 783 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to 784 64 bits. */ 785 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 786 (TREE_CODE (TYPE) == VECTOR_TYPE \ 787 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \ 788 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \ 789 ? 64 : 128) \ 790 : ((TARGET_E500_DOUBLE \ 791 && TREE_CODE (TYPE) == REAL_TYPE \ 792 && TYPE_MODE (TYPE) == DFmode) \ 793 ? 64 \ 794 : (TREE_CODE (TYPE) == ARRAY_TYPE \ 795 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 796 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) 797 798 /* Nonzero if move instructions will actually fail to work 799 when given unaligned data. */ 800 #define STRICT_ALIGNMENT 0 801 802 /* Define this macro to be the value 1 if unaligned accesses have a cost 803 many times greater than aligned accesses, for example if they are 804 emulated in a trap handler. */ 805 /* Altivec vector memory instructions simply ignore the low bits; SPE vector 806 memory instructions trap on unaligned accesses; VSX memory instructions are 807 aligned to 4 or 8 bytes. */ 808 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 809 (STRICT_ALIGNMENT \ 810 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 811 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \ 812 && (ALIGN) < 32) \ 813 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))) 814 815 816 /* Standard register usage. */ 817 818 /* Number of actual hardware registers. 819 The hardware registers are assigned numbers for the compiler 820 from 0 to just below FIRST_PSEUDO_REGISTER. 821 All registers that the compiler knows about must be given numbers, 822 even those that are not normally considered general registers. 823 824 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 825 a count register, a link register, and 8 condition register fields, 826 which we view here as separate registers. AltiVec adds 32 vector 827 registers and a VRsave register. 828 829 In addition, the difference between the frame and argument pointers is 830 a function of the number of registers saved, so we need to have a 831 register for AP that will later be eliminated in favor of SP or FP. 832 This is a normal register, but it is fixed. 833 834 We also create a pseudo register for float/int conversions, that will 835 really represent the memory location used. It is represented here as 836 a register, in order to work around problems in allocating stack storage 837 in inline functions. 838 839 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 840 pointer, which is eventually eliminated in favor of SP or FP. */ 841 842 #define FIRST_PSEUDO_REGISTER 114 843 844 /* This must be included for pre gcc 3.0 glibc compatibility. */ 845 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 846 847 /* Add 32 dwarf columns for synthetic SPE registers. */ 848 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) 849 850 /* The SPE has an additional 32 synthetic registers, with DWARF debug 851 info numbering for these registers starting at 1200. While eh_frame 852 register numbering need not be the same as the debug info numbering, 853 we choose to number these regs for eh_frame at 1200 too. This allows 854 future versions of the rs6000 backend to add hard registers and 855 continue to use the gcc hard register numbering for eh_frame. If the 856 extra SPE registers in eh_frame were numbered starting from the 857 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER 858 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to 859 avoid invalidating older SPE eh_frame info. 860 861 We must map them here to avoid huge unwinder tables mostly consisting 862 of unused space. */ 863 #define DWARF_REG_TO_UNWIND_COLUMN(r) \ 864 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) 865 866 /* Use standard DWARF numbering for DWARF debugging information. */ 867 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) 868 869 /* Use gcc hard register numbering for eh_frame. */ 870 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 871 872 /* Map register numbers held in the call frame info that gcc has 873 collected using DWARF_FRAME_REGNUM to those that should be output in 874 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers 875 for .eh_frame, but use the numbers mandated by the various ABIs for 876 .debug_frame. rs6000_emit_prologue has translated any combination of 877 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves 878 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ 879 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 880 ((FOR_EH) ? (REGNO) \ 881 : (REGNO) == CR2_REGNO ? 64 \ 882 : DBX_REGISTER_NUMBER (REGNO)) 883 884 /* 1 for registers that have pervasive standard uses 885 and are not available for the register allocator. 886 887 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 888 as a local register; for all other OS's r2 is the TOC pointer. 889 890 cr5 is not supposed to be used. 891 892 On System V implementations, r13 is fixed and not available for use. */ 893 894 #define FIXED_REGISTERS \ 895 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 899 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 900 /* AltiVec registers. */ \ 901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 903 1, 1 \ 904 , 1, 1, 1 \ 905 } 906 907 /* 1 for registers not available across function calls. 908 These must include the FIXED_REGISTERS and also any 909 registers that can be used without being saved. 910 The latter must include the registers where values are returned 911 and the register where structure-value addresses are passed. 912 Aside from that, you can include as many other registers as you like. */ 913 914 #define CALL_USED_REGISTERS \ 915 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 916 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 917 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 918 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 919 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 920 /* AltiVec registers. */ \ 921 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 922 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 923 1, 1 \ 924 , 1, 1, 1 \ 925 } 926 927 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 928 the entire set of `FIXED_REGISTERS' be included. 929 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 930 This macro is optional. If not specified, it defaults to the value 931 of `CALL_USED_REGISTERS'. */ 932 933 #define CALL_REALLY_USED_REGISTERS \ 934 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 935 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 936 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 937 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 938 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 939 /* AltiVec registers. */ \ 940 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 941 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 942 0, 0 \ 943 , 0, 0, 0 \ 944 } 945 946 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 947 948 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 949 #define FIRST_SAVED_FP_REGNO (14+32) 950 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 951 952 /* List the order in which to allocate registers. Each register must be 953 listed once, even those in FIXED_REGISTERS. 954 955 We allocate in the following order: 956 fp0 (not saved or used for anything) 957 fp13 - fp2 (not saved; incoming fp arg registers) 958 fp1 (not saved; return value) 959 fp31 - fp14 (saved; order given to save least number) 960 cr7, cr6 (not saved or special) 961 cr1 (not saved, but used for FP operations) 962 cr0 (not saved, but used for arithmetic operations) 963 cr4, cr3, cr2 (saved) 964 r9 (not saved; best for TImode) 965 r10, r8-r4 (not saved; highest first for less conflict with params) 966 r3 (not saved; return value register) 967 r11 (not saved; later alloc to help shrink-wrap) 968 r0 (not saved; cannot be base reg) 969 r31 - r13 (saved; order given to save least number) 970 r12 (not saved; if used for DImode or DFmode would use r13) 971 ctr (not saved; when we have the choice ctr is better) 972 lr (saved) 973 cr5, r1, r2, ap, ca (fixed) 974 v0 - v1 (not saved or used for anything) 975 v13 - v3 (not saved; incoming vector arg registers) 976 v2 (not saved; incoming vector arg reg; return value) 977 v19 - v14 (not saved or used for anything) 978 v31 - v20 (saved; order given to save least number) 979 vrsave, vscr (fixed) 980 spe_acc, spefscr (fixed) 981 sfp (fixed) 982 */ 983 984 #if FIXED_R2 == 1 985 #define MAYBE_R2_AVAILABLE 986 #define MAYBE_R2_FIXED 2, 987 #else 988 #define MAYBE_R2_AVAILABLE 2, 989 #define MAYBE_R2_FIXED 990 #endif 991 992 #if FIXED_R13 == 1 993 #define EARLY_R12 12, 994 #define LATE_R12 995 #else 996 #define EARLY_R12 997 #define LATE_R12 12, 998 #endif 999 1000 #define REG_ALLOC_ORDER \ 1001 {32, \ 1002 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 1003 33, \ 1004 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 1005 50, 49, 48, 47, 46, \ 1006 75, 74, 69, 68, 72, 71, 70, \ 1007 MAYBE_R2_AVAILABLE \ 1008 9, 10, 8, 7, 6, 5, 4, \ 1009 3, EARLY_R12 11, 0, \ 1010 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 1011 18, 17, 16, 15, 14, 13, LATE_R12 \ 1012 66, 65, \ 1013 73, 1, MAYBE_R2_FIXED 67, 76, \ 1014 /* AltiVec registers. */ \ 1015 77, 78, \ 1016 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 1017 79, \ 1018 96, 95, 94, 93, 92, 91, \ 1019 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 1020 109, 110, \ 1021 111, 112, 113 \ 1022 } 1023 1024 /* True if register is floating-point. */ 1025 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1026 1027 /* True if register is a condition register. */ 1028 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 1029 1030 /* True if register is a condition register, but not cr0. */ 1031 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 1032 1033 /* True if register is an integer register. */ 1034 #define INT_REGNO_P(N) \ 1035 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 1036 1037 /* SPE SIMD registers are just the GPRs. */ 1038 #define SPE_SIMD_REGNO_P(N) ((N) <= 31) 1039 1040 /* PAIRED SIMD registers are just the FPRs. */ 1041 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1042 1043 /* True if register is the CA register. */ 1044 #define CA_REGNO_P(N) ((N) == CA_REGNO) 1045 1046 /* True if register is an AltiVec register. */ 1047 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1048 1049 /* True if register is a VSX register. */ 1050 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1051 1052 /* Alternate name for any vector register supporting floating point, no matter 1053 which instruction set(s) are available. */ 1054 #define VFLOAT_REGNO_P(N) \ 1055 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1056 1057 /* Alternate name for any vector register supporting integer, no matter which 1058 instruction set(s) are available. */ 1059 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1060 1061 /* Alternate name for any vector register supporting logical operations, no 1062 matter which instruction set(s) are available. */ 1063 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N) 1064 1065 /* Return number of consecutive hard regs needed starting at reg REGNO 1066 to hold something of mode MODE. */ 1067 1068 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] 1069 1070 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1071 enough space to account for vectors in FP regs. However, TFmode/TDmode 1072 should not use VSX instructions to do a caller save. */ 1073 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1074 (TARGET_VSX \ 1075 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1076 && FP_REGNO_P (REGNO) \ 1077 ? V2DFmode \ 1078 : ((MODE) == TFmode && FP_REGNO_P (REGNO)) \ 1079 ? DFmode \ 1080 : ((MODE) == TDmode && FP_REGNO_P (REGNO)) \ 1081 ? DImode \ 1082 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 1083 1084 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1085 (((TARGET_32BIT && TARGET_POWERPC64 \ 1086 && (GET_MODE_SIZE (MODE) > 4) \ 1087 && INT_REGNO_P (REGNO)) ? 1 : 0) \ 1088 || (TARGET_VSX && FP_REGNO_P (REGNO) \ 1089 && GET_MODE_SIZE (MODE) > 8 && ((MODE) != TDmode) \ 1090 && ((MODE) != TFmode))) 1091 1092 #define VSX_VECTOR_MODE(MODE) \ 1093 ((MODE) == V4SFmode \ 1094 || (MODE) == V2DFmode) \ 1095 1096 #define ALTIVEC_VECTOR_MODE(MODE) \ 1097 ((MODE) == V16QImode \ 1098 || (MODE) == V8HImode \ 1099 || (MODE) == V4SFmode \ 1100 || (MODE) == V4SImode) 1101 1102 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1103 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1104 || (MODE) == V2DImode) 1105 1106 #define SPE_VECTOR_MODE(MODE) \ 1107 ((MODE) == V4HImode \ 1108 || (MODE) == V2SFmode \ 1109 || (MODE) == V1DImode \ 1110 || (MODE) == V2SImode) 1111 1112 #define PAIRED_VECTOR_MODE(MODE) \ 1113 ((MODE) == V2SFmode) 1114 1115 /* Value is TRUE if hard register REGNO can hold a value of 1116 machine-mode MODE. */ 1117 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1118 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] 1119 1120 /* Value is 1 if it is a good idea to tie two pseudo registers 1121 when one has mode MODE1 and one has mode MODE2. 1122 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1123 for any hard reg, then this must be 0 for correct output. */ 1124 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1125 (SCALAR_FLOAT_MODE_P (MODE1) \ 1126 ? SCALAR_FLOAT_MODE_P (MODE2) \ 1127 : SCALAR_FLOAT_MODE_P (MODE2) \ 1128 ? SCALAR_FLOAT_MODE_P (MODE1) \ 1129 : GET_MODE_CLASS (MODE1) == MODE_CC \ 1130 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 1131 : GET_MODE_CLASS (MODE2) == MODE_CC \ 1132 ? GET_MODE_CLASS (MODE1) == MODE_CC \ 1133 : SPE_VECTOR_MODE (MODE1) \ 1134 ? SPE_VECTOR_MODE (MODE2) \ 1135 : SPE_VECTOR_MODE (MODE2) \ 1136 ? SPE_VECTOR_MODE (MODE1) \ 1137 : ALTIVEC_VECTOR_MODE (MODE1) \ 1138 ? ALTIVEC_VECTOR_MODE (MODE2) \ 1139 : ALTIVEC_VECTOR_MODE (MODE2) \ 1140 ? ALTIVEC_VECTOR_MODE (MODE1) \ 1141 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ 1142 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1143 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1144 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ 1145 : 1) 1146 1147 /* Post-reload, we can't use any new AltiVec registers, as we already 1148 emitted the vrsave mask. */ 1149 1150 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1151 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1152 1153 /* Specify the cost of a branch insn; roughly the number of extra insns that 1154 should be added to avoid a branch. 1155 1156 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1157 unscheduled conditional branch. */ 1158 1159 #define BRANCH_COST(speed_p, predictable_p) 3 1160 1161 /* Override BRANCH_COST heuristic which empirically produces worse 1162 performance for removing short circuiting from the logical ops. */ 1163 1164 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1165 1166 /* A fixed register used at epilogue generation to address SPE registers 1167 with negative offsets. The 64-bit load/store instructions on the SPE 1168 only take positive offsets (and small ones at that), so we need to 1169 reserve a register for consing up negative offsets. */ 1170 1171 #define FIXED_SCRATCH 0 1172 1173 /* Specify the registers used for certain standard purposes. 1174 The values of these macros are register numbers. */ 1175 1176 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1177 /* #define PC_REGNUM */ 1178 1179 /* Register to use for pushing function arguments. */ 1180 #define STACK_POINTER_REGNUM 1 1181 1182 /* Base register for access to local variables of the function. */ 1183 #define HARD_FRAME_POINTER_REGNUM 31 1184 1185 /* Base register for access to local variables of the function. */ 1186 #define FRAME_POINTER_REGNUM 113 1187 1188 /* Base register for access to arguments of the function. */ 1189 #define ARG_POINTER_REGNUM 67 1190 1191 /* Place to put static chain when calling a function that requires it. */ 1192 #define STATIC_CHAIN_REGNUM 11 1193 1194 1195 /* Define the classes of registers for register constraints in the 1196 machine description. Also define ranges of constants. 1197 1198 One of the classes must always be named ALL_REGS and include all hard regs. 1199 If there is more than one class, another class must be named NO_REGS 1200 and contain no registers. 1201 1202 The name GENERAL_REGS must be the name of a class (or an alias for 1203 another name such as ALL_REGS). This is the class of registers 1204 that is allowed by "g" or "r" in a register constraint. 1205 Also, registers outside this class are allocated only when 1206 instructions express preferences for them. 1207 1208 The classes must be numbered in nondecreasing order; that is, 1209 a larger-numbered class must never be contained completely 1210 in a smaller-numbered class. 1211 1212 For any two classes, it is very desirable that there be another 1213 class that represents their union. */ 1214 1215 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1216 condition registers, plus three special registers, CTR, and the link 1217 register. AltiVec adds a vector register class. VSX registers overlap the 1218 FPR registers and the Altivec registers. 1219 1220 However, r0 is special in that it cannot be used as a base register. 1221 So make a class for registers valid as base registers. 1222 1223 Also, cr0 is the only condition code register that can be used in 1224 arithmetic insns, so make a separate class for it. */ 1225 1226 enum reg_class 1227 { 1228 NO_REGS, 1229 BASE_REGS, 1230 GENERAL_REGS, 1231 FLOAT_REGS, 1232 ALTIVEC_REGS, 1233 VSX_REGS, 1234 VRSAVE_REGS, 1235 VSCR_REGS, 1236 SPE_ACC_REGS, 1237 SPEFSCR_REGS, 1238 NON_SPECIAL_REGS, 1239 LINK_REGS, 1240 CTR_REGS, 1241 LINK_OR_CTR_REGS, 1242 SPECIAL_REGS, 1243 SPEC_OR_GEN_REGS, 1244 CR0_REGS, 1245 CR_REGS, 1246 NON_FLOAT_REGS, 1247 CA_REGS, 1248 ALL_REGS, 1249 LIM_REG_CLASSES 1250 }; 1251 1252 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1253 1254 /* Give names of register classes as strings for dump file. */ 1255 1256 #define REG_CLASS_NAMES \ 1257 { \ 1258 "NO_REGS", \ 1259 "BASE_REGS", \ 1260 "GENERAL_REGS", \ 1261 "FLOAT_REGS", \ 1262 "ALTIVEC_REGS", \ 1263 "VSX_REGS", \ 1264 "VRSAVE_REGS", \ 1265 "VSCR_REGS", \ 1266 "SPE_ACC_REGS", \ 1267 "SPEFSCR_REGS", \ 1268 "NON_SPECIAL_REGS", \ 1269 "LINK_REGS", \ 1270 "CTR_REGS", \ 1271 "LINK_OR_CTR_REGS", \ 1272 "SPECIAL_REGS", \ 1273 "SPEC_OR_GEN_REGS", \ 1274 "CR0_REGS", \ 1275 "CR_REGS", \ 1276 "NON_FLOAT_REGS", \ 1277 "CA_REGS", \ 1278 "ALL_REGS" \ 1279 } 1280 1281 /* Define which registers fit in which classes. 1282 This is an initializer for a vector of HARD_REG_SET 1283 of length N_REG_CLASSES. */ 1284 1285 #define REG_CLASS_CONTENTS \ 1286 { \ 1287 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1288 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ 1289 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ 1290 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ 1291 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ 1292 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ 1293 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ 1294 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ 1295 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ 1296 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ 1297 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ 1298 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ 1299 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ 1300 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ 1301 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ 1302 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ 1303 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ 1304 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ 1305 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ 1306 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ 1307 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \ 1308 } 1309 1310 /* The same information, inverted: 1311 Return the class number of the smallest class containing 1312 reg number REGNO. This could be a conditional expression 1313 or could index an array. */ 1314 1315 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1316 1317 #if ENABLE_CHECKING 1318 #define REGNO_REG_CLASS(REGNO) \ 1319 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ 1320 rs6000_regno_regclass[(REGNO)]) 1321 1322 #else 1323 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] 1324 #endif 1325 1326 /* Register classes for various constraints that are based on the target 1327 switches. */ 1328 enum r6000_reg_class_enum { 1329 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1330 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1331 RS6000_CONSTRAINT_v, /* Altivec registers */ 1332 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1333 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ 1334 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ 1335 RS6000_CONSTRAINT_ws, /* VSX register for DF */ 1336 RS6000_CONSTRAINT_MAX 1337 }; 1338 1339 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1340 1341 /* The class value for index registers, and the one for base regs. */ 1342 #define INDEX_REG_CLASS GENERAL_REGS 1343 #define BASE_REG_CLASS BASE_REGS 1344 1345 /* Return whether a given register class can hold VSX objects. */ 1346 #define VSX_REG_CLASS_P(CLASS) \ 1347 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1348 1349 /* Given an rtx X being reloaded into a reg required to be 1350 in class CLASS, return the class of reg to actually use. 1351 In general this is just CLASS; but on some machines 1352 in some cases it is preferable to use a more restrictive class. 1353 1354 On the RS/6000, we have to return NO_REGS when we want to reload a 1355 floating-point CONST_DOUBLE to force it to be copied to memory. 1356 1357 We also don't want to reload integer values into floating-point 1358 registers if we can at all help it. In fact, this can 1359 cause reload to die, if it tries to generate a reload of CTR 1360 into a FP register and discovers it doesn't have the memory location 1361 required. 1362 1363 ??? Would it be a good idea to have reload do the converse, that is 1364 try to reload floating modes into FP registers if possible? 1365 */ 1366 1367 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1368 rs6000_preferred_reload_class_ptr (X, CLASS) 1369 1370 /* Return the register class of a scratch register needed to copy IN into 1371 or out of a register in CLASS in MODE. If it can be done directly, 1372 NO_REGS is returned. */ 1373 1374 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1375 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1376 1377 /* If we are copying between FP or AltiVec registers and anything 1378 else, we need a memory location. The exception is when we are 1379 targeting ppc64 and the move to/from fpr to gpr instructions 1380 are available.*/ 1381 1382 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1383 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) 1384 1385 /* For cpus that cannot load/store SDmode values from the 64-bit 1386 FP registers without using a full 64-bit load/store, we need 1387 to allocate a full 64-bit stack slot for them. */ 1388 1389 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1390 rs6000_secondary_memory_needed_rtx (MODE) 1391 1392 /* Return the maximum number of consecutive registers 1393 needed to represent mode MODE in a register of class CLASS. 1394 1395 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1396 a single reg is enough for two words, unless we have VSX, where the FP 1397 registers can hold 128 bits. */ 1398 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1399 1400 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ 1401 1402 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1403 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) 1404 1405 /* Stack layout; function entry, exit and calling. */ 1406 1407 /* Define this if pushing a word on the stack 1408 makes the stack pointer a smaller address. */ 1409 #define STACK_GROWS_DOWNWARD 1410 1411 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1412 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1413 1414 /* Define this to nonzero if the nominal address of the stack frame 1415 is at the high-address end of the local variables; 1416 that is, each additional local variable allocated 1417 goes at a more negative offset in the frame. 1418 1419 On the RS/6000, we grow upwards, from the area after the outgoing 1420 arguments. */ 1421 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0) 1422 1423 /* Size of the outgoing register save area */ 1424 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ 1425 || DEFAULT_ABI == ABI_DARWIN) \ 1426 ? (TARGET_64BIT ? 64 : 32) \ 1427 : 0) 1428 1429 /* Size of the fixed area on the stack */ 1430 #define RS6000_SAVE_AREA \ 1431 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ 1432 << (TARGET_64BIT ? 1 : 0)) 1433 1434 /* MEM representing address to save the TOC register */ 1435 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ 1436 plus_constant (Pmode, stack_pointer_rtx, \ 1437 (TARGET_32BIT ? 20 : 40))) 1438 1439 /* Align an address */ 1440 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1441 1442 /* Offset within stack frame to start allocating local variables at. 1443 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1444 first local allocated. Otherwise, it is the offset to the BEGINNING 1445 of the first local allocated. 1446 1447 On the RS/6000, the frame pointer is the same as the stack pointer, 1448 except for dynamic allocations. So we start after the fixed area and 1449 outgoing parameter area. */ 1450 1451 #define STARTING_FRAME_OFFSET \ 1452 (FRAME_GROWS_DOWNWARD \ 1453 ? 0 \ 1454 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1455 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1456 + RS6000_SAVE_AREA)) 1457 1458 /* Offset from the stack pointer register to an item dynamically 1459 allocated on the stack, e.g., by `alloca'. 1460 1461 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1462 length of the outgoing arguments. The default is correct for most 1463 machines. See `function.c' for details. */ 1464 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1465 (RS6000_ALIGN (crtl->outgoing_args_size, \ 1466 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1467 + (STACK_POINTER_OFFSET)) 1468 1469 /* If we generate an insn to push BYTES bytes, 1470 this says how many the stack pointer really advances by. 1471 On RS/6000, don't define this because there are no push insns. */ 1472 /* #define PUSH_ROUNDING(BYTES) */ 1473 1474 /* Offset of first parameter from the argument pointer register value. 1475 On the RS/6000, we define the argument pointer to the start of the fixed 1476 area. */ 1477 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1478 1479 /* Offset from the argument pointer register value to the top of 1480 stack. This is different from FIRST_PARM_OFFSET because of the 1481 register save area. */ 1482 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1483 1484 /* Define this if stack space is still allocated for a parameter passed 1485 in a register. The value is the number of bytes allocated to this 1486 area. */ 1487 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE 1488 1489 /* Define this if the above stack space is to be considered part of the 1490 space allocated by the caller. */ 1491 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1492 1493 /* This is the difference between the logical top of stack and the actual sp. 1494 1495 For the RS/6000, sp points past the fixed area. */ 1496 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1497 1498 /* Define this if the maximum size of all the outgoing args is to be 1499 accumulated and pushed during the prologue. The amount can be 1500 found in the variable crtl->outgoing_args_size. */ 1501 #define ACCUMULATE_OUTGOING_ARGS 1 1502 1503 /* Define how to find the value returned by a library function 1504 assuming the value has mode MODE. */ 1505 1506 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1507 1508 /* DRAFT_V4_STRUCT_RET defaults off. */ 1509 #define DRAFT_V4_STRUCT_RET 0 1510 1511 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1512 #define DEFAULT_PCC_STRUCT_RETURN 0 1513 1514 /* Mode of stack savearea. 1515 FUNCTION is VOIDmode because calling convention maintains SP. 1516 BLOCK needs Pmode for SP. 1517 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1518 #define STACK_SAVEAREA_MODE(LEVEL) \ 1519 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1520 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) 1521 1522 /* Minimum and maximum general purpose registers used to hold arguments. */ 1523 #define GP_ARG_MIN_REG 3 1524 #define GP_ARG_MAX_REG 10 1525 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1526 1527 /* Minimum and maximum floating point registers used to hold arguments. */ 1528 #define FP_ARG_MIN_REG 33 1529 #define FP_ARG_AIX_MAX_REG 45 1530 #define FP_ARG_V4_MAX_REG 40 1531 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ 1532 || DEFAULT_ABI == ABI_DARWIN) \ 1533 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) 1534 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1535 1536 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1537 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1538 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1539 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1540 1541 /* Return registers */ 1542 #define GP_ARG_RETURN GP_ARG_MIN_REG 1543 #define FP_ARG_RETURN FP_ARG_MIN_REG 1544 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1545 1546 /* Flags for the call/call_value rtl operations set up by function_arg */ 1547 #define CALL_NORMAL 0x00000000 /* no special processing */ 1548 /* Bits in 0x00000001 are unused. */ 1549 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1550 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1551 #define CALL_LONG 0x00000008 /* always call indirect */ 1552 #define CALL_LIBCALL 0x00000010 /* libcall */ 1553 1554 /* We don't have prologue and epilogue functions to save/restore 1555 everything for most ABIs. */ 1556 #define WORLD_SAVE_P(INFO) 0 1557 1558 /* 1 if N is a possible register number for a function value 1559 as seen by the caller. 1560 1561 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1562 #define FUNCTION_VALUE_REGNO_P(N) \ 1563 ((N) == GP_ARG_RETURN \ 1564 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ 1565 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1566 1567 /* 1 if N is a possible register number for function argument passing. 1568 On RS/6000, these are r3-r10 and fp1-fp13. 1569 On AltiVec, v2 - v13 are used for passing vectors. */ 1570 #define FUNCTION_ARG_REGNO_P(N) \ 1571 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1572 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1573 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1574 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1575 && TARGET_HARD_FLOAT && TARGET_FPRS)) 1576 1577 /* Define a data type for recording info about an argument list 1578 during the scan of that argument list. This data type should 1579 hold all necessary information about the function itself 1580 and about the args processed so far, enough to enable macros 1581 such as FUNCTION_ARG to determine where the next arg should go. 1582 1583 On the RS/6000, this is a structure. The first element is the number of 1584 total argument words, the second is used to store the next 1585 floating-point register number, and the third says how many more args we 1586 have prototype types for. 1587 1588 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1589 the next available GP register, `fregno' is the next available FP 1590 register, and `words' is the number of words used on the stack. 1591 1592 The varargs/stdarg support requires that this structure's size 1593 be a multiple of sizeof(int). */ 1594 1595 typedef struct rs6000_args 1596 { 1597 int words; /* # words used for passing GP registers */ 1598 int fregno; /* next available FP register */ 1599 int vregno; /* next available AltiVec register */ 1600 int nargs_prototype; /* # args left in the current prototype */ 1601 int prototype; /* Whether a prototype was defined */ 1602 int stdarg; /* Whether function is a stdarg function. */ 1603 int call_cookie; /* Do special things for this call */ 1604 int sysv_gregno; /* next available GP register */ 1605 int intoffset; /* running offset in struct (darwin64) */ 1606 int use_stack; /* any part of struct on stack (darwin64) */ 1607 int floats_in_gpr; /* count of SFmode floats taking up 1608 GPR space (darwin64) */ 1609 int named; /* false for varargs params */ 1610 int escapes; /* if function visible outside tu */ 1611 } CUMULATIVE_ARGS; 1612 1613 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1614 for a call to a function whose data type is FNTYPE. 1615 For a library call, FNTYPE is 0. */ 1616 1617 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1618 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1619 N_NAMED_ARGS, FNDECL, VOIDmode) 1620 1621 /* Similar, but when scanning the definition of a procedure. We always 1622 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1623 1624 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1625 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1626 1000, current_function_decl, VOIDmode) 1627 1628 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1629 1630 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1631 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1632 0, NULL_TREE, MODE) 1633 1634 /* If defined, a C expression which determines whether, and in which 1635 direction, to pad out an argument with extra space. The value 1636 should be of type `enum direction': either `upward' to pad above 1637 the argument, `downward' to pad below, or `none' to inhibit 1638 padding. */ 1639 1640 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1641 1642 #define PAD_VARARGS_DOWN \ 1643 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1644 1645 /* Output assembler code to FILE to increment profiler label # LABELNO 1646 for profiling a function entry. */ 1647 1648 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1649 output_function_profiler ((FILE), (LABELNO)); 1650 1651 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1652 the stack pointer does not matter. No definition is equivalent to 1653 always zero. 1654 1655 On the RS/6000, this is nonzero because we can restore the stack from 1656 its backpointer, which we maintain. */ 1657 #define EXIT_IGNORE_STACK 1 1658 1659 /* Define this macro as a C expression that is nonzero for registers 1660 that are used by the epilogue or the return' pattern. The stack 1661 and frame pointer registers are already be assumed to be used as 1662 needed. */ 1663 1664 #define EPILOGUE_USES(REGNO) \ 1665 ((reload_completed && (REGNO) == LR_REGNO) \ 1666 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1667 || (crtl->calls_eh_return \ 1668 && TARGET_AIX \ 1669 && (REGNO) == 2)) 1670 1671 1672 /* Length in units of the trampoline for entering a nested function. */ 1673 1674 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1675 1676 /* Definitions for __builtin_return_address and __builtin_frame_address. 1677 __builtin_return_address (0) should give link register (65), enable 1678 this. */ 1679 /* This should be uncommented, so that the link register is used, but 1680 currently this would result in unmatched insns and spilling fixed 1681 registers so we'll leave it for another day. When these problems are 1682 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1683 (mrs) */ 1684 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1685 1686 /* Number of bytes into the frame return addresses can be found. See 1687 rs6000_stack_info in rs6000.c for more information on how the different 1688 abi's store the return address. */ 1689 #define RETURN_ADDRESS_OFFSET \ 1690 ((DEFAULT_ABI == ABI_AIX \ 1691 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ 1692 (DEFAULT_ABI == ABI_V4) ? 4 : \ 1693 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) 1694 1695 /* The current return address is in link register (65). The return address 1696 of anything farther back is accessed normally at an offset of 8 from the 1697 frame pointer. */ 1698 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1699 (rs6000_return_addr (COUNT, FRAME)) 1700 1701 1702 /* Definitions for register eliminations. 1703 1704 We have two registers that can be eliminated on the RS/6000. First, the 1705 frame pointer register can often be eliminated in favor of the stack 1706 pointer register. Secondly, the argument pointer register can always be 1707 eliminated; it is replaced with either the stack or frame pointer. 1708 1709 In addition, we use the elimination mechanism to see if r30 is needed 1710 Initially we assume that it isn't. If it is, we spill it. This is done 1711 by making it an eliminable register. We replace it with itself so that 1712 if it isn't needed, then existing uses won't be modified. */ 1713 1714 /* This is an array of structures. Each structure initializes one pair 1715 of eliminable registers. The "from" register number is given first, 1716 followed by "to". Eliminations of the same "from" register are listed 1717 in order of preference. */ 1718 #define ELIMINABLE_REGS \ 1719 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1720 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1721 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1722 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1723 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1724 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1725 1726 /* Define the offset between two registers, one to be eliminated, and the other 1727 its replacement, at the start of a routine. */ 1728 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1729 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1730 1731 /* Addressing modes, and classification of registers for them. */ 1732 1733 #define HAVE_PRE_DECREMENT 1 1734 #define HAVE_PRE_INCREMENT 1 1735 #define HAVE_PRE_MODIFY_DISP 1 1736 #define HAVE_PRE_MODIFY_REG 1 1737 1738 /* Macros to check register numbers against specific register classes. */ 1739 1740 /* These assume that REGNO is a hard or pseudo reg number. 1741 They give nonzero only if REGNO is a hard reg of the suitable class 1742 or a pseudo reg currently allocated to a suitable hard reg. 1743 Since they use reg_renumber, they are safe only once reg_renumber 1744 has been allocated, which happens in reginfo.c during register 1745 allocation. */ 1746 1747 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1748 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1749 ? (REGNO) <= 31 || (REGNO) == 67 \ 1750 || (REGNO) == FRAME_POINTER_REGNUM \ 1751 : (reg_renumber[REGNO] >= 0 \ 1752 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1753 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1754 1755 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1756 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1757 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1758 || (REGNO) == FRAME_POINTER_REGNUM \ 1759 : (reg_renumber[REGNO] > 0 \ 1760 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1761 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1762 1763 /* Nonzero if X is a hard reg that can be used as an index 1764 or if it is a pseudo reg in the non-strict case. */ 1765 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1766 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1767 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1768 1769 /* Nonzero if X is a hard reg that can be used as a base reg 1770 or if it is a pseudo reg in the non-strict case. */ 1771 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1772 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1773 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1774 1775 1776 /* Maximum number of registers that can appear in a valid memory address. */ 1777 1778 #define MAX_REGS_PER_ADDRESS 2 1779 1780 /* Recognize any constant value that is a valid address. */ 1781 1782 #define CONSTANT_ADDRESS_P(X) \ 1783 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1784 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1785 || GET_CODE (X) == HIGH) 1786 1787 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1788 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1789 && EASY_VECTOR_15((n) >> 1) \ 1790 && ((n) & 1) == 0) 1791 1792 #define EASY_VECTOR_MSB(n,mode) \ 1793 (((unsigned HOST_WIDE_INT)n) == \ 1794 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1795 1796 1797 /* Try a machine-dependent way of reloading an illegitimate address 1798 operand. If we find one, push the reload and jump to WIN. This 1799 macro is used in only one place: `find_reloads_address' in reload.c. 1800 1801 Implemented on rs6000 by rs6000_legitimize_reload_address. 1802 Note that (X) is evaluated twice; this is safe in current usage. */ 1803 1804 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1805 do { \ 1806 int win; \ 1807 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ 1808 (int)(TYPE), (IND_LEVELS), &win); \ 1809 if ( win ) \ 1810 goto WIN; \ 1811 } while (0) 1812 1813 #define FIND_BASE_TERM rs6000_find_base_term 1814 1815 /* The register number of the register used to address a table of 1816 static data addresses in memory. In some cases this register is 1817 defined by a processor's "application binary interface" (ABI). 1818 When this macro is defined, RTL is generated for this register 1819 once, as with the stack pointer and frame pointer registers. If 1820 this macro is not defined, it is up to the machine-dependent files 1821 to allocate such a register (if necessary). */ 1822 1823 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1824 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 1825 1826 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1827 1828 /* Define this macro if the register defined by 1829 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1830 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1831 1832 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1833 1834 /* A C expression that is nonzero if X is a legitimate immediate 1835 operand on the target machine when generating position independent 1836 code. You can assume that X satisfies `CONSTANT_P', so you need 1837 not check this. You can also assume FLAG_PIC is true, so you need 1838 not check it either. You need not define this macro if all 1839 constants (including `SYMBOL_REF') can be immediate operands when 1840 generating position independent code. */ 1841 1842 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1843 1844 /* Define this if some processing needs to be done immediately before 1845 emitting code for an insn. */ 1846 1847 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ 1848 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) 1849 1850 /* Specify the machine mode that this machine uses 1851 for the index in the tablejump instruction. */ 1852 #define CASE_VECTOR_MODE SImode 1853 1854 /* Define as C expression which evaluates to nonzero if the tablejump 1855 instruction expects the table to contain offsets from the address of the 1856 table. 1857 Do not define this if the table should contain absolute addresses. */ 1858 #define CASE_VECTOR_PC_RELATIVE 1 1859 1860 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1861 #define DEFAULT_SIGNED_CHAR 0 1862 1863 /* An integer expression for the size in bits of the largest integer machine 1864 mode that should actually be used. */ 1865 1866 /* Allow pairs of registers to be used, which is the intent of the default. */ 1867 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1868 1869 /* Max number of bytes we can move from memory to memory 1870 in one reasonably fast instruction. */ 1871 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1872 #define MAX_MOVE_MAX 8 1873 1874 /* Nonzero if access to memory by bytes is no faster than for words. 1875 Also nonzero if doing byte operations (specifically shifts) in registers 1876 is undesirable. */ 1877 #define SLOW_BYTE_ACCESS 1 1878 1879 /* Define if operations between registers always perform the operation 1880 on the full register even if a narrower mode is specified. */ 1881 #define WORD_REGISTER_OPERATIONS 1882 1883 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1884 will either zero-extend or sign-extend. The value of this macro should 1885 be the code that says which one of the two operations is implicitly 1886 done, UNKNOWN if none. */ 1887 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1888 1889 /* Define if loading short immediate values into registers sign extends. */ 1890 #define SHORT_IMMEDIATES_SIGN_EXTEND 1891 1892 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1893 is done just by pretending it is already truncated. */ 1894 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1895 1896 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1897 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1898 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1899 1900 /* The CTZ patterns return -1 for input of zero. */ 1901 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 1902 1903 /* Specify the machine mode that pointers have. 1904 After generation of rtl, the compiler makes no further distinction 1905 between pointers and any other objects of this machine mode. */ 1906 extern unsigned rs6000_pmode; 1907 #define Pmode ((enum machine_mode)rs6000_pmode) 1908 1909 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1910 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1911 1912 /* Mode of a function address in a call instruction (for indexing purposes). 1913 Doesn't matter on RS/6000. */ 1914 #define FUNCTION_MODE SImode 1915 1916 /* Define this if addresses of constant functions 1917 shouldn't be put through pseudo regs where they can be cse'd. 1918 Desirable on machines where ordinary constants are expensive 1919 but a CALL with constant address is cheap. */ 1920 #define NO_FUNCTION_CSE 1921 1922 /* Define this to be nonzero if shift instructions ignore all but the low-order 1923 few bits. 1924 1925 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1926 have been dropped from the PowerPC architecture. */ 1927 #define SHIFT_COUNT_TRUNCATED 0 1928 1929 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 1930 should be adjusted to reflect any required changes. This macro is used when 1931 there is some systematic length adjustment required that would be difficult 1932 to express in the length attribute. */ 1933 1934 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 1935 1936 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 1937 COMPARE, return the mode to be used for the comparison. For 1938 floating-point, CCFPmode should be used. CCUNSmode should be used 1939 for unsigned comparisons. CCEQmode should be used when we are 1940 doing an inequality comparison on the result of a 1941 comparison. CCmode should be used in all other cases. */ 1942 1943 #define SELECT_CC_MODE(OP,X,Y) \ 1944 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 1945 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1946 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1947 ? CCEQmode : CCmode)) 1948 1949 /* Can the condition code MODE be safely reversed? This is safe in 1950 all cases on this port, because at present it doesn't use the 1951 trapping FP comparisons (fcmpo). */ 1952 #define REVERSIBLE_CC_MODE(MODE) 1 1953 1954 /* Given a condition code and a mode, return the inverse condition. */ 1955 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1956 1957 1958 /* Control the assembler format that we output. */ 1959 1960 /* A C string constant describing how to begin a comment in the target 1961 assembler language. The compiler assumes that the comment will end at 1962 the end of the line. */ 1963 #define ASM_COMMENT_START " #" 1964 1965 /* Flag to say the TOC is initialized */ 1966 extern int toc_initialized; 1967 1968 /* Macro to output a special constant pool entry. Go to WIN if we output 1969 it. Otherwise, it is written the usual way. 1970 1971 On the RS/6000, toc entries are handled this way. */ 1972 1973 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1974 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1975 { \ 1976 output_toc (FILE, X, LABELNO, MODE); \ 1977 goto WIN; \ 1978 } \ 1979 } 1980 1981 #ifdef HAVE_GAS_WEAK 1982 #define RS6000_WEAK 1 1983 #else 1984 #define RS6000_WEAK 0 1985 #endif 1986 1987 #if RS6000_WEAK 1988 /* Used in lieu of ASM_WEAKEN_LABEL. */ 1989 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 1990 do \ 1991 { \ 1992 fputs ("\t.weak\t", (FILE)); \ 1993 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1994 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1995 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1996 { \ 1997 if (TARGET_XCOFF) \ 1998 fputs ("[DS]", (FILE)); \ 1999 fputs ("\n\t.weak\t.", (FILE)); \ 2000 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2001 } \ 2002 fputc ('\n', (FILE)); \ 2003 if (VAL) \ 2004 { \ 2005 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2006 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2007 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2008 { \ 2009 fputs ("\t.set\t.", (FILE)); \ 2010 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2011 fputs (",.", (FILE)); \ 2012 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2013 fputc ('\n', (FILE)); \ 2014 } \ 2015 } \ 2016 } \ 2017 while (0) 2018 #endif 2019 2020 #if HAVE_GAS_WEAKREF 2021 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 2022 do \ 2023 { \ 2024 fputs ("\t.weakref\t", (FILE)); \ 2025 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2026 fputs (", ", (FILE)); \ 2027 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2028 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2029 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2030 { \ 2031 fputs ("\n\t.weakref\t.", (FILE)); \ 2032 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2033 fputs (", .", (FILE)); \ 2034 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2035 } \ 2036 fputc ('\n', (FILE)); \ 2037 } while (0) 2038 #endif 2039 2040 /* This implements the `alias' attribute. */ 2041 #undef ASM_OUTPUT_DEF_FROM_DECLS 2042 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2043 do \ 2044 { \ 2045 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2046 const char *name = IDENTIFIER_POINTER (TARGET); \ 2047 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2048 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2049 { \ 2050 if (TREE_PUBLIC (DECL)) \ 2051 { \ 2052 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2053 { \ 2054 fputs ("\t.globl\t.", FILE); \ 2055 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2056 putc ('\n', FILE); \ 2057 } \ 2058 } \ 2059 else if (TARGET_XCOFF) \ 2060 { \ 2061 fputs ("\t.lglobl\t.", FILE); \ 2062 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2063 putc ('\n', FILE); \ 2064 } \ 2065 fputs ("\t.set\t.", FILE); \ 2066 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2067 fputs (",.", FILE); \ 2068 RS6000_OUTPUT_BASENAME (FILE, name); \ 2069 fputc ('\n', FILE); \ 2070 } \ 2071 ASM_OUTPUT_DEF (FILE, alias, name); \ 2072 } \ 2073 while (0) 2074 2075 #define TARGET_ASM_FILE_START rs6000_file_start 2076 2077 /* Output to assembler file text saying following lines 2078 may contain character constants, extra white space, comments, etc. */ 2079 2080 #define ASM_APP_ON "" 2081 2082 /* Output to assembler file text saying following lines 2083 no longer contain unusual constructs. */ 2084 2085 #define ASM_APP_OFF "" 2086 2087 /* How to refer to registers in assembler output. 2088 This sequence is indexed by compiler's hard-register-number (see above). */ 2089 2090 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2091 2092 #define REGISTER_NAMES \ 2093 { \ 2094 &rs6000_reg_names[ 0][0], /* r0 */ \ 2095 &rs6000_reg_names[ 1][0], /* r1 */ \ 2096 &rs6000_reg_names[ 2][0], /* r2 */ \ 2097 &rs6000_reg_names[ 3][0], /* r3 */ \ 2098 &rs6000_reg_names[ 4][0], /* r4 */ \ 2099 &rs6000_reg_names[ 5][0], /* r5 */ \ 2100 &rs6000_reg_names[ 6][0], /* r6 */ \ 2101 &rs6000_reg_names[ 7][0], /* r7 */ \ 2102 &rs6000_reg_names[ 8][0], /* r8 */ \ 2103 &rs6000_reg_names[ 9][0], /* r9 */ \ 2104 &rs6000_reg_names[10][0], /* r10 */ \ 2105 &rs6000_reg_names[11][0], /* r11 */ \ 2106 &rs6000_reg_names[12][0], /* r12 */ \ 2107 &rs6000_reg_names[13][0], /* r13 */ \ 2108 &rs6000_reg_names[14][0], /* r14 */ \ 2109 &rs6000_reg_names[15][0], /* r15 */ \ 2110 &rs6000_reg_names[16][0], /* r16 */ \ 2111 &rs6000_reg_names[17][0], /* r17 */ \ 2112 &rs6000_reg_names[18][0], /* r18 */ \ 2113 &rs6000_reg_names[19][0], /* r19 */ \ 2114 &rs6000_reg_names[20][0], /* r20 */ \ 2115 &rs6000_reg_names[21][0], /* r21 */ \ 2116 &rs6000_reg_names[22][0], /* r22 */ \ 2117 &rs6000_reg_names[23][0], /* r23 */ \ 2118 &rs6000_reg_names[24][0], /* r24 */ \ 2119 &rs6000_reg_names[25][0], /* r25 */ \ 2120 &rs6000_reg_names[26][0], /* r26 */ \ 2121 &rs6000_reg_names[27][0], /* r27 */ \ 2122 &rs6000_reg_names[28][0], /* r28 */ \ 2123 &rs6000_reg_names[29][0], /* r29 */ \ 2124 &rs6000_reg_names[30][0], /* r30 */ \ 2125 &rs6000_reg_names[31][0], /* r31 */ \ 2126 \ 2127 &rs6000_reg_names[32][0], /* fr0 */ \ 2128 &rs6000_reg_names[33][0], /* fr1 */ \ 2129 &rs6000_reg_names[34][0], /* fr2 */ \ 2130 &rs6000_reg_names[35][0], /* fr3 */ \ 2131 &rs6000_reg_names[36][0], /* fr4 */ \ 2132 &rs6000_reg_names[37][0], /* fr5 */ \ 2133 &rs6000_reg_names[38][0], /* fr6 */ \ 2134 &rs6000_reg_names[39][0], /* fr7 */ \ 2135 &rs6000_reg_names[40][0], /* fr8 */ \ 2136 &rs6000_reg_names[41][0], /* fr9 */ \ 2137 &rs6000_reg_names[42][0], /* fr10 */ \ 2138 &rs6000_reg_names[43][0], /* fr11 */ \ 2139 &rs6000_reg_names[44][0], /* fr12 */ \ 2140 &rs6000_reg_names[45][0], /* fr13 */ \ 2141 &rs6000_reg_names[46][0], /* fr14 */ \ 2142 &rs6000_reg_names[47][0], /* fr15 */ \ 2143 &rs6000_reg_names[48][0], /* fr16 */ \ 2144 &rs6000_reg_names[49][0], /* fr17 */ \ 2145 &rs6000_reg_names[50][0], /* fr18 */ \ 2146 &rs6000_reg_names[51][0], /* fr19 */ \ 2147 &rs6000_reg_names[52][0], /* fr20 */ \ 2148 &rs6000_reg_names[53][0], /* fr21 */ \ 2149 &rs6000_reg_names[54][0], /* fr22 */ \ 2150 &rs6000_reg_names[55][0], /* fr23 */ \ 2151 &rs6000_reg_names[56][0], /* fr24 */ \ 2152 &rs6000_reg_names[57][0], /* fr25 */ \ 2153 &rs6000_reg_names[58][0], /* fr26 */ \ 2154 &rs6000_reg_names[59][0], /* fr27 */ \ 2155 &rs6000_reg_names[60][0], /* fr28 */ \ 2156 &rs6000_reg_names[61][0], /* fr29 */ \ 2157 &rs6000_reg_names[62][0], /* fr30 */ \ 2158 &rs6000_reg_names[63][0], /* fr31 */ \ 2159 \ 2160 &rs6000_reg_names[64][0], /* was mq */ \ 2161 &rs6000_reg_names[65][0], /* lr */ \ 2162 &rs6000_reg_names[66][0], /* ctr */ \ 2163 &rs6000_reg_names[67][0], /* ap */ \ 2164 \ 2165 &rs6000_reg_names[68][0], /* cr0 */ \ 2166 &rs6000_reg_names[69][0], /* cr1 */ \ 2167 &rs6000_reg_names[70][0], /* cr2 */ \ 2168 &rs6000_reg_names[71][0], /* cr3 */ \ 2169 &rs6000_reg_names[72][0], /* cr4 */ \ 2170 &rs6000_reg_names[73][0], /* cr5 */ \ 2171 &rs6000_reg_names[74][0], /* cr6 */ \ 2172 &rs6000_reg_names[75][0], /* cr7 */ \ 2173 \ 2174 &rs6000_reg_names[76][0], /* ca */ \ 2175 \ 2176 &rs6000_reg_names[77][0], /* v0 */ \ 2177 &rs6000_reg_names[78][0], /* v1 */ \ 2178 &rs6000_reg_names[79][0], /* v2 */ \ 2179 &rs6000_reg_names[80][0], /* v3 */ \ 2180 &rs6000_reg_names[81][0], /* v4 */ \ 2181 &rs6000_reg_names[82][0], /* v5 */ \ 2182 &rs6000_reg_names[83][0], /* v6 */ \ 2183 &rs6000_reg_names[84][0], /* v7 */ \ 2184 &rs6000_reg_names[85][0], /* v8 */ \ 2185 &rs6000_reg_names[86][0], /* v9 */ \ 2186 &rs6000_reg_names[87][0], /* v10 */ \ 2187 &rs6000_reg_names[88][0], /* v11 */ \ 2188 &rs6000_reg_names[89][0], /* v12 */ \ 2189 &rs6000_reg_names[90][0], /* v13 */ \ 2190 &rs6000_reg_names[91][0], /* v14 */ \ 2191 &rs6000_reg_names[92][0], /* v15 */ \ 2192 &rs6000_reg_names[93][0], /* v16 */ \ 2193 &rs6000_reg_names[94][0], /* v17 */ \ 2194 &rs6000_reg_names[95][0], /* v18 */ \ 2195 &rs6000_reg_names[96][0], /* v19 */ \ 2196 &rs6000_reg_names[97][0], /* v20 */ \ 2197 &rs6000_reg_names[98][0], /* v21 */ \ 2198 &rs6000_reg_names[99][0], /* v22 */ \ 2199 &rs6000_reg_names[100][0], /* v23 */ \ 2200 &rs6000_reg_names[101][0], /* v24 */ \ 2201 &rs6000_reg_names[102][0], /* v25 */ \ 2202 &rs6000_reg_names[103][0], /* v26 */ \ 2203 &rs6000_reg_names[104][0], /* v27 */ \ 2204 &rs6000_reg_names[105][0], /* v28 */ \ 2205 &rs6000_reg_names[106][0], /* v29 */ \ 2206 &rs6000_reg_names[107][0], /* v30 */ \ 2207 &rs6000_reg_names[108][0], /* v31 */ \ 2208 &rs6000_reg_names[109][0], /* vrsave */ \ 2209 &rs6000_reg_names[110][0], /* vscr */ \ 2210 &rs6000_reg_names[111][0], /* spe_acc */ \ 2211 &rs6000_reg_names[112][0], /* spefscr */ \ 2212 &rs6000_reg_names[113][0], /* sfp */ \ 2213 } 2214 2215 /* Table of additional register names to use in user input. */ 2216 2217 #define ADDITIONAL_REGISTER_NAMES \ 2218 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2219 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2220 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2221 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2222 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2223 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2224 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2225 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2226 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2227 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2228 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2229 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2230 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2231 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2232 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2233 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2234 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2235 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2236 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2237 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2238 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2239 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2240 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2241 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2242 {"vrsave", 109}, {"vscr", 110}, \ 2243 {"spe_acc", 111}, {"spefscr", 112}, \ 2244 /* no additional names for: lr, ctr, ap */ \ 2245 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2246 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2247 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ 2248 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2249 {"xer", 76}, \ 2250 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2251 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2252 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2253 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2254 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2255 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2256 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2257 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2258 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2259 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ 2260 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ 2261 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ 2262 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ 2263 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ 2264 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ 2265 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ 2266 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} } 2267 2268 /* This is how to output an element of a case-vector that is relative. */ 2269 2270 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2271 do { char buf[100]; \ 2272 fputs ("\t.long ", FILE); \ 2273 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2274 assemble_name (FILE, buf); \ 2275 putc ('-', FILE); \ 2276 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2277 assemble_name (FILE, buf); \ 2278 putc ('\n', FILE); \ 2279 } while (0) 2280 2281 /* This is how to output an assembler line 2282 that says to advance the location counter 2283 to a multiple of 2**LOG bytes. */ 2284 2285 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2286 if ((LOG) != 0) \ 2287 fprintf (FILE, "\t.align %d\n", (LOG)) 2288 2289 /* How to align the given loop. */ 2290 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2291 2292 /* Pick up the return address upon entry to a procedure. Used for 2293 dwarf2 unwind information. This also enables the table driven 2294 mechanism. */ 2295 2296 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2297 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2298 2299 /* Describe how we implement __builtin_eh_return. */ 2300 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2301 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2302 2303 /* Print operand X (an rtx) in assembler syntax to file FILE. 2304 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2305 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2306 2307 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2308 2309 /* Define which CODE values are valid. */ 2310 2311 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2312 2313 /* Print a memory address as an operand to reference that memory location. */ 2314 2315 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2316 2317 /* uncomment for disabling the corresponding default options */ 2318 /* #define MACHINE_no_sched_interblock */ 2319 /* #define MACHINE_no_sched_speculative */ 2320 /* #define MACHINE_no_sched_speculative_load */ 2321 2322 /* General flags. */ 2323 extern int frame_pointer_needed; 2324 2325 /* Classification of the builtin functions as to which switches enable the 2326 builtin, and what attributes it should have. We used to use the target 2327 flags macros, but we've run out of bits, so we now map the options into new 2328 settings used here. */ 2329 2330 /* Builtin attributes. */ 2331 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2332 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2333 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2334 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2335 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ 2336 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ 2337 #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ 2338 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ 2339 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ 2340 2341 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2342 #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ 2343 #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ 2344 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2345 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ 2346 2347 /* Miscellaneous information. */ 2348 #define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */ 2349 2350 /* Convenience macros to document the instruction type. */ 2351 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2352 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2353 2354 /* Builtin targets. For now, we reuse the masks for those options that are in 2355 target flags, and pick two random bits for SPE and paired which aren't in 2356 target_flags. */ 2357 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2358 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2359 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2360 #define RS6000_BTM_SPE MASK_STRING /* E500 */ 2361 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ 2362 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2363 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2364 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2365 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2366 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2367 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2368 2369 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2370 | RS6000_BTM_VSX \ 2371 | RS6000_BTM_FRE \ 2372 | RS6000_BTM_FRES \ 2373 | RS6000_BTM_FRSQRTE \ 2374 | RS6000_BTM_FRSQRTES \ 2375 | RS6000_BTM_POPCNTD \ 2376 | RS6000_BTM_CELL) 2377 2378 /* Define builtin enum index. */ 2379 2380 #undef RS6000_BUILTIN_1 2381 #undef RS6000_BUILTIN_2 2382 #undef RS6000_BUILTIN_3 2383 #undef RS6000_BUILTIN_A 2384 #undef RS6000_BUILTIN_D 2385 #undef RS6000_BUILTIN_E 2386 #undef RS6000_BUILTIN_P 2387 #undef RS6000_BUILTIN_Q 2388 #undef RS6000_BUILTIN_S 2389 #undef RS6000_BUILTIN_X 2390 2391 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2392 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2393 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2394 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2395 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2396 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2397 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2398 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2399 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2400 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2401 2402 enum rs6000_builtins 2403 { 2404 #include "rs6000-builtin.def" 2405 2406 RS6000_BUILTIN_COUNT 2407 }; 2408 2409 #undef RS6000_BUILTIN_1 2410 #undef RS6000_BUILTIN_2 2411 #undef RS6000_BUILTIN_3 2412 #undef RS6000_BUILTIN_A 2413 #undef RS6000_BUILTIN_D 2414 #undef RS6000_BUILTIN_E 2415 #undef RS6000_BUILTIN_P 2416 #undef RS6000_BUILTIN_Q 2417 #undef RS6000_BUILTIN_S 2418 #undef RS6000_BUILTIN_X 2419 2420 enum rs6000_builtin_type_index 2421 { 2422 RS6000_BTI_NOT_OPAQUE, 2423 RS6000_BTI_opaque_V2SI, 2424 RS6000_BTI_opaque_V2SF, 2425 RS6000_BTI_opaque_p_V2SI, 2426 RS6000_BTI_opaque_V4SI, 2427 RS6000_BTI_V16QI, 2428 RS6000_BTI_V2SI, 2429 RS6000_BTI_V2SF, 2430 RS6000_BTI_V2DI, 2431 RS6000_BTI_V2DF, 2432 RS6000_BTI_V4HI, 2433 RS6000_BTI_V4SI, 2434 RS6000_BTI_V4SF, 2435 RS6000_BTI_V8HI, 2436 RS6000_BTI_unsigned_V16QI, 2437 RS6000_BTI_unsigned_V8HI, 2438 RS6000_BTI_unsigned_V4SI, 2439 RS6000_BTI_unsigned_V2DI, 2440 RS6000_BTI_bool_char, /* __bool char */ 2441 RS6000_BTI_bool_short, /* __bool short */ 2442 RS6000_BTI_bool_int, /* __bool int */ 2443 RS6000_BTI_bool_long, /* __bool long */ 2444 RS6000_BTI_pixel, /* __pixel */ 2445 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2446 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2447 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2448 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2449 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2450 RS6000_BTI_long, /* long_integer_type_node */ 2451 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2452 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2453 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2454 RS6000_BTI_INTQI, /* intQI_type_node */ 2455 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2456 RS6000_BTI_INTHI, /* intHI_type_node */ 2457 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2458 RS6000_BTI_INTSI, /* intSI_type_node */ 2459 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2460 RS6000_BTI_INTDI, /* intDI_type_node */ 2461 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2462 RS6000_BTI_float, /* float_type_node */ 2463 RS6000_BTI_double, /* double_type_node */ 2464 RS6000_BTI_void, /* void_type_node */ 2465 RS6000_BTI_MAX 2466 }; 2467 2468 2469 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 2470 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 2471 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 2472 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2473 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2474 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2475 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2476 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 2477 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 2478 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2479 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2480 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2481 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2482 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2483 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2484 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2485 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2486 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2487 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2488 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2489 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) 2490 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2491 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2492 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2493 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2494 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2495 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2496 2497 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2498 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2499 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2500 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2501 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2502 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2503 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2504 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2505 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2506 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2507 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2508 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2509 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2510 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2511 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2512 2513 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2514 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2515 2516