1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_ll_fsmc.h 4 * @author MCD Application Team 5 * @version V1.2.0 6 * @date 01-July-2016 7 * @brief Header file of FSMC HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32L1xx_LL_FSMC_H 40 #define __STM32L1xx_LL_FSMC_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l1xx_hal_def.h" 48 49 /** @addtogroup STM32L1xx_HAL_Driver 50 * @{ 51 */ 52 53 #if defined(FSMC_BANK1) 54 55 /** @addtogroup FSMC_LL 56 * @{ 57 */ 58 59 /** @addtogroup FSMC_LL_Private_Macros 60 * @{ 61 */ 62 63 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ 64 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ 65 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ 66 ((__BANK__) == FSMC_NORSRAM_BANK4)) 67 68 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ 69 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) 70 71 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ 72 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ 73 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) 74 75 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 76 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 77 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) 78 79 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ 80 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 81 82 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ 83 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ 84 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ 85 ((__MODE__) == FSMC_ACCESS_MODE_D)) 86 87 88 /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance 89 * @{ 90 */ 91 92 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) 93 94 /** 95 * @} 96 */ 97 98 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance 99 * @{ 100 */ 101 102 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) 103 104 /** 105 * @} 106 */ 107 108 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ 109 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) 110 111 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ 112 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) 113 114 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ 115 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 116 117 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ 118 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 119 120 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ 121 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) 122 123 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ 124 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 125 126 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ 127 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) 128 129 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 130 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) 131 132 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) 133 134 /** @defgroup FSMC_Data_Latency FSMC Data Latency 135 * @{ 136 */ 137 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) 138 /** 139 * @} 140 */ 141 142 /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time 143 * @{ 144 */ 145 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) 146 /** 147 * @} 148 */ 149 150 /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time 151 * @{ 152 */ 153 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) 154 /** 155 * @} 156 */ 157 158 /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time 159 * @{ 160 */ 161 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) 162 /** 163 * @} 164 */ 165 166 /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration 167 * @{ 168 */ 169 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) 170 /** 171 * @} 172 */ 173 174 /** 175 * @} 176 */ 177 178 /* Exported typedef ----------------------------------------------------------*/ 179 180 /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types 181 * @{ 182 */ 183 184 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef 185 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef 186 187 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 188 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E 189 190 /** 191 * @brief FSMC_NORSRAM Configuration Structure definition 192 */ 193 typedef struct 194 { 195 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 196 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 197 198 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 199 multiplexed on the data bus or not. 200 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ 201 202 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 203 the corresponding memory device. 204 This parameter can be a value of @ref FSMC_Memory_Type */ 205 206 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 207 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ 208 209 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 210 valid only with synchronous burst Flash memories. 211 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 212 213 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 214 the Flash memory in burst mode. 215 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 216 217 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 218 memory, valid only when accessing Flash memories in burst mode. 219 This parameter can be a value of @ref FSMC_Wrap_Mode */ 220 221 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 222 clock cycle before the wait state or during the wait state, 223 valid only when accessing memories in burst mode. 224 This parameter can be a value of @ref FSMC_Wait_Timing */ 225 226 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. 227 This parameter can be a value of @ref FSMC_Write_Operation */ 228 229 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 230 signal, valid for Flash memory access in burst mode. 231 This parameter can be a value of @ref FSMC_Wait_Signal */ 232 233 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 234 This parameter can be a value of @ref FSMC_Extended_Mode */ 235 236 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 237 valid only with asynchronous Flash memories. 238 This parameter can be a value of @ref FSMC_AsynchronousWait */ 239 240 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 241 This parameter can be a value of @ref FSMC_Write_Burst */ 242 243 }FSMC_NORSRAM_InitTypeDef; 244 245 /** 246 * @brief FSMC_NORSRAM Timing parameters structure definition 247 */ 248 typedef struct 249 { 250 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 251 the duration of the address setup time. 252 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 253 @note This parameter is not used with synchronous NOR Flash memories. */ 254 255 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 256 the duration of the address hold time. 257 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 258 @note This parameter is not used with synchronous NOR Flash memories. */ 259 260 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 261 the duration of the data setup time. 262 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 263 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 264 NOR Flash memories. */ 265 266 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 267 the duration of the bus turnaround. 268 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 269 @note This parameter is only used for multiplexed NOR Flash memories. */ 270 271 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 272 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. 273 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 274 accesses. */ 275 276 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 277 to the memory before getting the first data. 278 The parameter value depends on the memory type as shown below: 279 - It must be set to 0 in case of a CRAM 280 - It is don't care in asynchronous NOR, SRAM or ROM accesses 281 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories 282 with synchronous burst mode enable */ 283 284 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 285 This parameter can be a value of @ref FSMC_Access_Mode */ 286 287 }FSMC_NORSRAM_TimingTypeDef; 288 289 /** 290 * @} 291 */ 292 293 /* Exported constants --------------------------------------------------------*/ 294 295 /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants 296 * @{ 297 */ 298 299 /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants 300 * @{ 301 */ 302 303 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank 304 * @{ 305 */ 306 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) 307 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) 308 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) 309 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) 310 311 /** 312 * @} 313 */ 314 315 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing 316 * @{ 317 */ 318 319 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) 320 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) 321 322 /** 323 * @} 324 */ 325 326 /** @defgroup FSMC_Memory_Type FSMC Memory Type 327 * @{ 328 */ 329 330 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) 331 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) 332 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) 333 334 /** 335 * @} 336 */ 337 338 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width 339 * @{ 340 */ 341 342 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) 343 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) 344 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) 345 346 /** 347 * @} 348 */ 349 350 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access 351 * @{ 352 */ 353 354 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) 355 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) 356 /** 357 * @} 358 */ 359 360 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode 361 * @{ 362 */ 363 364 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) 365 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) 366 367 /** 368 * @} 369 */ 370 371 372 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity 373 * @{ 374 */ 375 376 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) 377 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) 378 379 /** 380 * @} 381 */ 382 383 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 384 * @{ 385 */ 386 387 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) 388 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) 389 390 /** 391 * @} 392 */ 393 394 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing 395 * @{ 396 */ 397 398 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) 399 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) 400 401 /** 402 * @} 403 */ 404 405 /** @defgroup FSMC_Write_Operation FSMC Write Operation 406 * @{ 407 */ 408 409 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) 410 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) 411 412 /** 413 * @} 414 */ 415 416 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal 417 * @{ 418 */ 419 420 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) 421 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) 422 423 /** 424 * @} 425 */ 426 427 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode 428 * @{ 429 */ 430 431 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) 432 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) 433 434 /** 435 * @} 436 */ 437 438 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait 439 * @{ 440 */ 441 442 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) 443 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) 444 445 /** 446 * @} 447 */ 448 449 /** @defgroup FSMC_Write_Burst FSMC Write Burst 450 * @{ 451 */ 452 453 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) 454 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) 455 456 /** 457 * @} 458 */ 459 460 /** @defgroup FSMC_Access_Mode FSMC Access Mode 461 * @{ 462 */ 463 464 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) 465 #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) 466 #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) 467 #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) 468 469 /** 470 * @} 471 */ 472 473 /** 474 * @} 475 */ 476 477 478 /** 479 * @} 480 */ 481 482 /* Exported macro ------------------------------------------------------------*/ 483 484 /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros 485 * @{ 486 */ 487 488 /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros 489 * @brief macros to handle NOR device enable/disable and read/write operations 490 * @{ 491 */ 492 493 /** 494 * @brief Enable the NORSRAM device access. 495 * @param __INSTANCE__ FSMC_NORSRAM Instance 496 * @param __BANK__ FSMC_NORSRAM Bank 497 * @retval none 498 */ 499 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) 500 501 /** 502 * @brief Disable the NORSRAM device access. 503 * @param __INSTANCE__ FSMC_NORSRAM Instance 504 * @param __BANK__ FSMC_NORSRAM Bank 505 * @retval none 506 */ 507 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) 508 509 /** 510 * @} 511 */ 512 513 514 /** 515 * @} 516 */ 517 518 /* Exported functions --------------------------------------------------------*/ 519 520 /** @addtogroup FSMC_LL_Exported_Functions 521 * @{ 522 */ 523 524 /** @addtogroup FSMC_NORSRAM 525 * @{ 526 */ 527 528 /** @addtogroup FSMC_NORSRAM_Group1 529 * @{ 530 */ 531 532 /* FSMC_NORSRAM Controller functions ******************************************/ 533 /* Initialization/de-initialization functions */ 534 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); 535 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 536 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); 537 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 538 539 /** 540 * @} 541 */ 542 543 /** @addtogroup FSMC_NORSRAM_Group2 544 * @{ 545 */ 546 547 /* FSMC_NORSRAM Control functions */ 548 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 549 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 550 551 /** 552 * @} 553 */ 554 555 /** 556 * @} 557 */ 558 559 /** 560 * @} 561 */ 562 563 /** 564 * @} 565 */ 566 567 #endif /* FSMC_BANK1 */ 568 569 /** 570 * @} 571 */ 572 573 #ifdef __cplusplus 574 } 575 #endif 576 577 #endif /* __STM32L1xx_LL_FSMC_H */ 578 579 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 580 581