1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2018 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Target CPU builtins. */ 26 #define TARGET_CPU_CPP_BUILTINS() \ 27 aarch64_cpu_cpp_builtins (pfile) 28 29 30 31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 32 33 /* Target machine storage layout. */ 34 35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 36 if (GET_MODE_CLASS (MODE) == MODE_INT \ 37 && GET_MODE_SIZE (MODE) < 4) \ 38 { \ 39 if (MODE == QImode || MODE == HImode) \ 40 { \ 41 MODE = SImode; \ 42 } \ 43 } 44 45 /* Bits are always numbered from the LSBit. */ 46 #define BITS_BIG_ENDIAN 0 47 48 /* Big/little-endian flavour. */ 49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 51 52 /* AdvSIMD is supported in the default configuration, unless disabled by 53 -mgeneral-regs-only or by the +nosimd extension. */ 54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 56 57 #define UNITS_PER_WORD 8 58 59 #define UNITS_PER_VREG 16 60 61 #define PARM_BOUNDARY 64 62 63 #define STACK_BOUNDARY 128 64 65 #define FUNCTION_BOUNDARY 32 66 67 #define EMPTY_FIELD_BOUNDARY 32 68 69 #define BIGGEST_ALIGNMENT 128 70 71 #define SHORT_TYPE_SIZE 16 72 73 #define INT_TYPE_SIZE 32 74 75 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 76 77 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 78 79 #define LONG_LONG_TYPE_SIZE 64 80 81 #define FLOAT_TYPE_SIZE 32 82 83 #define DOUBLE_TYPE_SIZE 64 84 85 #define LONG_DOUBLE_TYPE_SIZE 128 86 87 /* The architecture reserves all bits of the address for hardware use, 88 so the vbit must go into the delta field of pointers to member 89 functions. This is the same config as that in the AArch32 90 port. */ 91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 92 93 /* Align definitions of arrays, unions and structures so that 94 initializations and copies can be made more efficient. This is not 95 ABI-changing, so it only affects places where we can see the 96 definition. Increasing the alignment tends to introduce padding, 97 so don't do this when optimizing for size/conserving stack space. */ 98 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 99 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 100 && (TREE_CODE (EXP) == ARRAY_TYPE \ 101 || TREE_CODE (EXP) == UNION_TYPE \ 102 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 103 104 /* Align global data. */ 105 #define DATA_ALIGNMENT(EXP, ALIGN) \ 106 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) 107 108 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 109 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 110 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) 111 112 #define STRUCTURE_SIZE_BOUNDARY 8 113 114 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ 115 #define MALLOC_ABI_ALIGNMENT 128 116 117 /* Defined by the ABI */ 118 #define WCHAR_TYPE "unsigned int" 119 #define WCHAR_TYPE_SIZE 32 120 121 /* Using long long breaks -ansi and -std=c90, so these will need to be 122 made conditional for an LLP64 ABI. */ 123 124 #define SIZE_TYPE "long unsigned int" 125 126 #define PTRDIFF_TYPE "long int" 127 128 #define PCC_BITFIELD_TYPE_MATTERS 1 129 130 /* Major revision number of the ARM Architecture implemented by the target. */ 131 extern unsigned aarch64_architecture_version; 132 133 /* Instruction tuning/selection flags. */ 134 135 /* Bit values used to identify processor capabilities. */ 136 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 137 #define AARCH64_FL_FP (1 << 1) /* Has FP. */ 138 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 139 #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ 140 /* ARMv8.1-A architecture extensions. */ 141 #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ 142 #define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ 143 #define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ 144 /* ARMv8.2-A architecture extensions. */ 145 #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ 146 #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ 147 #define AARCH64_FL_SVE (1 << 10) /* Has Scalable Vector Extensions. */ 148 /* ARMv8.3-A architecture extensions. */ 149 #define AARCH64_FL_V8_3 (1 << 11) /* Has ARMv8.3-A features. */ 150 #define AARCH64_FL_RCPC (1 << 12) /* Has support for RCpc model. */ 151 #define AARCH64_FL_DOTPROD (1 << 13) /* Has ARMv8.2-A Dot Product ins. */ 152 /* New flags to split crypto into aes and sha2. */ 153 #define AARCH64_FL_AES (1 << 14) /* Has Crypto AES. */ 154 #define AARCH64_FL_SHA2 (1 << 15) /* Has Crypto SHA2. */ 155 /* ARMv8.4-A architecture extensions. */ 156 #define AARCH64_FL_V8_4 (1 << 16) /* Has ARMv8.4-A features. */ 157 #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ 158 #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ 159 #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ 160 161 /* Has FP and SIMD. */ 162 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 163 164 /* Has FP without SIMD. */ 165 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 166 167 /* Architecture flags that effect instruction selection. */ 168 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 169 #define AARCH64_FL_FOR_ARCH8_1 \ 170 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \ 171 | AARCH64_FL_RDMA | AARCH64_FL_V8_1) 172 #define AARCH64_FL_FOR_ARCH8_2 \ 173 (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) 174 #define AARCH64_FL_FOR_ARCH8_3 \ 175 (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3) 176 #define AARCH64_FL_FOR_ARCH8_4 \ 177 (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ 178 | AARCH64_FL_DOTPROD) 179 180 /* Macros to test ISA flags. */ 181 182 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 183 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 184 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 185 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 186 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 187 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) 188 #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) 189 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) 190 #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) 191 #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) 192 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) 193 #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) 194 #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) 195 #define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4) 196 #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) 197 #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) 198 #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) 199 200 /* Crypto is an optional extension to AdvSIMD. */ 201 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 202 203 /* SHA2 is an optional extension to AdvSIMD. */ 204 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO) 205 206 /* SHA3 is an optional extension to AdvSIMD. */ 207 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3) 208 209 /* AES is an optional extension to AdvSIMD. */ 210 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO) 211 212 /* SM is an optional extension to AdvSIMD. */ 213 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4) 214 215 /* FP16FML is an optional extension to AdvSIMD. */ 216 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) 217 218 /* CRC instructions that can be enabled through +crc arch extension. */ 219 #define TARGET_CRC32 (AARCH64_ISA_CRC) 220 221 /* Atomic instructions that can be enabled through the +lse extension. */ 222 #define TARGET_LSE (AARCH64_ISA_LSE) 223 224 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ 225 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) 226 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) 227 228 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ 229 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) 230 231 /* SVE instructions, enabled through +sve. */ 232 #define TARGET_SVE (AARCH64_ISA_SVE) 233 234 /* ARMv8.3-A features. */ 235 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) 236 237 /* Make sure this is always defined so we don't have to check for ifdefs 238 but rather use normal ifs. */ 239 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 240 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 241 #else 242 #undef TARGET_FIX_ERR_A53_835769_DEFAULT 243 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 244 #endif 245 246 /* Apply the workaround for Cortex-A53 erratum 835769. */ 247 #define TARGET_FIX_ERR_A53_835769 \ 248 ((aarch64_fix_a53_err835769 == 2) \ 249 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 250 251 /* Make sure this is always defined so we don't have to check for ifdefs 252 but rather use normal ifs. */ 253 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 254 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 255 #else 256 #undef TARGET_FIX_ERR_A53_843419_DEFAULT 257 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 258 #endif 259 260 /* Apply the workaround for Cortex-A53 erratum 843419. */ 261 #define TARGET_FIX_ERR_A53_843419 \ 262 ((aarch64_fix_a53_err843419 == 2) \ 263 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 264 265 /* ARMv8.1-A Adv.SIMD support. */ 266 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 267 268 /* Standard register usage. */ 269 270 /* 31 64-bit general purpose registers R0-R30: 271 R30 LR (link register) 272 R29 FP (frame pointer) 273 R19-R28 Callee-saved registers 274 R18 The platform register; use as temporary register. 275 R17 IP1 The second intra-procedure-call temporary register 276 (can be used by call veneers and PLT code); otherwise use 277 as a temporary register 278 R16 IP0 The first intra-procedure-call temporary register (can 279 be used by call veneers and PLT code); otherwise use as a 280 temporary register 281 R9-R15 Temporary registers 282 R8 Structure value parameter / temporary register 283 R0-R7 Parameter/result registers 284 285 SP stack pointer, encoded as X/R31 where permitted. 286 ZR zero register, encoded as X/R31 elsewhere 287 288 32 x 128-bit floating-point/vector registers 289 V16-V31 Caller-saved (temporary) registers 290 V8-V15 Callee-saved registers 291 V0-V7 Parameter/result registers 292 293 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 294 significant bits. Unlike AArch32 S1 is not packed into D0, etc. 295 296 P0-P7 Predicate low registers: valid in all predicate contexts 297 P8-P15 Predicate high registers: used as scratch space 298 299 VG Pseudo "vector granules" register 300 301 VG is the number of 64-bit elements in an SVE vector. We define 302 it as a hard register so that we can easily map it to the DWARF VG 303 register. GCC internally uses the poly_int variable aarch64_sve_vg 304 instead. */ 305 306 /* Note that we don't mark X30 as a call-clobbered register. The idea is 307 that it's really the call instructions themselves which clobber X30. 308 We don't care what the called function does with it afterwards. 309 310 This approach makes it easier to implement sibcalls. Unlike normal 311 calls, sibcalls don't clobber X30, so the register reaches the 312 called function intact. EPILOGUE_USES says that X30 is useful 313 to the called function. */ 314 315 #define FIXED_REGISTERS \ 316 { \ 317 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 318 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 319 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 320 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 321 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 322 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 323 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 324 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 325 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 326 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ 327 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ 328 } 329 330 #define CALL_USED_REGISTERS \ 331 { \ 332 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 333 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 334 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 335 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 336 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 337 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 338 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 339 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 340 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 341 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ 342 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ 343 } 344 345 #define REGISTER_NAMES \ 346 { \ 347 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 348 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 349 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 350 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 351 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 352 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 353 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 354 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 355 "sfp", "ap", "cc", "vg", \ 356 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ 357 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ 358 } 359 360 /* Generate the register aliases for core register N */ 361 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 362 {"w" # N, R0_REGNUM + (N)} 363 364 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 365 {"d" # N, V0_REGNUM + (N)}, \ 366 {"s" # N, V0_REGNUM + (N)}, \ 367 {"h" # N, V0_REGNUM + (N)}, \ 368 {"b" # N, V0_REGNUM + (N)}, \ 369 {"z" # N, V0_REGNUM + (N)} 370 371 /* Provide aliases for all of the ISA defined register name forms. 372 These aliases are convenient for use in the clobber lists of inline 373 asm statements. */ 374 375 #define ADDITIONAL_REGISTER_NAMES \ 376 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 377 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 378 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 379 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 380 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 381 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 382 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 383 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 384 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 385 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 386 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 387 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 388 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 389 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 390 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 391 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 392 } 393 394 /* Say that the epilogue uses the return address register. Note that 395 in the case of sibcalls, the values "used by the epilogue" are 396 considered live at the start of the called function. */ 397 398 #define EPILOGUE_USES(REGNO) \ 399 (epilogue_completed && (REGNO) == LR_REGNUM) 400 401 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 402 the stack pointer does not matter. This is only true if the function 403 uses alloca. */ 404 #define EXIT_IGNORE_STACK (cfun->calls_alloca) 405 406 #define STATIC_CHAIN_REGNUM R18_REGNUM 407 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 408 #define FRAME_POINTER_REGNUM SFP_REGNUM 409 #define STACK_POINTER_REGNUM SP_REGNUM 410 #define ARG_POINTER_REGNUM AP_REGNUM 411 #define FIRST_PSEUDO_REGISTER (P15_REGNUM + 1) 412 413 /* The number of (integer) argument register available. */ 414 #define NUM_ARG_REGS 8 415 #define NUM_FP_ARG_REGS 8 416 417 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 418 four members. */ 419 #define HA_MAX_NUM_FLDS 4 420 421 /* External dwarf register number scheme. These number are used to 422 identify registers in dwarf debug information, the values are 423 defined by the AArch64 ABI. The numbering scheme is independent of 424 GCC's internal register numbering scheme. */ 425 426 #define AARCH64_DWARF_R0 0 427 428 /* The number of R registers, note 31! not 32. */ 429 #define AARCH64_DWARF_NUMBER_R 31 430 431 #define AARCH64_DWARF_SP 31 432 #define AARCH64_DWARF_VG 46 433 #define AARCH64_DWARF_P0 48 434 #define AARCH64_DWARF_V0 64 435 436 /* The number of V registers. */ 437 #define AARCH64_DWARF_NUMBER_V 32 438 439 /* For signal frames we need to use an alternative return column. This 440 value must not correspond to a hard register and must be out of the 441 range of DWARF_FRAME_REGNUM(). */ 442 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 443 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 444 445 /* We add 1 extra frame register for use as the 446 DWARF_ALT_FRAME_RETURN_COLUMN. */ 447 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 448 449 450 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 451 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 452 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 453 as the default definition in dwarf2out.c. */ 454 #undef DWARF_FRAME_REGNUM 455 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 456 457 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 458 459 #define DWARF2_UNWIND_INFO 1 460 461 /* Use R0 through R3 to pass exception handling information. */ 462 #define EH_RETURN_DATA_REGNO(N) \ 463 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 464 465 /* Select a format to encode pointers in exception handling data. */ 466 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 467 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 468 469 /* Output the assembly strings we want to add to a function definition. */ 470 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 471 aarch64_declare_function_name (STR, NAME, DECL) 472 473 /* For EH returns X4 contains the stack adjustment. */ 474 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) 475 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () 476 477 /* Don't use __builtin_setjmp until we've defined it. */ 478 #undef DONT_USE_BUILTIN_SETJMP 479 #define DONT_USE_BUILTIN_SETJMP 1 480 481 /* Register in which the structure value is to be returned. */ 482 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 483 484 /* Non-zero if REGNO is part of the Core register set. 485 486 The rather unusual way of expressing this check is to avoid 487 warnings when building the compiler when R0_REGNUM is 0 and REGNO 488 is unsigned. */ 489 #define GP_REGNUM_P(REGNO) \ 490 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 491 492 #define FP_REGNUM_P(REGNO) \ 493 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 494 495 #define FP_LO_REGNUM_P(REGNO) \ 496 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 497 498 #define PR_REGNUM_P(REGNO)\ 499 (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) 500 501 #define PR_LO_REGNUM_P(REGNO)\ 502 (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) 503 504 505 /* Register and constant classes. */ 506 507 enum reg_class 508 { 509 NO_REGS, 510 TAILCALL_ADDR_REGS, 511 GENERAL_REGS, 512 STACK_REG, 513 POINTER_REGS, 514 FP_LO_REGS, 515 FP_REGS, 516 POINTER_AND_FP_REGS, 517 PR_LO_REGS, 518 PR_HI_REGS, 519 PR_REGS, 520 ALL_REGS, 521 LIM_REG_CLASSES /* Last */ 522 }; 523 524 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 525 526 #define REG_CLASS_NAMES \ 527 { \ 528 "NO_REGS", \ 529 "TAILCALL_ADDR_REGS", \ 530 "GENERAL_REGS", \ 531 "STACK_REG", \ 532 "POINTER_REGS", \ 533 "FP_LO_REGS", \ 534 "FP_REGS", \ 535 "POINTER_AND_FP_REGS", \ 536 "PR_LO_REGS", \ 537 "PR_HI_REGS", \ 538 "PR_REGS", \ 539 "ALL_REGS" \ 540 } 541 542 #define REG_CLASS_CONTENTS \ 543 { \ 544 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 545 { 0x0004ffff, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 546 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 547 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 548 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 549 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 550 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 551 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ 552 { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ 553 { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ 554 { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ 555 { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ 556 } 557 558 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 559 560 #define INDEX_REG_CLASS GENERAL_REGS 561 #define BASE_REG_CLASS POINTER_REGS 562 563 /* Register pairs used to eliminate unneeded registers that point into 564 the stack frame. */ 565 #define ELIMINABLE_REGS \ 566 { \ 567 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 568 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 569 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 570 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 571 } 572 573 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 574 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 575 576 /* CPU/ARCH option handling. */ 577 #include "config/aarch64/aarch64-opts.h" 578 579 enum target_cpus 580 { 581 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 582 TARGET_CPU_##INTERNAL_IDENT, 583 #include "aarch64-cores.def" 584 TARGET_CPU_generic 585 }; 586 587 /* If there is no CPU defined at configure, use generic as default. */ 588 #ifndef TARGET_CPU_DEFAULT 589 #define TARGET_CPU_DEFAULT \ 590 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 591 #endif 592 593 /* If inserting NOP before a mult-accumulate insn remember to adjust the 594 length so that conditional branching code is updated appropriately. */ 595 #define ADJUST_INSN_LENGTH(insn, length) \ 596 do \ 597 { \ 598 if (aarch64_madd_needs_nop (insn)) \ 599 length += 4; \ 600 } while (0) 601 602 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 603 aarch64_final_prescan_insn (INSN); \ 604 605 /* The processor for which instructions should be scheduled. */ 606 extern enum aarch64_processor aarch64_tune; 607 608 /* RTL generation support. */ 609 #define INIT_EXPANDERS aarch64_init_expanders () 610 611 612 /* Stack layout; function entry, exit and calling. */ 613 #define STACK_GROWS_DOWNWARD 1 614 615 #define FRAME_GROWS_DOWNWARD 1 616 617 #define ACCUMULATE_OUTGOING_ARGS 1 618 619 #define FIRST_PARM_OFFSET(FNDECL) 0 620 621 /* Fix for VFP */ 622 #define LIBCALL_VALUE(MODE) \ 623 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 624 625 #define DEFAULT_PCC_STRUCT_RETURN 0 626 627 #ifdef HAVE_POLY_INT_H 628 struct GTY (()) aarch64_frame 629 { 630 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 631 632 /* The number of extra stack bytes taken up by register varargs. 633 This area is allocated by the callee at the very top of the 634 frame. This value is rounded up to a multiple of 635 STACK_BOUNDARY. */ 636 HOST_WIDE_INT saved_varargs_size; 637 638 /* The size of the saved callee-save int/FP registers. */ 639 640 HOST_WIDE_INT saved_regs_size; 641 642 /* Offset from the base of the frame (incomming SP) to the 643 top of the locals area. This value is always a multiple of 644 STACK_BOUNDARY. */ 645 poly_int64 locals_offset; 646 647 /* Offset from the base of the frame (incomming SP) to the 648 hard_frame_pointer. This value is always a multiple of 649 STACK_BOUNDARY. */ 650 poly_int64 hard_fp_offset; 651 652 /* The size of the frame. This value is the offset from base of the 653 frame (incomming SP) to the stack_pointer. This value is always 654 a multiple of STACK_BOUNDARY. */ 655 poly_int64 frame_size; 656 657 /* The size of the initial stack adjustment before saving callee-saves. */ 658 poly_int64 initial_adjust; 659 660 /* The writeback value when pushing callee-save registers. 661 It is zero when no push is used. */ 662 HOST_WIDE_INT callee_adjust; 663 664 /* The offset from SP to the callee-save registers after initial_adjust. 665 It may be non-zero if no push is used (ie. callee_adjust == 0). */ 666 poly_int64 callee_offset; 667 668 /* The size of the stack adjustment after saving callee-saves. */ 669 poly_int64 final_adjust; 670 671 /* Store FP,LR and setup a frame pointer. */ 672 bool emit_frame_chain; 673 674 unsigned wb_candidate1; 675 unsigned wb_candidate2; 676 677 bool laid_out; 678 }; 679 680 typedef struct GTY (()) machine_function 681 { 682 struct aarch64_frame frame; 683 /* One entry for each hard register. */ 684 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; 685 } machine_function; 686 #endif 687 688 /* Which ABI to use. */ 689 enum aarch64_abi_type 690 { 691 AARCH64_ABI_LP64 = 0, 692 AARCH64_ABI_ILP32 = 1 693 }; 694 695 #ifndef AARCH64_ABI_DEFAULT 696 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 697 #endif 698 699 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 700 701 enum arm_pcs 702 { 703 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 704 ARM_PCS_UNKNOWN 705 }; 706 707 708 709 710 /* We can't use machine_mode inside a generator file because it 711 hasn't been created yet; we shouldn't be using any code that 712 needs the real definition though, so this ought to be safe. */ 713 #ifdef GENERATOR_FILE 714 #define MACHMODE int 715 #else 716 #include "insn-modes.h" 717 #define MACHMODE machine_mode 718 #endif 719 720 #ifndef USED_FOR_TARGET 721 /* AAPCS related state tracking. */ 722 typedef struct 723 { 724 enum arm_pcs pcs_variant; 725 int aapcs_arg_processed; /* No need to lay out this argument again. */ 726 int aapcs_ncrn; /* Next Core register number. */ 727 int aapcs_nextncrn; /* Next next core register number. */ 728 int aapcs_nvrn; /* Next Vector register number. */ 729 int aapcs_nextnvrn; /* Next Next Vector register number. */ 730 rtx aapcs_reg; /* Register assigned to this argument. This 731 is NULL_RTX if this parameter goes on 732 the stack. */ 733 MACHMODE aapcs_vfp_rmode; 734 int aapcs_stack_words; /* If the argument is passed on the stack, this 735 is the number of words needed, after rounding 736 up. Only meaningful when 737 aapcs_reg == NULL_RTX. */ 738 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 739 stack arg area so far. */ 740 } CUMULATIVE_ARGS; 741 #endif 742 743 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 744 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 745 746 #define PAD_VARARGS_DOWN 0 747 748 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 749 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 750 751 #define FUNCTION_ARG_REGNO_P(REGNO) \ 752 aarch64_function_arg_regno_p(REGNO) 753 754 755 /* ISA Features. */ 756 757 /* Addressing modes, etc. */ 758 #define HAVE_POST_INCREMENT 1 759 #define HAVE_PRE_INCREMENT 1 760 #define HAVE_POST_DECREMENT 1 761 #define HAVE_PRE_DECREMENT 1 762 #define HAVE_POST_MODIFY_DISP 1 763 #define HAVE_PRE_MODIFY_DISP 1 764 765 #define MAX_REGS_PER_ADDRESS 2 766 767 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 768 769 #define REGNO_OK_FOR_BASE_P(REGNO) \ 770 aarch64_regno_ok_for_base_p (REGNO, true) 771 772 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 773 aarch64_regno_ok_for_index_p (REGNO, true) 774 775 #define LEGITIMATE_PIC_OPERAND_P(X) \ 776 aarch64_legitimate_pic_operand_p (X) 777 778 #define CASE_VECTOR_MODE Pmode 779 780 #define DEFAULT_SIGNED_CHAR 0 781 782 /* An integer expression for the size in bits of the largest integer machine 783 mode that should actually be used. We allow pairs of registers. */ 784 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 785 786 /* Maximum bytes moved by a single instruction (load/store pair). */ 787 #define MOVE_MAX (UNITS_PER_WORD * 2) 788 789 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 790 #define AARCH64_CALL_RATIO 8 791 792 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 793 move_by_pieces will continually copy the largest safe chunks. So a 794 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 795 for both size and speed of copy, so we will instead use the "movmem" 796 standard name to implement the copy. This logic does not apply when 797 targeting -mstrict-align, so keep a sensible default in that case. */ 798 #define MOVE_RATIO(speed) \ 799 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 800 801 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 802 of the length of a memset call, but use the default otherwise. */ 803 #define CLEAR_RATIO(speed) \ 804 ((speed) ? 15 : AARCH64_CALL_RATIO) 805 806 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 807 optimizing for size adjust the ratio to account for the overhead of loading 808 the constant. */ 809 #define SET_RATIO(speed) \ 810 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 811 812 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 813 rarely a good idea in straight-line code since it adds an extra address 814 dependency between each instruction. Better to use incrementing offsets. */ 815 #define USE_LOAD_POST_INCREMENT(MODE) 0 816 #define USE_LOAD_POST_DECREMENT(MODE) 0 817 #define USE_LOAD_PRE_INCREMENT(MODE) 0 818 #define USE_LOAD_PRE_DECREMENT(MODE) 0 819 #define USE_STORE_POST_INCREMENT(MODE) 0 820 #define USE_STORE_POST_DECREMENT(MODE) 0 821 #define USE_STORE_PRE_INCREMENT(MODE) 0 822 #define USE_STORE_PRE_DECREMENT(MODE) 0 823 824 /* WORD_REGISTER_OPERATIONS does not hold for AArch64. 825 The assigned word_mode is DImode but operations narrower than SImode 826 behave as 32-bit operations if using the W-form of the registers rather 827 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS 828 expects. */ 829 #define WORD_REGISTER_OPERATIONS 0 830 831 /* Define if loading from memory in MODE, an integral mode narrower than 832 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 833 macro should be the code that says which one of the two operations is 834 implicitly done, or UNKNOWN if none. */ 835 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 836 837 /* Define this macro to be non-zero if instructions will fail to work 838 if given data not on the nominal alignment. */ 839 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 840 841 /* Define this macro to be non-zero if accessing less than a word of 842 memory is no faster than accessing a word of memory, i.e., if such 843 accesses require more than one instruction or if there is no 844 difference in cost. 845 Although there's no difference in instruction count or cycles, 846 in AArch64 we don't want to expand to a sub-word to a 64-bit access 847 if we don't have to, for power-saving reasons. */ 848 #define SLOW_BYTE_ACCESS 0 849 850 #define NO_FUNCTION_CSE 1 851 852 /* Specify the machine mode that the hardware addresses have. 853 After generation of rtl, the compiler makes no further distinction 854 between pointers and any other objects of this machine mode. */ 855 #define Pmode DImode 856 857 /* A C expression whose value is zero if pointers that need to be extended 858 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 859 greater then zero if they are zero-extended and less then zero if the 860 ptr_extend instruction should be used. */ 861 #define POINTERS_EXTEND_UNSIGNED 1 862 863 /* Mode of a function address in a call instruction (for indexing purposes). */ 864 #define FUNCTION_MODE Pmode 865 866 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 867 868 #define REVERSIBLE_CC_MODE(MODE) 1 869 870 #define REVERSE_CONDITION(CODE, MODE) \ 871 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 872 ? reverse_condition_maybe_unordered (CODE) \ 873 : reverse_condition (CODE)) 874 875 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 876 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 877 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 878 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 879 880 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 881 882 #define RETURN_ADDR_RTX aarch64_return_addr 883 884 /* 3 insns + padding + 2 pointer-sized entries. */ 885 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) 886 887 /* Trampolines contain dwords, so must be dword aligned. */ 888 #define TRAMPOLINE_ALIGNMENT 64 889 890 /* Put trampolines in the text section so that mapping symbols work 891 correctly. */ 892 #define TRAMPOLINE_SECTION text_section 893 894 /* To start with. */ 895 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 896 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 897 898 899 /* Assembly output. */ 900 901 /* For now we'll make all jump tables pc-relative. */ 902 #define CASE_VECTOR_PC_RELATIVE 1 903 904 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 905 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 906 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 907 : QImode) 908 909 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 910 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 911 912 #define MCOUNT_NAME "_mcount" 913 914 #define NO_PROFILE_COUNTERS 1 915 916 /* Emit rtl for profiling. Output assembler code to FILE 917 to call "_mcount" for profiling a function entry. */ 918 #define PROFILE_HOOK(LABEL) \ 919 { \ 920 rtx fun, lr; \ 921 lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ 922 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 923 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ 924 } 925 926 /* All the work done in PROFILE_HOOK, but still required. */ 927 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 928 929 /* For some reason, the Linux headers think they know how to define 930 these macros. They don't!!! */ 931 #undef ASM_APP_ON 932 #undef ASM_APP_OFF 933 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 934 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 935 936 #define CONSTANT_POOL_BEFORE_FUNCTION 0 937 938 /* This definition should be relocated to aarch64-elf-raw.h. This macro 939 should be undefined in aarch64-linux.h and a clear_cache pattern 940 implmented to emit either the call to __aarch64_sync_cache_range() 941 directly or preferably the appropriate sycall or cache clear 942 instructions inline. */ 943 #define CLEAR_INSN_CACHE(beg, end) \ 944 extern void __aarch64_sync_cache_range (void *, void *); \ 945 __aarch64_sync_cache_range (beg, end) 946 947 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) 948 949 /* Choose appropriate mode for caller saves, so we do the minimum 950 required size of load/store. */ 951 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 952 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 953 954 #undef SWITCHABLE_TARGET 955 #define SWITCHABLE_TARGET 1 956 957 /* Check TLS Descriptors mechanism is selected. */ 958 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 959 960 extern enum aarch64_code_model aarch64_cmodel; 961 962 /* When using the tiny addressing model conditional and unconditional branches 963 can span the whole of the available address space (1MB). */ 964 #define HAS_LONG_COND_BRANCH \ 965 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 966 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 967 968 #define HAS_LONG_UNCOND_BRANCH \ 969 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 970 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 971 972 #define TARGET_SUPPORTS_WIDE_INT 1 973 974 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 975 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 976 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 977 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 978 || (MODE) == DFmode) 979 980 /* Modes valid for AdvSIMD Q registers. */ 981 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 982 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 983 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 984 || (MODE) == V2DFmode) 985 986 #define ENDIAN_LANE_N(NUNITS, N) \ 987 (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) 988 989 /* Support for a configure-time default CPU, etc. We currently support 990 --with-arch and --with-cpu. Both are ignored if either is specified 991 explicitly on the command line at run time. */ 992 #define OPTION_DEFAULT_SPECS \ 993 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 994 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, 995 996 #define MCPU_TO_MARCH_SPEC \ 997 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" 998 999 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 1000 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 1001 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 1002 1003 #if defined(__aarch64__) 1004 extern const char *host_detect_local_cpu (int argc, const char **argv); 1005 #define HAVE_LOCAL_CPU_DETECT 1006 # define EXTRA_SPEC_FUNCTIONS \ 1007 { "local_cpu_detect", host_detect_local_cpu }, \ 1008 MCPU_TO_MARCH_SPEC_FUNCTIONS 1009 1010 # define MCPU_MTUNE_NATIVE_SPECS \ 1011 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 1012 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 1013 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 1014 #else 1015 # define MCPU_MTUNE_NATIVE_SPECS "" 1016 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 1017 #endif 1018 1019 #define ASM_CPU_SPEC \ 1020 MCPU_TO_MARCH_SPEC 1021 1022 #define EXTRA_SPECS \ 1023 { "asm_cpu_spec", ASM_CPU_SPEC } 1024 1025 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 1026 1027 /* This type is the user-visible __fp16, and a pointer to that type. We 1028 need it in many places in the backend. Defined in aarch64-builtins.c. */ 1029 extern tree aarch64_fp16_type_node; 1030 extern tree aarch64_fp16_ptr_type_node; 1031 1032 /* The generic unwind code in libgcc does not initialize the frame pointer. 1033 So in order to unwind a function using a frame pointer, the very first 1034 function that is unwound must save the frame pointer. That way the frame 1035 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 1036 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 1037 #define LIBGCC2_UNWIND_ATTRIBUTE \ 1038 __attribute__((optimize ("no-omit-frame-pointer"))) 1039 1040 #ifndef USED_FOR_TARGET 1041 extern poly_uint16 aarch64_sve_vg; 1042 1043 /* The number of bits and bytes in an SVE vector. */ 1044 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) 1045 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) 1046 1047 /* The number of bytes in an SVE predicate. */ 1048 #define BYTES_PER_SVE_PRED aarch64_sve_vg 1049 1050 /* The SVE mode for a vector of bytes. */ 1051 #define SVE_BYTE_MODE VNx16QImode 1052 1053 /* The maximum number of bytes in a fixed-size vector. This is 256 bytes 1054 (for -msve-vector-bits=2048) multiplied by the maximum number of 1055 vectors in a structure mode (4). 1056 1057 This limit must not be used for variable-size vectors, since 1058 VL-agnostic code must work with arbitary vector lengths. */ 1059 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) 1060 #endif 1061 1062 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) 1063 1064 #endif /* GCC_AARCH64_H */ 1065