1 /* Subroutines for the C front end on the PowerPC architecture.
2 Copyright (C) 2002-2018 Free Software Foundation, Inc.
3
4 Contributed by Zack Weinberg <zack@codesourcery.com>
5 and Paolo Bonzini <bonzini@gnu.org>
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #define IN_TARGET_CODE 1
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "target.h"
29 #include "c-family/c-common.h"
30 #include "memmodel.h"
31 #include "tm_p.h"
32 #include "stringpool.h"
33 #include "stor-layout.h"
34 #include "c-family/c-pragma.h"
35 #include "langhooks.h"
36 #include "c/c-tree.h"
37
38
39
40 /* Handle the machine specific pragma longcall. Its syntax is
41
42 # pragma longcall ( TOGGLE )
43
44 where TOGGLE is either 0 or 1.
45
46 rs6000_default_long_calls is set to the value of TOGGLE, changing
47 whether or not new function declarations receive a longcall
48 attribute by default. */
49
50 #define SYNTAX_ERROR(gmsgid) do { \
51 warning (OPT_Wpragmas, gmsgid); \
52 warning (OPT_Wpragmas, "ignoring malformed #pragma longcall"); \
53 return; \
54 } while (0)
55
56 void
rs6000_pragma_longcall(cpp_reader * pfile ATTRIBUTE_UNUSED)57 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
58 {
59 tree x, n;
60
61 /* If we get here, generic code has already scanned the directive
62 leader and the word "longcall". */
63
64 if (pragma_lex (&x) != CPP_OPEN_PAREN)
65 SYNTAX_ERROR ("missing open paren");
66 if (pragma_lex (&n) != CPP_NUMBER)
67 SYNTAX_ERROR ("missing number");
68 if (pragma_lex (&x) != CPP_CLOSE_PAREN)
69 SYNTAX_ERROR ("missing close paren");
70
71 if (n != integer_zero_node && n != integer_one_node)
72 SYNTAX_ERROR ("number must be 0 or 1");
73
74 if (pragma_lex (&x) != CPP_EOF)
75 warning (OPT_Wpragmas, "junk at end of #pragma longcall");
76
77 rs6000_default_long_calls = (n == integer_one_node);
78 }
79
80 /* Handle defining many CPP flags based on TARGET_xxx. As a general
81 policy, rather than trying to guess what flags a user might want a
82 #define for, it's better to define a flag for everything. */
83
84 #define builtin_define(TXT) cpp_define (pfile, TXT)
85 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
86
87 /* Keep the AltiVec keywords handy for fast comparisons. */
88 static GTY(()) tree __vector_keyword;
89 static GTY(()) tree vector_keyword;
90 static GTY(()) tree __pixel_keyword;
91 static GTY(()) tree pixel_keyword;
92 static GTY(()) tree __bool_keyword;
93 static GTY(()) tree bool_keyword;
94 static GTY(()) tree _Bool_keyword;
95 static GTY(()) tree __int128_type;
96 static GTY(()) tree __uint128_type;
97
98 /* Preserved across calls. */
99 static tree expand_bool_pixel;
100
101 static cpp_hashnode *
altivec_categorize_keyword(const cpp_token * tok)102 altivec_categorize_keyword (const cpp_token *tok)
103 {
104 if (tok->type == CPP_NAME)
105 {
106 cpp_hashnode *ident = tok->val.node.node;
107
108 if (ident == C_CPP_HASHNODE (vector_keyword))
109 return C_CPP_HASHNODE (__vector_keyword);
110
111 if (ident == C_CPP_HASHNODE (pixel_keyword))
112 return C_CPP_HASHNODE (__pixel_keyword);
113
114 if (ident == C_CPP_HASHNODE (bool_keyword))
115 return C_CPP_HASHNODE (__bool_keyword);
116
117 if (ident == C_CPP_HASHNODE (_Bool_keyword))
118 return C_CPP_HASHNODE (__bool_keyword);
119
120 return ident;
121 }
122
123 return 0;
124 }
125
126 static void
init_vector_keywords(void)127 init_vector_keywords (void)
128 {
129 /* Keywords without two leading underscores are context-sensitive, and hence
130 implemented as conditional macros, controlled by the
131 rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit
132 support, record the __int128_t and __uint128_t types. */
133
134 __vector_keyword = get_identifier ("__vector");
135 C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
136
137 __pixel_keyword = get_identifier ("__pixel");
138 C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
139
140 __bool_keyword = get_identifier ("__bool");
141 C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
142
143 vector_keyword = get_identifier ("vector");
144 C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
145
146 pixel_keyword = get_identifier ("pixel");
147 C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
148
149 bool_keyword = get_identifier ("bool");
150 C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
151
152 _Bool_keyword = get_identifier ("_Bool");
153 C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
154
155 if (TARGET_VADDUQM)
156 {
157 __int128_type = get_identifier ("__int128_t");
158 __uint128_type = get_identifier ("__uint128_t");
159 }
160 }
161
162 /* Helper function to find out which RID_INT_N_* code is the one for
163 __int128, if any. Returns RID_MAX+1 if none apply, which is safe
164 (for our purposes, since we always expect to have __int128) to
165 compare against. */
166 static int
rid_int128(void)167 rid_int128(void)
168 {
169 int i;
170
171 for (i = 0; i < NUM_INT_N_ENTS; i ++)
172 if (int_n_enabled_p[i]
173 && int_n_data[i].bitsize == 128)
174 return RID_INT_N_0 + i;
175
176 return RID_MAX + 1;
177 }
178
179 /* Called to decide whether a conditional macro should be expanded.
180 Since we have exactly one such macro (i.e, 'vector'), we do not
181 need to examine the 'tok' parameter. */
182
183 static cpp_hashnode *
rs6000_macro_to_expand(cpp_reader * pfile,const cpp_token * tok)184 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
185 {
186 cpp_hashnode *expand_this = tok->val.node.node;
187 cpp_hashnode *ident;
188
189 /* If the current machine does not have altivec, don't look for the
190 keywords. */
191 if (!TARGET_ALTIVEC)
192 return NULL;
193
194 ident = altivec_categorize_keyword (tok);
195
196 if (ident != expand_this)
197 expand_this = NULL;
198
199 if (ident == C_CPP_HASHNODE (__vector_keyword))
200 {
201 int idx = 0;
202 do
203 tok = cpp_peek_token (pfile, idx++);
204 while (tok->type == CPP_PADDING);
205 ident = altivec_categorize_keyword (tok);
206
207 if (ident == C_CPP_HASHNODE (__pixel_keyword))
208 {
209 expand_this = C_CPP_HASHNODE (__vector_keyword);
210 expand_bool_pixel = __pixel_keyword;
211 }
212 else if (ident == C_CPP_HASHNODE (__bool_keyword))
213 {
214 expand_this = C_CPP_HASHNODE (__vector_keyword);
215 expand_bool_pixel = __bool_keyword;
216 }
217 /* The boost libraries have code with Iterator::vector vector in it. If
218 we allow the normal handling, this module will be called recursively,
219 and the vector will be skipped.; */
220 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
221 {
222 enum rid rid_code = (enum rid)(ident->rid_code);
223 enum node_type itype = ident->type;
224 /* If there is a function-like macro, check if it is going to be
225 invoked with or without arguments. Without following ( treat
226 it like non-macro, otherwise the following cpp_get_token eats
227 what should be preserved. */
228 if (itype == NT_MACRO && cpp_fun_like_macro_p (ident))
229 {
230 int idx2 = idx;
231 do
232 tok = cpp_peek_token (pfile, idx2++);
233 while (tok->type == CPP_PADDING);
234 if (tok->type != CPP_OPEN_PAREN)
235 itype = NT_VOID;
236 }
237 if (itype == NT_MACRO)
238 {
239 do
240 (void) cpp_get_token (pfile);
241 while (--idx > 0);
242 do
243 tok = cpp_peek_token (pfile, idx++);
244 while (tok->type == CPP_PADDING);
245 ident = altivec_categorize_keyword (tok);
246 if (ident == C_CPP_HASHNODE (__pixel_keyword))
247 {
248 expand_this = C_CPP_HASHNODE (__vector_keyword);
249 expand_bool_pixel = __pixel_keyword;
250 rid_code = RID_MAX;
251 }
252 else if (ident == C_CPP_HASHNODE (__bool_keyword))
253 {
254 expand_this = C_CPP_HASHNODE (__vector_keyword);
255 expand_bool_pixel = __bool_keyword;
256 rid_code = RID_MAX;
257 }
258 else if (ident)
259 rid_code = (enum rid)(ident->rid_code);
260 }
261
262 if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
263 || rid_code == RID_SHORT || rid_code == RID_SIGNED
264 || rid_code == RID_INT || rid_code == RID_CHAR
265 || rid_code == RID_FLOAT
266 || (rid_code == RID_DOUBLE && TARGET_VSX)
267 || (rid_code == rid_int128 () && TARGET_VADDUQM))
268 {
269 expand_this = C_CPP_HASHNODE (__vector_keyword);
270 /* If the next keyword is bool or pixel, it
271 will need to be expanded as well. */
272 do
273 tok = cpp_peek_token (pfile, idx++);
274 while (tok->type == CPP_PADDING);
275 ident = altivec_categorize_keyword (tok);
276
277 if (ident == C_CPP_HASHNODE (__pixel_keyword))
278 expand_bool_pixel = __pixel_keyword;
279 else if (ident == C_CPP_HASHNODE (__bool_keyword))
280 expand_bool_pixel = __bool_keyword;
281 else
282 {
283 /* Try two tokens down, too. */
284 do
285 tok = cpp_peek_token (pfile, idx++);
286 while (tok->type == CPP_PADDING);
287 ident = altivec_categorize_keyword (tok);
288 if (ident == C_CPP_HASHNODE (__pixel_keyword))
289 expand_bool_pixel = __pixel_keyword;
290 else if (ident == C_CPP_HASHNODE (__bool_keyword))
291 expand_bool_pixel = __bool_keyword;
292 }
293 }
294
295 /* Support vector __int128_t, but we don't need to worry about bool
296 or pixel on this type. */
297 else if (TARGET_VADDUQM
298 && (ident == C_CPP_HASHNODE (__int128_type)
299 || ident == C_CPP_HASHNODE (__uint128_type)))
300 expand_this = C_CPP_HASHNODE (__vector_keyword);
301 }
302 }
303 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
304 {
305 expand_this = C_CPP_HASHNODE (__pixel_keyword);
306 expand_bool_pixel = 0;
307 }
308 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
309 {
310 expand_this = C_CPP_HASHNODE (__bool_keyword);
311 expand_bool_pixel = 0;
312 }
313
314 return expand_this;
315 }
316
317
318 /* Define or undefine a single macro. */
319
320 static void
rs6000_define_or_undefine_macro(bool define_p,const char * name)321 rs6000_define_or_undefine_macro (bool define_p, const char *name)
322 {
323 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
324 fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
325
326 if (define_p)
327 cpp_define (parse_in, name);
328 else
329 cpp_undef (parse_in, name);
330 }
331
332 /* Define or undefine macros based on the current target. If the user does
333 #pragma GCC target, we need to adjust the macros dynamically. Note, some of
334 the options needed for builtins have been moved to separate variables, so
335 have both the target flags and the builtin flags as arguments. */
336
337 void
rs6000_target_modify_macros(bool define_p,HOST_WIDE_INT flags,HOST_WIDE_INT bu_mask)338 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
339 HOST_WIDE_INT bu_mask)
340 {
341 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
342 fprintf (stderr,
343 "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
344 ", " HOST_WIDE_INT_PRINT_HEX ")\n",
345 (define_p) ? "define" : "undef",
346 flags, bu_mask);
347
348 /* Each of the flags mentioned below controls whether certain
349 preprocessor macros will be automatically defined when
350 preprocessing source files for compilation by this compiler.
351 While most of these flags can be enabled or disabled
352 explicitly by specifying certain command-line options when
353 invoking the compiler, there are also many ways in which these
354 flags are enabled or disabled implicitly, based on compiler
355 defaults, configuration choices, and on the presence of certain
356 related command-line options. Many, but not all, of these
357 implicit behaviors can be found in file "rs6000.c", the
358 rs6000_option_override_internal() function.
359
360 In general, each of the flags may be automatically enabled in
361 any of the following conditions:
362
363 1. If no -mcpu target is specified on the command line and no
364 --with-cpu target is specified to the configure command line
365 and the TARGET_DEFAULT macro for this default cpu host
366 includes the flag, and the flag has not been explicitly disabled
367 by command-line options.
368
369 2. If the target specified with -mcpu=target on the command line, or
370 in the absence of a -mcpu=target command-line option, if the
371 target specified using --with-cpu=target on the configure
372 command line, is disqualified because the associated binary
373 tools (e.g. the assembler) lack support for the requested cpu,
374 and the TARGET_DEFAULT macro for this default cpu host
375 includes the flag, and the flag has not been explicitly disabled
376 by command-line options.
377
378 3. If either of the above two conditions apply except that the
379 TARGET_DEFAULT macro is defined to equal zero, and
380 TARGET_POWERPC64 and
381 a) BYTES_BIG_ENDIAN and the flag to be enabled is either
382 MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
383 target), or
384 b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
385 MASK_POWERPC64 or it is one of the flags included in
386 ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
387
388 4. If a cpu has been requested with a -mcpu=target command-line option
389 and this cpu has not been disqualified due to shortcomings of the
390 binary tools, and the set of flags associated with the requested cpu
391 include the flag to be enabled. See rs6000-cpus.def for macro
392 definitions that represent various ABI standards
393 (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
394 the specific flags that are associated with each of the cpu
395 choices that can be specified as the target of a -mcpu=target
396 compile option, or as the the target of a --with-cpu=target
397 configure option. Target flags that are specified in either
398 of these two ways are considered "implicit" since the flags
399 are not mentioned specifically by name.
400
401 Additional documentation describing behavior specific to
402 particular flags is provided below, immediately preceding the
403 use of each relevant flag.
404
405 5. If there is no -mcpu=target command-line option, and the cpu
406 requested by a --with-cpu=target command-line option has not
407 been disqualified due to shortcomings of the binary tools, and
408 the set of flags associated with the specified target include
409 the flag to be enabled. See the notes immediately above for a
410 summary of the flags associated with particular cpu
411 definitions. */
412
413 /* rs6000_isa_flags based options. */
414 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
415 if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
416 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
417 if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
418 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
419 if ((flags & OPTION_MASK_POWERPC64) != 0)
420 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
421 if ((flags & OPTION_MASK_MFCRF) != 0)
422 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
423 if ((flags & OPTION_MASK_POPCNTB) != 0)
424 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
425 if ((flags & OPTION_MASK_FPRND) != 0)
426 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
427 if ((flags & OPTION_MASK_CMPB) != 0)
428 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
429 if ((flags & OPTION_MASK_MFPGPR) != 0)
430 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
431 if ((flags & OPTION_MASK_POPCNTD) != 0)
432 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
433 /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
434 turned on in the following condition:
435 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
436 explicitly disabled.
437 Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
438 have been turned on explicitly.
439 Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
440 turned off in any of the following conditions:
441 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
442 disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
443 enabled.
444 2. TARGET_VSX is off. */
445 if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
446 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
447 if ((flags & OPTION_MASK_MODULO) != 0)
448 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
449 if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
450 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
451 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
452 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
453 /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
454 in any of the following conditions:
455 1. The command line specifies either -maltivec=le or -maltivec=be.
456 2. The operating system is Darwin and it is configured for 64
457 bit. (See darwin_rs6000_override_options.)
458 3. The operating system is Darwin and the operating system
459 version is 10.5 or higher and the user has not explicitly
460 disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
461 the compiler is not producing code for integration within the
462 kernel. (See darwin_rs6000_override_options.)
463 Note that the OPTION_MASK_ALTIVEC flag is automatically turned
464 off in any of the following conditions:
465 1. The operating system does not support saving of AltiVec
466 registers (OS_MISSING_ALTIVEC).
467 2. If an inner context (as introduced by
468 __attribute__((__target__())) or #pragma GCC target()
469 requests a target that normally enables the
470 OPTION_MASK_ALTIVEC flag but the outer-most "main target"
471 does not support the rs6000_altivec_abi, this flag is
472 turned off for the inner context unless OPTION_MASK_ALTIVEC
473 was explicitly enabled for the inner context. */
474 if ((flags & OPTION_MASK_ALTIVEC) != 0)
475 {
476 const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
477 rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
478 rs6000_define_or_undefine_macro (define_p, vec_str);
479
480 /* Define this when supporting context-sensitive keywords. */
481 if (!flag_iso)
482 rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
483 }
484 /* Note that the OPTION_MASK_VSX flag is automatically turned on in
485 the following conditions:
486 1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
487 was not explicitly turned off. Hereafter, the OPTION_MASK_VSX
488 flag is considered to have been explicitly turned on.
489 Note that the OPTION_MASK_VSX flag is automatically turned off in
490 the following conditions:
491 1. The operating system does not support saving of AltiVec
492 registers (OS_MISSING_ALTIVEC).
493 2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
494 or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
495 OPTION_MASK_VSX flag is considered to have been turned off
496 explicitly.
497 3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the
498 OPTION_MASK_VSX flag is considered to have been turned off
499 explicitly.
500 4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
501 compilation context, or if it is turned on by any means in an
502 inner compilation context. Hereafter, the OPTION_MASK_VSX
503 flag is considered to have been turned off explicitly.
504 5. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
505 OPTION_MASK_VSX flag is considered to have been turned off
506 explicitly.
507 6. If an inner context (as introduced by
508 __attribute__((__target__())) or #pragma GCC target()
509 requests a target that normally enables the
510 OPTION_MASK_VSX flag but the outer-most "main target"
511 does not support the rs6000_altivec_abi, this flag is
512 turned off for the inner context unless OPTION_MASK_VSX
513 was explicitly enabled for the inner context. */
514 if ((flags & OPTION_MASK_VSX) != 0)
515 rs6000_define_or_undefine_macro (define_p, "__VSX__");
516 if ((flags & OPTION_MASK_HTM) != 0)
517 {
518 rs6000_define_or_undefine_macro (define_p, "__HTM__");
519 /* Tell the user that our HTM insn patterns act as memory barriers. */
520 rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
521 }
522 /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
523 on in the following conditions:
524 1. TARGET_P9_VECTOR is explicitly turned on and
525 OPTION_MASK_P8_VECTOR is not explicitly turned off.
526 Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
527 have been turned off explicitly.
528 Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
529 off in the following conditions:
530 1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
531 were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
532 not turned on explicitly.
533 2. If TARGET_ALTIVEC is turned off. Hereafter, the
534 OPTION_MASK_P8_VECTOR flag is considered to have been turned off
535 explicitly.
536 3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
537 explicitly enabled. If TARGET_VSX is explicitly enabled, the
538 OPTION_MASK_P8_VECTOR flag is hereafter also considered to
539 have been turned off explicitly. */
540 if ((flags & OPTION_MASK_P8_VECTOR) != 0)
541 rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
542 /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
543 off in the following conditions:
544 1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
545 not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
546 was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
547 also considered to have been turned off explicitly.
548 Note that the OPTION_MASK_P9_VECTOR is automatically turned on
549 in the following conditions:
550 1. If TARGET_P9_MINMAX was turned on explicitly.
551 Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
552 have been turned on explicitly. */
553 if ((flags & OPTION_MASK_P9_VECTOR) != 0)
554 rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
555 /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
556 turned off in the following conditions:
557 1. If TARGET_POWERPC64 is turned off.
558 2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
559 load/store are disabled on little endian). */
560 if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
561 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
562 /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
563 turned off in the following conditions:
564 1. If TARGET_POWERPC64 is turned off.
565 Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
566 automatically turned on in the following conditions:
567 1. If TARGET_QUAD_MEMORY and this flag was not explicitly
568 disabled. */
569 if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
570 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
571 /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
572 in the following conditions:
573 1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
574 are turned off explicitly and OPTION_MASK_CRYPTO is not turned
575 on explicitly.
576 2. If TARGET_ALTIVEC is turned off. */
577 if ((flags & OPTION_MASK_CRYPTO) != 0)
578 rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
579 if ((flags & OPTION_MASK_FLOAT128_KEYWORD) != 0)
580 {
581 rs6000_define_or_undefine_macro (define_p, "__FLOAT128__");
582 if (define_p)
583 rs6000_define_or_undefine_macro (true, "__float128=__ieee128");
584 else
585 rs6000_define_or_undefine_macro (false, "__float128");
586 }
587 /* OPTION_MASK_FLOAT128_HARDWARE can be turned on if -mcpu=power9 is used or
588 via the target attribute/pragma. */
589 if ((flags & OPTION_MASK_FLOAT128_HW) != 0)
590 rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
591
592 /* options from the builtin masks. */
593 /* Note that RS6000_BTM_PAIRED is enabled only if
594 TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
595 if ((bu_mask & RS6000_BTM_PAIRED) != 0)
596 rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
597 /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
598 PROCESSOR_CELL) (e.g. -mcpu=cell). */
599 if ((bu_mask & RS6000_BTM_CELL) != 0)
600 rs6000_define_or_undefine_macro (define_p, "__PPU__");
601 }
602
603 void
rs6000_cpu_cpp_builtins(cpp_reader * pfile)604 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
605 {
606 /* Define all of the common macros. */
607 rs6000_target_modify_macros (true, rs6000_isa_flags,
608 rs6000_builtin_mask_calculate ());
609
610 if (TARGET_FRE)
611 builtin_define ("__RECIP__");
612 if (TARGET_FRES)
613 builtin_define ("__RECIPF__");
614 if (TARGET_FRSQRTE)
615 builtin_define ("__RSQRTE__");
616 if (TARGET_FRSQRTES)
617 builtin_define ("__RSQRTEF__");
618 if (TARGET_FLOAT128_TYPE)
619 builtin_define ("__FLOAT128_TYPE__");
620 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
621 builtin_define ("__BUILTIN_CPU_SUPPORTS__");
622 #endif
623
624 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
625 {
626 /* Define the AltiVec syntactic elements. */
627 builtin_define ("__vector=__attribute__((altivec(vector__)))");
628 builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
629 builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
630
631 if (!flag_iso)
632 {
633 builtin_define ("vector=vector");
634 builtin_define ("pixel=pixel");
635 builtin_define ("bool=bool");
636 builtin_define ("_Bool=_Bool");
637 init_vector_keywords ();
638
639 /* Enable context-sensitive macros. */
640 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
641 }
642 }
643 if (!TARGET_HARD_FLOAT || !TARGET_DOUBLE_FLOAT)
644 builtin_define ("_SOFT_DOUBLE");
645 /* Used by lwarx/stwcx. errata work-around. */
646 if (rs6000_cpu == PROCESSOR_PPC405)
647 builtin_define ("__PPC405__");
648 /* Used by libstdc++. */
649 if (TARGET_NO_LWSYNC)
650 builtin_define ("__NO_LWSYNC__");
651
652 if (TARGET_EXTRA_BUILTINS)
653 {
654 /* For the VSX builtin functions identical to Altivec functions, just map
655 the altivec builtin into the vsx version (the altivec functions
656 generate VSX code if -mvsx). */
657 builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
658 builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
659 builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
660 builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
661 builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
662 builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
663 builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
664
665 /* Also map the a and m versions of the multiply/add instructions to the
666 builtin for people blindly going off the instruction manual. */
667 builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
668 builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
669 builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
670 builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
671 builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
672 builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
673 builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
674 builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
675 builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
676 builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
677 builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
678 builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
679 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
680 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
681 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
682 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
683 }
684
685 /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */
686 if (TARGET_FLOAT128_TYPE)
687 {
688 builtin_define ("__builtin_fabsq=__builtin_fabsf128");
689 builtin_define ("__builtin_copysignq=__builtin_copysignf128");
690 builtin_define ("__builtin_nanq=__builtin_nanf128");
691 builtin_define ("__builtin_nansq=__builtin_nansf128");
692 builtin_define ("__builtin_infq=__builtin_inff128");
693 builtin_define ("__builtin_huge_valq=__builtin_huge_valf128");
694 }
695
696 /* Tell users they can use __builtin_bswap{16,64}. */
697 builtin_define ("__HAVE_BSWAP__");
698
699 /* May be overridden by target configuration. */
700 RS6000_CPU_CPP_ENDIAN_BUILTINS();
701
702 if (TARGET_LONG_DOUBLE_128)
703 {
704 builtin_define ("__LONG_DOUBLE_128__");
705 builtin_define ("__LONGDOUBLE128");
706
707 if (TARGET_IEEEQUAD)
708 {
709 /* Older versions of GLIBC used __attribute__((__KC__)) to create the
710 IEEE 128-bit floating point complex type for C++ (which does not
711 support _Float128 _Complex). If the default for long double is
712 IEEE 128-bit mode, the library would need to use
713 __attribute__((__TC__)) instead. Defining __KF__ and __KC__
714 is a stop-gap to build with the older libraries, until we
715 get an updated library. */
716 builtin_define ("__LONG_DOUBLE_IEEE128__");
717 builtin_define ("__KF__=__TF__");
718 builtin_define ("__KC__=__TC__");
719 }
720 else
721 builtin_define ("__LONG_DOUBLE_IBM128__");
722 }
723
724 switch (TARGET_CMODEL)
725 {
726 /* Deliberately omit __CMODEL_SMALL__ since that was the default
727 before --mcmodel support was added. */
728 case CMODEL_MEDIUM:
729 builtin_define ("__CMODEL_MEDIUM__");
730 break;
731 case CMODEL_LARGE:
732 builtin_define ("__CMODEL_LARGE__");
733 break;
734 default:
735 break;
736 }
737
738 switch (rs6000_current_abi)
739 {
740 case ABI_V4:
741 builtin_define ("_CALL_SYSV");
742 break;
743 case ABI_AIX:
744 builtin_define ("_CALL_AIXDESC");
745 builtin_define ("_CALL_AIX");
746 builtin_define ("_CALL_ELF=1");
747 break;
748 case ABI_ELFv2:
749 builtin_define ("_CALL_ELF=2");
750 break;
751 case ABI_DARWIN:
752 builtin_define ("_CALL_DARWIN");
753 break;
754 default:
755 break;
756 }
757
758 /* Vector element order. */
759 if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
760 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
761 else
762 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
763
764 /* Let the compiled code know if 'f' class registers will not be available. */
765 if (TARGET_SOFT_FLOAT)
766 builtin_define ("__NO_FPRS__");
767
768 /* Whether aggregates passed by value are aligned to a 16 byte boundary
769 if their alignment is 16 bytes or larger. */
770 if ((TARGET_MACHO && rs6000_darwin64_abi)
771 || DEFAULT_ABI == ABI_ELFv2
772 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
773 builtin_define ("__STRUCT_PARM_ALIGN__=16");
774
775 /* Generate defines for Xilinx FPU. */
776 if (rs6000_xilinx_fpu)
777 {
778 builtin_define ("_XFPU");
779 if (rs6000_single_float && ! rs6000_double_float)
780 {
781 if (rs6000_simple_fpu)
782 builtin_define ("_XFPU_SP_LITE");
783 else
784 builtin_define ("_XFPU_SP_FULL");
785 }
786 if (rs6000_double_float)
787 {
788 if (rs6000_simple_fpu)
789 builtin_define ("_XFPU_DP_LITE");
790 else
791 builtin_define ("_XFPU_DP_FULL");
792 }
793 }
794 }
795
796
797 struct altivec_builtin_types
798 {
799 enum rs6000_builtins code;
800 enum rs6000_builtins overloaded_code;
801 signed char ret_type;
802 signed char op1;
803 signed char op2;
804 signed char op3;
805 };
806
807 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
808 /* Unary AltiVec/VSX builtins. */
809 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
810 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
811 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
812 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
813 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
814 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
815 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
816 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
817 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
818 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
819 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
820 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
821 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
822 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
823 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
824 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
825 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
826 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
827 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
828 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
829 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
830 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
831 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
832 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
833 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
834 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
835 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
836 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
837 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
838 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
839 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
840 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
841 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
842 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
843 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
844 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
845 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
846 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
847 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
848 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
849 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
850 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
851 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
852 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
853 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
854 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
855 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
856 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
857 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
858 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
859 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
860 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
861 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
862 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
863 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
864 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
865 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
866 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
867 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
868 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
869 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
870 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
871 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
872 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
873 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
874 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
875 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
876 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
877 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
878 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
879 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
880 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
881 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
882 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
883 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
884 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
885 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
886 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
887 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
888 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
889 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
890 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
891 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
892 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
893 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
894 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
895 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
896 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
897 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
898 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
899 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
900 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
901 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
902 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
903 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
904 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
905 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
906 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
907 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
908 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
909 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
910 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
911 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
912 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
913 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
914 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
915 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
916 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
917 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
918 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
919 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
920 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
921 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
922 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
923 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
924 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
925 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
926 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
927 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
928 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
929 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
930 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
931 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
932 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
933 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
934 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
935 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
936 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
937 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
938 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
939 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
940 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
941 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
942 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
943
944 /* Binary AltiVec/VSX builtins. */
945 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
946 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
947 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
948 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
949 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
950 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
951 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
952 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
953 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
954 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
955 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
956 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
957 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
958 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
959 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
960 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
961 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
962 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
963 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
964 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
965 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
966 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
967 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
968 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
969 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
970 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
971 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
972 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
973 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
974 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
975 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
976 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
977 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
978 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
979 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
980 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
981 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
982 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
983 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
984 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
985 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
986 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
987 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
988 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
989 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
991 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
992 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
993 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
994 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
995 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
996 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
997 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
998 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
999 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
1000 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1001 RS6000_BTI_unsigned_V1TI, 0 },
1002 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
1003 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1004 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1005 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1006 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1007 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1008 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1009 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1010 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1011 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1012 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1013 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1014 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1015 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1016 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1017 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1018 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1019 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1020 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1021 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1022 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1023 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1024 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1025 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1026 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1027 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1028 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1029 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1030 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1031 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1032 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1033 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1034 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1035 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1036 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1037 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1038 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1039 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1040 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1041 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1042 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1043 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1044 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1045 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1046 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1047 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1048 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1049 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1050 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1051 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1052 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1053 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1054 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1055 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1056 RS6000_BTI_unsigned_V4SI, 0 },
1057 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1058 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1059 RS6000_BTI_unsigned_V1TI, 0 },
1060 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1061 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1062 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1063 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1064 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1065 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1066 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
1067 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1068 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1069 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1070 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1071 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1072 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1073 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1074 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1075 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1076 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1077 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1078 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1079 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1080 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1081 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1082 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1083 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1084 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1085 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1086 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1087 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1088 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1089 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1090 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1091 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1092 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1093 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1094 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1095 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1096 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1097 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1098 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1099 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1100 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1101 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1102 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1103 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1104 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1105 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1106 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1107 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1108 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1109 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1110 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1111 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1112 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1113 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1114 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1115 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1116 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1117 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1118 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1119 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1120 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1121 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1122 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1123 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1124 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1125 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1126 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1127 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1128 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1129 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1130 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1131 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1132 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1133 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1134 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1135 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1136 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1137 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1138 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1139 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1140 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1141 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1142 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1143 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1144 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1145 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1146 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1147 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1148 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1149 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1150 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1151 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1152 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1153 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1154 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1155 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1156 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1157 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1158 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1159 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1160 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1161 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1162 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1163 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1164 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1165 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1166 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1167 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1168 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1169 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1170 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1171 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1172 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1173 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1174 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1175 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1176 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1177 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1178 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1179 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1180 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1181 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1182 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1183 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1184 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1185 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1186 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1187 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1188 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1189 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1190 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1191 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1192 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1193 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1194 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1195 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1196 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1197 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1198 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1199 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1201 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1202 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1203 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1204 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1205 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1206 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1207 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1208 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1209 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1210 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1211 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1212 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1213 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1214 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1215 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1216 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1217 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1218 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1219 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1220 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1221 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1222 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1223 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1224 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1225 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1226 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1227 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1228 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1229 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1230 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1231 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1232 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1233 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1234 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1235 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1236 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1237 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1238 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1239 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1240 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1241 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1242 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1243 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1244 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1245 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1246 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1247 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1248 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1249 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1250 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1251 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1252 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1253 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1254 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1255 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1256 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1257 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1258 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1259 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1260 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1261 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1262 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1263 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1264 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1265 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1266 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1267 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1268 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1269 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1270 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1271 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1272 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1273 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1274 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1275 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1276 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1277 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1278 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1279 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1280 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1281 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1282 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1283 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1284 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1285 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1286 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1287 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1288 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1289 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1290 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1291 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1292 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1293 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1294 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1295 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1296 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1297 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1298 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1299 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1300 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1301 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1302 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1303 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1304 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1305 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1306 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1307 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1308 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1309 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1310 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1311 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1312 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1313 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1314 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1315 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1316 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1317 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1318 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1319 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1320 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1321 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1322 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1323 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1324 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1325 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1326 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1327 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1328 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1329 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1330 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1331 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1332 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1333 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1334 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1335 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1336 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1337 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1338 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1339 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1340 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1341 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
1342 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1343
1344 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1345 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1346 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1347 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1348
1349 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1350 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1351 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1352 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1353
1354 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1355 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1356 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1357 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1358
1359 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1360 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1361 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1362 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1363 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1364 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1365 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1366 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1367 RS6000_BTI_unsigned_V16QI, 0},
1368 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1369 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1370 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1371 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1372 RS6000_BTI_unsigned_V8HI, 0},
1373 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1374 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1375 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1376 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1377 RS6000_BTI_unsigned_V4SI, 0},
1378 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1379 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1380 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1381 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1382 RS6000_BTI_unsigned_V2DI, 0},
1383 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1384 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1385 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1386 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1387 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1388 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1389 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1390 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1391 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1392 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1393 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1394 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1395 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1396 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1397 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1398 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1399 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1400 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1401 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1402 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1403 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1404 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1405 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1406 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1407 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1408 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1409 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1410 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1411 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1412 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1413 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1414 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1415 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1416 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1417 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1418 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1419 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1420 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1421 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1422 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1423 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1424 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1425 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1426 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1427 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1428 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1429 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1430 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1431 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1432 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1433 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1434 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1435 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1436 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1437 RS6000_BTI_unsigned_V16QI, 0},
1438 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1439 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1440 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1441 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1442 RS6000_BTI_unsigned_V8HI, 0},
1443 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1444 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1445 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1446 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1447 RS6000_BTI_unsigned_V4SI, 0},
1448 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1449 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1450 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1451 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1452 RS6000_BTI_unsigned_V2DI, 0},
1453 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1454 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1455 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1456 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1457 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1458 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1459 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1460 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1461 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1462 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1463 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1464 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1465 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1466 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1467 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1468 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1469 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1470 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1471 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1472 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1473 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1474 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1475 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1476 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1477 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1478 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1479 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1480 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1481 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1482 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1483 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1484 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1485 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1486 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1487 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1488 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1489 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1490 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1491 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1492 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1493 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1494 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1495 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1496 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1497 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1498 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1499 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1500 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1501 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1502 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1503 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1504 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1505 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1506 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1507 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1508 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1509
1510 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1511 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1512 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1513 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1514 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1515 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1516
1517 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1518 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1519 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1520 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1521 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1522 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1523
1524 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1525 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1526 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1527 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1528 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1529 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1530
1531 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1532 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1533 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1534 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1535 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1536 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1537
1538 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1539 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1540 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1541 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1542 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1543 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1544 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1545 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1546 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1547 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1548 RS6000_BTI_unsigned_V2DI, 0 },
1549 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1550 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1551 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1552 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1553 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1554 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1555 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1556 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1557 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1558 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1559 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1560 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1561
1562 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1563 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1564 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1565 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1566 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1567 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1568 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1569 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1570
1571 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1572 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1573 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1574 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1575 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1576 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1577 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1578 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1579 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1580 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1581 ~RS6000_BTI_unsigned_V2DI, 0 },
1582 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1583 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1584 ~RS6000_BTI_unsigned_long_long, 0 },
1585 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1586 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1587 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1588 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1589 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1590 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1591 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1592 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1593 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1594 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1595 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1596 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1597 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1598 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1599 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1600 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1601 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1602 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1603 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1604 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1605 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1606 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1607 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1608 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1609 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1610 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1611 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1612 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1613 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1614 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1615 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1616 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1617 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1618 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1619 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1620 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1621 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1622 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1623 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1624 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1625 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1626 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1627 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1628 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1629 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1630 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1631 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1632 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1633 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1634 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1635 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1636 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1637 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1638 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1639 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1640 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1641 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1642 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1643 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1644 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1645 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1646 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1647 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1648 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1649 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1650 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1651 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1652 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1653 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1654 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1655 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1656 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1657 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1658 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1659 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1660 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1661 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1662 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1663
1664 /* vector float vec_ldl (int, vector float *);
1665 vector float vec_ldl (int, float *); */
1666 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1667 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1668 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1669 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1670
1671 /* vector bool int vec_ldl (int, vector bool int *);
1672 vector bool int vec_ldl (int, bool int *);
1673 vector int vec_ldl (int, vector int *);
1674 vector int vec_ldl (int, int *);
1675 vector unsigned int vec_ldl (int, vector unsigned int *);
1676 vector unsigned int vec_ldl (int, unsigned int *); */
1677 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1678 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1679 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1680 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1681 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1682 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1683 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1684 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1685 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1686 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1687 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1688 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1689
1690 /* vector bool short vec_ldl (int, vector bool short *);
1691 vector bool short vec_ldl (int, bool short *);
1692 vector pixel vec_ldl (int, vector pixel *);
1693 vector short vec_ldl (int, vector short *);
1694 vector short vec_ldl (int, short *);
1695 vector unsigned short vec_ldl (int, vector unsigned short *);
1696 vector unsigned short vec_ldl (int, unsigned short *); */
1697 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1698 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1699 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1700 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1701 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1702 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1703 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1704 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1705 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1706 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1707 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1708 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1709 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1710 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1711
1712 /* vector bool char vec_ldl (int, vector bool char *);
1713 vector bool char vec_ldl (int, bool char *);
1714 vector char vec_ldl (int, vector char *);
1715 vector char vec_ldl (int, char *);
1716 vector unsigned char vec_ldl (int, vector unsigned char *);
1717 vector unsigned char vec_ldl (int, unsigned char *); */
1718 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1719 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1720 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1721 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1722 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1723 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1724 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1725 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1726 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1727 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1728 ~RS6000_BTI_unsigned_V16QI, 0 },
1729 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1730 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1731
1732 /* vector double vec_ldl (int, vector double *);
1733 vector double vec_ldl (int, double *); */
1734 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1735 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1736 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1737 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1738
1739 /* vector long long vec_ldl (int, vector long long *);
1740 vector long long vec_ldl (int, long long *);
1741 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1742 vector unsigned long long vec_ldl (int, unsigned long long *);
1743 vector bool long long vec_ldl (int, vector bool long long *);
1744 vector bool long long vec_ldl (int, bool long long *); */
1745 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1746 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1747 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1748 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1749 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1750 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1751 ~RS6000_BTI_unsigned_V2DI, 0 },
1752 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1753 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1754 ~RS6000_BTI_unsigned_long_long, 0 },
1755 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1756 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1757 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1758 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1759
1760 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1761 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1762 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1763 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1764 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1765 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1766 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1767 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1768 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1769 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1770 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1771 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1772 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1773 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1774 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1776 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1777 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1778 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1779 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1780 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1781 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1782 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1783 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1784 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1785 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1786 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1787 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1788 ~RS6000_BTI_unsigned_long_long, 0 },
1789 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1790 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1791 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1792 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1793 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1794 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1795 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1796 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1797 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1798 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1799 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1800 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1801 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1802 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1803 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1804 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1805 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1806 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1807 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1808 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1809 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1810 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1811 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1812 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1813 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1814 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1815 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1816 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1817 ~RS6000_BTI_unsigned_long_long, 0 },
1818 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1819 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1820 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1821 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1822 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1823 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1824 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1825 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1826 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1827 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1828 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1829 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1830 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1831 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1832 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1833 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1834 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1835 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1836 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1837 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1838 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1839 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1840 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1841 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1842 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1843 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1844 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1845 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1846 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1847 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1848 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1849 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1850 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1851 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1852 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1853 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1854 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1855 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1856 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1857 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1858 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1859 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1860 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1861 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1862 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1863 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1864 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1865 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1866 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1867 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1868 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1869 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1870 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1871 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1872 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1873 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1874 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1875 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1876 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1877 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1878 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1879 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1880 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1881 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1882 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1883 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1884 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1885 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1886 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1887 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1888 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1889 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1890 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1891 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1892 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1893 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1894 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1895 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1896 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1897 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1898 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1899 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1900 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1901 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1902 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1903 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1904 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1905 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1906 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1907 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1908 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1909 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1910 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1911 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1912 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1913 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1914 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1915 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1916 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1917 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1918 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1919 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1920 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1921 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1922 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1923 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1924 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1925 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1926 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1927 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1928 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1929 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1930 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1931 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1932 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1933 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1934 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1935 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1936 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1937 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1938 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1939 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1940 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1941 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1942 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1943 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1944 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1945 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1946 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1947 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1948 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1949 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1950 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1951 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1952 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1953 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1954 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1955 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1956 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1957 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1958 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1959 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1960 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1961 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1962 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1963 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1964 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1965 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1966 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1967 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1968 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1969 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1970 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1971 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1972 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1973 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1974 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1975 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1976 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1977 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1978 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1979 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1980 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1981 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1982 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1983 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1984 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1985 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1986 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1987 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1988 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1989 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1990 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1991 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1992 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1993 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1994 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1995 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1996 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1997 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1998 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1999 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2000 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
2001 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2002 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
2003 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2004 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
2005 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2006 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
2007 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2008 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
2009 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2010 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
2011 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2012 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
2013 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2014 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
2015 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2016 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
2017 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2018 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
2019 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2020 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
2021 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2022 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2023 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2024 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2025 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2026 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2027 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2028 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2029 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2030 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
2031 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2032 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
2033 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2034 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
2035 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2036 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
2037 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2038 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2039 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2040 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2041 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2042 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2043 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2044 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2045 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2046 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
2047 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2048 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2049 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2050 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2051 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2052 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
2053 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2054 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2055 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2056 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2057 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2058 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2059 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2060 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2061 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2062 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
2063 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2064 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2065 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2066 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2067 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2068 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
2069 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2070 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2071 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2072 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2073 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2074 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2075 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2076 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
2077 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2078 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2079 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2080 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2081 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2082 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2083 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2084 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
2085 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2086 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
2087 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2088 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2089 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2090 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2091 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2092 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2093 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2094 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2095 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2096 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2097 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2098 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2099 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2100 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2101 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2102 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2103 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2104 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2105 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2106 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2107 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2108 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2109 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2110 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2111 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2112 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2113 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2114 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2115 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2116 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2117 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2118 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2119 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2120 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2121 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2122 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2123 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2124 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2125 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2126 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2127 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2128 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2129 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2130 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2131 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2132 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2133 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2134 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2135 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2136 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2137 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2138 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2139 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2140 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2141 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2142 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2143 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2144 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2145 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2146 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2147 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2148 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2149 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2150 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2151 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2152 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2153 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2154 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2155 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2156 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2157 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2158 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2159 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2160 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2161 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2162 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2163 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2164 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2165 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2166 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2168 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2169 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2170 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2171 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2172 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2173 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2174 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2175 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2176 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2177 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2178 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2179 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2180 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2181 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2182 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2183 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2184 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2185 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2186 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2187 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2188 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2189 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2190 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2191 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2192 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2193 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2194 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2195 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2196 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2197 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2198 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2199 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2200 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2201 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2202 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2203 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2204 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2205 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2206 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2207 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2208 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2209 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2210 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2211 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2212 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2213 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2214 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2215 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2216 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2217 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2218 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2219 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2220 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2221 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2222 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2223 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2224 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2225 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2226 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2227 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2228 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2229 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2230 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2231 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2232 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2233 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2234 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2235 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2236 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2237 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2238 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2239 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2240 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2241 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2242 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2243 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2244 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2246 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2247 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2248 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2249 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2250 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2251 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2252 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2253 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2254 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2255 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2256 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2257 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2258 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2259 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2260 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2261 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2262 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2263 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2264 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2265 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2266 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2267 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2268 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2269 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2270 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2271 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2272 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2273 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2274 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2275 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2276 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2277 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2278 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2279 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2280 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2281 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2282 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2283 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2284 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2285 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2286 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2287 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2288 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2289 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2290 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2291 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2292 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2293 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2294 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
2295 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2296 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
2297 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2298 RS6000_BTI_unsigned_V4SI, 0 },
2299 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2300 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2301 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2302 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2303 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2304 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2305 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2306 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2307 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
2308 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2309 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
2310 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2311 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2312 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2313 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2314 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2315 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2316 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2317 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
2318 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2319 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
2320 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2321 RS6000_BTI_unsigned_V4SI, 0 },
2322 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2323 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2324 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2325 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2326 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2327 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2328 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2329 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2330 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2331 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2332 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
2333 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2334 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
2335 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2336
2337 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2338 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2339 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2340 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2341 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2342 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2343 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2344 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2345 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2346 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2347 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2348 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2349 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2350 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2351 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2352 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2353
2354 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2355 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2356 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2357 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2358 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2359 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2360 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2361 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2362 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2363 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2364 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2365 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2366 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2367 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2368 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2369 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2370 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2371 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2372 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2373 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2374 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2375 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2376 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2377 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2378 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2379 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2380 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2381 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2382 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2383 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2384 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2385 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2386 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2387 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2388 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2389 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2390 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2391 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2392 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2393 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2394 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2395 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2396 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2397 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2398 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2399 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2400 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2401 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2402 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2403 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2404 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2405 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2406 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2407 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2408 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2409 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2410 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2411 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2412 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2413 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2414 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2415 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2416 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2417 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2418 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2419 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2420 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2421 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2422 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2423 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2424 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2425 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2426 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2427 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2428 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2429 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2430 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2431 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2432 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2433 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2434 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2435 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2436 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2437 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2438 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2439 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2440 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2441 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2442 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2443 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2444 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2445 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2446 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2447 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2448 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2449 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2450 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2451 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2452 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2453 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2454 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2456 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2457 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2458 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2459 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2460 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2461 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2462 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2463 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2464 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2465 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2466 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2467 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2468 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2469 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2470 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2471 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2472 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2473 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2474 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2475 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2476 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
2477 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2478
2479 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
2480 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2481 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
2482 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2483 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
2484 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2485 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
2486 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2487 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
2488 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2489 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
2490 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2491
2492 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2493 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2494
2495 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2496 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2497 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2498 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2499 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2500 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2501 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2502 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2503 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2504 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2505 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2506 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2507 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2508 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2509 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2510 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2511 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2512 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2513 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2514 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2515 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2516 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2517 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2518 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2519 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2520 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2521 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2522 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2523 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2524 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2525 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2526 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2527 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2528 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2529 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2530 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2531
2532 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2533 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2534 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2535 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2536 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2537 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2538 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2539 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2540 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2541 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2542 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2543 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2544 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2545 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2546 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2547 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2548 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2549 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2550
2551 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2552 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2553 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2554 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2555 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2556 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2557 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2558 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2559 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2560 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2561 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2562 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2563 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2564 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2565 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2566 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2567 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2568 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2569 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2570 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2571 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2572 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2573 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2574 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2575 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2576 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2577 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2578 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2579 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2580 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2581 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2582 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2583 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2584 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2586 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2587 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2588 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2589 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2590 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2591 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2592 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2594 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2595 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
2596 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2597 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2598 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2599 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2600 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2601 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2602 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2603 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2604 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2605 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2606 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2607 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2608 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2609 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2610 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2611 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2612 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2614 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2615 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2616 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2617 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2618 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2619 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2620 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2621 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2622 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2623 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2624 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2625 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2626 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2627 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2628 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2629 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2630 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2631 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2632 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2633 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2634 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2635 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2636 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2637 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2638 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2639 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2640 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2641 RS6000_BTI_unsigned_V4SI, 0 },
2642 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2643 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2644 RS6000_BTI_unsigned_V2DI, 0 },
2645 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2646 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2647 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2648 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2649 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2650 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2651 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2652 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2653 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2654 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2655 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2656 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2657 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2658 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2659 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2660 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2661 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2662 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2663 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2664 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2665 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2666 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2667 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2668 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2669 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2670 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2671 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2672 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2673 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2674 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2675 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2676 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2677 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2678 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2679 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2680 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2681 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2682 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2683 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2684 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2685 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2686 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2687 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2688 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2689 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2690 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2691 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2692 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2693 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2694 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2695 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2696 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2697 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2698 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2699 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2700 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2701 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2702 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2703 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2704 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2705 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2706 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2707 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2708 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2709 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2710 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2711 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2712 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2713 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2714 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2715 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2716 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2717 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2718 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2719 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2720 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2721 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2722 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2723 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2724 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2725 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2726 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2727 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2728 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2729 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2730 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2731 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2732 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2733 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2734 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2735 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2736 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2737
2738 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2739 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2740 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2741 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2742 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2743 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2744 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2745 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2746 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2747 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2748
2749 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2750 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2751 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2752 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2753 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2754 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2755 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2756 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2757 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2758 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2759 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2760 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2761 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2762 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2763 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2764 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2765 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2766 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2767 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2768 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2769 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2770 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2771 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2772 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2773 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2774 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2775 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2776 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2777 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2778 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2779 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2780 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2781 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2782 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2783 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2784 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2785 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2786 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2787 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2788 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2789 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2790 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2791 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2792 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2793 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2794 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2795 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2796 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2797 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2798 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2799 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2800 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2801 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2802 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2803 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2804 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2805 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2806 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2807 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2808 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2809 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2810 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2811 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2812 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2813 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2814 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2815 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2816 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2817 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2818 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2819 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2820 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2821 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2822 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2823 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2824 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2825 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2826 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2827 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2828 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2829 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2830 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2831 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2832 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2833 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2834 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2835 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2836 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2837 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2838 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2839 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2840 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2841 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2842 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2843 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2844 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2845 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2846 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2847 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2848 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2849 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2850 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2851 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2852 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2853 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2854 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2855 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2856 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2857 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2858 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2859 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2860 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2861 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2862 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2863 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2864 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2865 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2866 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2867 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2868 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2869 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2870 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2871 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2872 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2873 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2874 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2875 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2876 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2877 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2878 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2879 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2880 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2881 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2882 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2883 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2884 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2885 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2886 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2887 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2888 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2889 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2890 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2891 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2892 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2893 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2894 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2895 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2896 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2897 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2898 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2899 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2900 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2901 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2902 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2903 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2904 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2905 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2906 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2907 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2908 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2909 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2910 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2911 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2912 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2913 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2914 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2915 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2916 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2917 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2918 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2919 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2920 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2921 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2922 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2923 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2924 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2925 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2926 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2927 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2928 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2929 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2930 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2931 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2932 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2933 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2934 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2935 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2936 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2937 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2938 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2939 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2940 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2941 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2942 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2943 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2944 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2945 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2946 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2947 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2948 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2949 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2950 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2951 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2952 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2953 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2954 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2955 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2956 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2957 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2958 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2959 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2960 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2961 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2962 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2963 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2964 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2965 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2966 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2967 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2968 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2969 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2970 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2971 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2972 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2973 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2974 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2975 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2976 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2977 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2978 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2979 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2980 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2981 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2982 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2983 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2984 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2985 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2986 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2987 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2988 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2989 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2990 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2991 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2992 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2993 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2994 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2995 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2996 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2997 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2998 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2999 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
3000 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
3001
3002 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3003 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3004 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3005 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3006 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3007 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3008 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3009 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3010 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3011 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3012 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
3013 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3014 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3015 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3016 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3017 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3018 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3019 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3020 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3021 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3022 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3023 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3024 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
3025 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3026 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3027 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3028 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3029 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3030 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3031 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3032 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3033 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3034 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3035 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3036 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
3037 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3038 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3039 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3040 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3041 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3042 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3043 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3044 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3045 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3046 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3047 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3048 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
3049 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3050 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
3051 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3052 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
3053 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3054 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
3055 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
3056 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
3057 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
3058 RS6000_BTI_unsigned_V1TI, 0 },
3059 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
3060 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3061 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3062 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3063 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3064 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3065 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3066 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3067 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3068 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3069 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3070 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3071 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3072 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3073 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3074 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
3075 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
3076 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3077 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3078 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3079 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3080 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3081 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3082 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3083 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3084 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3085 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3086 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3087 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3088 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3089 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3090 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3091 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
3092 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3093 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3094 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3095 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3096 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3097 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3098 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3099 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3100 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3101 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3102 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3103 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3104 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3105 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3106 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3107 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
3108 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3109
3110 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
3111 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3112 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
3113 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3114 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
3115 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
3116 RS6000_BTI_unsigned_V1TI, 0 },
3117 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
3118 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
3119
3120 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3121 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3122 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3123 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3124 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
3125 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3126 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3127 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3128 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3129 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3130 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
3131 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3132 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3133 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3134 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3135 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3136 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
3137 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3138 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3139 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3140 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3141 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3142 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
3143 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3144 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3145 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3146 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3147 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3148 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
3149 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3150 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3151 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3152 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3153 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3154 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
3155 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3156 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3157 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3158 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3159 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3160 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
3161 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3162 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3163 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3164 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3165 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
3166 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3168 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3169 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3170 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
3171 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3172 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3173 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3174 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3175 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3176 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3177 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3178 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3179 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3180 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3181 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3182 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3183 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3184 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3185 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3186 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3187 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3188 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3189 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3190 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3191 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3192 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3193 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3194 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3195 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3196 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3197 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3198 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3199 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3200 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3201 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3202 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3203 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3204 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
3205 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3206 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
3207 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3208 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
3209 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3210 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
3211 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3212 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
3213 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3214 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
3215 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3216 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3217 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3218 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3219 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3220
3221 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
3222 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3223 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
3224 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3225 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3226 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3227 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3228 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
3229 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
3230 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3231 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3232 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3233 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3234 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3235 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3236 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
3237 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3238 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3239 ~RS6000_BTI_unsigned_V2DI, 0 },
3240 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3241 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3242 ~RS6000_BTI_unsigned_long_long, 0 },
3243 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3244 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
3245
3246 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3247 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3248 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3249 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3250 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3251 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3252 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3253 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3254 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3255 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3256 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3257 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3258 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3259 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3260 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3261 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3262 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3263 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3264 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3265 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3266 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3267 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3268 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3269 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3270 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3271 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3272 ~RS6000_BTI_unsigned_V16QI, 0 },
3273 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3274 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3275
3276 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3277 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3278 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3279 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3280 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3281 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3282 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3283 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3284 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3285 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3286 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3287 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3288 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3289 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3290 ~RS6000_BTI_unsigned_V2DI, 0 },
3291 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3292 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3293 ~RS6000_BTI_unsigned_long_long, 0 },
3294 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3295 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3296 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3297 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3298 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3299 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3300 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3301 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3302 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3303 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3304 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3305 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3306 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3307 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3308 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3309 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3310 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3311 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3312 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3313 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3314 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3315 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3316 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3317 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3318 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3319 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3320 ~RS6000_BTI_unsigned_V16QI, 0 },
3321 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3322 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3323 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3324 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3325 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3326 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3327 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3328 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
3329 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3330 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3331 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3332 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3333 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3334 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3335 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3336 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3337 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3338 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3339 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3340 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3341 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3342 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3343 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3344 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3345 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3346 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3347 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3348 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3349 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3350 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3351 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3352 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3353 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3354 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3355 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3356 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3357 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3358 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3359 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3360 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3361 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3362 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3363 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3364 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3365 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3366 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3367 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3368 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3369 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3370 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3371 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3372 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3373 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3374 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3375 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3376 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3377 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3378 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3379 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3380 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3381 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3382 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3383 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3384 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3385 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3386 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3387 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3388 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3389 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3390 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3391
3392 /* Ternary AltiVec/VSX builtins. */
3393 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3394 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3395 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3396 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3397 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3398 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3399 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3400 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3401 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3402 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3403 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3404 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3405 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3406 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3407 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3408 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3409 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3410 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3411 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3412 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3413 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3414 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3415 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3416 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3417 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3418 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3419 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3420 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3421 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3422 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3423 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3424 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3425 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3426 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3427 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3428 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3429 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3430 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3431 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3432 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3433 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3434 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3435 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3436 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3437 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3438 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3439 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3440 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3441 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3442 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3443 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3444 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3445 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3446 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3447 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3448 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3449 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3450 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3451 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3452 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3453 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3454 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3455 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3456 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3457 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3458 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3459 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3460 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3461 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3462 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3463 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3464 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3465 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3466 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3467 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3468 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3469 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3470 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3471 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3472 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3473 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3474 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3475 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3476 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3477 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3478 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3479 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3480 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3481 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3482 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3483 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3484 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3485 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3486 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3487 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3488 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3489 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3490 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3491 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3492 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3493 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3494 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3495 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3496 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3497 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3498 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3499 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3500 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3501 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3502 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3503 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3504 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3505 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3506 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3507 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3508 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3509 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3510 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3511 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3512 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3513 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3514 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3515 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3516 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3517 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3518 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3519 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3520 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3521 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3522 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3523 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3524 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3525 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3526 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3527 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3528 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3529 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3530 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3531 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3532 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3533 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3534 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3535 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3536 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3537 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3538 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3539 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3540 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3541 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3542 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3543 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3544 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3545 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3546 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3547 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3548 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3549 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3550 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3551 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3552 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3553 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3554 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3555 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3556 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3557 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3558 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3559 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3560 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3561 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3562 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3563 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3564 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3565 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3566 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3567 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3568 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3569 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3570 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3571 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3572 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3573 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3574 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3575 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3576 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3577 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3578 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3579 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3580 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3581 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3582 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3583 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3584 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3585 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3586 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3587 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3588 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3589 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3590 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3591 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3592 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3593 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3594 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3595 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3596 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3597 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3598 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3599 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3600 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3601 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3602 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3603 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3604 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3605 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3606 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3607 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3608 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3609 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3610 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3611 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3612 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3613 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3614 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3615 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3616 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3617 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3618 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3619 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3620 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3621 RS6000_BTI_unsigned_V16QI },
3622 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3623 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3624 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3625 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3626 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3627 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3628 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3629 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3630 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3631 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3632 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3634 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3635 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3636 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3637 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3638 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3639 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3640 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3641 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3642 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3643 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3644 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3645 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3646 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3647 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3648
3649 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3650 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3651 RS6000_BTI_bool_V16QI },
3652 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3653 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3654 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3655 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3656 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3657
3658 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3659 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3660 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3661 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3662 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3663 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3664 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3665 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3666 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3667 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3668 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3669 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3670 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3671 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3672 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3673 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3674 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3675 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3676 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3677 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3678 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3679 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3680 RS6000_BTI_bool_V2DI },
3681 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3682 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3683 RS6000_BTI_unsigned_V2DI },
3684 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3685 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3686 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3687 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3688 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3689 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3690 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3691 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3692 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3693 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3694 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3695 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3696 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3697 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3698 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3699 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3700 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3701 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3702 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3703 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3704 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3705 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3706 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3707 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3708 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3709 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3710 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3711 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3712 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3713 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3714 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3715 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3716 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3717 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3718 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3719 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3720 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3721 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3722 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3723 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3724 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3725 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3726 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3727 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3728 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3729 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3730 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3731 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3732 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3733 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3734 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3735 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3736 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3737 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3738 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3739 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3740 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3741 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3742 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3743 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3744 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3745 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3746 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3747 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3748 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3749 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3750 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3751 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3752 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3753 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3754 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3755 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3756 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3757 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3758
3759 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3760 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3761 RS6000_BTI_INTSI },
3762 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3763 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3764 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3765 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3766 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3767 RS6000_BTI_INTSI },
3768 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3769 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3770 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3771 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3772 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3773 RS6000_BTI_INTSI },
3774 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3775 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3776 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3777 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3778 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3779 RS6000_BTI_INTSI },
3780 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3781 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3782 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3783
3784 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3785 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3786 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3787 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3788 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3789 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3790 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3791 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3792 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3793 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3794 ~RS6000_BTI_unsigned_V2DI },
3795 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3796 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3797 ~RS6000_BTI_unsigned_long_long },
3798 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3799 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3800 ~RS6000_BTI_bool_V2DI },
3801 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3802 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3803 ~RS6000_BTI_long_long },
3804 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3805 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3806 ~RS6000_BTI_unsigned_long_long },
3807 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3808 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3809 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3810 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3811 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3812 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3813 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3814 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3815 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3816 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3817 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3818 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3819 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3820 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3821 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3822 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3823 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3824 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3825 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3826 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3827 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3828 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3829 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3830 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3831 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3832 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3833 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3834 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3835 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3836 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3837 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3838 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3839 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3840 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3841 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3842 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3843 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3844 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3845 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3846 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3847 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3848 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3849 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3850 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3851 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3852 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3853 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3854 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3855 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3856 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3857 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3858 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3859 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3860 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3861 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3862 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3863 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3864 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3865 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3866 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3867 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3868 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3869 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3870 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3871 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3872 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3873 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3874 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3875 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3876 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3877 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3878 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3879 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3880 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3881 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3882 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3883 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3884 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3885 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3886 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3887 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3888 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3889 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3890 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3891 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3892 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3893 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3894 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3895 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3896 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3897 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3898 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3899 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3900 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3901 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3902 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3903 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3904 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3905 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3906 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3907 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3908 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3909 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3910 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3911 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3912 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3913 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3914 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3915 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3916 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3917 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3918 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3919 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3920 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3921 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3922 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3923 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3924 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3925 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3926 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3927 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3928 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3929 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3930 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3931 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3932 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3933 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3934 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3935 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3936 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3937 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3938 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3939 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3940 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3941 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3942 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3943 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3944 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3945 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3946 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3947 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3948 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3949 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3950 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3951 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3952 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3953 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3954 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3955 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3956 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3957 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3958 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3959 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3960 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3961 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3962 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3963 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3964 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3965 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3966 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3967 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3968 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3969 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3970 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3971 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3972 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3973 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3974 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3975 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3976 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3977 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3978 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3979 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3980 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3981 ~RS6000_BTI_unsigned_V2DI },
3982 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3983 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3984 ~RS6000_BTI_bool_V2DI },
3985 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3986 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3987 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3988 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3989 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3990 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3991 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3992 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3993 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3994 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3995 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3996 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3997 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3998 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3999 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4000 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4001 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4002 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4003 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4004 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4005 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4006 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4007 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4008 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4009 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4010 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4011 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4012 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4013 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4014 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4015 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4016 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4017 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4018 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4019 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
4020 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4021 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4022 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4023 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4024 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4025 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4026 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4027 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4028 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4029 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4030 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4031 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4032 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4033 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4034 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4035 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4036 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4037 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4038 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4039 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4040 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4041 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4042 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4043 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4044 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4045 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4046 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4047 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4048 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4049 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4050 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4051 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4052 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4053 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4054 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4055 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
4056 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4057 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4058 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4059 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4060 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4061 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4062 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4063 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4064 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4065 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4066 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4067 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4068 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4069 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4070 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4071 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4072 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4073 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4074 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4075 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4076 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4077 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4078 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4079 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4080 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4081 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4082 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4083 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4084 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4085 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4086 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4087 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4088 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4089 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4090 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4091 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
4092 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4093 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4094 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4095 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4096 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4097 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4098 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4099 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4100 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4101 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4102 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4103 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4104 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4105 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4106 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4107 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4108 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4109 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4110 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4111 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4112 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4113 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4114 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4115 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4116 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4117 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4118 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4119 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4120 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4121 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4122 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4123 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4124 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4125 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4126 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4127 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
4128 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4129 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
4130 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4131 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4132 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4133 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4134 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4135 ~RS6000_BTI_unsigned_V2DI },
4136 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
4137 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4138 ~RS6000_BTI_bool_V2DI },
4139 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4140 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4141 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
4142 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4143 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4144 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4145 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4146 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4147 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4148 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
4149 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4150 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4151 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4152 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
4153 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4154 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
4155 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
4156 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4157 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4158 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4159 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4160 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4161 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4162 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
4163 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4164 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4165 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4166 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
4167 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4168 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
4169 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4170 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4171 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4172 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4173 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4174 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4175 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4176 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
4177 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4178 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4179 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4180 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
4181 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4182 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
4183 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
4184 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4185 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
4186 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
4187 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
4188 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4189 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
4190 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4191 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4192 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
4193 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
4194 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
4195 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4196 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4197 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4198 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
4199 ~RS6000_BTI_long_long },
4200 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4201 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4202 ~RS6000_BTI_unsigned_V2DI },
4203 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
4204 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4205 ~RS6000_BTI_unsigned_long_long },
4206 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
4207 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4208 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
4209 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4210 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4211 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4212 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4213 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4214 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4215 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4216 ~RS6000_BTI_unsigned_V4SI },
4217 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4218 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4219 ~RS6000_BTI_UINTSI },
4220 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4221 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4222 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4223 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4224 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4225 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4226 ~RS6000_BTI_unsigned_V8HI },
4227 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4228 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4229 ~RS6000_BTI_UINTHI },
4230 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4231 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4232 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4233 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4234 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4235 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4236 ~RS6000_BTI_unsigned_V16QI },
4237 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4238 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4239 ~RS6000_BTI_UINTQI },
4240 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4241 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
4242 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4243 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4244 RS6000_BTI_INTSI },
4245 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4246 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
4247 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4248 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4249 RS6000_BTI_INTSI },
4250 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4251 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
4252 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4253 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4254 RS6000_BTI_INTSI },
4255 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4256 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
4257 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4258 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4259 RS6000_BTI_INTSI },
4260 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
4261 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
4262 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
4263 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4264
4265 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
4266 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4267 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4268 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
4269 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4270 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4271 RS6000_BTI_INTSI },
4272 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
4273 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
4274 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4275 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
4276 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4277 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4278 RS6000_BTI_INTSI },
4279 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4280 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
4281 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4282 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4283 RS6000_BTI_INTSI },
4284 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4285 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
4286 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4287 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4288 RS6000_BTI_INTSI },
4289
4290 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4291 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
4292 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4293 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
4294 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4295 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
4296 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4297 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
4298 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4299 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
4300 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4301 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
4302 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4303 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
4304 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4305 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4306 ~RS6000_BTI_unsigned_V2DI, 0 },
4307 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4308 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
4309 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4310 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
4311 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4312 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
4313 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4314 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
4315 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4316 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
4317 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4318 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
4319 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4320 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
4321 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4322 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
4323 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4324 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4325 ~RS6000_BTI_unsigned_V4SI, 0 },
4326 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4327 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
4328 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4329 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4330 ~RS6000_BTI_unsigned_long, 0 },
4331 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4332 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
4333 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4334 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
4335 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4336 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
4337 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4338 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
4339 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4340 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4341 ~RS6000_BTI_unsigned_V8HI, 0 },
4342 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4343 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
4344 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4345 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
4346 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4347 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
4348 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4349 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
4350 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4351 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4352 ~RS6000_BTI_unsigned_V16QI, 0 },
4353 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4354 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4355
4356 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4357 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4358 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4359 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4360 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4361 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
4362 ~RS6000_BTI_long_long },
4363 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4364 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
4365 ~RS6000_BTI_unsigned_long_long },
4366 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4367 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
4368 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4369 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
4370 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4371 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4372 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4373 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4374 ~RS6000_BTI_unsigned_V2DI },
4375 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4376 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4377 ~RS6000_BTI_bool_V2DI },
4378 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4379 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4380 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4381 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4382 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4383 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4384 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4385 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4386 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4387 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4388 ~RS6000_BTI_unsigned_V4SI },
4389 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4390 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4391 ~RS6000_BTI_UINTSI },
4392 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4393 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4394 ~RS6000_BTI_bool_V4SI },
4395 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4396 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4397 ~RS6000_BTI_UINTSI },
4398 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4399 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4400 ~RS6000_BTI_INTSI },
4401 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4402 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4403 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4404 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4405 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4406 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4407 ~RS6000_BTI_unsigned_V8HI },
4408 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4409 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4410 ~RS6000_BTI_UINTHI },
4411 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4412 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4413 ~RS6000_BTI_bool_V8HI },
4414 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4415 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4416 ~RS6000_BTI_UINTHI },
4417 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4418 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4419 ~RS6000_BTI_INTHI },
4420 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4421 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4422 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4423 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4424 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4425 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4426 ~RS6000_BTI_unsigned_V16QI },
4427 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4428 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4429 ~RS6000_BTI_UINTQI },
4430 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4431 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4432 ~RS6000_BTI_bool_V16QI },
4433 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4434 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4435 ~RS6000_BTI_UINTQI },
4436 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4437 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4438 ~RS6000_BTI_INTQI },
4439 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4440 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4441 ~RS6000_BTI_pixel_V8HI },
4442
4443 /* Predicates. */
4444 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4445 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4446 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4447 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4448 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4449 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4450 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4451 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4452 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4453 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4454 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4455 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4456 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4457 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4458 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4459 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4460 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4461 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4462 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4463 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4464 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4465 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4466 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4467 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4468 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4469 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4470 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4471 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4472 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4473 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4474 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4475 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4476 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4477 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4478 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4479 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4480 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4481 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4482 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4483 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4484 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4485 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4486 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4487 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4488 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4489 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4490 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4491 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4492 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4493 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4494 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4495 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4496
4497
4498 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4499 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4500 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4501 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4502 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4503 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4504 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4505 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4506 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4507 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4508 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4509 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4510 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4511 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4512 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4513 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4514 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4515 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4516 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4517 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4518 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4519 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4520 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4521 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4522 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4523 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4524 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4525 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4526 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4527 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4528 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4529 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4530 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4531 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4532 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4533 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4534 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4535 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4536 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4537 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4538 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4539 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4540 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4541 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4542 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4543 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4544 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4545 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4546 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4547 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4548 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4549 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4550 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4551 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4552 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4553 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4554 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4555 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4556 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4557 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4558 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4559 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4560
4561
4562 /* cmpge is the same as cmpgt for all cases except floating point.
4563 There is further code to deal with this special case in
4564 altivec_build_resolved_builtin. */
4565 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4566 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4567 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4568 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4569 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4570 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4571 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4572 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4573 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4574 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4575 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4576 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4577 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4578 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4579 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4580 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4581 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4582 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4583 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4584 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4585 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4586 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4587 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4588 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4589 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4590 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4591 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4592 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4593 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4594 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4595 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4596 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4597 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4598 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4599 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4600 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4601 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4602 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4603 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4604 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4605 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4606 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4607 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4608 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4609 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4610 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4611 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4612 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4613 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4614 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4615 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4616 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4617
4618 /* Power8 vector overloaded functions. */
4619 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4620 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4621 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4622 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4623 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4624 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4625 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4626 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4627 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4628 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4629 RS6000_BTI_unsigned_V16QI, 0 },
4630 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4631 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4632 RS6000_BTI_bool_V16QI, 0 },
4633 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4634 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4635 RS6000_BTI_unsigned_V16QI, 0 },
4636 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4637 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4638 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4639 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4640 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4641 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4642 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4643 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4644 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4645 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4646 RS6000_BTI_unsigned_V8HI, 0 },
4647 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4648 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4649 RS6000_BTI_bool_V8HI, 0 },
4650 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4651 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4652 RS6000_BTI_unsigned_V8HI, 0 },
4653 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4654 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4655 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4656 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4657 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4658 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4659 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4660 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4661 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4662 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4663 RS6000_BTI_unsigned_V4SI, 0 },
4664 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4665 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4666 RS6000_BTI_bool_V4SI, 0 },
4667 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4668 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4669 RS6000_BTI_unsigned_V4SI, 0 },
4670 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4671 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4672 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4673 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4674 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4675 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4676 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4677 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4678 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4679 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4680 RS6000_BTI_unsigned_V2DI, 0 },
4681 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4682 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4683 RS6000_BTI_bool_V2DI, 0 },
4684 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4685 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4686 RS6000_BTI_unsigned_V2DI, 0 },
4687 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4688 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4689 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4690 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4691
4692 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4693 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4694 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4695 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4696 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4697 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4698 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4700 RS6000_BTI_unsigned_V16QI, 0 },
4701 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4702 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4703 RS6000_BTI_bool_V16QI, 0 },
4704 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4705 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4706 RS6000_BTI_unsigned_V16QI, 0 },
4707 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4708 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4709 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4710 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4711 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4712 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4713 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4714 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4715 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4716 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4717 RS6000_BTI_unsigned_V8HI, 0 },
4718 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4719 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4720 RS6000_BTI_bool_V8HI, 0 },
4721 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4722 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4723 RS6000_BTI_unsigned_V8HI, 0 },
4724 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4725 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4726 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4727 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4728 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4729 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4730 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4731 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4732 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4733 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4734 RS6000_BTI_unsigned_V4SI, 0 },
4735 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4736 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4737 RS6000_BTI_bool_V4SI, 0 },
4738 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4739 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4740 RS6000_BTI_unsigned_V4SI, 0 },
4741 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4742 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4743 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4744 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4745 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4746 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4747 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4748 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4749 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4750 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4751 RS6000_BTI_unsigned_V2DI, 0 },
4752 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4753 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4754 RS6000_BTI_bool_V2DI, 0 },
4755 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4756 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4757 RS6000_BTI_unsigned_V2DI, 0 },
4758 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4759 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4760 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4761 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4762 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4763 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4764
4765 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4766 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4767 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4768 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4769 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4770 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4771 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4772 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4773 RS6000_BTI_unsigned_V16QI, 0 },
4774 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4776 RS6000_BTI_bool_V16QI, 0 },
4777 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4778 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4779 RS6000_BTI_unsigned_V16QI, 0 },
4780 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4781 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4782 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4783 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4784 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4785 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4786 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4787 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4788 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4789 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4790 RS6000_BTI_unsigned_V8HI, 0 },
4791 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4792 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4793 RS6000_BTI_bool_V8HI, 0 },
4794 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4795 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4796 RS6000_BTI_unsigned_V8HI, 0 },
4797 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4798 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4799 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4800 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4801 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4802 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4803 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4804 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4805 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4806 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4807 RS6000_BTI_unsigned_V4SI, 0 },
4808 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4809 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4810 RS6000_BTI_bool_V4SI, 0 },
4811 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4812 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4813 RS6000_BTI_unsigned_V4SI, 0 },
4814 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4815 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4816 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4817 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4818 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4819 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4820 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4821 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4822 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4823 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4824 RS6000_BTI_unsigned_V2DI, 0 },
4825 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4826 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4827 RS6000_BTI_bool_V2DI, 0 },
4828 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4829 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4830 RS6000_BTI_unsigned_V2DI, 0 },
4831 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4832 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4833 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4834 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4835 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4836 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4837
4838 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4839 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4840 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4841 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4842 RS6000_BTI_unsigned_V1TI, 0 },
4843
4844 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4845 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4846 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4847 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4848 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4849 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4850 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4851 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4852 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4853 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4854 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4855 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4856
4857 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4858 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4859 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4860 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4861 RS6000_BTI_unsigned_V1TI, 0 },
4862
4863 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4864 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4865 RS6000_BTI_unsigned_V16QI, 0 },
4866 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4867 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4868 RS6000_BTI_unsigned_V16QI, 0 },
4869 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4870 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4871 RS6000_BTI_unsigned_V16QI, 0 },
4872
4873 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4874 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4875 RS6000_BTI_unsigned_V16QI, 0 },
4876 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4877 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4878 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4879 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4880 RS6000_BTI_unsigned_V16QI, 0 },
4881 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4882 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4883 RS6000_BTI_unsigned_V16QI, 0 },
4884
4885 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4886 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4887 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4888 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4889 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4890 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4891 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4892 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4893 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4894 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4895 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4896 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4897 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4898 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4899 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4900 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4901
4902 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4903 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4904 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4905 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4906
4907 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4908 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4909 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4910 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4911
4912 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4913 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4914 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4915 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4916
4917 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4918 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4919 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4920 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4921
4922 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4923 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4924 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4925 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4926
4927 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4928 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4929 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4930 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4931
4932 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4933 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4934 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4935 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4936
4937 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4938 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4939 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4940 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4941
4942 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4943 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4944 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4945 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4946
4947 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4948 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4949 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4950 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4951
4952 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4953 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4954 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4955 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4956
4957 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4958 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4959 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4960 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4961
4962 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4963 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4964 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4965 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4966 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4967 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4968 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4969 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4970 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4971 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4972 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4973 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4974 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4975 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4976 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4977 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4978
4979 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4980 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4981 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4982 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4983
4984 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4985 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4986 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4987 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4988
4989 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4990 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4991 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4992 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4993
4994 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4995 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4996 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4997 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4998
4999 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
5000 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5001 RS6000_BTI_unsigned_V16QI, 0 },
5002 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
5003 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5004 RS6000_BTI_unsigned_V8HI, 0 },
5005 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
5006 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5007 RS6000_BTI_unsigned_V4SI, 0 },
5008
5009 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
5010 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5011 RS6000_BTI_unsigned_V16QI, 0 },
5012
5013 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
5014 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5015 RS6000_BTI_unsigned_V8HI, 0 },
5016
5017 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
5018 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5019 RS6000_BTI_unsigned_V4SI, 0 },
5020
5021 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
5022 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5023 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
5024 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5025
5026 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
5027 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5028 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
5029 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5030
5031 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
5032 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5033 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
5034 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5035
5036 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
5037 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5038 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
5039 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5040
5041 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
5042 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
5043 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
5044 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
5045
5046 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
5047 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
5048 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
5049 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
5050
5051 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
5052 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
5053 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
5054 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
5055
5056 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
5057 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5058 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
5059 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
5060
5061 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
5062 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
5063 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
5064 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
5065
5066 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
5067 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5068 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
5069 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
5070
5071 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
5072 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
5073 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
5074 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
5075 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
5076 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
5077
5078 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
5079 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
5080 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
5081 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
5082 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
5083 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
5084
5085 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
5086 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
5087 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
5088 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
5089 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
5090 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
5091
5092 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
5093 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
5094 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
5095 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
5096 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
5097 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
5098
5099 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
5100 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
5101 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
5102 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
5103
5104 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
5105 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
5106 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
5107 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
5108
5109 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
5110 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5111 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
5112 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
5113
5114 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
5115 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
5116 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
5117 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
5118
5119 { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
5120 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5121 { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
5122 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5123 { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
5124 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5125 { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
5126 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
5127
5128 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
5129 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5130 RS6000_BTI_unsigned_long_long, 0 },
5131
5132 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5133 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
5134 RS6000_BTI_unsigned_long_long, 0 },
5135 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5136 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5137 RS6000_BTI_unsigned_long_long, 0 },
5138
5139 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5140 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
5141 RS6000_BTI_unsigned_long_long, 0 },
5142 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5143 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
5144 RS6000_BTI_unsigned_long_long, 0 },
5145
5146 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5147 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
5148 RS6000_BTI_unsigned_long_long, 0 },
5149 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5150 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5151 RS6000_BTI_unsigned_long_long, 0 },
5152
5153 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5154 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5155 RS6000_BTI_unsigned_long_long, 0 },
5156 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5157 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5158 RS6000_BTI_unsigned_long_long, 0 },
5159
5160 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5161 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5162 RS6000_BTI_unsigned_long_long, 0 },
5163 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5164 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5165 RS6000_BTI_unsigned_long_long, 0 },
5166
5167 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5168 RS6000_BTI_V2DF, ~RS6000_BTI_double,
5169 RS6000_BTI_unsigned_long_long, 0 },
5170 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
5171 RS6000_BTI_V4SF, ~RS6000_BTI_float,
5172 RS6000_BTI_unsigned_long_long, 0 },
5173 /* At an appropriate future time, add support for the
5174 RS6000_BTI_Float16 (exact name to be determined) type here. */
5175
5176 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
5177 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
5178 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
5179
5180 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5181 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
5182 RS6000_BTI_unsigned_long_long },
5183 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5184 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
5185 RS6000_BTI_unsigned_long_long },
5186
5187 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5188 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
5189 RS6000_BTI_unsigned_long_long },
5190 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5191 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
5192 RS6000_BTI_unsigned_long_long },
5193
5194 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5195 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
5196 RS6000_BTI_unsigned_long_long },
5197 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5198 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5199 RS6000_BTI_unsigned_long_long },
5200
5201 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5202 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5203 RS6000_BTI_unsigned_long_long },
5204 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5205 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5206 RS6000_BTI_unsigned_long_long },
5207
5208 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5209 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5210 RS6000_BTI_unsigned_long_long },
5211 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5212 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5213 RS6000_BTI_unsigned_long_long },
5214
5215 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5216 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
5217 RS6000_BTI_unsigned_long_long },
5218 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5219 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
5220 RS6000_BTI_unsigned_long_long },
5221 /* At an appropriate future time, add support for the
5222 RS6000_BTI_Float16 (exact name to be determined) type here. */
5223
5224 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5225 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
5226 RS6000_BTI_bool_V16QI, 0 },
5227 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5228 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5229 RS6000_BTI_V16QI, 0 },
5230 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5231 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5232 RS6000_BTI_unsigned_V16QI, 0 },
5233
5234 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5235 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
5236 RS6000_BTI_bool_V8HI, 0 },
5237 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5238 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5239 RS6000_BTI_V8HI, 0 },
5240 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5241 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5242 RS6000_BTI_unsigned_V8HI, 0 },
5243
5244 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5245 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
5246 RS6000_BTI_bool_V4SI, 0 },
5247 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5248 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5249 RS6000_BTI_V4SI, 0 },
5250 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5251 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5252 RS6000_BTI_unsigned_V4SI, 0 },
5253
5254 /* The following 2 entries have been deprecated. */
5255 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5256 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5257 RS6000_BTI_unsigned_V16QI, 0 },
5258 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5259 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5260 RS6000_BTI_bool_V16QI, 0 },
5261 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5262 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5263 RS6000_BTI_unsigned_V16QI, 0 },
5264
5265 /* The following 2 entries have been deprecated. */
5266 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5267 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5268 RS6000_BTI_V16QI, 0 },
5269 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5270 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5271 RS6000_BTI_bool_V16QI, 0 },
5272 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5273 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5274 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5275 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5276 RS6000_BTI_bool_V16QI, 0 },
5277
5278 /* The following 2 entries have been deprecated. */
5279 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5280 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5281 RS6000_BTI_unsigned_V8HI, 0 },
5282 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5283 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5284 RS6000_BTI_bool_V8HI, 0 },
5285 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5286 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5287 RS6000_BTI_unsigned_V8HI, 0 },
5288 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5289 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5290
5291 /* The following 2 entries have been deprecated. */
5292 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5293 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5294 RS6000_BTI_V8HI, 0 },
5295 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5296 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5297 RS6000_BTI_bool_V8HI, 0 },
5298 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5299 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5300 RS6000_BTI_bool_V8HI, 0 },
5301 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5302 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5303 RS6000_BTI_pixel_V8HI, 0 },
5304
5305 /* The following 2 entries have been deprecated. */
5306 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5307 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5308 RS6000_BTI_unsigned_V4SI, 0 },
5309 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5310 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5311 RS6000_BTI_bool_V4SI, 0 },
5312 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5313 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5314 RS6000_BTI_unsigned_V4SI, 0 },
5315
5316 /* The following 2 entries have been deprecated. */
5317 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5318 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5319 RS6000_BTI_V4SI, 0 },
5320 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5321 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5322 RS6000_BTI_bool_V4SI, 0 },
5323 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5324 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5325 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5326 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5327 RS6000_BTI_bool_V4SI, 0 },
5328
5329 /* The following 2 entries have been deprecated. */
5330 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5331 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5332 RS6000_BTI_unsigned_V2DI, 0 },
5333 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5334 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5335 RS6000_BTI_bool_V2DI, 0 },
5336 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5337 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5338 RS6000_BTI_unsigned_V2DI, 0
5339 },
5340
5341 /* The following 2 entries have been deprecated. */
5342 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5343 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5344 RS6000_BTI_V2DI, 0 },
5345 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5346 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5347 RS6000_BTI_bool_V2DI, 0 },
5348 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5349 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5350 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5351 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5352 RS6000_BTI_bool_V2DI, 0 },
5353
5354 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
5355 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5356 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
5357 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5358
5359 /* The following 2 entries have been deprecated. */
5360 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5361 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5362 RS6000_BTI_unsigned_V16QI, 0 },
5363 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5364 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5365 RS6000_BTI_bool_V16QI, 0 },
5366 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5367 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5368 RS6000_BTI_unsigned_V16QI, 0 },
5369
5370 /* The following 2 entries have been deprecated. */
5371 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5372 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5373 RS6000_BTI_V16QI, 0 },
5374 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5375 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5376 RS6000_BTI_bool_V16QI, 0 },
5377 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5378 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5379 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5380 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5381 RS6000_BTI_bool_V16QI, 0 },
5382
5383 /* The following 2 entries have been deprecated. */
5384 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5385 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5386 RS6000_BTI_unsigned_V8HI, 0 },
5387 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5388 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5389 RS6000_BTI_bool_V8HI, 0 },
5390 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5391 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5392 RS6000_BTI_unsigned_V8HI, 0 },
5393 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5394 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5395
5396 /* The following 2 entries have been deprecated. */
5397 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5398 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5399 RS6000_BTI_V8HI, 0 },
5400 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5401 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5402 RS6000_BTI_bool_V8HI, 0 },
5403 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5404 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5405 RS6000_BTI_bool_V8HI, 0 },
5406 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5407 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5408 RS6000_BTI_pixel_V8HI, 0 },
5409
5410 /* The following 2 entries have been deprecated. */
5411 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5412 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5413 RS6000_BTI_unsigned_V4SI, 0 },
5414 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5415 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5416 RS6000_BTI_bool_V4SI, 0 },
5417 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5418 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5419 RS6000_BTI_unsigned_V4SI, 0 },
5420
5421 /* The following 2 entries have been deprecated. */
5422 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5423 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5424 RS6000_BTI_V4SI, 0 },
5425 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5426 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5427 RS6000_BTI_bool_V4SI, 0 },
5428 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5429 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5430 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5431 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5432 RS6000_BTI_bool_V4SI, 0 },
5433
5434 /* The following 2 entries have been deprecated. */
5435 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5436 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5437 RS6000_BTI_unsigned_V2DI, 0 },
5438 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5439 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5440 RS6000_BTI_bool_V2DI, 0 },
5441 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5442 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5443 RS6000_BTI_unsigned_V2DI, 0
5444 },
5445
5446 /* The following 2 entries have been deprecated. */
5447 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5448 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5449 RS6000_BTI_V2DI, 0 },
5450 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5451 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5452 RS6000_BTI_bool_V2DI, 0 },
5453 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5454 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5455 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5456 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5457 RS6000_BTI_bool_V2DI, 0 },
5458
5459 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5460 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5461 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5462 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5463
5464 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5465 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5466 RS6000_BTI_unsigned_V16QI },
5467 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5468 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5469
5470 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5471 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5472 RS6000_BTI_unsigned_V8HI },
5473 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5474 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5475
5476 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5477 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5478 RS6000_BTI_unsigned_V4SI },
5479 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5480 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5481
5482 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5483 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5484 RS6000_BTI_V16QI, 0 },
5485 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5486 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5487 RS6000_BTI_unsigned_V16QI, 0 },
5488
5489 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5490 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5491 RS6000_BTI_V8HI, 0 },
5492 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5493 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5494 RS6000_BTI_unsigned_V8HI, 0 },
5495
5496 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5497 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5498 RS6000_BTI_V4SI, 0 },
5499 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5500 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5501 RS6000_BTI_unsigned_V4SI, 0 },
5502
5503 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5504 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5505 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5506 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5507
5508 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5509 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5510 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5511 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5512 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5513 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5514 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5515 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5516
5517 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5518 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5519
5520 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5521 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5522 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5523 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5524
5525 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5526 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5527 RS6000_BTI_V16QI, 0 },
5528 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5529 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5530 RS6000_BTI_unsigned_V16QI, 0 },
5531
5532 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5533 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5534 RS6000_BTI_V8HI, 0 },
5535 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5536 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5537 RS6000_BTI_unsigned_V8HI, 0 },
5538
5539 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5540 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5541 RS6000_BTI_V4SI, 0 },
5542 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5543 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5544 RS6000_BTI_unsigned_V4SI, 0 },
5545 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5546 RS6000_BTI_float, RS6000_BTI_UINTSI,
5547 RS6000_BTI_V4SF, 0 },
5548
5549 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5550 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5551 RS6000_BTI_V16QI, 0 },
5552 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5553 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5554 RS6000_BTI_unsigned_V16QI, 0 },
5555
5556 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5557 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5558 RS6000_BTI_V8HI, 0 },
5559 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5560 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5561 RS6000_BTI_unsigned_V8HI, 0 },
5562
5563 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5564 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5565 RS6000_BTI_V4SI, 0 },
5566 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5567 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5568 RS6000_BTI_unsigned_V4SI, 0 },
5569 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5570 RS6000_BTI_float, RS6000_BTI_UINTSI,
5571 RS6000_BTI_V4SF, 0 },
5572
5573 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5574 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5575 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5576 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5577
5578 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5579 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5580 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5581 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5582 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5583 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5584
5585 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5586 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5587 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5588 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5589 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5590
5591 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5592 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5593 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5594 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5595 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5596
5597 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5598 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5599 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5600 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5601 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5602
5603 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5604 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5605 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5606 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5607 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5608
5609 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5610 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5611 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5612 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5613 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5614 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5615
5616 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5617 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5618 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5619 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5620 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5621 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5622
5623 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5624 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5625 RS6000_BTI_unsigned_V2DI, 0 },
5626 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5627 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5628 RS6000_BTI_bool_V2DI, 0 },
5629 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5630 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5631 RS6000_BTI_unsigned_V2DI, 0 },
5632
5633 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5634 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5635 RS6000_BTI_unsigned_V2DI, 0 },
5636 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5637 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5638 RS6000_BTI_bool_V2DI, 0 },
5639 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5640 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5641 RS6000_BTI_unsigned_V2DI, 0 },
5642
5643 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5644 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5645 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5646 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5647 RS6000_BTI_unsigned_V2DI, 0 },
5648 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5649 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5650 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5651 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5652 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5653 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5654 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5655 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5656 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5657 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5658 RS6000_BTI_unsigned_V4SI, 0 },
5659 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5660 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5661
5662 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5663 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5664 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5665 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5666 RS6000_BTI_unsigned_V4SI, 0 },
5667 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5668 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5669 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5670 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5671 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5672 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5673 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5674 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5675 RS6000_BTI_unsigned_V2DI, 0 },
5676 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5677 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5678 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5679 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5680 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5681 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5682
5683 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5684 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5685 RS6000_BTI_unsigned_V16QI, 0 },
5686 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5687 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5688 RS6000_BTI_unsigned_V8HI, 0 },
5689 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5690 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5691 RS6000_BTI_unsigned_V4SI, 0 },
5692 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5693 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5694 RS6000_BTI_unsigned_V2DI, 0 },
5695
5696 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5697 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5698 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5700 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5701 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5702 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5703 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5704 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5705 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5706 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5707 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5708 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5709 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5710 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5711 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5712
5713 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5714 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5715 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5716 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5717
5718 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5719 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5720 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5721 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5722
5723 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5724 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5725 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5726 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5727
5728 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5729 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5730 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5731 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5732
5733 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5734 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5735 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5736 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5737
5738 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5739 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5740 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5741 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5742
5743 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5744 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5745 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5746 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5747
5748 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5749 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5750 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5751 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5752
5753 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5754 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5755 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5756 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5757 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5758 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5759 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5760 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5761 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5762 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5763 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5764 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5765 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5766 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5767 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5768 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5769
5770 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5771 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5772 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5773 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5774
5775 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5776 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5777 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5778 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5779
5780 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5781 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5782 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5783 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5784 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5785 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5786 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5787 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5788
5789 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5790 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5791 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5792 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5793 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5794 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5795 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5796 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5797 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5798 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5799 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5800 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5801
5802 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5803 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5804 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5805 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5806 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5807 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5808
5809 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5810 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5811 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5812 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5813 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5814 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5815
5816 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5817 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5818
5819 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5820 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5821
5822 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5823 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5824
5825 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5826 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5827 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5828 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5829
5830 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5831 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5832 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5833 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5834
5835 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5836 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5837 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5838 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5839
5840 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5841 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5842 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5843 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5844
5845 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5846 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5847 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5848 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5849 RS6000_BTI_unsigned_V1TI, 0 },
5850
5851 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5852 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5853 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5854 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5855 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5856 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5857 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5858 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5859 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5860 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5861 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5862 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5863
5864 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5865 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5866 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5867 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5868 RS6000_BTI_unsigned_V1TI, 0 },
5869
5870 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5871 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5872 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5873 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5874
5875 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5876 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5877 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5878 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5879
5880 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5881 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5882 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5883 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5884
5885 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5886 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5887 RS6000_BTI_unsigned_V16QI, 0 },
5888 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5889 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5890 RS6000_BTI_unsigned_V16QI, 0 },
5891
5892 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5893 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5894 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5895 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5896 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5897 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5898 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5899 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5900 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5901 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5902 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5903 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5904 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5905 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5906 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5907 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5908 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5909 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5910 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5911 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5912 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5913 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5914 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5915 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5916 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5917 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5918 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5919 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5920 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5921 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5922 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5923 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5924
5925 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5926 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5927 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5928 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5929 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5930 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5931 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5932 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5933 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5934 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5935 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5936 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5937 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5938 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5939 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5940 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5941 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5942 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5943 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5944 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5945 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5946 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5947 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5948 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5949 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5950 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5951 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5952 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5953
5954 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5955 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5956 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5957 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5958 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5959 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5960 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5961 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5962 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5963 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5964
5965 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5966 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5967 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5968 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5969 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5970 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5971 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5972 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5973 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5974 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5975 RS6000_BTI_V2DF, 0 },
5976
5977 /* Crypto builtins. */
5978 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5979 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5980 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5981 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5982 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5983 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5984 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5985 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5986 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5987 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5988 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5989 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5990
5991 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5992 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5993 RS6000_BTI_unsigned_V16QI, 0 },
5994 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5995 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5996 RS6000_BTI_unsigned_V8HI, 0 },
5997 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5998 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5999 RS6000_BTI_unsigned_V4SI, 0 },
6000 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
6001 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
6002 RS6000_BTI_unsigned_V2DI, 0 },
6003
6004 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
6005 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
6006 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
6007 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
6008 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
6009 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
6010
6011 { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
6012 };
6013
6014
6015 /* Convert a type stored into a struct altivec_builtin_types as ID,
6016 into a tree. The types are in rs6000_builtin_types: negative values
6017 create a pointer type for the type associated to ~ID. Note it is
6018 a logical NOT, rather than a negation, otherwise you cannot represent
6019 a pointer type for ID 0. */
6020
6021 static inline tree
rs6000_builtin_type(int id)6022 rs6000_builtin_type (int id)
6023 {
6024 tree t;
6025 t = rs6000_builtin_types[id < 0 ? ~id : id];
6026 return id < 0 ? build_pointer_type (t) : t;
6027 }
6028
6029 /* Check whether the type of an argument, T, is compatible with a type ID
6030 stored into a struct altivec_builtin_types. Integer types are considered
6031 compatible; otherwise, the language hook lang_hooks.types_compatible_p makes
6032 the decision. Also allow long double and _Float128 to be compatible if
6033 -mabi=ieeelongdouble. */
6034
6035 static inline bool
is_float128_p(tree t)6036 is_float128_p (tree t)
6037 {
6038 return (t == float128_type_node
6039 || (TARGET_IEEEQUAD
6040 && TARGET_LONG_DOUBLE_128
6041 && t == long_double_type_node));
6042 }
6043
6044 static inline bool
rs6000_builtin_type_compatible(tree t,int id)6045 rs6000_builtin_type_compatible (tree t, int id)
6046 {
6047 tree builtin_type;
6048 builtin_type = rs6000_builtin_type (id);
6049 if (t == error_mark_node)
6050 return false;
6051 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
6052 return true;
6053 else if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6054 && is_float128_p (t) && is_float128_p (builtin_type))
6055 return true;
6056 else
6057 return lang_hooks.types_compatible_p (t, builtin_type);
6058 }
6059
6060
6061 /* In addition to calling fold_convert for EXPR of type TYPE, also
6062 call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
6063 hiding there (PR47197). */
6064
6065 static tree
fully_fold_convert(tree type,tree expr)6066 fully_fold_convert (tree type, tree expr)
6067 {
6068 tree result = fold_convert (type, expr);
6069 bool maybe_const = true;
6070
6071 if (!c_dialect_cxx ())
6072 result = c_fully_fold (result, false, &maybe_const);
6073
6074 return result;
6075 }
6076
6077 /* Build a tree for a function call to an Altivec non-overloaded builtin.
6078 The overloaded builtin that matched the types and args is described
6079 by DESC. The N arguments are given in ARGS, respectively.
6080
6081 Actually the only thing it does is calling fold_convert on ARGS, with
6082 a small exception for vec_{all,any}_{ge,le} predicates. */
6083
6084 static tree
altivec_build_resolved_builtin(tree * args,int n,const struct altivec_builtin_types * desc)6085 altivec_build_resolved_builtin (tree *args, int n,
6086 const struct altivec_builtin_types *desc)
6087 {
6088 tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
6089 tree ret_type = rs6000_builtin_type (desc->ret_type);
6090 tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
6091 tree arg_type[3];
6092 tree call;
6093
6094 int i;
6095 for (i = 0; i < n; i++)
6096 arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
6097
6098 /* The AltiVec overloading implementation is overall gross, but this
6099 is particularly disgusting. The vec_{all,any}_{ge,le} builtins
6100 are completely different for floating-point vs. integer vector
6101 types, because the former has vcmpgefp, but the latter should use
6102 vcmpgtXX.
6103
6104 In practice, the second and third arguments are swapped, and the
6105 condition (LT vs. EQ, which is recognizable by bit 1 of the first
6106 argument) is reversed. Patch the arguments here before building
6107 the resolved CALL_EXPR. */
6108 if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
6109 && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
6110 && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
6111 {
6112 tree t;
6113 t = args[2], args[2] = args[1], args[1] = t;
6114 t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
6115
6116 args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
6117 build_int_cst (NULL_TREE, 2));
6118 }
6119
6120 switch (n)
6121 {
6122 case 0:
6123 call = build_call_expr (impl_fndecl, 0);
6124 break;
6125 case 1:
6126 call = build_call_expr (impl_fndecl, 1,
6127 fully_fold_convert (arg_type[0], args[0]));
6128 break;
6129 case 2:
6130 call = build_call_expr (impl_fndecl, 2,
6131 fully_fold_convert (arg_type[0], args[0]),
6132 fully_fold_convert (arg_type[1], args[1]));
6133 break;
6134 case 3:
6135 call = build_call_expr (impl_fndecl, 3,
6136 fully_fold_convert (arg_type[0], args[0]),
6137 fully_fold_convert (arg_type[1], args[1]),
6138 fully_fold_convert (arg_type[2], args[2]));
6139 break;
6140 default:
6141 gcc_unreachable ();
6142 }
6143 return fold_convert (ret_type, call);
6144 }
6145
6146 /* Implementation of the resolve_overloaded_builtin target hook, to
6147 support Altivec's overloaded builtins. */
6148
6149 tree
altivec_resolve_overloaded_builtin(location_t loc,tree fndecl,void * passed_arglist)6150 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
6151 void *passed_arglist)
6152 {
6153 vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
6154 unsigned int nargs = vec_safe_length (arglist);
6155 enum rs6000_builtins fcode
6156 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
6157 tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
6158 tree types[3], args[3];
6159 const struct altivec_builtin_types *desc;
6160 unsigned int n;
6161
6162 if (!rs6000_overloaded_builtin_p (fcode))
6163 return NULL_TREE;
6164
6165 if (TARGET_DEBUG_BUILTIN)
6166 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
6167 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
6168
6169 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */
6170 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG)
6171 warning (OPT_Wdeprecated,
6172 "vec_lvsl is deprecated for little endian; use "
6173 "assignment for unaligned loads and stores");
6174 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG)
6175 warning (OPT_Wdeprecated,
6176 "vec_lvsr is deprecated for little endian; use "
6177 "assignment for unaligned loads and stores");
6178
6179 if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
6180 {
6181 /* vec_mul needs to be special cased because there are no instructions
6182 for it for the {un}signed char, {un}signed short, and {un}signed int
6183 types. */
6184 if (nargs != 2)
6185 {
6186 error ("builtin %qs only accepts 2 arguments", "vec_mul");
6187 return error_mark_node;
6188 }
6189
6190 tree arg0 = (*arglist)[0];
6191 tree arg0_type = TREE_TYPE (arg0);
6192 tree arg1 = (*arglist)[1];
6193 tree arg1_type = TREE_TYPE (arg1);
6194
6195 /* Both arguments must be vectors and the types must be compatible. */
6196 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6197 goto bad;
6198 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
6199 goto bad;
6200
6201 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6202 {
6203 case E_QImode:
6204 case E_HImode:
6205 case E_SImode:
6206 case E_DImode:
6207 case E_TImode:
6208 {
6209 /* For scalar types just use a multiply expression. */
6210 return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
6211 fold_convert (TREE_TYPE (arg0), arg1));
6212 }
6213 case E_SFmode:
6214 {
6215 /* For floats use the xvmulsp instruction directly. */
6216 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
6217 return build_call_expr (call, 2, arg0, arg1);
6218 }
6219 case E_DFmode:
6220 {
6221 /* For doubles use the xvmuldp instruction directly. */
6222 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
6223 return build_call_expr (call, 2, arg0, arg1);
6224 }
6225 /* Other types are errors. */
6226 default:
6227 goto bad;
6228 }
6229 }
6230
6231 if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
6232 {
6233 /* vec_cmpne needs to be special cased because there are no instructions
6234 for it (prior to power 9). */
6235 if (nargs != 2)
6236 {
6237 error ("builtin %qs only accepts 2 arguments", "vec_cmpne");
6238 return error_mark_node;
6239 }
6240
6241 tree arg0 = (*arglist)[0];
6242 tree arg0_type = TREE_TYPE (arg0);
6243 tree arg1 = (*arglist)[1];
6244 tree arg1_type = TREE_TYPE (arg1);
6245
6246 /* Both arguments must be vectors and the types must be compatible. */
6247 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6248 goto bad;
6249 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
6250 goto bad;
6251
6252 /* Power9 instructions provide the most efficient implementation of
6253 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
6254 or SFmode or DFmode. */
6255 if (!TARGET_P9_VECTOR
6256 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
6257 || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
6258 || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
6259 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
6260 {
6261 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6262 {
6263 /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
6264 vec_cmpeq (va, vb)). */
6265 /* Note: vec_nand also works but opt changes vec_nand's
6266 to vec_nor's anyway. */
6267 case E_QImode:
6268 case E_HImode:
6269 case E_SImode:
6270 case E_DImode:
6271 case E_TImode:
6272 case E_SFmode:
6273 case E_DFmode:
6274 {
6275 /* call = vec_cmpeq (va, vb)
6276 result = vec_nor (call, call). */
6277 vec<tree, va_gc> *params = make_tree_vector ();
6278 vec_safe_push (params, arg0);
6279 vec_safe_push (params, arg1);
6280 tree call = altivec_resolve_overloaded_builtin
6281 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
6282 params);
6283 /* Use save_expr to ensure that operands used more than once
6284 that may have side effects (like calls) are only evaluated
6285 once. */
6286 call = save_expr (call);
6287 params = make_tree_vector ();
6288 vec_safe_push (params, call);
6289 vec_safe_push (params, call);
6290 return altivec_resolve_overloaded_builtin
6291 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
6292 }
6293 /* Other types are errors. */
6294 default:
6295 goto bad;
6296 }
6297 }
6298 /* else, fall through and process the Power9 alternative below */
6299 }
6300
6301 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE
6302 || fcode == ALTIVEC_BUILTIN_VEC_SUBE)
6303 {
6304 /* vec_adde needs to be special cased because there is no instruction
6305 for the {un}signed int version. */
6306 if (nargs != 3)
6307 {
6308 const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ?
6309 "vec_adde": "vec_sube";
6310 error ("builtin %qs only accepts 3 arguments", name);
6311 return error_mark_node;
6312 }
6313
6314 tree arg0 = (*arglist)[0];
6315 tree arg0_type = TREE_TYPE (arg0);
6316 tree arg1 = (*arglist)[1];
6317 tree arg1_type = TREE_TYPE (arg1);
6318 tree arg2 = (*arglist)[2];
6319 tree arg2_type = TREE_TYPE (arg2);
6320
6321 /* All 3 arguments must be vectors of (signed or unsigned) (int or
6322 __int128) and the types must be compatible. */
6323 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6324 goto bad;
6325 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6326 || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
6327 goto bad;
6328
6329 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6330 {
6331 /* For {un}signed ints,
6332 vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
6333 vec_and (carryv, 1)).
6334 vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb),
6335 vec_and (carryv, 1)). */
6336 case E_SImode:
6337 {
6338 tree add_sub_builtin;
6339
6340 vec<tree, va_gc> *params = make_tree_vector ();
6341 vec_safe_push (params, arg0);
6342 vec_safe_push (params, arg1);
6343
6344 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6345 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6346 else
6347 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6348
6349 tree call = altivec_resolve_overloaded_builtin (loc,
6350 add_sub_builtin,
6351 params);
6352 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6353 tree ones_vector = build_vector_from_val (arg0_type, const1);
6354 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6355 arg2, ones_vector);
6356 params = make_tree_vector ();
6357 vec_safe_push (params, call);
6358 vec_safe_push (params, and_expr);
6359 return altivec_resolve_overloaded_builtin (loc, add_sub_builtin,
6360 params);
6361 }
6362 /* For {un}signed __int128s use the vaddeuqm instruction
6363 directly. */
6364 case E_TImode:
6365 {
6366 tree bii;
6367
6368 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6369 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
6370
6371 else
6372 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM];
6373
6374 return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6375 }
6376
6377 /* Types other than {un}signed int and {un}signed __int128
6378 are errors. */
6379 default:
6380 goto bad;
6381 }
6382 }
6383
6384 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC
6385 || fcode == ALTIVEC_BUILTIN_VEC_SUBEC)
6386 {
6387 /* vec_addec and vec_subec needs to be special cased because there is
6388 no instruction for the {un}signed int version. */
6389 if (nargs != 3)
6390 {
6391 const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ?
6392 "vec_addec": "vec_subec";
6393 error ("builtin %qs only accepts 3 arguments", name);
6394 return error_mark_node;
6395 }
6396
6397 tree arg0 = (*arglist)[0];
6398 tree arg0_type = TREE_TYPE (arg0);
6399 tree arg1 = (*arglist)[1];
6400 tree arg1_type = TREE_TYPE (arg1);
6401 tree arg2 = (*arglist)[2];
6402 tree arg2_type = TREE_TYPE (arg2);
6403
6404 /* All 3 arguments must be vectors of (signed or unsigned) (int or
6405 __int128) and the types must be compatible. */
6406 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6407 goto bad;
6408 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6409 || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
6410 goto bad;
6411
6412 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6413 {
6414 /* For {un}signed ints,
6415 vec_addec (va, vb, carryv) ==
6416 vec_or (vec_addc (va, vb),
6417 vec_addc (vec_add (va, vb),
6418 vec_and (carryv, 0x1))). */
6419 case E_SImode:
6420 {
6421 /* Use save_expr to ensure that operands used more than once
6422 that may have side effects (like calls) are only evaluated
6423 once. */
6424 tree as_builtin;
6425 tree as_c_builtin;
6426
6427 arg0 = save_expr (arg0);
6428 arg1 = save_expr (arg1);
6429 vec<tree, va_gc> *params = make_tree_vector ();
6430 vec_safe_push (params, arg0);
6431 vec_safe_push (params, arg1);
6432
6433 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6434 as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
6435 else
6436 as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC];
6437
6438 tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6439 params);
6440 params = make_tree_vector ();
6441 vec_safe_push (params, arg0);
6442 vec_safe_push (params, arg1);
6443
6444
6445 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6446 as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6447 else
6448 as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6449
6450 tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin,
6451 params);
6452 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6453 tree ones_vector = build_vector_from_val (arg0_type, const1);
6454 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6455 arg2, ones_vector);
6456 params = make_tree_vector ();
6457 vec_safe_push (params, call2);
6458 vec_safe_push (params, and_expr);
6459 call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6460 params);
6461 params = make_tree_vector ();
6462 vec_safe_push (params, call1);
6463 vec_safe_push (params, call2);
6464 tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
6465 return altivec_resolve_overloaded_builtin (loc, or_builtin,
6466 params);
6467 }
6468 /* For {un}signed __int128s use the vaddecuq/vsubbecuq
6469 instructions. */
6470 case E_TImode:
6471 {
6472 tree bii;
6473
6474 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6475 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
6476
6477 else
6478 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ];
6479
6480 return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6481 }
6482 /* Types other than {un}signed int and {un}signed __int128
6483 are errors. */
6484 default:
6485 goto bad;
6486 }
6487 }
6488
6489 /* For now treat vec_splats and vec_promote as the same. */
6490 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
6491 || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
6492 {
6493 tree type, arg;
6494 int size;
6495 int i;
6496 bool unsigned_p;
6497 vec<constructor_elt, va_gc> *vec;
6498 const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
6499
6500 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
6501 {
6502 error ("builtin %qs only accepts 1 argument", name);
6503 return error_mark_node;
6504 }
6505 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
6506 {
6507 error ("builtin %qs only accepts 2 arguments", name);
6508 return error_mark_node;
6509 }
6510 /* Ignore promote's element argument. */
6511 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
6512 && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
6513 goto bad;
6514
6515 arg = (*arglist)[0];
6516 type = TREE_TYPE (arg);
6517 if (!SCALAR_FLOAT_TYPE_P (type)
6518 && !INTEGRAL_TYPE_P (type))
6519 goto bad;
6520 unsigned_p = TYPE_UNSIGNED (type);
6521 switch (TYPE_MODE (type))
6522 {
6523 case E_TImode:
6524 type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
6525 size = 1;
6526 break;
6527 case E_DImode:
6528 type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
6529 size = 2;
6530 break;
6531 case E_SImode:
6532 type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
6533 size = 4;
6534 break;
6535 case E_HImode:
6536 type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
6537 size = 8;
6538 break;
6539 case E_QImode:
6540 type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
6541 size = 16;
6542 break;
6543 case E_SFmode: type = V4SF_type_node; size = 4; break;
6544 case E_DFmode: type = V2DF_type_node; size = 2; break;
6545 default:
6546 goto bad;
6547 }
6548 arg = save_expr (fold_convert (TREE_TYPE (type), arg));
6549 vec_alloc (vec, size);
6550 for(i = 0; i < size; i++)
6551 {
6552 constructor_elt elt = {NULL_TREE, arg};
6553 vec->quick_push (elt);
6554 }
6555 return build_constructor (type, vec);
6556 }
6557
6558 /* For now use pointer tricks to do the extraction, unless we are on VSX
6559 extracting a double from a constant offset. */
6560 if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
6561 {
6562 tree arg1;
6563 tree arg1_type;
6564 tree arg2;
6565 tree arg1_inner_type;
6566 tree decl, stmt;
6567 tree innerptrtype;
6568 machine_mode mode;
6569
6570 /* No second argument. */
6571 if (nargs != 2)
6572 {
6573 error ("builtin %qs only accepts 2 arguments", "vec_extract");
6574 return error_mark_node;
6575 }
6576
6577 arg2 = (*arglist)[1];
6578 arg1 = (*arglist)[0];
6579 arg1_type = TREE_TYPE (arg1);
6580
6581 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6582 goto bad;
6583 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6584 goto bad;
6585
6586 /* If we are targeting little-endian, but -maltivec=be has been
6587 specified to override the element order, adjust the element
6588 number accordingly. */
6589 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6590 {
6591 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6592 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6593 build_int_cstu (TREE_TYPE (arg2), last_elem),
6594 arg2);
6595 }
6596
6597 /* See if we can optimize vec_extracts with the current VSX instruction
6598 set. */
6599 mode = TYPE_MODE (arg1_type);
6600 if (VECTOR_MEM_VSX_P (mode))
6601
6602 {
6603 tree call = NULL_TREE;
6604 int nunits = GET_MODE_NUNITS (mode);
6605
6606 arg2 = fold_for_warn (arg2);
6607
6608 /* If the second argument is an integer constant, if the value is in
6609 the expected range, generate the built-in code if we can. We need
6610 64-bit and direct move to extract the small integer vectors. */
6611 if (TREE_CODE (arg2) == INTEGER_CST
6612 && wi::ltu_p (wi::to_wide (arg2), nunits))
6613 {
6614 switch (mode)
6615 {
6616 default:
6617 break;
6618
6619 case E_V1TImode:
6620 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
6621 break;
6622
6623 case E_V2DFmode:
6624 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6625 break;
6626
6627 case E_V2DImode:
6628 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6629 break;
6630
6631 case E_V4SFmode:
6632 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6633 break;
6634
6635 case E_V4SImode:
6636 if (TARGET_DIRECT_MOVE_64BIT)
6637 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6638 break;
6639
6640 case E_V8HImode:
6641 if (TARGET_DIRECT_MOVE_64BIT)
6642 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6643 break;
6644
6645 case E_V16QImode:
6646 if (TARGET_DIRECT_MOVE_64BIT)
6647 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6648 break;
6649 }
6650 }
6651
6652 /* If the second argument is variable, we can optimize it if we are
6653 generating 64-bit code on a machine with direct move. */
6654 else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
6655 {
6656 switch (mode)
6657 {
6658 default:
6659 break;
6660
6661 case E_V2DFmode:
6662 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6663 break;
6664
6665 case E_V2DImode:
6666 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6667 break;
6668
6669 case E_V4SFmode:
6670 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6671 break;
6672
6673 case E_V4SImode:
6674 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6675 break;
6676
6677 case E_V8HImode:
6678 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6679 break;
6680
6681 case E_V16QImode:
6682 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6683 break;
6684 }
6685 }
6686
6687 if (call)
6688 {
6689 tree result = build_call_expr (call, 2, arg1, arg2);
6690 /* Coerce the result to vector element type. May be no-op. */
6691 arg1_inner_type = TREE_TYPE (arg1_type);
6692 result = fold_convert (arg1_inner_type, result);
6693 return result;
6694 }
6695 }
6696
6697 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6698 arg1_inner_type = TREE_TYPE (arg1_type);
6699 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6700 build_int_cst (TREE_TYPE (arg2),
6701 TYPE_VECTOR_SUBPARTS (arg1_type)
6702 - 1), 0);
6703 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6704 DECL_EXTERNAL (decl) = 0;
6705 TREE_PUBLIC (decl) = 0;
6706 DECL_CONTEXT (decl) = current_function_decl;
6707 TREE_USED (decl) = 1;
6708 TREE_TYPE (decl) = arg1_type;
6709 TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6710 if (c_dialect_cxx ())
6711 {
6712 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6713 NULL_TREE, NULL_TREE);
6714 SET_EXPR_LOCATION (stmt, loc);
6715 }
6716 else
6717 {
6718 DECL_INITIAL (decl) = arg1;
6719 stmt = build1 (DECL_EXPR, arg1_type, decl);
6720 TREE_ADDRESSABLE (decl) = 1;
6721 SET_EXPR_LOCATION (stmt, loc);
6722 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6723 }
6724
6725 innerptrtype = build_pointer_type (arg1_inner_type);
6726
6727 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6728 stmt = convert (innerptrtype, stmt);
6729 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6730 stmt = build_indirect_ref (loc, stmt, RO_NULL);
6731
6732 /* PR83660: We mark this as having side effects so that
6733 downstream in fold_build_cleanup_point_expr () it will get a
6734 CLEANUP_POINT_EXPR. If it does not we can run into an ICE
6735 later in gimplify_cleanup_point_expr (). Potentially this
6736 causes missed optimization because the actually is no side
6737 effect. */
6738 if (c_dialect_cxx ())
6739 TREE_SIDE_EFFECTS (stmt) = 1;
6740
6741 return stmt;
6742 }
6743
6744 /* For now use pointer tricks to do the insertion, unless we are on VSX
6745 inserting a double to a constant offset.. */
6746 if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6747 {
6748 tree arg0;
6749 tree arg1;
6750 tree arg2;
6751 tree arg1_type;
6752 tree arg1_inner_type;
6753 tree decl, stmt;
6754 tree innerptrtype;
6755 machine_mode mode;
6756
6757 /* No second or third arguments. */
6758 if (nargs != 3)
6759 {
6760 error ("builtin %qs only accepts 3 arguments", "vec_insert");
6761 return error_mark_node;
6762 }
6763
6764 arg0 = (*arglist)[0];
6765 arg1 = (*arglist)[1];
6766 arg1_type = TREE_TYPE (arg1);
6767 arg2 = fold_for_warn ((*arglist)[2]);
6768
6769 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6770 goto bad;
6771 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6772 goto bad;
6773
6774 /* If we are targeting little-endian, but -maltivec=be has been
6775 specified to override the element order, adjust the element
6776 number accordingly. */
6777 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6778 {
6779 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6780 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6781 build_int_cstu (TREE_TYPE (arg2), last_elem),
6782 arg2);
6783 }
6784
6785 /* If we can use the VSX xxpermdi instruction, use that for insert. */
6786 mode = TYPE_MODE (arg1_type);
6787 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6788 && TREE_CODE (arg2) == INTEGER_CST
6789 && wi::ltu_p (wi::to_wide (arg2), 2))
6790 {
6791 tree call = NULL_TREE;
6792
6793 if (mode == V2DFmode)
6794 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6795 else if (mode == V2DImode)
6796 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6797
6798 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6799 reversed. */
6800 if (call)
6801 return build_call_expr (call, 3, arg1, arg0, arg2);
6802 }
6803 else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6804 && TREE_CODE (arg2) == INTEGER_CST
6805 && wi::eq_p (wi::to_wide (arg2), 0))
6806 {
6807 tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6808
6809 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6810 reversed. */
6811 return build_call_expr (call, 3, arg1, arg0, arg2);
6812 }
6813
6814 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6815 arg1_inner_type = TREE_TYPE (arg1_type);
6816 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6817 build_int_cst (TREE_TYPE (arg2),
6818 TYPE_VECTOR_SUBPARTS (arg1_type)
6819 - 1), 0);
6820 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6821 DECL_EXTERNAL (decl) = 0;
6822 TREE_PUBLIC (decl) = 0;
6823 DECL_CONTEXT (decl) = current_function_decl;
6824 TREE_USED (decl) = 1;
6825 TREE_TYPE (decl) = arg1_type;
6826 TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6827 if (c_dialect_cxx ())
6828 {
6829 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6830 NULL_TREE, NULL_TREE);
6831 SET_EXPR_LOCATION (stmt, loc);
6832 }
6833 else
6834 {
6835 DECL_INITIAL (decl) = arg1;
6836 stmt = build1 (DECL_EXPR, arg1_type, decl);
6837 TREE_ADDRESSABLE (decl) = 1;
6838 SET_EXPR_LOCATION (stmt, loc);
6839 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6840 }
6841
6842 innerptrtype = build_pointer_type (arg1_inner_type);
6843
6844 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6845 stmt = convert (innerptrtype, stmt);
6846 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6847 stmt = build_indirect_ref (loc, stmt, RO_NULL);
6848 stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6849 convert (TREE_TYPE (stmt), arg0));
6850 stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6851 return stmt;
6852 }
6853
6854 for (n = 0;
6855 !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6856 fnargs = TREE_CHAIN (fnargs), n++)
6857 {
6858 tree decl_type = TREE_VALUE (fnargs);
6859 tree arg = (*arglist)[n];
6860 tree type;
6861
6862 if (arg == error_mark_node)
6863 return error_mark_node;
6864
6865 if (n >= 3)
6866 abort ();
6867
6868 arg = default_conversion (arg);
6869
6870 /* The C++ front-end converts float * to const void * using
6871 NOP_EXPR<const void *> (NOP_EXPR<void *> (x)). */
6872 type = TREE_TYPE (arg);
6873 if (POINTER_TYPE_P (type)
6874 && TREE_CODE (arg) == NOP_EXPR
6875 && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6876 const_ptr_type_node)
6877 && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6878 ptr_type_node))
6879 {
6880 arg = TREE_OPERAND (arg, 0);
6881 type = TREE_TYPE (arg);
6882 }
6883
6884 /* Remove the const from the pointers to simplify the overload
6885 matching further down. */
6886 if (POINTER_TYPE_P (decl_type)
6887 && POINTER_TYPE_P (type)
6888 && TYPE_QUALS (TREE_TYPE (type)) != 0)
6889 {
6890 if (TYPE_READONLY (TREE_TYPE (type))
6891 && !TYPE_READONLY (TREE_TYPE (decl_type)))
6892 warning (0, "passing arg %d of %qE discards qualifiers from "
6893 "pointer target type", n + 1, fndecl);
6894 type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6895 0));
6896 arg = fold_convert (type, arg);
6897 }
6898
6899 args[n] = arg;
6900 types[n] = type;
6901 }
6902
6903 /* If the number of arguments did not match the prototype, return NULL
6904 and the generic code will issue the appropriate error message. */
6905 if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
6906 return NULL;
6907
6908 if (n == 0)
6909 abort ();
6910
6911 if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6912 {
6913 if (TREE_CODE (types[0]) != VECTOR_TYPE)
6914 goto bad;
6915
6916 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6917 }
6918
6919 {
6920 bool unsupported_builtin = false;
6921 enum rs6000_builtins overloaded_code;
6922 tree result = NULL;
6923 for (desc = altivec_overloaded_builtins;
6924 desc->code && desc->code != fcode; desc++)
6925 continue;
6926
6927 /* Need to special case __builtin_cmp because the overloaded forms
6928 of this function take (unsigned int, unsigned int) or (unsigned
6929 long long int, unsigned long long int). Since C conventions
6930 allow the respective argument types to be implicitly coerced into
6931 each other, the default handling does not provide adequate
6932 discrimination between the desired forms of the function. */
6933 if (fcode == P6_OV_BUILTIN_CMPB)
6934 {
6935 machine_mode arg1_mode = TYPE_MODE (types[0]);
6936 machine_mode arg2_mode = TYPE_MODE (types[1]);
6937
6938 if (nargs != 2)
6939 {
6940 error ("builtin %qs only accepts 2 arguments", "__builtin_cmpb");
6941 return error_mark_node;
6942 }
6943
6944 /* If any supplied arguments are wider than 32 bits, resolve to
6945 64-bit variant of built-in function. */
6946 if ((GET_MODE_PRECISION (arg1_mode) > 32)
6947 || (GET_MODE_PRECISION (arg2_mode) > 32))
6948 {
6949 /* Assure all argument and result types are compatible with
6950 the built-in function represented by P6_BUILTIN_CMPB. */
6951 overloaded_code = P6_BUILTIN_CMPB;
6952 }
6953 else
6954 {
6955 /* Assure all argument and result types are compatible with
6956 the built-in function represented by P6_BUILTIN_CMPB_32. */
6957 overloaded_code = P6_BUILTIN_CMPB_32;
6958 }
6959
6960 while (desc->code && desc->code == fcode
6961 && desc->overloaded_code != overloaded_code)
6962 desc++;
6963
6964 if (desc->code && (desc->code == fcode)
6965 && rs6000_builtin_type_compatible (types[0], desc->op1)
6966 && rs6000_builtin_type_compatible (types[1], desc->op2))
6967 {
6968 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6969 {
6970 result = altivec_build_resolved_builtin (args, n, desc);
6971 /* overloaded_code is set above */
6972 if (!rs6000_builtin_is_supported_p (overloaded_code))
6973 unsupported_builtin = true;
6974 else
6975 return result;
6976 }
6977 else
6978 unsupported_builtin = true;
6979 }
6980 }
6981 else if (fcode == P9V_BUILTIN_VEC_VSIEDP)
6982 {
6983 machine_mode arg1_mode = TYPE_MODE (types[0]);
6984
6985 if (nargs != 2)
6986 {
6987 error ("builtin %qs only accepts 2 arguments",
6988 "scalar_insert_exp");
6989 return error_mark_node;
6990 }
6991
6992 /* If supplied first argument is wider than 64 bits, resolve to
6993 128-bit variant of built-in function. */
6994 if (GET_MODE_PRECISION (arg1_mode) > 64)
6995 {
6996 /* If first argument is of float variety, choose variant
6997 that expects __ieee128 argument. Otherwise, expect
6998 __int128 argument. */
6999 if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
7000 overloaded_code = P9V_BUILTIN_VSIEQPF;
7001 else
7002 overloaded_code = P9V_BUILTIN_VSIEQP;
7003 }
7004 else
7005 {
7006 /* If first argument is of float variety, choose variant
7007 that expects double argument. Otherwise, expect
7008 long long int argument. */
7009 if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
7010 overloaded_code = P9V_BUILTIN_VSIEDPF;
7011 else
7012 overloaded_code = P9V_BUILTIN_VSIEDP;
7013 }
7014 while (desc->code && desc->code == fcode
7015 && desc->overloaded_code != overloaded_code)
7016 desc++;
7017
7018 if (desc->code && (desc->code == fcode)
7019 && rs6000_builtin_type_compatible (types[0], desc->op1)
7020 && rs6000_builtin_type_compatible (types[1], desc->op2))
7021 {
7022 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
7023 {
7024 result = altivec_build_resolved_builtin (args, n, desc);
7025 /* overloaded_code is set above. */
7026 if (!rs6000_builtin_is_supported_p (overloaded_code))
7027 unsupported_builtin = true;
7028 else
7029 return result;
7030 }
7031 else
7032 unsupported_builtin = true;
7033 }
7034 }
7035 else
7036 {
7037 /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
7038 the opX fields. */
7039 for (; desc->code == fcode; desc++)
7040 {
7041 if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
7042 || rs6000_builtin_type_compatible (types[0], desc->op1))
7043 && (desc->op2 == RS6000_BTI_NOT_OPAQUE
7044 || rs6000_builtin_type_compatible (types[1], desc->op2))
7045 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
7046 || rs6000_builtin_type_compatible (types[2], desc->op3)))
7047 {
7048 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
7049 {
7050 result = altivec_build_resolved_builtin (args, n, desc);
7051 if (!rs6000_builtin_is_supported_p (desc->overloaded_code))
7052 {
7053 /* Allow loop to continue in case a different
7054 definition is supported. */
7055 overloaded_code = desc->overloaded_code;
7056 unsupported_builtin = true;
7057 }
7058 else
7059 return result;
7060 }
7061 else
7062 unsupported_builtin = true;
7063 }
7064 }
7065 }
7066
7067 if (unsupported_builtin)
7068 {
7069 const char *name = rs6000_overloaded_builtin_name (fcode);
7070 if (result != NULL)
7071 {
7072 const char *internal_name
7073 = rs6000_overloaded_builtin_name (overloaded_code);
7074 /* An error message making reference to the name of the
7075 non-overloaded function has already been issued. Add
7076 clarification of the previous message. */
7077 rich_location richloc (line_table, input_location);
7078 inform (&richloc, "builtin %qs requires builtin %qs",
7079 name, internal_name);
7080 }
7081 else
7082 error ("builtin function %qs not supported in this compiler "
7083 "configuration", name);
7084 /* If an error-representing result tree was returned from
7085 altivec_build_resolved_builtin above, use it. */
7086 return (result != NULL) ? result : error_mark_node;
7087 }
7088 }
7089 bad:
7090 {
7091 const char *name = rs6000_overloaded_builtin_name (fcode);
7092 error ("invalid parameter combination for AltiVec intrinsic %qs", name);
7093 return error_mark_node;
7094 }
7095 }
7096