1; Options for the Synopsys DesignWare ARC port of the compiler 2; 3; Copyright (C) 2005-2018 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT 13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15; License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/arc/arc-opts.h 23 24mbig-endian 25Target Report RejectNegative Mask(BIG_ENDIAN) 26Compile code for big endian mode. 27 28mlittle-endian 29Target Report RejectNegative InverseMask(BIG_ENDIAN) 30Compile code for little endian mode. This is the default. 31 32mno-cond-exec 33Target Report RejectNegative Mask(NO_COND_EXEC) 34Disable ARCompact specific pass to generate conditional execution instructions. 35 36mA6 37Target Report 38Generate ARCompact 32-bit code for ARC600 processor. 39 40mARC600 41Target Report 42Same as -mA6. 43 44mARC601 45Target Report 46Generate ARCompact 32-bit code for ARC601 processor. 47 48mA7 49Target Report 50Generate ARCompact 32-bit code for ARC700 processor. 51 52mARC700 53Target Report 54Same as -mA7. 55 56mjli-always 57Target Report Mask(JLI_ALWAYS) 58Force all calls to be made via a jli instruction. 59 60mmpy-option= 61Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option) 62-mmpy-option=MPY Compile ARCv2 code with a multiplier design option. 63 64Enum 65Name(arc_mpy) Type(int) 66 67EnumValue 68Enum(arc_mpy) String(0) Value(0) 69 70EnumValue 71Enum(arc_mpy) String(none) Value(0) Canonical 72 73EnumValue 74Enum(arc_mpy) String(1) Value(1) 75 76EnumValue 77Enum(arc_mpy) String(w) Value(1) Canonical 78 79EnumValue 80Enum(arc_mpy) String(2) Value(2) 81 82EnumValue 83Enum(arc_mpy) String(mpy) Value(2) 84 85EnumValue 86Enum(arc_mpy) String(wlh1) Value(2) Canonical 87 88EnumValue 89Enum(arc_mpy) String(3) Value(3) 90 91EnumValue 92Enum(arc_mpy) String(wlh2) Value(3) Canonical 93 94EnumValue 95Enum(arc_mpy) String(4) Value(4) 96 97EnumValue 98Enum(arc_mpy) String(wlh3) Value(4) Canonical 99 100EnumValue 101Enum(arc_mpy) String(5) Value(5) 102 103EnumValue 104Enum(arc_mpy) String(wlh4) Value(5) Canonical 105 106EnumValue 107Enum(arc_mpy) String(6) Value(6) 108 109EnumValue 110Enum(arc_mpy) String(wlh5) Value(6) Canonical 111 112EnumValue 113Enum(arc_mpy) String(7) Value(7) 114 115EnumValue 116Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical 117 118EnumValue 119Enum(arc_mpy) String(8) Value(8) 120 121EnumValue 122Enum(arc_mpy) String(plus_macd) Value(8) Canonical 123 124EnumValue 125Enum(arc_mpy) String(9) Value(9) 126 127EnumValue 128Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical 129 130mdiv-rem 131Target Report Mask(DIVREM) 132Enable DIV-REM instructions for ARCv2. 133 134mcode-density 135Target Report Mask(CODE_DENSITY) 136Enable code density instructions for ARCv2. 137 138mmixed-code 139Target Report Mask(MIXED_CODE_SET) 140Tweak register allocation to help 16-bit instruction generation. 141; originally this was: 142;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions 143; but we do that without -mmixed-code, too, it's just a different instruction 144; count / size tradeoff. 145 146; We use an explict definition for the negative form because that is the 147; actually interesting option, and we want that to have its own comment. 148mvolatile-cache 149Target Report RejectNegative Mask(VOLATILE_CACHE_SET) 150Use ordinarily cached memory accesses for volatile references. 151 152mno-volatile-cache 153Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) 154Enable cache bypass for volatile references. 155 156mbarrel-shifter 157Target Report Mask(BARREL_SHIFTER) 158Generate instructions supported by barrel shifter. 159 160mnorm 161Target Report Mask(NORM_SET) 162Generate norm instruction. 163 164mswap 165Target Report Mask(SWAP_SET) 166Generate swap instruction. 167 168mmul64 169Target Report Mask(MUL64_SET) 170Generate mul64 and mulu64 instructions. 171 172mno-mpy 173Target Report Mask(NOMPY_SET) Warn(%qs is deprecated) 174Do not generate mpy instructions for ARC700. 175 176mea 177Target Report Mask(EA_SET) 178Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported. 179 180msoft-float 181Target Report Mask(0) 182Dummy flag. This is the default unless FPX switches are provided explicitly. 183 184mlong-calls 185Target Report Mask(LONG_CALLS_SET) 186Generate call insns as register indirect calls. 187 188mno-brcc 189Target Report Mask(NO_BRCC_SET) 190Do no generate BRcc instructions in arc_reorg. 191 192msdata 193Target Report InverseMask(NO_SDATA_SET) 194Generate sdata references. This is the default, unless you compile for PIC. 195 196mno-millicode 197Target Report Mask(NO_MILLICODE_THUNK_SET) 198Do not generate millicode thunks (needed only with -Os). 199 200mspfp 201Target Report Mask(SPFP_COMPACT_SET) 202FPX: Generate Single Precision FPX (compact) instructions. 203 204mspfp-compact 205Target Report Mask(SPFP_COMPACT_SET) MaskExists 206FPX: Generate Single Precision FPX (compact) instructions. 207 208mspfp-fast 209Target Report Mask(SPFP_FAST_SET) 210FPX: Generate Single Precision FPX (fast) instructions. 211 212margonaut 213Target Report Mask(ARGONAUT_SET) 214FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. 215 216mdpfp 217Target Report Mask(DPFP_COMPACT_SET) 218FPX: Generate Double Precision FPX (compact) instructions. 219 220mdpfp-compact 221Target Report Mask(DPFP_COMPACT_SET) MaskExists 222FPX: Generate Double Precision FPX (compact) instructions. 223 224mdpfp-fast 225Target Report Mask(DPFP_FAST_SET) 226FPX: Generate Double Precision FPX (fast) instructions. 227 228mno-dpfp-lrsr 229Target Report Mask(DPFP_DISABLE_LRSR) 230Disable LR and SR instructions from using FPX extension aux registers. 231 232msimd 233Target Report Mask(SIMD_SET) 234Enable generation of ARC SIMD instructions via target-specific builtins. 235 236mcpu= 237Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE) 238-mcpu=CPU Compile code for ARC variant CPU. 239 240msize-level= 241Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) 242size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. 243 244misize 245Target Report PchIgnore Var(TARGET_DUMPISIZE) 246Annotate assembler instructions with estimated addresses. 247 248mmultcost= 249Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1) 250Cost to assume for a multiply instruction, with 4 being equal to a normal insn. 251 252mtune= 253Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE) 254-mcpu=TUNE Tune code for given ARC variant. 255 256Enum 257Name(arc_tune_attr) Type(int) 258 259EnumValue 260Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600) 261 262EnumValue 263Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600) 264 265EnumValue 266Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD) 267 268EnumValue 269Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC) 270 271EnumValue 272Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC) 273 274EnumValue 275Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC) 276 277EnumValue 278Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3) 279 280mindexed-loads 281Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT) 282Enable the use of indexed loads. 283 284mauto-modify-reg 285Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT) 286Enable the use of pre/post modify with register displacement. 287 288mmul32x16 289Target Report Mask(MULMAC_32BY16_SET) 290Generate 32x16 multiply and mac instructions. 291 292; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , 293; alas, basic-block.h is not included in options.c . 294munalign-prob-threshold= 295Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2) 296Set probability threshold for unaligning branches. 297 298mmedium-calls 299Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) 300Don't use less than 25 bit addressing range for calls. 301 302mannotate-align 303Target Var(TARGET_ANNOTATE_ALIGN) 304Explain what alignment considerations lead to the decision to make an insn short or long. 305 306malign-call 307Target Var(TARGET_ALIGN_CALL) 308Do alignment optimizations for call instructions. 309 310mRcq 311Target Var(TARGET_Rcq) 312Enable Rcq constraint handling - most short code generation depends on this. 313 314mRcw 315Target Var(TARGET_Rcw) 316Enable Rcw constraint handling - ccfsm condexec mostly depends on this. 317 318mearly-cbranchsi 319Target Var(TARGET_EARLY_CBRANCHSI) 320Enable pre-reload use of cbranchsi pattern. 321 322mbbit-peephole 323Target Var(TARGET_BBIT_PEEPHOLE) 324Enable bbit peephole2. 325 326mcase-vector-pcrel 327Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) 328Use pc-relative switch case tables - this enables case table shortening. 329 330mcompact-casesi 331Target Var(TARGET_COMPACT_CASESI) 332Enable compact casesi pattern. 333 334mq-class 335Target Var(TARGET_Q_CLASS) 336Enable 'q' instruction alternatives. 337 338mexpand-adddi 339Target Warn(%qs is deprecated) 340Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. 341 342 343; Flags used by the assembler, but for which we define preprocessor 344; macro symbols as well. 345mcrc 346Target Report Warn(%qs is deprecated) 347Enable variable polynomial CRC extension. 348 349mdsp-packa 350Target Report Warn(%qs is deprecated) 351Enable DSP 3.1 Pack A extensions. 352 353mdvbf 354Target Report Warn(%qs is deprecated) 355Enable dual viterbi butterfly extension. 356 357mmac-d16 358Target Report Undocumented Warn(%qs is deprecated) 359 360mmac-24 361Target Report Undocumented Warn(%qs is deprecated) 362 363mtelephony 364Target Report RejectNegative Warn(%qs is deprecated) 365Enable Dual and Single Operand Instructions for Telephony. 366 367mxy 368Target Report 369Enable XY Memory extension (DSP version 3). 370 371; ARC700 4.10 extension instructions 372mlock 373Target Report 374Enable Locked Load/Store Conditional extension. 375 376mswape 377Target Report 378Enable swap byte ordering extension instruction. 379 380mrtsc 381Target Report Warn(%qs is deprecated) 382Enable 64-bit Time-Stamp Counter extension instruction. 383 384EB 385Target 386Pass -EB option through to linker. 387 388EL 389Target 390Pass -EL option through to linker. 391 392marclinux 393Target 394Pass -marclinux option through to linker. 395 396marclinux_prof 397Target 398Pass -marclinux_prof option through to linker. 399 400;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. 401;Target InverseMask(NO_LRA) 402; lra still won't allow to configure libgcc; see PR rtl-optimization/55464. 403; so don't enable by default. 404mlra 405Target Mask(LRA) 406Enable lra. 407 408mlra-priority-none 409Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE) 410Don't indicate any priority with TARGET_REGISTER_PRIORITY. 411 412mlra-priority-compact 413Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT) 414Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. 415 416mlra-priority-noncompact 417Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT) 418Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. 419 420; backward-compatibility aliases, translated by DRIVER_SELF_SPECS 421 422mEA 423Target 424 425multcost= 426Target RejectNegative Joined 427 428matomic 429Target Report Mask(ATOMIC) 430Enable atomic instructions. 431 432mll64 433Target Report Mask(LL64) 434Enable double load/store instructions for ARC HS. 435 436mfpu= 437Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build) 438Specify the name of the target floating point configuration. 439 440Enum 441Name(arc_fpu) Type(int) 442 443EnumValue 444Enum(arc_fpu) String(fpus) Value(FPU_FPUS) 445 446EnumValue 447Enum(arc_fpu) String(fpud) Value(FPU_FPUD) 448 449EnumValue 450Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA) 451 452EnumValue 453Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV) 454 455EnumValue 456Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA) 457 458EnumValue 459Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL) 460 461EnumValue 462Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV) 463 464EnumValue 465Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV) 466 467EnumValue 468Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA) 469 470EnumValue 471Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA) 472 473EnumValue 474Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL) 475 476EnumValue 477Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL) 478 479mtp-regno= 480Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT) 481Specify thread pointer register number. 482 483mtp-regno=none 484Target RejectNegative Var(arc_tp_regno,-1) 485 486mbitops 487Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) 488Enable use of NPS400 bit operations. 489 490mcmem 491Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) 492Enable use of NPS400 xld/xst extension. 493 494munaligned-access 495Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) 496Enable unaligned word and halfword accesses to packed data. 497 498mirq-ctrl-saved= 499Target RejectNegative Joined Var(arc_deferred_options) Defer 500Specifies the registers that the processor saves on an interrupt entry and exit. 501 502mrgf-banked-regs= 503Target RejectNegative Joined Var(arc_deferred_options) Defer 504Specifies the number of registers replicated in second register bank on entry to fast interrupt. 505 506mlpc-width= 507Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32) 508Sets LP_COUNT register width. Possible values are 8, 16, 20, 24, 28, and 32. 509 510Enum 511Name(arc_lpc) Type(int) 512 513EnumValue 514Enum(arc_lpc) String(8) Value(8) 515 516EnumValue 517Enum(arc_lpc) String(16) Value(16) 518 519EnumValue 520Enum(arc_lpc) String(20) Value(20) 521 522EnumValue 523Enum(arc_lpc) String(24) Value(24) 524 525EnumValue 526Enum(arc_lpc) String(28) Value(28) 527 528EnumValue 529Enum(arc_lpc) String(32) Value(32) 530 531mrf16 532Target Report Mask(RF16) 533Enable 16-entry register file. 534