1;__kernel void test_switch(__global int* res, uchar val)
2;{
3;  switch(val)
4;  {
5;  case 0:
6;    *res = 1;
7;    break;
8;  case 1:
9;    *res = 2;
10;    break;
11;  case 2:
12;    *res = 3;
13;    break;
14;  }
15;}
16
17; RUN: llvm-as %s -o %t.bc
18; RUN: llvm-spirv %t.bc -spirv-text -o %t.spt
19; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
20; RUN: llvm-spirv %t.bc -o %t.spv
21; RUN: spirv-val %t.spv
22; RUN: llvm-spirv -r %t.spv -o %t.bc
23; RUN: llvm-dis < %t.bc | FileCheck %s --check-prefix=CHECK-LLVM
24
25; CHECK-SPIRV: 9 Switch {{[0-9]+}} {{[0-9]+}} 0 {{[0-9]+}} 1 {{[0-9]+}} 2 {{[0-9]+}}
26
27; ModuleID = 'switch.cl'
28target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
29target triple = "spir-unknown-unknown"
30
31;CHECK-LLVM-LABEL: @test_switch
32;CHECK-LLVM: switch i8 %0, label %sw.epilog
33;CHECK-LLVM: i8 0, label %sw.bb
34;CHECK-LLVM: i8 1, label %sw.bb1
35;CHECK-LLVM: i8 2, label %sw.bb2
36
37; Function Attrs: convergent noinline nounwind optnone
38define spir_kernel void @test_switch(i32 addrspace(1)* %res, i8 zeroext %val) #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
39entry:
40  %res.addr = alloca i32 addrspace(1)*, align 4
41  %val.addr = alloca i8, align 1
42  store i32 addrspace(1)* %res, i32 addrspace(1)** %res.addr, align 4
43  store i8 %val, i8* %val.addr, align 1
44  %0 = load i8, i8* %val.addr, align 1
45  switch i8 %0, label %sw.epilog [
46    i8 0, label %sw.bb
47    i8 1, label %sw.bb1
48    i8 2, label %sw.bb2
49  ]
50
51sw.bb:                                            ; preds = %entry
52  %1 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
53  store i32 1, i32 addrspace(1)* %1, align 4
54  br label %sw.epilog
55
56sw.bb1:                                           ; preds = %entry
57  %2 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
58  store i32 2, i32 addrspace(1)* %2, align 4
59  br label %sw.epilog
60
61sw.bb2:                                           ; preds = %entry
62  %3 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
63  store i32 3, i32 addrspace(1)* %3, align 4
64  br label %sw.epilog
65
66sw.epilog:                                        ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb
67  ret void
68}
69
70attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
71
72!llvm.module.flags = !{!0}
73!opencl.ocl.version = !{!1}
74!opencl.spir.version = !{!1}
75!llvm.ident = !{!2}
76
77!0 = !{i32 1, !"wchar_size", i32 4}
78!1 = !{i32 2, i32 0}
79!2 = !{!"clang version 9.0.0"}
80!3 = !{i32 1, i32 0}
81!4 = !{!"none", !"none"}
82!5 = !{!"int*", !"uchar"}
83!6 = !{!"", !""}
84