1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20 #include "ansidecl.h"
21 #include "libiberty.h"
22 #include "dis-asm.h"
23 #include "opcode/arc.h"
24 #include "elf-bfd.h"
25 #include "elf/arc.h"
26 #include <string.h>
27 #include "opintl.h"
28
29 #include <stdarg.h>
30 #include "arc-dis.h"
31 #include "arc-ext.h"
32
33 #ifndef dbg
34 #define dbg (0)
35 #endif
36
37
38 /* Classification of the opcodes for the decoder to print
39 the instructions. */
40
41 typedef enum {
42 CLASS_A4_ARITH,
43 CLASS_A4_OP3_GENERAL,
44 CLASS_A4_FLAG,
45 /* All branches other than JC. */
46 CLASS_A4_BRANCH,
47 CLASS_A4_JC ,
48 /* All loads other than immediate
49 indexed loads. */
50 CLASS_A4_LD0,
51 CLASS_A4_LD1,
52 CLASS_A4_ST,
53 CLASS_A4_SR,
54 /* All single operand instructions. */
55 CLASS_A4_OP3_SUBOPC3F,
56 CLASS_A4_LR
57 } a4_decoding_class;
58
59
60 #define BIT(word,n) ((word) & (1 << n))
61 #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
62 #define OPCODE(word) (BITS ((word), 27, 31))
63 #define FIELDA(word) (BITS ((word), 21, 26))
64 #define FIELDB(word) (BITS ((word), 15, 20))
65 #define FIELDC(word) (BITS ((word), 9, 14))
66
67
68 /* FIELD D is signed in all of its uses, so we make sure argument is
69 treated as signed for bit shifting purposes: */
70 #define FIELDD(word) (BITS (((signed int)word), 0, 8))
71
72 #define PUT_NEXT_WORD_IN(a) \
73 do \
74 { \
75 if (is_limm == 1 && !NEXT_WORD (1)) \
76 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
77 a = state->words[1]; \
78 } \
79 while (0)
80
81 #define CHECK_FLAG_COND_NULLIFY() \
82 do \
83 { \
84 if (is_shimm == 0) \
85 { \
86 flag = BIT (state->words[0], 8); \
87 state->nullifyMode = BITS (state->words[0], 5, 6); \
88 cond = BITS (state->words[0], 0, 4); \
89 } \
90 } \
91 while (0)
92
93 #define CHECK_COND() \
94 do \
95 { \
96 if (is_shimm == 0) \
97 cond = BITS (state->words[0], 0, 4); \
98 } \
99 while (0)
100
101 #define CHECK_FIELD(field) \
102 do \
103 { \
104 if (field == 62) \
105 { \
106 is_limm++; \
107 field##isReg = 0; \
108 PUT_NEXT_WORD_IN (field); \
109 limm_value = field; \
110 } \
111 else if (field > 60) \
112 { \
113 field##isReg = 0; \
114 is_shimm++; \
115 flag = (field == 61); \
116 field = FIELDD (state->words[0]); \
117 } \
118 } \
119 while (0)
120
121 #define CHECK_FIELD_A() \
122 do \
123 { \
124 fieldA = FIELDA (state->words[0]); \
125 if (fieldA > 60) \
126 { \
127 fieldAisReg = 0; \
128 fieldA = 0; \
129 } \
130 } \
131 while (0)
132
133 #define CHECK_FIELD_B() \
134 do \
135 { \
136 fieldB = FIELDB (state->words[0]); \
137 CHECK_FIELD (fieldB); \
138 } \
139 while (0)
140
141 #define CHECK_FIELD_C() \
142 do \
143 { \
144 fieldC = FIELDC (state->words[0]); \
145 CHECK_FIELD (fieldC); \
146 } \
147 while (0)
148
149 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
150 #define IS_REG(x) (field##x##isReg)
151 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
152 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
153 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
154 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
155 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
156 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
157 #define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
158 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
159 (IS_REG (x) ? cb1"%r"ca1 : \
160 usesAuxReg ? cb"%a"ca : \
161 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
162 #define WRITE_FORMAT_RB() strcat (formatString, "]")
163 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
164 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
165
166 #define NEXT_WORD(x) (offset += 4, state->words[x])
167
168 #define add_target(x) (state->targets[state->tcnt++] = (x))
169
170 static char comment_prefix[] = "\t; ";
171
172 static const char *core_reg_name PARAMS ((struct arcDisState *, int));
173 static const char *aux_reg_name PARAMS ((struct arcDisState *, int));
174 static const char *cond_code_name PARAMS ((struct arcDisState *, int));
175 static const char *instruction_name
176 PARAMS ((struct arcDisState *, int, int, int *));
177 static void mwerror PARAMS ((struct arcDisState *, const char *));
178 static const char *post_address PARAMS ((struct arcDisState *, int));
179 static void write_comments_
180 PARAMS ((struct arcDisState *, int, int, long int));
181 static void write_instr_name_
182 PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int));
183 static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *));
184 static const char *_coreRegName PARAMS ((void *, int));
185 static int decodeInstr PARAMS ((bfd_vma, disassemble_info *));
186
187 static const char *
core_reg_name(state,val)188 core_reg_name (state, val)
189 struct arcDisState * state;
190 int val;
191 {
192 if (state->coreRegName)
193 return (*state->coreRegName)(state->_this, val);
194 return 0;
195 }
196
197 static const char *
aux_reg_name(state,val)198 aux_reg_name (state, val)
199 struct arcDisState * state;
200 int val;
201 {
202 if (state->auxRegName)
203 return (*state->auxRegName)(state->_this, val);
204 return 0;
205 }
206
207 static const char *
cond_code_name(state,val)208 cond_code_name (state, val)
209 struct arcDisState * state;
210 int val;
211 {
212 if (state->condCodeName)
213 return (*state->condCodeName)(state->_this, val);
214 return 0;
215 }
216
217 static const char *
instruction_name(state,op1,op2,flags)218 instruction_name (state, op1, op2, flags)
219 struct arcDisState * state;
220 int op1;
221 int op2;
222 int * flags;
223 {
224 if (state->instName)
225 return (*state->instName)(state->_this, op1, op2, flags);
226 return 0;
227 }
228
229 static void
mwerror(state,msg)230 mwerror (state, msg)
231 struct arcDisState * state;
232 const char * msg;
233 {
234 if (state->err != 0)
235 (*state->err)(state->_this, (msg));
236 }
237
238 static const char *
post_address(state,addr)239 post_address (state, addr)
240 struct arcDisState * state;
241 int addr;
242 {
243 static char id[3 * ARRAY_SIZE (state->addresses)];
244 int j, i = state->acnt;
245
246 if (i < ((int) ARRAY_SIZE (state->addresses)))
247 {
248 state->addresses[i] = addr;
249 ++state->acnt;
250 j = i*3;
251 id[j+0] = '@';
252 id[j+1] = '0'+i;
253 id[j+2] = 0;
254
255 return id + j;
256 }
257 return "";
258 }
259
260 static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *,
261 ...));
262
263 static void
my_sprintf(struct arcDisState * state,char * buf,const char * format,...)264 my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
265 ...))
266 {
267 char *bp;
268 const char *p;
269 int size, leading_zero, regMap[2];
270 long auxNum;
271
272 VA_OPEN (ap, format);
273 VA_FIXEDARG (ap, struct arcDisState *, state);
274 VA_FIXEDARG (ap, char *, buf);
275 VA_FIXEDARG (ap, const char *, format);
276
277 bp = buf;
278 *bp = 0;
279 p = format;
280 auxNum = -1;
281 regMap[0] = 0;
282 regMap[1] = 0;
283
284 while (1)
285 switch (*p++)
286 {
287 case 0:
288 goto DOCOMM; /* (return) */
289 default:
290 *bp++ = p[-1];
291 break;
292 case '%':
293 size = 0;
294 leading_zero = 0;
295 RETRY: ;
296 switch (*p++)
297 {
298 case '0':
299 case '1':
300 case '2':
301 case '3':
302 case '4':
303 case '5':
304 case '6':
305 case '7':
306 case '8':
307 case '9':
308 {
309 /* size. */
310 size = p[-1] - '0';
311 if (size == 0)
312 leading_zero = 1; /* e.g. %08x */
313 while (*p >= '0' && *p <= '9')
314 {
315 size = size * 10 + *p - '0';
316 p++;
317 }
318 goto RETRY;
319 }
320 #define inc_bp() bp = bp + strlen (bp)
321
322 case 'h':
323 {
324 unsigned u = va_arg (ap, int);
325
326 /* Hex. We can change the format to 0x%08x in
327 one place, here, if we wish.
328 We add underscores for easy reading. */
329 if (u > 65536)
330 sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
331 else
332 sprintf (bp, "0x%x", u);
333 inc_bp ();
334 }
335 break;
336 case 'X': case 'x':
337 {
338 int val = va_arg (ap, int);
339
340 if (size != 0)
341 if (leading_zero)
342 sprintf (bp, "%0*x", size, val);
343 else
344 sprintf (bp, "%*x", size, val);
345 else
346 sprintf (bp, "%x", val);
347 inc_bp ();
348 }
349 break;
350 case 'd':
351 {
352 int val = va_arg (ap, int);
353
354 if (size != 0)
355 sprintf (bp, "%*d", size, val);
356 else
357 sprintf (bp, "%d", val);
358 inc_bp ();
359 }
360 break;
361 case 'r':
362 {
363 /* Register. */
364 int val = va_arg (ap, int);
365
366 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
367 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
368
369 switch (val)
370 {
371 REG2NAME (26, "gp");
372 REG2NAME (27, "fp");
373 REG2NAME (28, "sp");
374 REG2NAME (29, "ilink1");
375 REG2NAME (30, "ilink2");
376 REG2NAME (31, "blink");
377 REG2NAME (60, "lp_count");
378 default:
379 {
380 const char * ext;
381
382 ext = core_reg_name (state, val);
383 if (ext)
384 sprintf (bp, "%s", ext);
385 else
386 sprintf (bp,"r%d",val);
387 }
388 break;
389 }
390 inc_bp ();
391 } break;
392
393 case 'a':
394 {
395 /* Aux Register. */
396 int val = va_arg (ap, int);
397
398 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
399
400 switch (val)
401 {
402 AUXREG2NAME (0x0, "status");
403 AUXREG2NAME (0x1, "semaphore");
404 AUXREG2NAME (0x2, "lp_start");
405 AUXREG2NAME (0x3, "lp_end");
406 AUXREG2NAME (0x4, "identity");
407 AUXREG2NAME (0x5, "debug");
408 default:
409 {
410 const char *ext;
411
412 ext = aux_reg_name (state, val);
413 if (ext)
414 sprintf (bp, "%s", ext);
415 else
416 my_sprintf (state, bp, "%h", val);
417 }
418 break;
419 }
420 inc_bp ();
421 }
422 break;
423
424 case 's':
425 {
426 sprintf (bp, "%s", va_arg (ap, char *));
427 inc_bp ();
428 }
429 break;
430
431 default:
432 fprintf (stderr, "?? format %c\n", p[-1]);
433 break;
434 }
435 }
436
437 DOCOMM: *bp = 0;
438 VA_CLOSE (ap);
439 }
440
441 static void
write_comments_(state,shimm,is_limm,limm_value)442 write_comments_(state, shimm, is_limm, limm_value)
443 struct arcDisState * state;
444 int shimm;
445 int is_limm;
446 long limm_value;
447 {
448 if (state->commentBuffer != 0)
449 {
450 int i;
451
452 if (is_limm)
453 {
454 const char *name = post_address (state, limm_value + shimm);
455
456 if (*name != 0)
457 WRITE_COMMENT (name);
458 }
459 for (i = 0; i < state->commNum; i++)
460 {
461 if (i == 0)
462 strcpy (state->commentBuffer, comment_prefix);
463 else
464 strcat (state->commentBuffer, ", ");
465 strncat (state->commentBuffer, state->comm[i],
466 sizeof (state->commentBuffer));
467 }
468 }
469 }
470
471 #define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
472 #define write_comments() write_comments2(0)
473
474 static const char *condName[] = {
475 /* 0..15. */
476 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
477 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
478 };
479
480 static void
write_instr_name_(state,instrName,cond,condCodeIsPartOfName,flag,signExtend,addrWriteBack,directMem)481 write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
482 struct arcDisState * state;
483 const char * instrName;
484 int cond;
485 int condCodeIsPartOfName;
486 int flag;
487 int signExtend;
488 int addrWriteBack;
489 int directMem;
490 {
491 strcpy (state->instrBuffer, instrName);
492
493 if (cond > 0)
494 {
495 const char *cc = 0;
496
497 if (!condCodeIsPartOfName)
498 strcat (state->instrBuffer, ".");
499
500 if (cond < 16)
501 cc = condName[cond];
502 else
503 cc = cond_code_name (state, cond);
504
505 if (!cc)
506 cc = "???";
507
508 strcat (state->instrBuffer, cc);
509 }
510
511 if (flag)
512 strcat (state->instrBuffer, ".f");
513
514 switch (state->nullifyMode)
515 {
516 case BR_exec_always:
517 strcat (state->instrBuffer, ".d");
518 break;
519 case BR_exec_when_jump:
520 strcat (state->instrBuffer, ".jd");
521 break;
522 }
523
524 if (signExtend)
525 strcat (state->instrBuffer, ".x");
526
527 if (addrWriteBack)
528 strcat (state->instrBuffer, ".a");
529
530 if (directMem)
531 strcat (state->instrBuffer, ".di");
532 }
533
534 #define write_instr_name() \
535 do \
536 { \
537 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
538 flag, signExtend, addrWriteBack, directMem); \
539 formatString[0] = '\0'; \
540 } \
541 while (0)
542
543 enum {
544 op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
545 op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
546 op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
547 op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
548 };
549
550 extern disassemble_info tm_print_insn_info;
551
552 static int
dsmOneArcInst(addr,state)553 dsmOneArcInst (addr, state)
554 bfd_vma addr;
555 struct arcDisState * state;
556 {
557 int condCodeIsPartOfName = 0;
558 a4_decoding_class decodingClass;
559 const char * instrName;
560 int repeatsOp = 0;
561 int fieldAisReg = 1;
562 int fieldBisReg = 1;
563 int fieldCisReg = 1;
564 int fieldA;
565 int fieldB;
566 int fieldC = 0;
567 int flag = 0;
568 int cond = 0;
569 int is_shimm = 0;
570 int is_limm = 0;
571 long limm_value = 0;
572 int signExtend = 0;
573 int addrWriteBack = 0;
574 int directMem = 0;
575 int is_linked = 0;
576 int offset = 0;
577 int usesAuxReg = 0;
578 int flags;
579 int ignoreFirstOpd;
580 char formatString[60];
581
582 state->instructionLen = 4;
583 state->nullifyMode = BR_exec_when_no_jump;
584 state->opWidth = 12;
585 state->isBranch = 0;
586
587 state->_mem_load = 0;
588 state->_ea_present = 0;
589 state->_load_len = 0;
590 state->ea_reg1 = no_reg;
591 state->ea_reg2 = no_reg;
592 state->_offset = 0;
593
594 if (! NEXT_WORD (0))
595 return 0;
596
597 state->_opcode = OPCODE (state->words[0]);
598 instrName = 0;
599 decodingClass = CLASS_A4_ARITH; /* default! */
600 repeatsOp = 0;
601 condCodeIsPartOfName=0;
602 state->commNum = 0;
603 state->tcnt = 0;
604 state->acnt = 0;
605 state->flow = noflow;
606 ignoreFirstOpd = 0;
607
608 if (state->commentBuffer)
609 state->commentBuffer[0] = '\0';
610
611 switch (state->_opcode)
612 {
613 case op_LD0:
614 switch (BITS (state->words[0],1,2))
615 {
616 case 0:
617 instrName = "ld";
618 state->_load_len = 4;
619 break;
620 case 1:
621 instrName = "ldb";
622 state->_load_len = 1;
623 break;
624 case 2:
625 instrName = "ldw";
626 state->_load_len = 2;
627 break;
628 default:
629 instrName = "??? (0[3])";
630 state->flow = invalid_instr;
631 break;
632 }
633 decodingClass = CLASS_A4_LD0;
634 break;
635
636 case op_LD1:
637 if (BIT (state->words[0],13))
638 {
639 instrName = "lr";
640 decodingClass = CLASS_A4_LR;
641 }
642 else
643 {
644 switch (BITS (state->words[0],10,11))
645 {
646 case 0:
647 instrName = "ld";
648 state->_load_len = 4;
649 break;
650 case 1:
651 instrName = "ldb";
652 state->_load_len = 1;
653 break;
654 case 2:
655 instrName = "ldw";
656 state->_load_len = 2;
657 break;
658 default:
659 instrName = "??? (1[3])";
660 state->flow = invalid_instr;
661 break;
662 }
663 decodingClass = CLASS_A4_LD1;
664 }
665 break;
666
667 case op_ST:
668 if (BIT (state->words[0],25))
669 {
670 instrName = "sr";
671 decodingClass = CLASS_A4_SR;
672 }
673 else
674 {
675 switch (BITS (state->words[0],22,23))
676 {
677 case 0:
678 instrName = "st";
679 break;
680 case 1:
681 instrName = "stb";
682 break;
683 case 2:
684 instrName = "stw";
685 break;
686 default:
687 instrName = "??? (2[3])";
688 state->flow = invalid_instr;
689 break;
690 }
691 decodingClass = CLASS_A4_ST;
692 }
693 break;
694
695 case op_3:
696 decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */
697 switch (FIELDC (state->words[0]))
698 {
699 case 0:
700 instrName = "flag";
701 decodingClass = CLASS_A4_FLAG;
702 break;
703 case 1:
704 instrName = "asr";
705 break;
706 case 2:
707 instrName = "lsr";
708 break;
709 case 3:
710 instrName = "ror";
711 break;
712 case 4:
713 instrName = "rrc";
714 break;
715 case 5:
716 instrName = "sexb";
717 break;
718 case 6:
719 instrName = "sexw";
720 break;
721 case 7:
722 instrName = "extb";
723 break;
724 case 8:
725 instrName = "extw";
726 break;
727 case 0x3f:
728 {
729 decodingClass = CLASS_A4_OP3_SUBOPC3F;
730 switch( FIELDD (state->words[0]) )
731 {
732 case 0:
733 instrName = "brk";
734 break;
735 case 1:
736 instrName = "sleep";
737 break;
738 case 2:
739 instrName = "swi";
740 break;
741 default:
742 instrName = "???";
743 state->flow=invalid_instr;
744 break;
745 }
746 }
747 break;
748
749 /* ARC Extension Library Instructions
750 NOTE: We assume that extension codes are these instrs. */
751 default:
752 instrName = instruction_name (state,
753 state->_opcode,
754 FIELDC (state->words[0]),
755 &flags);
756 if (!instrName)
757 {
758 instrName = "???";
759 state->flow = invalid_instr;
760 }
761 if (flags & IGNORE_FIRST_OPD)
762 ignoreFirstOpd = 1;
763 break;
764 }
765 break;
766
767 case op_BC:
768 instrName = "b";
769 case op_BLC:
770 if (!instrName)
771 instrName = "bl";
772 case op_LPC:
773 if (!instrName)
774 instrName = "lp";
775 case op_JC:
776 if (!instrName)
777 {
778 if (BITS (state->words[0],9,9))
779 {
780 instrName = "jl";
781 is_linked = 1;
782 }
783 else
784 {
785 instrName = "j";
786 is_linked = 0;
787 }
788 }
789 condCodeIsPartOfName = 1;
790 decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
791 state->isBranch = 1;
792 break;
793
794 case op_ADD:
795 case op_ADC:
796 case op_AND:
797 repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
798
799 switch (state->_opcode)
800 {
801 case op_ADD:
802 instrName = (repeatsOp ? "asl" : "add");
803 break;
804 case op_ADC:
805 instrName = (repeatsOp ? "rlc" : "adc");
806 break;
807 case op_AND:
808 instrName = (repeatsOp ? "mov" : "and");
809 break;
810 }
811 break;
812
813 case op_SUB: instrName = "sub";
814 break;
815 case op_SBC: instrName = "sbc";
816 break;
817 case op_OR: instrName = "or";
818 break;
819 case op_BIC: instrName = "bic";
820 break;
821
822 case op_XOR:
823 if (state->words[0] == 0x7fffffff)
824 {
825 /* nop encoded as xor -1, -1, -1 */
826 instrName = "nop";
827 decodingClass = CLASS_A4_OP3_SUBOPC3F;
828 }
829 else
830 instrName = "xor";
831 break;
832
833 default:
834 instrName = instruction_name (state,state->_opcode,0,&flags);
835 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
836 if (!instrName)
837 {
838 instrName = "???";
839 state->flow=invalid_instr;
840 }
841 if (flags & IGNORE_FIRST_OPD)
842 ignoreFirstOpd = 1;
843 break;
844 }
845
846 fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
847 flag = cond = is_shimm = is_limm = 0;
848 state->nullifyMode = BR_exec_when_no_jump; /* 0 */
849 signExtend = addrWriteBack = directMem = 0;
850 usesAuxReg = 0;
851
852 switch (decodingClass)
853 {
854 case CLASS_A4_ARITH:
855 CHECK_FIELD_A ();
856 CHECK_FIELD_B ();
857 if (!repeatsOp)
858 CHECK_FIELD_C ();
859 CHECK_FLAG_COND_NULLIFY ();
860
861 write_instr_name ();
862 if (!ignoreFirstOpd)
863 {
864 WRITE_FORMAT_x (A);
865 WRITE_FORMAT_COMMA_x (B);
866 if (!repeatsOp)
867 WRITE_FORMAT_COMMA_x (C);
868 WRITE_NOP_COMMENT ();
869 my_sprintf (state, state->operandBuffer, formatString,
870 fieldA, fieldB, fieldC);
871 }
872 else
873 {
874 WRITE_FORMAT_x (B);
875 if (!repeatsOp)
876 WRITE_FORMAT_COMMA_x (C);
877 my_sprintf (state, state->operandBuffer, formatString,
878 fieldB, fieldC);
879 }
880 write_comments ();
881 break;
882
883 case CLASS_A4_OP3_GENERAL:
884 CHECK_FIELD_A ();
885 CHECK_FIELD_B ();
886 CHECK_FLAG_COND_NULLIFY ();
887
888 write_instr_name ();
889 if (!ignoreFirstOpd)
890 {
891 WRITE_FORMAT_x (A);
892 WRITE_FORMAT_COMMA_x (B);
893 WRITE_NOP_COMMENT ();
894 my_sprintf (state, state->operandBuffer, formatString,
895 fieldA, fieldB);
896 }
897 else
898 {
899 WRITE_FORMAT_x (B);
900 my_sprintf (state, state->operandBuffer, formatString, fieldB);
901 }
902 write_comments ();
903 break;
904
905 case CLASS_A4_FLAG:
906 CHECK_FIELD_B ();
907 CHECK_FLAG_COND_NULLIFY ();
908 flag = 0; /* this is the FLAG instruction -- it's redundant */
909
910 write_instr_name ();
911 WRITE_FORMAT_x (B);
912 my_sprintf (state, state->operandBuffer, formatString, fieldB);
913 write_comments ();
914 break;
915
916 case CLASS_A4_BRANCH:
917 fieldA = BITS (state->words[0],7,26) << 2;
918 fieldA = (fieldA << 10) >> 10; /* make it signed */
919 fieldA += addr + 4;
920 CHECK_FLAG_COND_NULLIFY ();
921 flag = 0;
922
923 write_instr_name ();
924 /* This address could be a label we know. Convert it. */
925 if (state->_opcode != op_LPC /* LP */)
926 {
927 add_target (fieldA); /* For debugger. */
928 state->flow = state->_opcode == op_BLC /* BL */
929 ? direct_call
930 : direct_jump;
931 /* indirect calls are achieved by "lr blink,[status];
932 lr dest<- func addr; j [dest]" */
933 }
934
935 strcat (formatString, "%s"); /* address/label name */
936 my_sprintf (state, state->operandBuffer, formatString,
937 post_address (state, fieldA));
938 write_comments ();
939 break;
940
941 case CLASS_A4_JC:
942 /* For op_JC -- jump to address specified.
943 Also covers jump and link--bit 9 of the instr. word
944 selects whether linked, thus "is_linked" is set above. */
945 fieldA = 0;
946 CHECK_FIELD_B ();
947 CHECK_FLAG_COND_NULLIFY ();
948
949 if (!fieldBisReg)
950 {
951 fieldAisReg = 0;
952 fieldA = (fieldB >> 25) & 0x7F; /* flags */
953 fieldB = (fieldB & 0xFFFFFF) << 2;
954 state->flow = is_linked ? direct_call : direct_jump;
955 add_target (fieldB);
956 /* screwy JLcc requires .jd mode to execute correctly
957 * but we pretend it is .nd (no delay slot). */
958 if (is_linked && state->nullifyMode == BR_exec_when_jump)
959 state->nullifyMode = BR_exec_when_no_jump;
960 }
961 else
962 {
963 state->flow = is_linked ? indirect_call : indirect_jump;
964 /* We should also treat this as indirect call if NOT linked
965 * but the preceding instruction was a "lr blink,[status]"
966 * and we have a delay slot with "add blink,blink,2".
967 * For now we can't detect such. */
968 state->register_for_indirect_jump = fieldB;
969 }
970
971 write_instr_name ();
972 strcat (formatString,
973 IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
974 if (fieldA != 0)
975 {
976 fieldAisReg = 0;
977 WRITE_FORMAT_COMMA_x (A);
978 }
979 if (IS_REG (B))
980 my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
981 else
982 my_sprintf (state, state->operandBuffer, formatString,
983 post_address (state, fieldB), fieldA);
984 write_comments ();
985 break;
986
987 case CLASS_A4_LD0:
988 /* LD instruction.
989 B and C can be regs, or one (both?) can be limm. */
990 CHECK_FIELD_A ();
991 CHECK_FIELD_B ();
992 CHECK_FIELD_C ();
993 if (dbg)
994 printf ("5:b reg %d %d c reg %d %d \n",
995 fieldBisReg,fieldB,fieldCisReg,fieldC);
996 state->_offset = 0;
997 state->_ea_present = 1;
998 if (fieldBisReg)
999 state->ea_reg1 = fieldB;
1000 else
1001 state->_offset += fieldB;
1002 if (fieldCisReg)
1003 state->ea_reg2 = fieldC;
1004 else
1005 state->_offset += fieldC;
1006 state->_mem_load = 1;
1007
1008 directMem = BIT (state->words[0],5);
1009 addrWriteBack = BIT (state->words[0],3);
1010 signExtend = BIT (state->words[0],0);
1011
1012 write_instr_name ();
1013 WRITE_FORMAT_x_COMMA_LB(A);
1014 if (fieldBisReg || fieldB != 0)
1015 WRITE_FORMAT_x_COMMA (B);
1016 else
1017 fieldB = fieldC;
1018
1019 WRITE_FORMAT_x_RB (C);
1020 my_sprintf (state, state->operandBuffer, formatString,
1021 fieldA, fieldB, fieldC);
1022 write_comments ();
1023 break;
1024
1025 case CLASS_A4_LD1:
1026 /* LD instruction. */
1027 CHECK_FIELD_B ();
1028 CHECK_FIELD_A ();
1029 fieldC = FIELDD (state->words[0]);
1030
1031 if (dbg)
1032 printf ("6:b reg %d %d c 0x%x \n",
1033 fieldBisReg, fieldB, fieldC);
1034 state->_ea_present = 1;
1035 state->_offset = fieldC;
1036 state->_mem_load = 1;
1037 if (fieldBisReg)
1038 state->ea_reg1 = fieldB;
1039 /* field B is either a shimm (same as fieldC) or limm (different!)
1040 Say ea is not present, so only one of us will do the name lookup. */
1041 else
1042 state->_offset += fieldB, state->_ea_present = 0;
1043
1044 directMem = BIT (state->words[0],14);
1045 addrWriteBack = BIT (state->words[0],12);
1046 signExtend = BIT (state->words[0],9);
1047
1048 write_instr_name ();
1049 WRITE_FORMAT_x_COMMA_LB (A);
1050 if (!fieldBisReg)
1051 {
1052 fieldB = state->_offset;
1053 WRITE_FORMAT_x_RB (B);
1054 }
1055 else
1056 {
1057 WRITE_FORMAT_x (B);
1058 if (fieldC != 0 && !BIT (state->words[0],13))
1059 {
1060 fieldCisReg = 0;
1061 WRITE_FORMAT_COMMA_x_RB (C);
1062 }
1063 else
1064 WRITE_FORMAT_RB ();
1065 }
1066 my_sprintf (state, state->operandBuffer, formatString,
1067 fieldA, fieldB, fieldC);
1068 write_comments ();
1069 break;
1070
1071 case CLASS_A4_ST:
1072 /* ST instruction. */
1073 CHECK_FIELD_B();
1074 CHECK_FIELD_C();
1075 fieldA = FIELDD(state->words[0]); /* shimm */
1076
1077 /* [B,A offset] */
1078 if (dbg) printf("7:b reg %d %x off %x\n",
1079 fieldBisReg,fieldB,fieldA);
1080 state->_ea_present = 1;
1081 state->_offset = fieldA;
1082 if (fieldBisReg)
1083 state->ea_reg1 = fieldB;
1084 /* field B is either a shimm (same as fieldA) or limm (different!)
1085 Say ea is not present, so only one of us will do the name lookup.
1086 (for is_limm we do the name translation here). */
1087 else
1088 state->_offset += fieldB, state->_ea_present = 0;
1089
1090 directMem = BIT(state->words[0],26);
1091 addrWriteBack = BIT(state->words[0],24);
1092
1093 write_instr_name();
1094 WRITE_FORMAT_x_COMMA_LB(C);
1095
1096 if (!fieldBisReg)
1097 {
1098 fieldB = state->_offset;
1099 WRITE_FORMAT_x_RB(B);
1100 }
1101 else
1102 {
1103 WRITE_FORMAT_x(B);
1104 if (fieldBisReg && fieldA != 0)
1105 {
1106 fieldAisReg = 0;
1107 WRITE_FORMAT_COMMA_x_RB(A);
1108 }
1109 else
1110 WRITE_FORMAT_RB();
1111 }
1112 my_sprintf (state, state->operandBuffer, formatString,
1113 fieldC, fieldB, fieldA);
1114 write_comments2(fieldA);
1115 break;
1116
1117 case CLASS_A4_SR:
1118 /* SR instruction */
1119 CHECK_FIELD_B();
1120 CHECK_FIELD_C();
1121
1122 write_instr_name();
1123 WRITE_FORMAT_x_COMMA_LB(C);
1124 /* Try to print B as an aux reg if it is not a core reg. */
1125 usesAuxReg = 1;
1126 WRITE_FORMAT_x(B);
1127 WRITE_FORMAT_RB();
1128 my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1129 write_comments();
1130 break;
1131
1132 case CLASS_A4_OP3_SUBOPC3F:
1133 write_instr_name();
1134 state->operandBuffer[0] = '\0';
1135 break;
1136
1137 case CLASS_A4_LR:
1138 /* LR instruction */
1139 CHECK_FIELD_A();
1140 CHECK_FIELD_B();
1141
1142 write_instr_name();
1143 WRITE_FORMAT_x_COMMA_LB(A);
1144 /* Try to print B as an aux reg if it is not a core reg. */
1145 usesAuxReg = 1;
1146 WRITE_FORMAT_x(B);
1147 WRITE_FORMAT_RB();
1148 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1149 write_comments();
1150 break;
1151
1152
1153 default:
1154 mwerror (state, "Bad decoding class in ARC disassembler");
1155 break;
1156 }
1157
1158 state->_cond = cond;
1159 return state->instructionLen = offset;
1160 }
1161
1162
1163 /* Returns the name the user specified core extension register. */
1164 static const char *
_coreRegName(arg,regval)1165 _coreRegName(arg, regval)
1166 void * arg ATTRIBUTE_UNUSED;
1167 int regval;
1168 {
1169 return arcExtMap_coreRegName (regval);
1170 }
1171
1172 /* Returns the name the user specified AUX extension register. */
1173 static const char *
_auxRegName(void * _this ATTRIBUTE_UNUSED,int regval)1174 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
1175 {
1176 return arcExtMap_auxRegName(regval);
1177 }
1178
1179
1180 /* Returns the name the user specified condition code name. */
1181 static const char *
_condCodeName(void * _this ATTRIBUTE_UNUSED,int regval)1182 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
1183 {
1184 return arcExtMap_condCodeName(regval);
1185 }
1186
1187 /* Returns the name the user specified extension instruction. */
1188 static const char *
_instName(void * _this ATTRIBUTE_UNUSED,int majop,int minop,int * flags)1189 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
1190 {
1191 return arcExtMap_instName(majop, minop, flags);
1192 }
1193
1194 /* Decode an instruction returning the size of the instruction
1195 in bytes or zero if unrecognized. */
1196 static int
decodeInstr(address,info)1197 decodeInstr (address, info)
1198 bfd_vma address; /* Address of this instruction. */
1199 disassemble_info * info;
1200 {
1201 int status;
1202 bfd_byte buffer[4];
1203 struct arcDisState s; /* ARC Disassembler state */
1204 void *stream = info->stream; /* output stream */
1205 fprintf_ftype func = info->fprintf_func;
1206 int bytes;
1207
1208 memset (&s, 0, sizeof(struct arcDisState));
1209
1210 /* read first instruction */
1211 status = (*info->read_memory_func) (address, buffer, 4, info);
1212 if (status != 0)
1213 {
1214 (*info->memory_error_func) (status, address, info);
1215 return 0;
1216 }
1217 if (info->endian == BFD_ENDIAN_LITTLE)
1218 s.words[0] = bfd_getl32(buffer);
1219 else
1220 s.words[0] = bfd_getb32(buffer);
1221 /* always read second word in case of limm */
1222
1223 /* we ignore the result since last insn may not have a limm */
1224 status = (*info->read_memory_func) (address + 4, buffer, 4, info);
1225 if (info->endian == BFD_ENDIAN_LITTLE)
1226 s.words[1] = bfd_getl32(buffer);
1227 else
1228 s.words[1] = bfd_getb32(buffer);
1229
1230 s._this = &s;
1231 s.coreRegName = _coreRegName;
1232 s.auxRegName = _auxRegName;
1233 s.condCodeName = _condCodeName;
1234 s.instName = _instName;
1235
1236 /* disassemble */
1237 bytes = dsmOneArcInst(address, (void *)&s);
1238
1239 /* display the disassembly instruction */
1240 (*func) (stream, "%08x ", s.words[0]);
1241 (*func) (stream, " ");
1242
1243 (*func) (stream, "%-10s ", s.instrBuffer);
1244
1245 if (__TRANSLATION_REQUIRED(s))
1246 {
1247 bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
1248 (*info->print_address_func) ((bfd_vma) addr, info);
1249 (*func) (stream, "\n");
1250 }
1251 else
1252 (*func) (stream, "%s",s.operandBuffer);
1253 return s.instructionLen;
1254 }
1255
1256 /* Return the print_insn function to use.
1257 Side effect: load (possibly empty) extension section */
1258
1259 disassembler_ftype
arc_get_disassembler(void * ptr)1260 arc_get_disassembler (void *ptr)
1261 {
1262 if (ptr)
1263 build_ARC_extmap (ptr);
1264 return decodeInstr;
1265 }
1266