1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <stdio.h>
24 #include "sysdep.h"
25 #include "opcode/ppc.h"
26 #include "opintl.h"
27
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39 /* Local insertion and extraction functions. */
40
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bd (unsigned long, long, int, const char **);
46 static long extract_bd (unsigned long, int, int *);
47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
48 static long extract_bdm (unsigned long, int, int *);
49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
50 static long extract_bdp (unsigned long, int, int *);
51 static unsigned long insert_bo (unsigned long, long, int, const char **);
52 static long extract_bo (unsigned long, int, int *);
53 static unsigned long insert_boe (unsigned long, long, int, const char **);
54 static long extract_boe (unsigned long, int, int *);
55 static unsigned long insert_dq (unsigned long, long, int, const char **);
56 static long extract_dq (unsigned long, int, int *);
57 static unsigned long insert_ds (unsigned long, long, int, const char **);
58 static long extract_ds (unsigned long, int, int *);
59 static unsigned long insert_de (unsigned long, long, int, const char **);
60 static long extract_de (unsigned long, int, int *);
61 static unsigned long insert_des (unsigned long, long, int, const char **);
62 static long extract_des (unsigned long, int, int *);
63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
64 static long extract_fxm (unsigned long, int, int *);
65 static unsigned long insert_li (unsigned long, long, int, const char **);
66 static long extract_li (unsigned long, int, int *);
67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
68 static long extract_mbe (unsigned long, int, int *);
69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70 static long extract_mb6 (unsigned long, int, int *);
71 static unsigned long insert_nb (unsigned long, long, int, const char **);
72 static long extract_nb (unsigned long, int, int *);
73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
74 static long extract_nsi (unsigned long, int, int *);
75 static unsigned long insert_ral (unsigned long, long, int, const char **);
76 static unsigned long insert_ram (unsigned long, long, int, const char **);
77 static unsigned long insert_raq (unsigned long, long, int, const char **);
78 static unsigned long insert_ras (unsigned long, long, int, const char **);
79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
80 static long extract_rbs (unsigned long, int, int *);
81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84 static long extract_sh6 (unsigned long, int, int *);
85 static unsigned long insert_spr (unsigned long, long, int, const char **);
86 static long extract_spr (unsigned long, int, int *);
87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
88 static long extract_tbr (unsigned long, int, int *);
89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
90 static long extract_ev2 (unsigned long, int, int *);
91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
92 static long extract_ev4 (unsigned long, int, int *);
93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
94 static long extract_ev8 (unsigned long, int, int *);
95
96 /* The operands table.
97
98 The fields are bits, shift, insert, extract, flags.
99
100 We used to put parens around the various additions, like the one
101 for BA just below. However, that caused trouble with feeble
102 compilers with a limit on depth of a parenthesized expression, like
103 (reportedly) the compiler in Microsoft Developer Studio 5. So we
104 omit the parens, since the macros are never used in a context where
105 the addition will be ambiguous. */
106
107 const struct powerpc_operand powerpc_operands[] =
108 {
109 /* The zero index is used to indicate the end of the list of
110 operands. */
111 #define UNUSED 0
112 { 0, 0, NULL, NULL, 0 },
113
114 /* The BA field in an XL form instruction. */
115 #define BA UNUSED + 1
116 #define BA_MASK (0x1f << 16)
117 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
118
119 /* The BA field in an XL form instruction when it must be the same
120 as the BT field in the same instruction. */
121 #define BAT BA + 1
122 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
123
124 /* The BB field in an XL form instruction. */
125 #define BB BAT + 1
126 #define BB_MASK (0x1f << 11)
127 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
128
129 /* The BB field in an XL form instruction when it must be the same
130 as the BA field in the same instruction. */
131 #define BBA BB + 1
132 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
133
134 /* The BD field in a B form instruction. The lower two bits are
135 forced to zero. */
136 #define BD BBA + 1
137 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
138
139 /* The BD field in a B form instruction when absolute addressing is
140 used. */
141 #define BDA BD + 1
142 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
143
144 /* The BD field in a B form instruction when the - modifier is used.
145 This sets the y bit of the BO field appropriately. */
146 #define BDM BDA + 1
147 { 16, 0, insert_bdm, extract_bdm,
148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
149
150 /* The BD field in a B form instruction when the - modifier is used
151 and absolute address is used. */
152 #define BDMA BDM + 1
153 { 16, 0, insert_bdm, extract_bdm,
154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
155
156 /* The BD field in a B form instruction when the + modifier is used.
157 This sets the y bit of the BO field appropriately. */
158 #define BDP BDMA + 1
159 { 16, 0, insert_bdp, extract_bdp,
160 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
161
162 /* The BD field in a B form instruction when the + modifier is used
163 and absolute addressing is used. */
164 #define BDPA BDP + 1
165 { 16, 0, insert_bdp, extract_bdp,
166 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
167
168 /* The BF field in an X or XL form instruction. */
169 #define BF BDPA + 1
170 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
171
172 /* An optional BF field. This is used for comparison instructions,
173 in which an omitted BF field is taken as zero. */
174 #define OBF BF + 1
175 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
176
177 /* The BFA field in an X or XL form instruction. */
178 #define BFA OBF + 1
179 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
180
181 /* The BI field in a B form or XL form instruction. */
182 #define BI BFA + 1
183 #define BI_MASK (0x1f << 16)
184 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
185
186 /* The BO field in a B form instruction. Certain values are
187 illegal. */
188 #define BO BI + 1
189 #define BO_MASK (0x1f << 21)
190 { 5, 21, insert_bo, extract_bo, 0 },
191
192 /* The BO field in a B form instruction when the + or - modifier is
193 used. This is like the BO field, but it must be even. */
194 #define BOE BO + 1
195 { 5, 21, insert_boe, extract_boe, 0 },
196
197 #define BH BOE + 1
198 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
199
200 /* The BT field in an X or XL form instruction. */
201 #define BT BH + 1
202 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
203
204 /* The condition register number portion of the BI field in a B form
205 or XL form instruction. This is used for the extended
206 conditional branch mnemonics, which set the lower two bits of the
207 BI field. This field is optional. */
208 #define CR BT + 1
209 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
210
211 /* The CRB field in an X form instruction. */
212 #define CRB CR + 1
213 { 5, 6, NULL, NULL, 0 },
214
215 /* The CRFD field in an X form instruction. */
216 #define CRFD CRB + 1
217 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
218
219 /* The CRFS field in an X form instruction. */
220 #define CRFS CRFD + 1
221 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
222
223 /* The CT field in an X form instruction. */
224 #define CT CRFS + 1
225 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
226
227 /* The D field in a D form instruction. This is a displacement off
228 a register, and implies that the next operand is a register in
229 parentheses. */
230 #define D CT + 1
231 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
232
233 /* The DE field in a DE form instruction. This is like D, but is 12
234 bits only. */
235 #define DE D + 1
236 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
237
238 /* The DES field in a DES form instruction. This is like DS, but is 14
239 bits only (12 stored.) */
240 #define DES DE + 1
241 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
242
243 /* The DQ field in a DQ form instruction. This is like D, but the
244 lower four bits are forced to zero. */
245 #define DQ DES + 1
246 { 16, 0, insert_dq, extract_dq,
247 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
248
249 /* The DS field in a DS form instruction. This is like D, but the
250 lower two bits are forced to zero. */
251 #define DS DQ + 1
252 { 16, 0, insert_ds, extract_ds,
253 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
254
255 /* The E field in a wrteei instruction. */
256 #define E DS + 1
257 { 1, 15, NULL, NULL, 0 },
258
259 /* The FL1 field in a POWER SC form instruction. */
260 #define FL1 E + 1
261 { 4, 12, NULL, NULL, 0 },
262
263 /* The FL2 field in a POWER SC form instruction. */
264 #define FL2 FL1 + 1
265 { 3, 2, NULL, NULL, 0 },
266
267 /* The FLM field in an XFL form instruction. */
268 #define FLM FL2 + 1
269 { 8, 17, NULL, NULL, 0 },
270
271 /* The FRA field in an X or A form instruction. */
272 #define FRA FLM + 1
273 #define FRA_MASK (0x1f << 16)
274 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
275
276 /* The FRB field in an X or A form instruction. */
277 #define FRB FRA + 1
278 #define FRB_MASK (0x1f << 11)
279 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
280
281 /* The FRC field in an A form instruction. */
282 #define FRC FRB + 1
283 #define FRC_MASK (0x1f << 6)
284 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
285
286 /* The FRS field in an X form instruction or the FRT field in a D, X
287 or A form instruction. */
288 #define FRS FRC + 1
289 #define FRT FRS
290 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
291
292 /* The FXM field in an XFX instruction. */
293 #define FXM FRS + 1
294 #define FXM_MASK (0xff << 12)
295 { 8, 12, insert_fxm, extract_fxm, 0 },
296
297 /* Power4 version for mfcr. */
298 #define FXM4 FXM + 1
299 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
300
301 /* The L field in a D or X form instruction. */
302 #define L FXM4 + 1
303 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
304
305 /* The LEV field in a POWER SC form instruction. */
306 #define LEV L + 1
307 { 7, 5, NULL, NULL, 0 },
308
309 /* The LI field in an I form instruction. The lower two bits are
310 forced to zero. */
311 #define LI LEV + 1
312 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
313
314 /* The LI field in an I form instruction when used as an absolute
315 address. */
316 #define LIA LI + 1
317 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
318
319 /* The LS field in an X (sync) form instruction. */
320 #define LS LIA + 1
321 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
322
323 /* The MB field in an M form instruction. */
324 #define MB LS + 1
325 #define MB_MASK (0x1f << 6)
326 { 5, 6, NULL, NULL, 0 },
327
328 /* The ME field in an M form instruction. */
329 #define ME MB + 1
330 #define ME_MASK (0x1f << 1)
331 { 5, 1, NULL, NULL, 0 },
332
333 /* The MB and ME fields in an M form instruction expressed a single
334 operand which is a bitmask indicating which bits to select. This
335 is a two operand form using PPC_OPERAND_NEXT. See the
336 description in opcode/ppc.h for what this means. */
337 #define MBE ME + 1
338 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
339 { 32, 0, insert_mbe, extract_mbe, 0 },
340
341 /* The MB or ME field in an MD or MDS form instruction. The high
342 bit is wrapped to the low end. */
343 #define MB6 MBE + 2
344 #define ME6 MB6
345 #define MB6_MASK (0x3f << 5)
346 { 6, 5, insert_mb6, extract_mb6, 0 },
347
348 /* The MO field in an mbar instruction. */
349 #define MO MB6 + 1
350 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
351
352 /* The NB field in an X form instruction. The value 32 is stored as
353 0. */
354 #define NB MO + 1
355 { 6, 11, insert_nb, extract_nb, 0 },
356
357 /* The NSI field in a D form instruction. This is the same as the
358 SI field, only negated. */
359 #define NSI NB + 1
360 { 16, 0, insert_nsi, extract_nsi,
361 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
362
363 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
364 #define RA NSI + 1
365 #define RA_MASK (0x1f << 16)
366 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
367
368 /* As above, but 0 in the RA field means zero, not r0. */
369 #define RA0 RA + 1
370 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
371
372 /* The RA field in the DQ form lq instruction, which has special
373 value restrictions. */
374 #define RAQ RA0 + 1
375 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
376
377 /* The RA field in a D or X form instruction which is an updating
378 load, which means that the RA field may not be zero and may not
379 equal the RT field. */
380 #define RAL RAQ + 1
381 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
382
383 /* The RA field in an lmw instruction, which has special value
384 restrictions. */
385 #define RAM RAL + 1
386 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
387
388 /* The RA field in a D or X form instruction which is an updating
389 store or an updating floating point load, which means that the RA
390 field may not be zero. */
391 #define RAS RAM + 1
392 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
393
394 /* The RA field of the tlbwe instruction, which is optional. */
395 #define RAOPT RAS + 1
396 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
397
398 /* The RB field in an X, XO, M, or MDS form instruction. */
399 #define RB RAOPT + 1
400 #define RB_MASK (0x1f << 11)
401 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
402
403 /* The RB field in an X form instruction when it must be the same as
404 the RS field in the instruction. This is used for extended
405 mnemonics like mr. */
406 #define RBS RB + 1
407 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
408
409 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
410 instruction or the RT field in a D, DS, X, XFX or XO form
411 instruction. */
412 #define RS RBS + 1
413 #define RT RS
414 #define RT_MASK (0x1f << 21)
415 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
416
417 /* The RS field of the DS form stq instruction, which has special
418 value restrictions. */
419 #define RSQ RS + 1
420 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
421
422 /* The RT field of the DQ form lq instruction, which has special
423 value restrictions. */
424 #define RTQ RSQ + 1
425 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
426
427 /* The RS field of the tlbwe instruction, which is optional. */
428 #define RSO RTQ + 1
429 #define RTO RSO
430 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
431
432 /* The SH field in an X or M form instruction. */
433 #define SH RSO + 1
434 #define SH_MASK (0x1f << 11)
435 { 5, 11, NULL, NULL, 0 },
436
437 /* The SH field in an MD form instruction. This is split. */
438 #define SH6 SH + 1
439 #define SH6_MASK ((0x1f << 11) | (1 << 1))
440 { 6, 1, insert_sh6, extract_sh6, 0 },
441
442 /* The SH field of the tlbwe instruction, which is optional. */
443 #define SHO SH6 + 1
444 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
445
446 /* The SI field in a D form instruction. */
447 #define SI SHO + 1
448 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
449
450 /* The SI field in a D form instruction when we accept a wide range
451 of positive values. */
452 #define SISIGNOPT SI + 1
453 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
454
455 /* The SPR field in an XFX form instruction. This is flipped--the
456 lower 5 bits are stored in the upper 5 and vice- versa. */
457 #define SPR SISIGNOPT + 1
458 #define PMR SPR
459 #define SPR_MASK (0x3ff << 11)
460 { 10, 11, insert_spr, extract_spr, 0 },
461
462 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
463 #define SPRBAT SPR + 1
464 #define SPRBAT_MASK (0x3 << 17)
465 { 2, 17, NULL, NULL, 0 },
466
467 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
468 #define SPRG SPRBAT + 1
469 #define SPRG_MASK (0x3 << 16)
470 { 2, 16, NULL, NULL, 0 },
471
472 /* The SR field in an X form instruction. */
473 #define SR SPRG + 1
474 { 4, 16, NULL, NULL, 0 },
475
476 /* The STRM field in an X AltiVec form instruction. */
477 #define STRM SR + 1
478 #define STRM_MASK (0x3 << 21)
479 { 2, 21, NULL, NULL, 0 },
480
481 /* The SV field in a POWER SC form instruction. */
482 #define SV STRM + 1
483 { 14, 2, NULL, NULL, 0 },
484
485 /* The TBR field in an XFX form instruction. This is like the SPR
486 field, but it is optional. */
487 #define TBR SV + 1
488 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
489
490 /* The TO field in a D or X form instruction. */
491 #define TO TBR + 1
492 #define TO_MASK (0x1f << 21)
493 { 5, 21, NULL, NULL, 0 },
494
495 /* The U field in an X form instruction. */
496 #define U TO + 1
497 { 4, 12, NULL, NULL, 0 },
498
499 /* The UI field in a D form instruction. */
500 #define UI U + 1
501 { 16, 0, NULL, NULL, 0 },
502
503 /* The VA field in a VA, VX or VXR form instruction. */
504 #define VA UI + 1
505 #define VA_MASK (0x1f << 16)
506 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
507
508 /* The VB field in a VA, VX or VXR form instruction. */
509 #define VB VA + 1
510 #define VB_MASK (0x1f << 11)
511 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
512
513 /* The VC field in a VA form instruction. */
514 #define VC VB + 1
515 #define VC_MASK (0x1f << 6)
516 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
517
518 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
519 #define VD VC + 1
520 #define VS VD
521 #define VD_MASK (0x1f << 21)
522 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
523
524 /* The SIMM field in a VX form instruction. */
525 #define SIMM VD + 1
526 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
527
528 /* The UIMM field in a VX form instruction. */
529 #define UIMM SIMM + 1
530 { 5, 16, NULL, NULL, 0 },
531
532 /* The SHB field in a VA form instruction. */
533 #define SHB UIMM + 1
534 { 4, 6, NULL, NULL, 0 },
535
536 /* The other UIMM field in a EVX form instruction. */
537 #define EVUIMM SHB + 1
538 { 5, 11, NULL, NULL, 0 },
539
540 /* The other UIMM field in a half word EVX form instruction. */
541 #define EVUIMM_2 EVUIMM + 1
542 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
543
544 /* The other UIMM field in a word EVX form instruction. */
545 #define EVUIMM_4 EVUIMM_2 + 1
546 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
547
548 /* The other UIMM field in a double EVX form instruction. */
549 #define EVUIMM_8 EVUIMM_4 + 1
550 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
551
552 /* The WS field. */
553 #define WS EVUIMM_8 + 1
554 #define WS_MASK (0x7 << 11)
555 { 3, 11, NULL, NULL, 0 },
556
557 /* The L field in an mtmsrd instruction */
558 #define MTMSRD_L WS + 1
559 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
560
561 };
562
563 /* The functions used to insert and extract complicated operands. */
564
565 /* The BA field in an XL form instruction when it must be the same as
566 the BT field in the same instruction. This operand is marked FAKE.
567 The insertion function just copies the BT field into the BA field,
568 and the extraction function just checks that the fields are the
569 same. */
570
571 static unsigned long
insert_bat(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)572 insert_bat (unsigned long insn,
573 long value ATTRIBUTE_UNUSED,
574 int dialect ATTRIBUTE_UNUSED,
575 const char **errmsg ATTRIBUTE_UNUSED)
576 {
577 return insn | (((insn >> 21) & 0x1f) << 16);
578 }
579
580 static long
extract_bat(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)581 extract_bat (unsigned long insn,
582 int dialect ATTRIBUTE_UNUSED,
583 int *invalid)
584 {
585 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
586 *invalid = 1;
587 return 0;
588 }
589
590 /* The BB field in an XL form instruction when it must be the same as
591 the BA field in the same instruction. This operand is marked FAKE.
592 The insertion function just copies the BA field into the BB field,
593 and the extraction function just checks that the fields are the
594 same. */
595
596 static unsigned long
insert_bba(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)597 insert_bba (unsigned long insn,
598 long value ATTRIBUTE_UNUSED,
599 int dialect ATTRIBUTE_UNUSED,
600 const char **errmsg ATTRIBUTE_UNUSED)
601 {
602 return insn | (((insn >> 16) & 0x1f) << 11);
603 }
604
605 static long
extract_bba(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)606 extract_bba (unsigned long insn,
607 int dialect ATTRIBUTE_UNUSED,
608 int *invalid)
609 {
610 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
611 *invalid = 1;
612 return 0;
613 }
614
615 /* The BD field in a B form instruction. The lower two bits are
616 forced to zero. */
617
618 static unsigned long
insert_bd(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)619 insert_bd (unsigned long insn,
620 long value,
621 int dialect ATTRIBUTE_UNUSED,
622 const char **errmsg ATTRIBUTE_UNUSED)
623 {
624 return insn | (value & 0xfffc);
625 }
626
627 static long
extract_bd(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)628 extract_bd (unsigned long insn,
629 int dialect ATTRIBUTE_UNUSED,
630 int *invalid ATTRIBUTE_UNUSED)
631 {
632 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
633 }
634
635 /* The BD field in a B form instruction when the - modifier is used.
636 This modifier means that the branch is not expected to be taken.
637 For chips built to versions of the architecture prior to version 2
638 (ie. not Power4 compatible), we set the y bit of the BO field to 1
639 if the offset is negative. When extracting, we require that the y
640 bit be 1 and that the offset be positive, since if the y bit is 0
641 we just want to print the normal form of the instruction.
642 Power4 compatible targets use two bits, "a", and "t", instead of
643 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
644 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
645 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
646 for branch on CTR. We only handle the taken/not-taken hint here. */
647
648 static unsigned long
insert_bdm(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)649 insert_bdm (unsigned long insn,
650 long value,
651 int dialect,
652 const char **errmsg ATTRIBUTE_UNUSED)
653 {
654 if ((dialect & PPC_OPCODE_POWER4) == 0)
655 {
656 if ((value & 0x8000) != 0)
657 insn |= 1 << 21;
658 }
659 else
660 {
661 if ((insn & (0x14 << 21)) == (0x04 << 21))
662 insn |= 0x02 << 21;
663 else if ((insn & (0x14 << 21)) == (0x10 << 21))
664 insn |= 0x08 << 21;
665 }
666 return insn | (value & 0xfffc);
667 }
668
669 static long
extract_bdm(unsigned long insn,int dialect,int * invalid)670 extract_bdm (unsigned long insn,
671 int dialect,
672 int *invalid)
673 {
674 if ((dialect & PPC_OPCODE_POWER4) == 0)
675 {
676 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
677 *invalid = 1;
678 }
679 else
680 {
681 if ((insn & (0x17 << 21)) != (0x06 << 21)
682 && (insn & (0x1d << 21)) != (0x18 << 21))
683 *invalid = 1;
684 }
685
686 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
687 }
688
689 /* The BD field in a B form instruction when the + modifier is used.
690 This is like BDM, above, except that the branch is expected to be
691 taken. */
692
693 static unsigned long
insert_bdp(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)694 insert_bdp (unsigned long insn,
695 long value,
696 int dialect,
697 const char **errmsg ATTRIBUTE_UNUSED)
698 {
699 if ((dialect & PPC_OPCODE_POWER4) == 0)
700 {
701 if ((value & 0x8000) == 0)
702 insn |= 1 << 21;
703 }
704 else
705 {
706 if ((insn & (0x14 << 21)) == (0x04 << 21))
707 insn |= 0x03 << 21;
708 else if ((insn & (0x14 << 21)) == (0x10 << 21))
709 insn |= 0x09 << 21;
710 }
711 return insn | (value & 0xfffc);
712 }
713
714 static long
extract_bdp(unsigned long insn,int dialect,int * invalid)715 extract_bdp (unsigned long insn,
716 int dialect,
717 int *invalid)
718 {
719 if ((dialect & PPC_OPCODE_POWER4) == 0)
720 {
721 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
722 *invalid = 1;
723 }
724 else
725 {
726 if ((insn & (0x17 << 21)) != (0x07 << 21)
727 && (insn & (0x1d << 21)) != (0x19 << 21))
728 *invalid = 1;
729 }
730
731 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
732 }
733
734 /* Check for legal values of a BO field. */
735
736 static int
valid_bo(long value,int dialect)737 valid_bo (long value, int dialect)
738 {
739 if ((dialect & PPC_OPCODE_POWER4) == 0)
740 {
741 /* Certain encodings have bits that are required to be zero.
742 These are (z must be zero, y may be anything):
743 001zy
744 011zy
745 1z00y
746 1z01y
747 1z1zz
748 */
749 switch (value & 0x14)
750 {
751 default:
752 case 0:
753 return 1;
754 case 0x4:
755 return (value & 0x2) == 0;
756 case 0x10:
757 return (value & 0x8) == 0;
758 case 0x14:
759 return value == 0x14;
760 }
761 }
762 else
763 {
764 /* Certain encodings have bits that are required to be zero.
765 These are (z must be zero, a & t may be anything):
766 0000z
767 0001z
768 0100z
769 0101z
770 001at
771 011at
772 1a00t
773 1a01t
774 1z1zz
775 */
776 if ((value & 0x14) == 0)
777 return (value & 0x1) == 0;
778 else if ((value & 0x14) == 0x14)
779 return value == 0x14;
780 else
781 return 1;
782 }
783 }
784
785 /* The BO field in a B form instruction. Warn about attempts to set
786 the field to an illegal value. */
787
788 static unsigned long
insert_bo(unsigned long insn,long value,int dialect,const char ** errmsg)789 insert_bo (unsigned long insn,
790 long value,
791 int dialect,
792 const char **errmsg)
793 {
794 if (!valid_bo (value, dialect))
795 *errmsg = _("invalid conditional option");
796 return insn | ((value & 0x1f) << 21);
797 }
798
799 static long
extract_bo(unsigned long insn,int dialect,int * invalid)800 extract_bo (unsigned long insn,
801 int dialect,
802 int *invalid)
803 {
804 long value;
805
806 value = (insn >> 21) & 0x1f;
807 if (!valid_bo (value, dialect))
808 *invalid = 1;
809 return value;
810 }
811
812 /* The BO field in a B form instruction when the + or - modifier is
813 used. This is like the BO field, but it must be even. When
814 extracting it, we force it to be even. */
815
816 static unsigned long
insert_boe(unsigned long insn,long value,int dialect,const char ** errmsg)817 insert_boe (unsigned long insn,
818 long value,
819 int dialect,
820 const char **errmsg)
821 {
822 if (!valid_bo (value, dialect))
823 *errmsg = _("invalid conditional option");
824 else if ((value & 1) != 0)
825 *errmsg = _("attempt to set y bit when using + or - modifier");
826
827 return insn | ((value & 0x1f) << 21);
828 }
829
830 static long
extract_boe(unsigned long insn,int dialect,int * invalid)831 extract_boe (unsigned long insn,
832 int dialect,
833 int *invalid)
834 {
835 long value;
836
837 value = (insn >> 21) & 0x1f;
838 if (!valid_bo (value, dialect))
839 *invalid = 1;
840 return value & 0x1e;
841 }
842
843 /* The DQ field in a DQ form instruction. This is like D, but the
844 lower four bits are forced to zero. */
845
846 static unsigned long
insert_dq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)847 insert_dq (unsigned long insn,
848 long value,
849 int dialect ATTRIBUTE_UNUSED,
850 const char **errmsg)
851 {
852 if ((value & 0xf) != 0)
853 *errmsg = _("offset not a multiple of 16");
854 return insn | (value & 0xfff0);
855 }
856
857 static long
extract_dq(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)858 extract_dq (unsigned long insn,
859 int dialect ATTRIBUTE_UNUSED,
860 int *invalid ATTRIBUTE_UNUSED)
861 {
862 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
863 }
864
865 static unsigned long
insert_ev2(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)866 insert_ev2 (unsigned long insn,
867 long value,
868 int dialect ATTRIBUTE_UNUSED,
869 const char **errmsg)
870 {
871 if ((value & 1) != 0)
872 *errmsg = _("offset not a multiple of 2");
873 if ((value > 62) != 0)
874 *errmsg = _("offset greater than 62");
875 return insn | ((value & 0x3e) << 10);
876 }
877
878 static long
extract_ev2(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)879 extract_ev2 (unsigned long insn,
880 int dialect ATTRIBUTE_UNUSED,
881 int *invalid ATTRIBUTE_UNUSED)
882 {
883 return (insn >> 10) & 0x3e;
884 }
885
886 static unsigned long
insert_ev4(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)887 insert_ev4 (unsigned long insn,
888 long value,
889 int dialect ATTRIBUTE_UNUSED,
890 const char **errmsg)
891 {
892 if ((value & 3) != 0)
893 *errmsg = _("offset not a multiple of 4");
894 if ((value > 124) != 0)
895 *errmsg = _("offset greater than 124");
896 return insn | ((value & 0x7c) << 9);
897 }
898
899 static long
extract_ev4(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)900 extract_ev4 (unsigned long insn,
901 int dialect ATTRIBUTE_UNUSED,
902 int *invalid ATTRIBUTE_UNUSED)
903 {
904 return (insn >> 9) & 0x7c;
905 }
906
907 static unsigned long
insert_ev8(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)908 insert_ev8 (unsigned long insn,
909 long value,
910 int dialect ATTRIBUTE_UNUSED,
911 const char **errmsg)
912 {
913 if ((value & 7) != 0)
914 *errmsg = _("offset not a multiple of 8");
915 if ((value > 248) != 0)
916 *errmsg = _("offset greater than 248");
917 return insn | ((value & 0xf8) << 8);
918 }
919
920 static long
extract_ev8(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)921 extract_ev8 (unsigned long insn,
922 int dialect ATTRIBUTE_UNUSED,
923 int *invalid ATTRIBUTE_UNUSED)
924 {
925 return (insn >> 8) & 0xf8;
926 }
927
928 /* The DS field in a DS form instruction. This is like D, but the
929 lower two bits are forced to zero. */
930
931 static unsigned long
insert_ds(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)932 insert_ds (unsigned long insn,
933 long value,
934 int dialect ATTRIBUTE_UNUSED,
935 const char **errmsg)
936 {
937 if ((value & 3) != 0)
938 *errmsg = _("offset not a multiple of 4");
939 return insn | (value & 0xfffc);
940 }
941
942 static long
extract_ds(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)943 extract_ds (unsigned long insn,
944 int dialect ATTRIBUTE_UNUSED,
945 int *invalid ATTRIBUTE_UNUSED)
946 {
947 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
948 }
949
950 /* The DE field in a DE form instruction. */
951
952 static unsigned long
insert_de(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)953 insert_de (unsigned long insn,
954 long value,
955 int dialect ATTRIBUTE_UNUSED,
956 const char **errmsg)
957 {
958 if (value > 2047 || value < -2048)
959 *errmsg = _("offset not between -2048 and 2047");
960 return insn | ((value << 4) & 0xfff0);
961 }
962
963 static long
extract_de(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)964 extract_de (unsigned long insn,
965 int dialect ATTRIBUTE_UNUSED,
966 int *invalid ATTRIBUTE_UNUSED)
967 {
968 return (insn & 0xfff0) >> 4;
969 }
970
971 /* The DES field in a DES form instruction. */
972
973 static unsigned long
insert_des(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)974 insert_des (unsigned long insn,
975 long value,
976 int dialect ATTRIBUTE_UNUSED,
977 const char **errmsg)
978 {
979 if (value > 8191 || value < -8192)
980 *errmsg = _("offset not between -8192 and 8191");
981 else if ((value & 3) != 0)
982 *errmsg = _("offset not a multiple of 4");
983 return insn | ((value << 2) & 0xfff0);
984 }
985
986 static long
extract_des(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)987 extract_des (unsigned long insn,
988 int dialect ATTRIBUTE_UNUSED,
989 int *invalid ATTRIBUTE_UNUSED)
990 {
991 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
992 }
993
994 /* FXM mask in mfcr and mtcrf instructions. */
995
996 static unsigned long
insert_fxm(unsigned long insn,long value,int dialect,const char ** errmsg)997 insert_fxm (unsigned long insn,
998 long value,
999 int dialect,
1000 const char **errmsg)
1001 {
1002 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1003 one bit of the mask field is set. */
1004 if ((insn & (1 << 20)) != 0)
1005 {
1006 if (value == 0 || (value & -value) != value)
1007 {
1008 *errmsg = _("invalid mask field");
1009 value = 0;
1010 }
1011 }
1012
1013 /* If the optional field on mfcr is missing that means we want to use
1014 the old form of the instruction that moves the whole cr. In that
1015 case we'll have VALUE zero. There doesn't seem to be a way to
1016 distinguish this from the case where someone writes mfcr %r3,0. */
1017 else if (value == 0)
1018 ;
1019
1020 /* If only one bit of the FXM field is set, we can use the new form
1021 of the instruction, which is faster. Unlike the Power4 branch hint
1022 encoding, this is not backward compatible. Do not generate the
1023 new form unless -mpower4 has been given, or -many and the two
1024 operand form of mfcr was used. */
1025 else if ((value & -value) == value
1026 && ((dialect & PPC_OPCODE_POWER4) != 0
1027 || ((dialect & PPC_OPCODE_ANY) != 0
1028 && (insn & (0x3ff << 1)) == 19 << 1)))
1029 insn |= 1 << 20;
1030
1031 /* Any other value on mfcr is an error. */
1032 else if ((insn & (0x3ff << 1)) == 19 << 1)
1033 {
1034 *errmsg = _("ignoring invalid mfcr mask");
1035 value = 0;
1036 }
1037
1038 return insn | ((value & 0xff) << 12);
1039 }
1040
1041 static long
extract_fxm(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1042 extract_fxm (unsigned long insn,
1043 int dialect ATTRIBUTE_UNUSED,
1044 int *invalid)
1045 {
1046 long mask = (insn >> 12) & 0xff;
1047
1048 /* Is this a Power4 insn? */
1049 if ((insn & (1 << 20)) != 0)
1050 {
1051 /* Exactly one bit of MASK should be set. */
1052 if (mask == 0 || (mask & -mask) != mask)
1053 *invalid = 1;
1054 }
1055
1056 /* Check that non-power4 form of mfcr has a zero MASK. */
1057 else if ((insn & (0x3ff << 1)) == 19 << 1)
1058 {
1059 if (mask != 0)
1060 *invalid = 1;
1061 }
1062
1063 return mask;
1064 }
1065
1066 /* The LI field in an I form instruction. The lower two bits are
1067 forced to zero. */
1068
1069 static unsigned long
insert_li(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1070 insert_li (unsigned long insn,
1071 long value,
1072 int dialect ATTRIBUTE_UNUSED,
1073 const char **errmsg)
1074 {
1075 if ((value & 3) != 0)
1076 *errmsg = _("ignoring least significant bits in branch offset");
1077 return insn | (value & 0x3fffffc);
1078 }
1079
1080 static long
extract_li(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1081 extract_li (unsigned long insn,
1082 int dialect ATTRIBUTE_UNUSED,
1083 int *invalid ATTRIBUTE_UNUSED)
1084 {
1085 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1086 }
1087
1088 /* The MB and ME fields in an M form instruction expressed as a single
1089 operand which is itself a bitmask. The extraction function always
1090 marks it as invalid, since we never want to recognize an
1091 instruction which uses a field of this type. */
1092
1093 static unsigned long
insert_mbe(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1094 insert_mbe (unsigned long insn,
1095 long value,
1096 int dialect ATTRIBUTE_UNUSED,
1097 const char **errmsg)
1098 {
1099 unsigned long uval, mask;
1100 int mb, me, mx, count, last;
1101
1102 uval = value;
1103
1104 if (uval == 0)
1105 {
1106 *errmsg = _("illegal bitmask");
1107 return insn;
1108 }
1109
1110 mb = 0;
1111 me = 32;
1112 if ((uval & 1) != 0)
1113 last = 1;
1114 else
1115 last = 0;
1116 count = 0;
1117
1118 /* mb: location of last 0->1 transition */
1119 /* me: location of last 1->0 transition */
1120 /* count: # transitions */
1121
1122 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1123 {
1124 if ((uval & mask) && !last)
1125 {
1126 ++count;
1127 mb = mx;
1128 last = 1;
1129 }
1130 else if (!(uval & mask) && last)
1131 {
1132 ++count;
1133 me = mx;
1134 last = 0;
1135 }
1136 }
1137 if (me == 0)
1138 me = 32;
1139
1140 if (count != 2 && (count != 0 || ! last))
1141 *errmsg = _("illegal bitmask");
1142
1143 return insn | (mb << 6) | ((me - 1) << 1);
1144 }
1145
1146 static long
extract_mbe(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1147 extract_mbe (unsigned long insn,
1148 int dialect ATTRIBUTE_UNUSED,
1149 int *invalid)
1150 {
1151 long ret;
1152 int mb, me;
1153 int i;
1154
1155 *invalid = 1;
1156
1157 mb = (insn >> 6) & 0x1f;
1158 me = (insn >> 1) & 0x1f;
1159 if (mb < me + 1)
1160 {
1161 ret = 0;
1162 for (i = mb; i <= me; i++)
1163 ret |= 1L << (31 - i);
1164 }
1165 else if (mb == me + 1)
1166 ret = ~0;
1167 else /* (mb > me + 1) */
1168 {
1169 ret = ~0;
1170 for (i = me + 1; i < mb; i++)
1171 ret &= ~(1L << (31 - i));
1172 }
1173 return ret;
1174 }
1175
1176 /* The MB or ME field in an MD or MDS form instruction. The high bit
1177 is wrapped to the low end. */
1178
1179 static unsigned long
insert_mb6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1180 insert_mb6 (unsigned long insn,
1181 long value,
1182 int dialect ATTRIBUTE_UNUSED,
1183 const char **errmsg ATTRIBUTE_UNUSED)
1184 {
1185 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1186 }
1187
1188 static long
extract_mb6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1189 extract_mb6 (unsigned long insn,
1190 int dialect ATTRIBUTE_UNUSED,
1191 int *invalid ATTRIBUTE_UNUSED)
1192 {
1193 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1194 }
1195
1196 /* The NB field in an X form instruction. The value 32 is stored as
1197 0. */
1198
1199 static unsigned long
insert_nb(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1200 insert_nb (unsigned long insn,
1201 long value,
1202 int dialect ATTRIBUTE_UNUSED,
1203 const char **errmsg)
1204 {
1205 if (value < 0 || value > 32)
1206 *errmsg = _("value out of range");
1207 if (value == 32)
1208 value = 0;
1209 return insn | ((value & 0x1f) << 11);
1210 }
1211
1212 static long
extract_nb(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1213 extract_nb (unsigned long insn,
1214 int dialect ATTRIBUTE_UNUSED,
1215 int *invalid ATTRIBUTE_UNUSED)
1216 {
1217 long ret;
1218
1219 ret = (insn >> 11) & 0x1f;
1220 if (ret == 0)
1221 ret = 32;
1222 return ret;
1223 }
1224
1225 /* The NSI field in a D form instruction. This is the same as the SI
1226 field, only negated. The extraction function always marks it as
1227 invalid, since we never want to recognize an instruction which uses
1228 a field of this type. */
1229
1230 static unsigned long
insert_nsi(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1231 insert_nsi (unsigned long insn,
1232 long value,
1233 int dialect ATTRIBUTE_UNUSED,
1234 const char **errmsg ATTRIBUTE_UNUSED)
1235 {
1236 return insn | (-value & 0xffff);
1237 }
1238
1239 static long
extract_nsi(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1240 extract_nsi (unsigned long insn,
1241 int dialect ATTRIBUTE_UNUSED,
1242 int *invalid)
1243 {
1244 *invalid = 1;
1245 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1246 }
1247
1248 /* The RA field in a D or X form instruction which is an updating
1249 load, which means that the RA field may not be zero and may not
1250 equal the RT field. */
1251
1252 static unsigned long
insert_ral(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1253 insert_ral (unsigned long insn,
1254 long value,
1255 int dialect ATTRIBUTE_UNUSED,
1256 const char **errmsg)
1257 {
1258 if (value == 0
1259 || (unsigned long) value == ((insn >> 21) & 0x1f))
1260 *errmsg = "invalid register operand when updating";
1261 return insn | ((value & 0x1f) << 16);
1262 }
1263
1264 /* The RA field in an lmw instruction, which has special value
1265 restrictions. */
1266
1267 static unsigned long
insert_ram(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1268 insert_ram (unsigned long insn,
1269 long value,
1270 int dialect ATTRIBUTE_UNUSED,
1271 const char **errmsg)
1272 {
1273 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1274 *errmsg = _("index register in load range");
1275 return insn | ((value & 0x1f) << 16);
1276 }
1277
1278 /* The RA field in the DQ form lq instruction, which has special
1279 value restrictions. */
1280
1281 static unsigned long
insert_raq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1282 insert_raq (unsigned long insn,
1283 long value,
1284 int dialect ATTRIBUTE_UNUSED,
1285 const char **errmsg)
1286 {
1287 long rtvalue = (insn & RT_MASK) >> 21;
1288
1289 if (value == rtvalue)
1290 *errmsg = _("source and target register operands must be different");
1291 return insn | ((value & 0x1f) << 16);
1292 }
1293
1294 /* The RA field in a D or X form instruction which is an updating
1295 store or an updating floating point load, which means that the RA
1296 field may not be zero. */
1297
1298 static unsigned long
insert_ras(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1299 insert_ras (unsigned long insn,
1300 long value,
1301 int dialect ATTRIBUTE_UNUSED,
1302 const char **errmsg)
1303 {
1304 if (value == 0)
1305 *errmsg = _("invalid register operand when updating");
1306 return insn | ((value & 0x1f) << 16);
1307 }
1308
1309 /* The RB field in an X form instruction when it must be the same as
1310 the RS field in the instruction. This is used for extended
1311 mnemonics like mr. This operand is marked FAKE. The insertion
1312 function just copies the BT field into the BA field, and the
1313 extraction function just checks that the fields are the same. */
1314
1315 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1316 insert_rbs (unsigned long insn,
1317 long value ATTRIBUTE_UNUSED,
1318 int dialect ATTRIBUTE_UNUSED,
1319 const char **errmsg ATTRIBUTE_UNUSED)
1320 {
1321 return insn | (((insn >> 21) & 0x1f) << 11);
1322 }
1323
1324 static long
extract_rbs(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1325 extract_rbs (unsigned long insn,
1326 int dialect ATTRIBUTE_UNUSED,
1327 int *invalid)
1328 {
1329 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1330 *invalid = 1;
1331 return 0;
1332 }
1333
1334 /* The RT field of the DQ form lq instruction, which has special
1335 value restrictions. */
1336
1337 static unsigned long
insert_rtq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1338 insert_rtq (unsigned long insn,
1339 long value,
1340 int dialect ATTRIBUTE_UNUSED,
1341 const char **errmsg)
1342 {
1343 if ((value & 1) != 0)
1344 *errmsg = _("target register operand must be even");
1345 return insn | ((value & 0x1f) << 21);
1346 }
1347
1348 /* The RS field of the DS form stq instruction, which has special
1349 value restrictions. */
1350
1351 static unsigned long
insert_rsq(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1352 insert_rsq (unsigned long insn,
1353 long value ATTRIBUTE_UNUSED,
1354 int dialect ATTRIBUTE_UNUSED,
1355 const char **errmsg)
1356 {
1357 if ((value & 1) != 0)
1358 *errmsg = _("source register operand must be even");
1359 return insn | ((value & 0x1f) << 21);
1360 }
1361
1362 /* The SH field in an MD form instruction. This is split. */
1363
1364 static unsigned long
insert_sh6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1365 insert_sh6 (unsigned long insn,
1366 long value,
1367 int dialect ATTRIBUTE_UNUSED,
1368 const char **errmsg ATTRIBUTE_UNUSED)
1369 {
1370 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1371 }
1372
1373 static long
extract_sh6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1374 extract_sh6 (unsigned long insn,
1375 int dialect ATTRIBUTE_UNUSED,
1376 int *invalid ATTRIBUTE_UNUSED)
1377 {
1378 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1379 }
1380
1381 /* The SPR field in an XFX form instruction. This is flipped--the
1382 lower 5 bits are stored in the upper 5 and vice- versa. */
1383
1384 static unsigned long
insert_spr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1385 insert_spr (unsigned long insn,
1386 long value,
1387 int dialect ATTRIBUTE_UNUSED,
1388 const char **errmsg ATTRIBUTE_UNUSED)
1389 {
1390 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1391 }
1392
1393 static long
extract_spr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1394 extract_spr (unsigned long insn,
1395 int dialect ATTRIBUTE_UNUSED,
1396 int *invalid ATTRIBUTE_UNUSED)
1397 {
1398 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1399 }
1400
1401 /* The TBR field in an XFX instruction. This is just like SPR, but it
1402 is optional. When TBR is omitted, it must be inserted as 268 (the
1403 magic number of the TB register). These functions treat 0
1404 (indicating an omitted optional operand) as 268. This means that
1405 ``mftb 4,0'' is not handled correctly. This does not matter very
1406 much, since the architecture manual does not define mftb as
1407 accepting any values other than 268 or 269. */
1408
1409 #define TB (268)
1410
1411 static unsigned long
insert_tbr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1412 insert_tbr (unsigned long insn,
1413 long value,
1414 int dialect ATTRIBUTE_UNUSED,
1415 const char **errmsg ATTRIBUTE_UNUSED)
1416 {
1417 if (value == 0)
1418 value = TB;
1419 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1420 }
1421
1422 static long
extract_tbr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1423 extract_tbr (unsigned long insn,
1424 int dialect ATTRIBUTE_UNUSED,
1425 int *invalid ATTRIBUTE_UNUSED)
1426 {
1427 long ret;
1428
1429 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1430 if (ret == TB)
1431 ret = 0;
1432 return ret;
1433 }
1434
1435 /* Macros used to form opcodes. */
1436
1437 /* The main opcode. */
1438 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1439 #define OP_MASK OP (0x3f)
1440
1441 /* The main opcode combined with a trap code in the TO field of a D
1442 form instruction. Used for extended mnemonics for the trap
1443 instructions. */
1444 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1445 #define OPTO_MASK (OP_MASK | TO_MASK)
1446
1447 /* The main opcode combined with a comparison size bit in the L field
1448 of a D form or X form instruction. Used for extended mnemonics for
1449 the comparison instructions. */
1450 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1451 #define OPL_MASK OPL (0x3f,1)
1452
1453 /* An A form instruction. */
1454 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1455 #define A_MASK A (0x3f, 0x1f, 1)
1456
1457 /* An A_MASK with the FRB field fixed. */
1458 #define AFRB_MASK (A_MASK | FRB_MASK)
1459
1460 /* An A_MASK with the FRC field fixed. */
1461 #define AFRC_MASK (A_MASK | FRC_MASK)
1462
1463 /* An A_MASK with the FRA and FRC fields fixed. */
1464 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1465
1466 /* A B form instruction. */
1467 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1468 #define B_MASK B (0x3f, 1, 1)
1469
1470 /* A B form instruction setting the BO field. */
1471 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1472 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1473
1474 /* A BBO_MASK with the y bit of the BO field removed. This permits
1475 matching a conditional branch regardless of the setting of the y
1476 bit. Similarly for the 'at' bits used for power4 branch hints. */
1477 #define Y_MASK (((unsigned long) 1) << 21)
1478 #define AT1_MASK (((unsigned long) 3) << 21)
1479 #define AT2_MASK (((unsigned long) 9) << 21)
1480 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1481 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1482
1483 /* A B form instruction setting the BO field and the condition bits of
1484 the BI field. */
1485 #define BBOCB(op, bo, cb, aa, lk) \
1486 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1487 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1488
1489 /* A BBOCB_MASK with the y bit of the BO field removed. */
1490 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1491 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1492 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1493
1494 /* A BBOYCB_MASK in which the BI field is fixed. */
1495 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1496 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1497
1498 /* An Context form instruction. */
1499 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1500 #define CTX_MASK CTX(0x3f, 0x7)
1501
1502 /* An User Context form instruction. */
1503 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1504 #define UCTX_MASK UCTX(0x3f, 0x1f)
1505
1506 /* The main opcode mask with the RA field clear. */
1507 #define DRA_MASK (OP_MASK | RA_MASK)
1508
1509 /* A DS form instruction. */
1510 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1511 #define DS_MASK DSO (0x3f, 3)
1512
1513 /* A DE form instruction. */
1514 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1515 #define DE_MASK DEO (0x3e, 0xf)
1516
1517 /* An EVSEL form instruction. */
1518 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1519 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1520
1521 /* An M form instruction. */
1522 #define M(op, rc) (OP (op) | ((rc) & 1))
1523 #define M_MASK M (0x3f, 1)
1524
1525 /* An M form instruction with the ME field specified. */
1526 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1527
1528 /* An M_MASK with the MB and ME fields fixed. */
1529 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1530
1531 /* An M_MASK with the SH and ME fields fixed. */
1532 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1533
1534 /* An MD form instruction. */
1535 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1536 #define MD_MASK MD (0x3f, 0x7, 1)
1537
1538 /* An MD_MASK with the MB field fixed. */
1539 #define MDMB_MASK (MD_MASK | MB6_MASK)
1540
1541 /* An MD_MASK with the SH field fixed. */
1542 #define MDSH_MASK (MD_MASK | SH6_MASK)
1543
1544 /* An MDS form instruction. */
1545 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1546 #define MDS_MASK MDS (0x3f, 0xf, 1)
1547
1548 /* An MDS_MASK with the MB field fixed. */
1549 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1550
1551 /* An SC form instruction. */
1552 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1553 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1554
1555 /* An VX form instruction. */
1556 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1557
1558 /* The mask for an VX form instruction. */
1559 #define VX_MASK VX(0x3f, 0x7ff)
1560
1561 /* An VA form instruction. */
1562 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1563
1564 /* The mask for an VA form instruction. */
1565 #define VXA_MASK VXA(0x3f, 0x3f)
1566
1567 /* An VXR form instruction. */
1568 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1569
1570 /* The mask for a VXR form instruction. */
1571 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1572
1573 /* An X form instruction. */
1574 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1575
1576 /* An X form instruction with the RC bit specified. */
1577 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1578
1579 /* The mask for an X form instruction. */
1580 #define X_MASK XRC (0x3f, 0x3ff, 1)
1581
1582 /* An X_MASK with the RA field fixed. */
1583 #define XRA_MASK (X_MASK | RA_MASK)
1584
1585 /* An X_MASK with the RB field fixed. */
1586 #define XRB_MASK (X_MASK | RB_MASK)
1587
1588 /* An X_MASK with the RT field fixed. */
1589 #define XRT_MASK (X_MASK | RT_MASK)
1590
1591 /* An X_MASK with the RA and RB fields fixed. */
1592 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1593
1594 /* An XRARB_MASK, but with the L bit clear. */
1595 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1596
1597 /* An X_MASK with the RT and RA fields fixed. */
1598 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1599
1600 /* An XRTRA_MASK, but with L bit clear. */
1601 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1602
1603 /* An X form instruction with the L bit specified. */
1604 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1605
1606 /* The mask for an X form comparison instruction. */
1607 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1608
1609 /* The mask for an X form comparison instruction with the L field
1610 fixed. */
1611 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1612
1613 /* An X form trap instruction with the TO field specified. */
1614 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1615 #define XTO_MASK (X_MASK | TO_MASK)
1616
1617 /* An X form tlb instruction with the SH field specified. */
1618 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1619 #define XTLB_MASK (X_MASK | SH_MASK)
1620
1621 /* An X form sync instruction. */
1622 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1623
1624 /* An X form sync instruction with everything filled in except the LS field. */
1625 #define XSYNC_MASK (0xff9fffff)
1626
1627 /* An X form AltiVec dss instruction. */
1628 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1629 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1630
1631 /* An XFL form instruction. */
1632 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1633 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1634
1635 /* An X form isel instruction. */
1636 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1637 #define XISEL_MASK XISEL(0x3f, 0x1f)
1638
1639 /* An XL form instruction with the LK field set to 0. */
1640 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1641
1642 /* An XL form instruction which uses the LK field. */
1643 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1644
1645 /* The mask for an XL form instruction. */
1646 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1647
1648 /* An XL form instruction which explicitly sets the BO field. */
1649 #define XLO(op, bo, xop, lk) \
1650 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1651 #define XLO_MASK (XL_MASK | BO_MASK)
1652
1653 /* An XL form instruction which explicitly sets the y bit of the BO
1654 field. */
1655 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1656 #define XLYLK_MASK (XL_MASK | Y_MASK)
1657
1658 /* An XL form instruction which sets the BO field and the condition
1659 bits of the BI field. */
1660 #define XLOCB(op, bo, cb, xop, lk) \
1661 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1662 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1663
1664 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1665 #define XLBB_MASK (XL_MASK | BB_MASK)
1666 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1667 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1668
1669 /* A mask for branch instructions using the BH field. */
1670 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1671
1672 /* An XL_MASK with the BO and BB fields fixed. */
1673 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1674
1675 /* An XL_MASK with the BO, BI and BB fields fixed. */
1676 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1677
1678 /* An XO form instruction. */
1679 #define XO(op, xop, oe, rc) \
1680 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1681 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1682
1683 /* An XO_MASK with the RB field fixed. */
1684 #define XORB_MASK (XO_MASK | RB_MASK)
1685
1686 /* An XS form instruction. */
1687 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1688 #define XS_MASK XS (0x3f, 0x1ff, 1)
1689
1690 /* A mask for the FXM version of an XFX form instruction. */
1691 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1692
1693 /* An XFX form instruction with the FXM field filled in. */
1694 #define XFXM(op, xop, fxm, p4) \
1695 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1696 | ((unsigned long)(p4) << 20))
1697
1698 /* An XFX form instruction with the SPR field filled in. */
1699 #define XSPR(op, xop, spr) \
1700 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1701 #define XSPR_MASK (X_MASK | SPR_MASK)
1702
1703 /* An XFX form instruction with the SPR field filled in except for the
1704 SPRBAT field. */
1705 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1706
1707 /* An XFX form instruction with the SPR field filled in except for the
1708 SPRG field. */
1709 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1710
1711 /* An X form instruction with everything filled in except the E field. */
1712 #define XE_MASK (0xffff7fff)
1713
1714 /* An X form user context instruction. */
1715 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1716 #define XUC_MASK XUC(0x3f, 0x1f)
1717
1718 /* The BO encodings used in extended conditional branch mnemonics. */
1719 #define BODNZF (0x0)
1720 #define BODNZFP (0x1)
1721 #define BODZF (0x2)
1722 #define BODZFP (0x3)
1723 #define BODNZT (0x8)
1724 #define BODNZTP (0x9)
1725 #define BODZT (0xa)
1726 #define BODZTP (0xb)
1727
1728 #define BOF (0x4)
1729 #define BOFP (0x5)
1730 #define BOFM4 (0x6)
1731 #define BOFP4 (0x7)
1732 #define BOT (0xc)
1733 #define BOTP (0xd)
1734 #define BOTM4 (0xe)
1735 #define BOTP4 (0xf)
1736
1737 #define BODNZ (0x10)
1738 #define BODNZP (0x11)
1739 #define BODZ (0x12)
1740 #define BODZP (0x13)
1741 #define BODNZM4 (0x18)
1742 #define BODNZP4 (0x19)
1743 #define BODZM4 (0x1a)
1744 #define BODZP4 (0x1b)
1745
1746 #define BOU (0x14)
1747
1748 /* The BI condition bit encodings used in extended conditional branch
1749 mnemonics. */
1750 #define CBLT (0)
1751 #define CBGT (1)
1752 #define CBEQ (2)
1753 #define CBSO (3)
1754
1755 /* The TO encodings used in extended trap mnemonics. */
1756 #define TOLGT (0x1)
1757 #define TOLLT (0x2)
1758 #define TOEQ (0x4)
1759 #define TOLGE (0x5)
1760 #define TOLNL (0x5)
1761 #define TOLLE (0x6)
1762 #define TOLNG (0x6)
1763 #define TOGT (0x8)
1764 #define TOGE (0xc)
1765 #define TONL (0xc)
1766 #define TOLT (0x10)
1767 #define TOLE (0x14)
1768 #define TONG (0x14)
1769 #define TONE (0x18)
1770 #define TOU (0x1f)
1771
1772 /* Smaller names for the flags so each entry in the opcodes table will
1773 fit on a single line. */
1774 #undef PPC
1775 #define PPC PPC_OPCODE_PPC
1776 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1777 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1778 #define POWER4 PPC_OPCODE_POWER4
1779 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1780 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1781 #define PPC403 PPC_OPCODE_403
1782 #define PPC405 PPC403
1783 #define PPC440 PPC_OPCODE_440
1784 #define PPC750 PPC
1785 #define PPC860 PPC
1786 #define PPCVEC PPC_OPCODE_ALTIVEC
1787 #define POWER PPC_OPCODE_POWER
1788 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1789 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1790 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1791 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1792 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1793 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1794 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1795 #define MFDEC1 PPC_OPCODE_POWER
1796 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1797 #define BOOKE PPC_OPCODE_BOOKE
1798 #define BOOKE64 PPC_OPCODE_BOOKE64
1799 #define CLASSIC PPC_OPCODE_CLASSIC
1800 #define PPCSPE PPC_OPCODE_SPE
1801 #define PPCISEL PPC_OPCODE_ISEL
1802 #define PPCEFS PPC_OPCODE_EFS
1803 #define PPCBRLK PPC_OPCODE_BRLOCK
1804 #define PPCPMR PPC_OPCODE_PMR
1805 #define PPCCHLK PPC_OPCODE_CACHELCK
1806 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1807 #define PPCRFMCI PPC_OPCODE_RFMCI
1808
1809 /* The opcode table.
1810
1811 The format of the opcode table is:
1812
1813 NAME OPCODE MASK FLAGS { OPERANDS }
1814
1815 NAME is the name of the instruction.
1816 OPCODE is the instruction opcode.
1817 MASK is the opcode mask; this is used to tell the disassembler
1818 which bits in the actual opcode must match OPCODE.
1819 FLAGS are flags indicated what processors support the instruction.
1820 OPERANDS is the list of operands.
1821
1822 The disassembler reads the table in order and prints the first
1823 instruction which matches, so this table is sorted to put more
1824 specific instructions before more general instructions. It is also
1825 sorted by major opcode. */
1826
1827 const struct powerpc_opcode powerpc_opcodes[] = {
1828 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1829 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1830 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1831 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1832 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1833 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1834 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1835 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1836 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1837 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1838 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1839 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1840 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1841 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1842 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1843 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1844
1845 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1846 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1847 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1848 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1849 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1850 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1851 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1852 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1853 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1854 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1855 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1856 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1857 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1858 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1859 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1860 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1861 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1862 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1863 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1864 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1865 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1866 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1867 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1868 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1869 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1870 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1871 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1872 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1873 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1874 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1875
1876 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1909 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1910 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1911 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1912 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1913 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1914 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1915 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1916 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1917 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1918 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1919 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1920 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1921 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1922 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1923 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1954 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1955 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1956 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1957 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1958 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1959 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1960 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1961 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1962
1963 /* Double-precision opcodes. */
1964 /* Some of these conflict with AltiVec, so move them before, since
1965 PPCVEC includes the PPC_OPCODE_PPC set. */
1966 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
1967 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
1968 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
1969 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
1970 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
1971 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
1972 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
1973 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
1974 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1975 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1976 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1977 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1978 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1979 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1980 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
1981 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
1982 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
1983 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
1984 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
1985 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
1986 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
1987 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
1988 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
1989 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
1990 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
1991 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
1992 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
1993 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
1994 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
1995 /* End of double-precision opcodes. */
1996
1997 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2002 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2003 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2004 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2005 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2006 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2007 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2009 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2010 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2011 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2012 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2013 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2014 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2015 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2017 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2018 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2021 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2022 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2023 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2024 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2026 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2030 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2031 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2032 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2033 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2034 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2035 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2036 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2037 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2038 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2039 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2043 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2045 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2046 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2047 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2048 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2049 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2051 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2054 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2055 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2057 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2058 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2060 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2061 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2062 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2064 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2065 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2066 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2067 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2073 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2074 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2075 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2076 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2077 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2078 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2081 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2085 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2087 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2089 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2090 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2092 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2093 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2094 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2095 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2096 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2097 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2098 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2100 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2101 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2102 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2103 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2104 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2105 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2106 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2107 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2108 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2109 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2110 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2111 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2112 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2113 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2114 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2115 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2116 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2117 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2118 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2119 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2120 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2121 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2122 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2123 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2124 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2125 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2126 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2127 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2128 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2129 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2130 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2131 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2132 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2133 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2134 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2135 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2136 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2137 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2138 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2139 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2140 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2141 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2142 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2143 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2144 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2145 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2146 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2147 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2148 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2149 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2150 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2151 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2152
2153 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2154 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2155 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2156 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2157 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2158 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2159 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2160 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2161 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2162 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2163 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2164 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2165 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2166
2167 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2168
2169 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2170 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2171 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2172 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2173 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2174 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2175 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2176 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2177 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2178 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2179
2180 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2181 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2182 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2183 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2184 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2185 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2187 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2188 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2189 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2190 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2193 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2194
2195 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2196 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2197 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2198 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2199 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2200 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2201
2202 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2203 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2205 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2206 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2207 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2208 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2209 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2210 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2211 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2212 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2213 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2214 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2215 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2216 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2217 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2218 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2219 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2220 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2221 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2222 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2223 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2224
2225 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2226 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2227 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2228 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2229 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2230 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2231 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2232 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2233 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2234 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2235 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2236 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2237 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2238 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2239
2240 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2241 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2242 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2243 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2244 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2245 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2246 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2247 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2248 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2249 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2250 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2251 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2252 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2253 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2254 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2255 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2256 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2257 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2258 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2259 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2260 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2261 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2262 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2263
2264 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2265 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2266 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2267 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2268 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2269 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2270 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2271 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2272 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2273 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2274 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2275 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2276 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2277 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2278 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2279 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2280 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2281 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2282 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2283 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2284 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2285 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2286 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2287
2288 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2294 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2295 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2302 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2304
2305 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2307 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2310 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2312 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2314 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2317
2318 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2324 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2330
2331 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2333 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2337
2338 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2344
2345 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2352 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2353
2354 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2356
2357 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2359 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2361
2362 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2364 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2365 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2366
2367 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2368 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2369 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2370 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2371 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2373 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2374 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2375
2376 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2377 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2378 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2379 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2380
2381 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2382 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2383 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2384 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2385
2386 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2387 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2388 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2389 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2390
2391 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2392 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2393 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2394 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2395
2396 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2397
2398 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2400
2401 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2402 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2403
2404 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2405 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2406
2407 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2408
2409 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2410 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2411 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2412 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2413
2414 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2415 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2416 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2417 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2418
2419 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2420 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2421 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2422 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2423
2424 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2425 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2426 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2427
2428 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2429 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2430 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2431
2432 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2433 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2434 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2435 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2436 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2437 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2438
2439 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2440 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2441 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2442 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2443 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2444
2445 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2446 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2447 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2448 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2449 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2450 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2451 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2452 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2453 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2454 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2455 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2456 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2457 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2458 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2459 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2460 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2461 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2462 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2463 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2464 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2465 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2466 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2467 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2468 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2469 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2470 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2471 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2472 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2473 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2474 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2475 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2476 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2477 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2478 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2479 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2480 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2481 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2482 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2483 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2484 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2485 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2486 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2487 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2488 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2491 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2492 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2493 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2494 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2497 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2498 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2499 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2500 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2503 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2504 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2505 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2506 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2509 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2510 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2511 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2512 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2515 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2516 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2517 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2518 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2521 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2522 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2523 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2524 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2525 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2526 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2527 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2528 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2529 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2530 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2531 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2532 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2533 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2534 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2535 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2536 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2537 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2538 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2539 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2540 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2541 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2542 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2543 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2544 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2545 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2546 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2547 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2548 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2549 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2550 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2551 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2552 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2553 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2554 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2555 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2556 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2557 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2558 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2559 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2560 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2561 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2562 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2563 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2564 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2565 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2566 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2567 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2568 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2569 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2570 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2571 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2572 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2573 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2574 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2575 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2576 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2577 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2578 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2579 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2580 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2581 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2582 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2583 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2584 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2585 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2586 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2587 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2588 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2589 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2590 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2591 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2592 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2593 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2594 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2595 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2596 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2597 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2598 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2599 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2600 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2601 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2602 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2603 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2604 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2605 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2606 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2607 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2608 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2609 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2610 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2611 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2612 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2613 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2614 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2615 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2616 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2617 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2618 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2619 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2620 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2621 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2622 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2623 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2624 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2625 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2626 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2627 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2628 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2629 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2630 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2631 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2632 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2633 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2634 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2635 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2636 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2637 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2638 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2639 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2640 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2641 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2642 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2643 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2644 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2645 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2646 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2647 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2648 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2649 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2650 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2651 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2652 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2653 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2654 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2655 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2656 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2657 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2658 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2659 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2660 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2661 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2662 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2663 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2664 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2665 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2666 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2667 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2668 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2669 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2670 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2671 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2672 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2673 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2674 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2675 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2676 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2677 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2678 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2679 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2680 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2681 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2682 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2683 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2684 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2685 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2686 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2687 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2688 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2689 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2690 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2691 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2692 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2693 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2694 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2695 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2696 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2697 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2698 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2699 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2700 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2701 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2702 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2703 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2704 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2705 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2706 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2707 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2708 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2709
2710 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2711 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2712 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2713 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2714 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2715
2716 { "b", B(18,0,0), B_MASK, COM, { LI } },
2717 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2718 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2719 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2720
2721 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2722
2723 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2724 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2725 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2726 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2727 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2728 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2729 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2730 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2731 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2732 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2733 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2734 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2735 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2736 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2737 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2738 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2739 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2740 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2741 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2742 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2743 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2744 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2745 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2746 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2747 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2748 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2752 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2753 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2754 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2758 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2759 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2760 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2765 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2766 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2768 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2769 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2770 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2771 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2772 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2775 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2776 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2777 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2778 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2781 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2782 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2783 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2784 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2787 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2788 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2789 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2790 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2793 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2794 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2795 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2796 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2799 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2800 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2801 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2804 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2805 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2806 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2808 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2811 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2812 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2814 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2817 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2818 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2819 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2820 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2823 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2824 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2826 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2828 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2829 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2830 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2831 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2832 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2833 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2834 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2835 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2836 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2837 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2838 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2840 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2841 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2842 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2843 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2844 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2845 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2846 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2847 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2848 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2849 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2850 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2851 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2852 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2853 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2854 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2855 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2856 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2857 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2858 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2859 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2860 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2861 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2862 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2863 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2864 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2865 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2866 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2867 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2868 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2869 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2870 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2871 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2872 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2873 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2874 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2875 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2876 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2877 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2878 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2879 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2880 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2881 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2882 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2883 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2884 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2885 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2886 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2887 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2888 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2890 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2891 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2892 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2893 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2894 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2895 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2896 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2897 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2898 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2899 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2900 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2901 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2902 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2903 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2904 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2905 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2906 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2907 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2908 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2909 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2910 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2911 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2912 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2913 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2914 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2915 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2916 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2917 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2918 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2919 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2920 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2921 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2922 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2923 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2924 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2925 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2926 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2927 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2928 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2929 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2930 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2931 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2932 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2933 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2934 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2935 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2936 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2937 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2938 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2939 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2940 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2941 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2942 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2943 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2944 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2945
2946 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2947
2948 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2949 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2950 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2951
2952 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2953 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2954
2955 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2956
2957 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2958
2959 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2960 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2961
2962 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2963 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2964
2965 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2966
2967 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2968
2969 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2970 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2971
2972 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2973
2974 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2975 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2976
2977 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2978 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2979 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2980 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2981 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2982 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2985 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2990 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2991 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2992 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2995 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2996 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2997 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3000 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3001 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3002 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3005 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3006 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3007 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3010 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3011 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3012 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3015 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3016 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3017 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3020 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3021 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3022 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3025 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3026 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3027 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3030 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3031 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3032 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3035 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3036 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3037 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3040 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3041 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3042 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3045 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3046 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3047 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3050 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3051 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3052 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3054 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3055 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3056 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3057 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3058 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3059 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3060 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3061 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3062 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3063 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3064 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3065 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3066 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3067 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3068 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3069 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3070 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3071 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3072 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3073 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3074 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3075 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3076 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3077 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3078 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3079 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3080 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3081 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3082 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3083 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3084 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3085 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3086 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3087 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3088 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3089 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3090 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3091 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3092 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3093 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3094 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3095 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3096 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3097 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3098 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3099 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3100 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3101 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3102 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3103 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3104 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3105 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3106 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3107 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3108 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3109 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3110 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3111 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3112 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3113 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3114 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3115 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3116 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3117 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3118 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3119 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3120 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3121 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3122 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3123 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3124 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3125 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3126 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3127 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3128 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3129
3130 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3131 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3132
3133 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3134 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3135
3136 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3137 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3138 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3139 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3140 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3141 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3142 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3143 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3144
3145 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3146 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3147
3148 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3149 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3150 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3151 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3152
3153 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3154 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3155 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3156 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3157 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3158 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3159
3160 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3161 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3162 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3163
3164 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3165 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3166
3167 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3168 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3169
3170 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3171 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3172
3173 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3174 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3175
3176 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3177 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3178
3179 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3180 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3181 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3182 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3183 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3184 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3185
3186 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3187 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3188
3189 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3190 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3191
3192 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3193 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3194
3195 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3196 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3197 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3198 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3199
3200 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3201 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3202
3203 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3204 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3205 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3206 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3207
3208 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3209 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3210 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3211 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3212 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3213 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3214 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3215 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3216 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3217 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3218 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3219 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3220 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3221 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3222 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3223 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3224 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3225 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3226 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3227 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3228 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3229 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3230 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3231 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3232 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3233 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3234 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3235 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3236 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3237 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3238 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3239
3240 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3241 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3242 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3243 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3244 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3245 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3246 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3247 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3248 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3249 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3250 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3251 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3252
3253 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3254 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3255
3256 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3257 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3258 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3259 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3260 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3261 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3262 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3263 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3264
3265 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3266 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3267
3268 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3269 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3270 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3271 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3272
3273 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3274 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3275 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3276
3277 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
3278
3279 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3280
3281 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3282 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3283
3284 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3285 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3286
3287 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3288 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3289 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3290 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3291
3292 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3293 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3294 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3295 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3296
3297 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3298 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3299
3300 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3301 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3302
3303 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3304 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3305
3306 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3307
3308 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3309
3310 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3311 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3312 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3313 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3314
3315 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3316 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3317 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3318 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3319 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3320 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3321 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3322 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3323
3324 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3325
3326 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3327
3328 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3329 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3330
3331 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3332
3333 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3334
3335 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3336 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3337
3338 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3339 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3340
3341 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3342 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3343 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3344 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3345 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3346 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3347 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3348 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3349 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3350 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3351 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3352 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3353 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3354 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3355 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3356
3357 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3358 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3359
3360 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3361 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3362
3363 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3364 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3365
3366 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3367
3368 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3369
3370 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
3371
3372 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3373
3374 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3375
3376 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3377
3378 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3379
3380 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3381 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3382 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3383 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3384
3385 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3386 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3387 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3388 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3389
3390 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3391
3392 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3393
3394 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3395
3396 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3397 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3398 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3399 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3400
3401 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3402
3403 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3404
3405 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3406
3407 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3408
3409 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3410 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3411 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3412 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3413 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3414 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3415 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3416 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3417
3418 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3419 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3420 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3421 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3422 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3423 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3424 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3425 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3426
3427 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3428
3429 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3430 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3431 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3432
3433 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3434
3435 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3436
3437 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3438
3439 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3440 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3441
3442 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3443
3444 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3445
3446 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3447 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3448
3449 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3450 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3451
3452 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3453
3454 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3455 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3456
3457 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3458
3459 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3460
3461 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3462 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3463
3464 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3465 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3466
3467 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3468
3469 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3470 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3471 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3472 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3473 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3474 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3475 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3476 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3477
3478 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3479 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3480 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3481 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3482 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3483 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3484 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3485 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3486
3487 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3488
3489 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3490
3491 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3492
3493 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3494 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3495
3496 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3497 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3498
3499 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3500
3501 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3502
3503 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3504 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3505 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3506 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3507 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3508 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3509 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3510 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3511
3512 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3513 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3514 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3515 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3516
3517 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3518 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3519 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3520 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3521 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3522 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3523 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3524 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3525
3526 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3527 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3528 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3529 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3530 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3531 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3532 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3533 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3534
3535 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3536 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3537 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3538
3539 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3540
3541 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3542
3543 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3544 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3545
3546 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3547
3548 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3549
3550 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3551
3552 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3553 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3554 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3555 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3556
3557 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3558 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3559 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3560 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3561 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3562 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3563 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3564 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3565
3566 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3567
3568 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3569
3570 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3571 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3572
3573 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3574
3575 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3576
3577 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3578 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3579
3580 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3581
3582 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3583
3584 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3585 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3586
3587 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3588
3589 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3590
3591 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3592 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3593
3594 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3595
3596 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3597 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3598 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3599 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3600 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3601 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3602 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3603 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3604 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3605 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3606 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3607 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3608 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3609 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3610 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3611 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3612 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3613 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3614 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3615 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3616 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3617 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3618 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3619 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3620 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3621 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3622 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3623 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3624 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3625 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3626 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3627 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3628 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3629 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3630 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3631
3632 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3633 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3634 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3635 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3636
3637 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3638
3639 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3640 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3641 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3642 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3643 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3644 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3645 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3646 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3647 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3648 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3649 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3650 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3651 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3652 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3653 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3654 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3655 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3656 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3657 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3658 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3659 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3660 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3661 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3662 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3663 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3664 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3665 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3666 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3667 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3668 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3669 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3670 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3671 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3672 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3673 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3674 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3675 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3676 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3677 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3678 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3679 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3680 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3681 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3682 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } },
3683 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3684 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } },
3685 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3686 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } },
3687 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3688 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } },
3689 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3690 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3691 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3692 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3693 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3694 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3695 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3696 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3697 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3698 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3699 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3700 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3701 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3702 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3703 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3704 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3705 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3706 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3707 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3708 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3709 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3710 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3711 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3712 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3713 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3714 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3715 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3716 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3717 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3718 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3719 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3720 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3721 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3722 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3723 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3724 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3725 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3726 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3727 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3728 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3729 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3730 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3731 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3732 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3733 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3734 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3735 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3736 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3737 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3738 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3739 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3740 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3741 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3742 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3743 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3744 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3745 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3746 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3747 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3748 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3749 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3750 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3751 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3752 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3753 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3754 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3755 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3756 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3757 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3758 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3759 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3760 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3761 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3762 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3763 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3764 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3765 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3766 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3767 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3768 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3769 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3770 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3771 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3772 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3773 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3774 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3775 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3776 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3777 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3778 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3779 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3780 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3781 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3782 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3783 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3784 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3785 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3786 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3787 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3788 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3789 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3790 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3791 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3792 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3793 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3794 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3795 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3796 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3797 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3798 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3799 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3800 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3801 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3802 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3803 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3804 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3805 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3806 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3807 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3808 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3809 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3810 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3811 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3812 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3813 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3814 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3815 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3816 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3817 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3818 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3819 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3820 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3821 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3822 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3823 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3824 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3825 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3826 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3827 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3828 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3829 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3830
3831 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3832
3833 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3834 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3835
3836 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3837
3838 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3839
3840 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3841 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3842
3843 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3844
3845 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3846 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3847 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3848 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3849
3850 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3851 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3852 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3853 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3854
3855 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3856
3857 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3858
3859 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3860
3861 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3862
3863 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3864
3865 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3866
3867 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3868 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3869
3870 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3871 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3872
3873 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3874
3875 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3876
3877 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3878
3879 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3880
3881 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3882
3883 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3884
3885 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3886
3887 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3888 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3889
3890 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3891 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3892
3893 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3894
3895 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3896
3897 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3898
3899 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3900
3901 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3902
3903 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3904 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3905 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3906 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3907
3908 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3909 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3910 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3911 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3912 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3913 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3914 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3915 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3916 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3917 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3918 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3919 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3920 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3921 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3922 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3923 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3924 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3925 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3926 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3927 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3928 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3929 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3930 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3931 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3932 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3933 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3934 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3935 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3936 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3937 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3938 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3939 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3940 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3941 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3942 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3943
3944 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3945 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3946
3947 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3948 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3949 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3950 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3951
3952 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3953 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3954
3955 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3956 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3957 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3958 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3959
3960 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3961 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3962 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3963 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3964 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3965 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3966 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3967 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3968 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3969 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3970 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3971 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3972 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3973 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3974 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3975 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3976 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3977 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3978 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3979 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3980 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3981 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3982 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3983 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3984 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3985 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3986 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3987 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3988 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3989 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3990 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3991 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3992 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3993 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3994 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3995 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3996 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3997 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3998 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3999 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4000 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4001 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4002 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
4003 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4004 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4005 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4006 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4007 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4008 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4009 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4010 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4011 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4012 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4013 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4014 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4015 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4016 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4017 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4018 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4019 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4020 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4021 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4022 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4023 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4024 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4025 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4026 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4027 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4028 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4029 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4030 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4031 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4032 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4033 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4034 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4035 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4036 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4037 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4038 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4039 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4040 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4041 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4042 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4043 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4044 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4045 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4046 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4047 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4048 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4049 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4050 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4051 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4052 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4053 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4054 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4055 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4056 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4057 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4058 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4059 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4060 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4061 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4062 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4063 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4064 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4065 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4066 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4067 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4068 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4069 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4070 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4071 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4072 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4073 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4074 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4075 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4076 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4077 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4078 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4079 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4080 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4081 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4082 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4083 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4084 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4085 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4086 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4087 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4088 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4089 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4090 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4091 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4092 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4093 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4094 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4095 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4096 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4097 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4098 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4099 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4100 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4101 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4102 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4103 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4104 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4105 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4106 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4107 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4108 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4109 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4110 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4111 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4112
4113 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4114
4115 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4116 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4117
4118 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4119
4120 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4121
4122 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4123
4124 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4125
4126 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4127 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4128 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4129 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4130 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4131 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4132
4133 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4134 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4135 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4136 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4137
4138 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4139 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4140
4141 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4142 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4143 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4144 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4145
4146 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4147
4148 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4149
4150 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4151
4152 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4153
4154 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4155
4156 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4157 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4158
4159 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4160
4161 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4162 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4163
4164 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4165 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4166
4167 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4168
4169 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4170 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4171 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4172 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4173
4174 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4175 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4176
4177 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4178 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4179
4180 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4181 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4182
4183 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4184
4185 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4186
4187 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4188
4189 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4190
4191 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4192
4193 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4194
4195 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4196
4197 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4198 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4199
4200 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4201 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4202 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4203 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4204 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4205
4206 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4207
4208 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4209
4210 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4211
4212 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4213
4214 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4215
4216 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4217
4218 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4219
4220 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4221 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4222
4223 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4224 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4225
4226 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4227
4228 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4229 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4230
4231 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4232 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4233
4234 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4235
4236 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4237
4238 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4239
4240 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4241 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4242
4243 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4244
4245 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4246 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4247
4248 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4249
4250 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4251 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4252
4253 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4254 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4255
4256 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4257
4258 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4259
4260 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4261
4262 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4263 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4264
4265 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4266
4267 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4268
4269 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4270 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4271
4272 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4273
4274 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4275 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4276 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4277 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4278
4279 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4280 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4281
4282 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4283
4284 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4285 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4286
4287 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4288
4289 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4290 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4291
4292 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4293 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4294 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4295 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4296
4297 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4298
4299 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4300 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4301
4302 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4303 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4304 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4305 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4306
4307 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4308
4309 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4310
4311 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4312 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4313
4314 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4315 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4316
4317 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4318 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4319 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4320 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4321
4322 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4323
4324 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4325
4326 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4327 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4328 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4329
4330 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4331 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4332
4333 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4334 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4335
4336 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4337
4338 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4339
4340 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4341 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4342 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4343 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4344
4345 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4346
4347 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4348
4349 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4350 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4351
4352 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4353
4354 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4355 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4356
4357 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4358
4359 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4360 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4361 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4362
4363 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4364
4365 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4366 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4367 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4368 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4369 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4370 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4371 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4372 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4373 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4374 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4375 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4376 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4377
4378 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4379 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4380
4381 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4382 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4383
4384 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4385
4386 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4387
4388 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4389 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4390
4391 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4392 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4393
4394 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4395
4396 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4397
4398 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4399
4400 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4401
4402 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4403
4404 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4405
4406 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4407
4408 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4409
4410 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4411 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4412
4413 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4414 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4415
4416 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4417
4418 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4419
4420 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4421
4422 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4423
4424 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4425
4426 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4427
4428 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4429
4430 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4431
4432 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4433
4434 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4435
4436 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4437
4438 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4439 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4440 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4441 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4442 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4443 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4444 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4445 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4446 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4447 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4448 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4449 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4450 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4451 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4452
4453 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4454
4455 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4456
4457 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4458
4459 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4460 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4461
4462 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4463 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4464
4465 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4466 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4467
4468 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4469 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4470
4471 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4472 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4473
4474 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4475 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4476
4477 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4478 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4479
4480 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4481 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4482
4483 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4484 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4485
4486 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4487 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4488
4489 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4490
4491 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4492
4493 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4494 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4495 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4496 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4497 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4498 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4499 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4500 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4501 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4502 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4503 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4504 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4505
4506 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4507
4508 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4509
4510 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4511
4512 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4513
4514 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4515 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4516
4517 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4518 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4519 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4520 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4521
4522 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4523 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4524 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4525 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4526
4527 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4528 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4529 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4530 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4531
4532 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4533 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4534 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4535 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4536
4537 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4538 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4539 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4540 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4541
4542 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4543 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4544
4545 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4546 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4547
4548 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4549 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4550 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4551 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4552
4553 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4554 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4555
4556 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4557 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4558 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4559 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4560
4561 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4562 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4563 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4564 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4565
4566 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4567 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4568 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4569 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4570
4571 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4572 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4573 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4574 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4575
4576 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4577
4578 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4579 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4580
4581 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4582 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4583
4584 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4585
4586 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4587 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4588
4589 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4590 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4591
4592 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4593 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4594
4595 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4596 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4597
4598 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4599 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4600
4601 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4602 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4603
4604 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4605 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4606
4607 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4608 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4609
4610 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4611 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4612
4613 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4614 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4615
4616 };
4617
4618 const int powerpc_num_opcodes =
4619 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4620
4621 /* The macro table. This is only used by the assembler. */
4622
4623 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4624 when x=0; 32-x when x is between 1 and 31; are negative if x is
4625 negative; and are 32 or more otherwise. This is what you want
4626 when, for instance, you are emulating a right shift by a
4627 rotate-left-and-mask, because the underlying instructions support
4628 shifts of size 0 but not shifts of size 32. By comparison, when
4629 extracting x bits from some word you want to use just 32-x, because
4630 the underlying instructions don't support extracting 0 bits but do
4631 support extracting the whole word (32 bits in this case). */
4632
4633 const struct powerpc_macro powerpc_macros[] = {
4634 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4635 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4636 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4637 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4638 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4639 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4640 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4641 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4642 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4643 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4644 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4645 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4646 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4647 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4648 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4649 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4650
4651 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4652 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4653 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4654 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4655 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4656 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4657 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4658 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4659 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4660 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4661 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4662 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4663 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4664 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4665 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4666 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4667 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4668 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4669 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4670 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4671 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4672 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4673 };
4674
4675 const int powerpc_num_macros =
4676 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
4677