1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com). 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GCC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING. If not, write to 22 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 23 Boston, MA 02110-1301, USA. */ 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 /* Define the specific costs for a given cpu */ 29 30 struct processor_costs { 31 /* Integer load */ 32 const int int_load; 33 34 /* Integer signed load */ 35 const int int_sload; 36 37 /* Integer zeroed load */ 38 const int int_zload; 39 40 /* Float load */ 41 const int float_load; 42 43 /* fmov, fneg, fabs */ 44 const int float_move; 45 46 /* fadd, fsub */ 47 const int float_plusminus; 48 49 /* fcmp */ 50 const int float_cmp; 51 52 /* fmov, fmovr */ 53 const int float_cmove; 54 55 /* fmul */ 56 const int float_mul; 57 58 /* fdivs */ 59 const int float_div_sf; 60 61 /* fdivd */ 62 const int float_div_df; 63 64 /* fsqrts */ 65 const int float_sqrt_sf; 66 67 /* fsqrtd */ 68 const int float_sqrt_df; 69 70 /* umul/smul */ 71 const int int_mul; 72 73 /* mulX */ 74 const int int_mulX; 75 76 /* integer multiply cost for each bit set past the most 77 significant 3, so the formula for multiply cost becomes: 78 79 if (rs1 < 0) 80 highest_bit = highest_clear_bit(rs1); 81 else 82 highest_bit = highest_set_bit(rs1); 83 if (highest_bit < 3) 84 highest_bit = 3; 85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); 86 87 A value of zero indicates that the multiply costs is fixed, 88 and not variable. */ 89 const int int_mul_bit_factor; 90 91 /* udiv/sdiv */ 92 const int int_div; 93 94 /* divX */ 95 const int int_divX; 96 97 /* movcc, movr */ 98 const int int_cmove; 99 100 /* penalty for shifts, due to scheduling rules etc. */ 101 const int shift_penalty; 102 }; 103 104 extern const struct processor_costs *sparc_costs; 105 106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of 107 Solaris only; otherwise just define __sparc__. Sadly the headers 108 are such a mess there is no Solaris-specific header. */ 109 #define TARGET_CPU_CPP_BUILTINS() \ 110 do \ 111 { \ 112 builtin_define_std ("sparc"); \ 113 if (TARGET_64BIT) \ 114 { \ 115 builtin_assert ("cpu=sparc64"); \ 116 builtin_assert ("machine=sparc64"); \ 117 } \ 118 else \ 119 { \ 120 builtin_assert ("cpu=sparc"); \ 121 builtin_assert ("machine=sparc"); \ 122 } \ 123 } \ 124 while (0) 125 126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 127 /* #define SPARC_BI_ARCH */ 128 129 /* Macro used later in this file to determine default architecture. */ 130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 131 132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 133 architectures to compile for. We allow targets to choose compile time or 134 runtime selection. */ 135 #ifdef IN_LIBGCC2 136 #if defined(__sparcv9) || defined(__arch64__) 137 #define TARGET_ARCH32 0 138 #else 139 #define TARGET_ARCH32 1 140 #endif /* sparc64 */ 141 #else 142 #ifdef SPARC_BI_ARCH 143 #define TARGET_ARCH32 (! TARGET_64BIT) 144 #else 145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 146 #endif /* SPARC_BI_ARCH */ 147 #endif /* IN_LIBGCC2 */ 148 #define TARGET_ARCH64 (! TARGET_ARCH32) 149 150 /* Code model selection in 64-bit environment. 151 152 The machine mode used for addresses is 32-bit wide: 153 154 TARGET_CM_32: 32-bit address space. 155 It is the code model used when generating 32-bit code. 156 157 The machine mode used for addresses is 64-bit wide: 158 159 TARGET_CM_MEDLOW: 32-bit address space. 160 The executable must be in the low 32 bits of memory. 161 This avoids generating %uhi and %ulo terms. Programs 162 can be statically or dynamically linked. 163 164 TARGET_CM_MEDMID: 44-bit address space. 165 The executable must be in the low 44 bits of memory, 166 and the %[hml]44 terms are used. The text and data 167 segments have a maximum size of 2GB (31-bit span). 168 The maximum offset from any instruction to the label 169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 170 171 TARGET_CM_MEDANY: 64-bit address space. 172 The text and data segments have a maximum size of 2GB 173 (31-bit span) and may be located anywhere in memory. 174 The maximum offset from any instruction to the label 175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 176 177 TARGET_CM_EMBMEDANY: 64-bit address space. 178 The text and data segments have a maximum size of 2GB 179 (31-bit span) and may be located anywhere in memory. 180 The global register %g4 contains the start address of 181 the data segment. Programs are statically linked and 182 PIC is not supported. 183 184 Different code models are not supported in 32-bit environment. */ 185 186 enum cmodel { 187 CM_32, 188 CM_MEDLOW, 189 CM_MEDMID, 190 CM_MEDANY, 191 CM_EMBMEDANY 192 }; 193 194 /* One of CM_FOO. */ 195 extern enum cmodel sparc_cmodel; 196 197 /* V9 code model selection. */ 198 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 199 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 200 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 201 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 202 203 #define SPARC_DEFAULT_CMODEL CM_32 204 205 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) 206 which requires the following macro to be true if enabled. Prior to V9, 207 there are no instructions to even talk about memory synchronization. 208 Note that the UltraSPARC III processors don't implement RMO, unlike the 209 UltraSPARC II processors. 210 211 Default to false; for example, Solaris never enables RMO, only ever uses 212 total memory ordering (TMO). */ 213 #define SPARC_RELAXED_ORDERING false 214 215 /* Do not use the .note.GNU-stack convention by default. */ 216 #define NEED_INDICATE_EXEC_STACK 0 217 218 /* This is call-clobbered in the normal ABI, but is reserved in the 219 home grown (aka upward compatible) embedded ABI. */ 220 #define EMBMEDANY_BASE_REG "%g4" 221 222 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 223 and specified by the user via --with-cpu=foo. 224 This specifies the cpu implementation, not the architecture size. */ 225 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 226 capable cpu's. */ 227 #define TARGET_CPU_sparc 0 228 #define TARGET_CPU_v7 0 /* alias for previous */ 229 #define TARGET_CPU_sparclet 1 230 #define TARGET_CPU_sparclite 2 231 #define TARGET_CPU_v8 3 /* generic v8 implementation */ 232 #define TARGET_CPU_supersparc 4 233 #define TARGET_CPU_hypersparc 5 234 #define TARGET_CPU_sparc86x 6 235 #define TARGET_CPU_sparclite86x 6 236 #define TARGET_CPU_v9 7 /* generic v9 implementation */ 237 #define TARGET_CPU_sparcv9 7 /* alias */ 238 #define TARGET_CPU_sparc64 7 /* alias */ 239 #define TARGET_CPU_ultrasparc 8 240 #define TARGET_CPU_ultrasparc3 9 241 242 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 243 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 244 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 245 246 #define CPP_CPU32_DEFAULT_SPEC "" 247 #define ASM_CPU32_DEFAULT_SPEC "" 248 249 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 250 /* ??? What does Sun's CC pass? */ 251 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 252 /* ??? It's not clear how other assemblers will handle this, so by default 253 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 254 is handled in sol2.h. */ 255 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 256 #endif 257 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 258 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 259 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 260 #endif 261 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 262 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 263 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 264 #endif 265 266 #else 267 268 #define CPP_CPU64_DEFAULT_SPEC "" 269 #define ASM_CPU64_DEFAULT_SPEC "" 270 271 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 272 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 273 #define CPP_CPU32_DEFAULT_SPEC "" 274 #define ASM_CPU32_DEFAULT_SPEC "" 275 #endif 276 277 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 278 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 279 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 280 #endif 281 282 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 283 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 284 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 285 #endif 286 287 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 288 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 289 #define ASM_CPU32_DEFAULT_SPEC "" 290 #endif 291 292 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 293 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 294 #define ASM_CPU32_DEFAULT_SPEC "" 295 #endif 296 297 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 298 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 299 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 300 #endif 301 302 #endif 303 304 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 305 #error Unrecognized value in TARGET_CPU_DEFAULT. 306 #endif 307 308 #ifdef SPARC_BI_ARCH 309 310 #define CPP_CPU_DEFAULT_SPEC \ 311 (DEFAULT_ARCH32_P ? "\ 312 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 313 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 314 " : "\ 315 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 316 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 317 ") 318 #define ASM_CPU_DEFAULT_SPEC \ 319 (DEFAULT_ARCH32_P ? "\ 320 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 321 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 322 " : "\ 323 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 324 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 325 ") 326 327 #else /* !SPARC_BI_ARCH */ 328 329 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 330 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 331 332 #endif /* !SPARC_BI_ARCH */ 333 334 /* Define macros to distinguish architectures. */ 335 336 /* Common CPP definitions used by CPP_SPEC amongst the various targets 337 for handling -mcpu=xxx switches. */ 338 #define CPP_CPU_SPEC "\ 339 %{msoft-float:-D_SOFT_FLOAT} \ 340 %{mcypress:} \ 341 %{msparclite:-D__sparclite__} \ 342 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 343 %{mv8:-D__sparc_v8__} \ 344 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 345 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 346 %{mcpu=sparclite:-D__sparclite__} \ 347 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 348 %{mcpu=v8:-D__sparc_v8__} \ 349 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 350 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 351 %{mcpu=sparclite86x:-D__sparclite86x__} \ 352 %{mcpu=v9:-D__sparc_v9__} \ 353 %{mcpu=ultrasparc:-D__sparc_v9__} \ 354 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 355 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ 356 " 357 #define CPP_ARCH32_SPEC "" 358 #define CPP_ARCH64_SPEC "-D__arch64__" 359 360 #define CPP_ARCH_DEFAULT_SPEC \ 361 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 362 363 #define CPP_ARCH_SPEC "\ 364 %{m32:%(cpp_arch32)} \ 365 %{m64:%(cpp_arch64)} \ 366 %{!m32:%{!m64:%(cpp_arch_default)}} \ 367 " 368 369 /* Macros to distinguish endianness. */ 370 #define CPP_ENDIAN_SPEC "\ 371 %{mlittle-endian:-D__LITTLE_ENDIAN__} \ 372 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" 373 374 /* Macros to distinguish the particular subtarget. */ 375 #define CPP_SUBTARGET_SPEC "" 376 377 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" 378 379 /* Prevent error on `-sun4' and `-target sun4' options. */ 380 /* This used to translate -dalign to -malign, but that is no good 381 because it can't turn off the usual meaning of making debugging dumps. */ 382 /* Translate old style -m<cpu> into new style -mcpu=<cpu>. 383 ??? Delete support for -m<cpu> for 2.9. */ 384 385 #define CC1_SPEC "\ 386 %{sun4:} %{target:} \ 387 %{mcypress:-mcpu=cypress} \ 388 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ 389 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ 390 " 391 392 /* Override in target specific files. */ 393 #define ASM_CPU_SPEC "\ 394 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 395 %{msparclite:-Asparclite} \ 396 %{mf930:-Asparclite} %{mf934:-Asparclite} \ 397 %{mcpu=sparclite:-Asparclite} \ 398 %{mcpu=sparclite86x:-Asparclite} \ 399 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 400 %{mv8plus:-Av8plus} \ 401 %{mcpu=v9:-Av9} \ 402 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 403 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 404 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ 405 " 406 407 /* Word size selection, among other things. 408 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 409 410 #define ASM_ARCH32_SPEC "-32" 411 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 412 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 413 #else 414 #define ASM_ARCH64_SPEC "-64" 415 #endif 416 #define ASM_ARCH_DEFAULT_SPEC \ 417 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 418 419 #define ASM_ARCH_SPEC "\ 420 %{m32:%(asm_arch32)} \ 421 %{m64:%(asm_arch64)} \ 422 %{!m32:%{!m64:%(asm_arch_default)}} \ 423 " 424 425 #ifdef HAVE_AS_RELAX_OPTION 426 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 427 #else 428 #define ASM_RELAX_SPEC "" 429 #endif 430 431 /* Special flags to the Sun-4 assembler when using pipe for input. */ 432 433 #define ASM_SPEC "\ 434 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ 435 %(asm_cpu) %(asm_relax)" 436 437 #define AS_NEEDS_DASH_FOR_PIPED_INPUT 438 439 /* This macro defines names of additional specifications to put in the specs 440 that can be used in various specifications like CC1_SPEC. Its definition 441 is an initializer with a subgrouping for each command option. 442 443 Each subgrouping contains a string constant, that defines the 444 specification name, and a string constant that used by the GCC driver 445 program. 446 447 Do not define this macro if it does not need to do anything. */ 448 449 #define EXTRA_SPECS \ 450 { "cpp_cpu", CPP_CPU_SPEC }, \ 451 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 452 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 453 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 454 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 455 { "cpp_arch", CPP_ARCH_SPEC }, \ 456 { "cpp_endian", CPP_ENDIAN_SPEC }, \ 457 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 458 { "asm_cpu", ASM_CPU_SPEC }, \ 459 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 460 { "asm_arch32", ASM_ARCH32_SPEC }, \ 461 { "asm_arch64", ASM_ARCH64_SPEC }, \ 462 { "asm_relax", ASM_RELAX_SPEC }, \ 463 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 464 { "asm_arch", ASM_ARCH_SPEC }, \ 465 SUBTARGET_EXTRA_SPECS 466 467 #define SUBTARGET_EXTRA_SPECS 468 469 /* Because libgcc can generate references back to libc (via .umul etc.) we have 470 to list libc again after the second libgcc. */ 471 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 472 473 474 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 475 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 476 477 /* ??? This should be 32 bits for v9 but what can we do? */ 478 #define WCHAR_TYPE "short unsigned int" 479 #define WCHAR_TYPE_SIZE 16 480 481 /* Show we can debug even without a frame pointer. */ 482 #define CAN_DEBUG_WITHOUT_FP 483 484 /* Option handling. */ 485 486 #define OVERRIDE_OPTIONS sparc_override_options () 487 488 /* Mask of all CPU selection flags. */ 489 #define MASK_ISA \ 490 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 491 492 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. 493 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y 494 to get high 32 bits. False in V8+ or V9 because multiply stores 495 a 64 bit result in a register. */ 496 497 #define TARGET_HARD_MUL32 \ 498 ((TARGET_V8 || TARGET_SPARCLITE \ 499 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ 500 && ! TARGET_V8PLUS && TARGET_ARCH32) 501 502 #define TARGET_HARD_MUL \ 503 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ 504 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) 505 506 /* MASK_APP_REGS must always be the default because that's what 507 FIXED_REGISTERS is set to and -ffixed- is processed before 508 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ 509 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 510 511 /* Processor type. 512 These must match the values for the cpu attribute in sparc.md. */ 513 enum processor_type { 514 PROCESSOR_V7, 515 PROCESSOR_CYPRESS, 516 PROCESSOR_V8, 517 PROCESSOR_SUPERSPARC, 518 PROCESSOR_SPARCLITE, 519 PROCESSOR_F930, 520 PROCESSOR_F934, 521 PROCESSOR_HYPERSPARC, 522 PROCESSOR_SPARCLITE86X, 523 PROCESSOR_SPARCLET, 524 PROCESSOR_TSC701, 525 PROCESSOR_V9, 526 PROCESSOR_ULTRASPARC, 527 PROCESSOR_ULTRASPARC3 528 }; 529 530 /* This is set from -m{cpu,tune}=xxx. */ 531 extern enum processor_type sparc_cpu; 532 533 /* Recast the cpu class to be the cpu attribute. 534 Every file includes us, but not every file includes insn-attr.h. */ 535 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 536 537 /* Support for a compile-time default CPU, et cetera. The rules are: 538 --with-cpu is ignored if -mcpu is specified. 539 --with-tune is ignored if -mtune is specified. 540 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 541 are specified. */ 542 #define OPTION_DEFAULT_SPECS \ 543 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 544 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 545 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" } 546 547 /* sparc_select[0] is reserved for the default cpu. */ 548 struct sparc_cpu_select 549 { 550 const char *string; 551 const char *const name; 552 const int set_tune_p; 553 const int set_arch_p; 554 }; 555 556 extern struct sparc_cpu_select sparc_select[]; 557 558 /* target machine storage layout */ 559 560 /* Define this if most significant bit is lowest numbered 561 in instructions that operate on numbered bit-fields. */ 562 #define BITS_BIG_ENDIAN 1 563 564 /* Define this if most significant byte of a word is the lowest numbered. */ 565 #define BYTES_BIG_ENDIAN 1 566 567 /* Define this if most significant word of a multiword number is the lowest 568 numbered. */ 569 #define WORDS_BIG_ENDIAN 1 570 571 /* Define this to set the endianness to use in libgcc2.c, which can 572 not depend on target_flags. */ 573 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) 574 #define LIBGCC2_WORDS_BIG_ENDIAN 0 575 #else 576 #define LIBGCC2_WORDS_BIG_ENDIAN 1 577 #endif 578 579 #define MAX_BITS_PER_WORD 64 580 581 /* Width of a word, in units (bytes). */ 582 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 583 #ifdef IN_LIBGCC2 584 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 585 #else 586 #define MIN_UNITS_PER_WORD 4 587 #endif 588 589 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : UNITS_PER_WORD) 590 591 /* Now define the sizes of the C data types. */ 592 593 #define SHORT_TYPE_SIZE 16 594 #define INT_TYPE_SIZE 32 595 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 596 #define LONG_LONG_TYPE_SIZE 64 597 #define FLOAT_TYPE_SIZE 32 598 #define DOUBLE_TYPE_SIZE 64 599 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 600 SPARC ABI says that it is 128-bit wide. */ 601 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 602 603 /* Width in bits of a pointer. 604 See also the macro `Pmode' defined below. */ 605 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 606 607 /* If we have to extend pointers (only when TARGET_ARCH64 and not 608 TARGET_PTR64), we want to do it unsigned. This macro does nothing 609 if ptr_mode and Pmode are the same. */ 610 #define POINTERS_EXTEND_UNSIGNED 1 611 612 /* For TARGET_ARCH64 we need this, as we don't have instructions 613 for arithmetic operations which do zero/sign extension at the same time, 614 so without this we end up with a srl/sra after every assignment to an 615 user variable, which means very very bad code. */ 616 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \ 617 if (TARGET_ARCH64 \ 618 && GET_MODE_CLASS (MODE) == MODE_INT \ 619 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 620 (MODE) = word_mode; 621 622 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 623 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 624 625 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 626 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 627 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 628 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 629 /* Temporary hack until the FIXME above is fixed. */ 630 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 631 632 /* ALIGN FRAMES on double word boundaries */ 633 634 #define SPARC_STACK_ALIGN(LOC) \ 635 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 636 637 /* Allocation boundary (in *bits*) for the code of a function. */ 638 #define FUNCTION_BOUNDARY 32 639 640 /* Alignment of field after `int : 0' in a structure. */ 641 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 642 643 /* Every structure's size must be a multiple of this. */ 644 #define STRUCTURE_SIZE_BOUNDARY 8 645 646 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 647 #define PCC_BITFIELD_TYPE_MATTERS 1 648 649 /* No data type wants to be aligned rounder than this. */ 650 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 651 652 /* The best alignment to use in cases where we have a choice. */ 653 #define FASTEST_ALIGNMENT 64 654 655 /* Define this macro as an expression for the alignment of a structure 656 (given by STRUCT as a tree node) if the alignment computed in the 657 usual way is COMPUTED and the alignment explicitly specified was 658 SPECIFIED. 659 660 The default is to use SPECIFIED if it is larger; otherwise, use 661 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 662 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 663 (TARGET_FASTER_STRUCTS ? \ 664 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 665 || TREE_CODE (STRUCT) == UNION_TYPE \ 666 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 667 && TYPE_FIELDS (STRUCT) != 0 \ 668 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 669 : MAX ((COMPUTED), (SPECIFIED))) \ 670 : MAX ((COMPUTED), (SPECIFIED))) 671 672 /* Make strings word-aligned so strcpy from constants will be faster. */ 673 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 674 ((TREE_CODE (EXP) == STRING_CST \ 675 && (ALIGN) < FASTEST_ALIGNMENT) \ 676 ? FASTEST_ALIGNMENT : (ALIGN)) 677 678 /* Make arrays of chars word-aligned for the same reasons. */ 679 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 680 (TREE_CODE (TYPE) == ARRAY_TYPE \ 681 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 682 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 683 684 /* Set this nonzero if move instructions will actually fail to work 685 when given unaligned data. */ 686 #define STRICT_ALIGNMENT 1 687 688 /* Things that must be doubleword aligned cannot go in the text section, 689 because the linker fails to align the text section enough! 690 Put them in the data section. This macro is only used in this file. */ 691 #define MAX_TEXT_ALIGN 32 692 693 /* Standard register usage. */ 694 695 /* Number of actual hardware registers. 696 The hardware registers are assigned numbers for the compiler 697 from 0 to just below FIRST_PSEUDO_REGISTER. 698 All registers that the compiler knows about must be given numbers, 699 even those that are not normally considered general registers. 700 701 SPARC has 32 integer registers and 32 floating point registers. 702 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not 703 accessible. We still account for them to simplify register computations 704 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 705 32+32+32+4 == 100. 706 Register 100 is used as the integer condition code register. 707 Register 101 is used as the soft frame pointer register. */ 708 709 #define FIRST_PSEUDO_REGISTER 102 710 711 #define SPARC_FIRST_FP_REG 32 712 /* Additional V9 fp regs. */ 713 #define SPARC_FIRST_V9_FP_REG 64 714 #define SPARC_LAST_V9_FP_REG 95 715 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 716 #define SPARC_FIRST_V9_FCC_REG 96 717 #define SPARC_LAST_V9_FCC_REG 99 718 /* V8 fcc reg. */ 719 #define SPARC_FCC_REG 96 720 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 721 #define SPARC_ICC_REG 100 722 723 /* Nonzero if REGNO is an fp reg. */ 724 #define SPARC_FP_REG_P(REGNO) \ 725 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 726 727 /* Argument passing regs. */ 728 #define SPARC_OUTGOING_INT_ARG_FIRST 8 729 #define SPARC_INCOMING_INT_ARG_FIRST 24 730 #define SPARC_FP_ARG_FIRST 32 731 732 /* 1 for registers that have pervasive standard uses 733 and are not available for the register allocator. 734 735 On non-v9 systems: 736 g1 is free to use as temporary. 737 g2-g4 are reserved for applications. Gcc normally uses them as 738 temporaries, but this can be disabled via the -mno-app-regs option. 739 g5 through g7 are reserved for the operating system. 740 741 On v9 systems: 742 g1,g5 are free to use as temporaries, and are free to use between calls 743 if the call is to an external function via the PLT. 744 g4 is free to use as a temporary in the non-embedded case. 745 g4 is reserved in the embedded case. 746 g2-g3 are reserved for applications. Gcc normally uses them as 747 temporaries, but this can be disabled via the -mno-app-regs option. 748 g6-g7 are reserved for the operating system (or application in 749 embedded case). 750 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 751 currently be a fixed register until this pattern is rewritten. 752 Register 1 is also used when restoring call-preserved registers in large 753 stack frames. 754 755 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 756 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 757 */ 758 759 #define FIXED_REGISTERS \ 760 {1, 0, 2, 2, 2, 2, 1, 1, \ 761 0, 0, 0, 0, 0, 0, 1, 0, \ 762 0, 0, 0, 0, 0, 0, 0, 0, \ 763 0, 0, 0, 0, 0, 0, 1, 1, \ 764 \ 765 0, 0, 0, 0, 0, 0, 0, 0, \ 766 0, 0, 0, 0, 0, 0, 0, 0, \ 767 0, 0, 0, 0, 0, 0, 0, 0, \ 768 0, 0, 0, 0, 0, 0, 0, 0, \ 769 \ 770 0, 0, 0, 0, 0, 0, 0, 0, \ 771 0, 0, 0, 0, 0, 0, 0, 0, \ 772 0, 0, 0, 0, 0, 0, 0, 0, \ 773 0, 0, 0, 0, 0, 0, 0, 0, \ 774 \ 775 0, 0, 0, 0, 0, 1} 776 777 /* 1 for registers not available across function calls. 778 These must include the FIXED_REGISTERS and also any 779 registers that can be used without being saved. 780 The latter must include the registers where values are returned 781 and the register where structure-value addresses are passed. 782 Aside from that, you can include as many other registers as you like. */ 783 784 #define CALL_USED_REGISTERS \ 785 {1, 1, 1, 1, 1, 1, 1, 1, \ 786 1, 1, 1, 1, 1, 1, 1, 1, \ 787 0, 0, 0, 0, 0, 0, 0, 0, \ 788 0, 0, 0, 0, 0, 0, 1, 1, \ 789 \ 790 1, 1, 1, 1, 1, 1, 1, 1, \ 791 1, 1, 1, 1, 1, 1, 1, 1, \ 792 1, 1, 1, 1, 1, 1, 1, 1, \ 793 1, 1, 1, 1, 1, 1, 1, 1, \ 794 \ 795 1, 1, 1, 1, 1, 1, 1, 1, \ 796 1, 1, 1, 1, 1, 1, 1, 1, \ 797 1, 1, 1, 1, 1, 1, 1, 1, \ 798 1, 1, 1, 1, 1, 1, 1, 1, \ 799 \ 800 1, 1, 1, 1, 1, 1} 801 802 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that 803 they won't be allocated. */ 804 805 #define CONDITIONAL_REGISTER_USAGE \ 806 do \ 807 { \ 808 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 809 { \ 810 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 811 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 812 } \ 813 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ 814 /* then honor it. */ \ 815 if (TARGET_ARCH32 && fixed_regs[5]) \ 816 fixed_regs[5] = 1; \ 817 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ 818 fixed_regs[5] = 0; \ 819 if (! TARGET_V9) \ 820 { \ 821 int regno; \ 822 for (regno = SPARC_FIRST_V9_FP_REG; \ 823 regno <= SPARC_LAST_V9_FP_REG; \ 824 regno++) \ 825 fixed_regs[regno] = 1; \ 826 /* %fcc0 is used by v8 and v9. */ \ 827 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ 828 regno <= SPARC_LAST_V9_FCC_REG; \ 829 regno++) \ 830 fixed_regs[regno] = 1; \ 831 } \ 832 if (! TARGET_FPU) \ 833 { \ 834 int regno; \ 835 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ 836 fixed_regs[regno] = 1; \ 837 } \ 838 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ 839 /* then honor it. Likewise with g3 and g4. */ \ 840 if (fixed_regs[2] == 2) \ 841 fixed_regs[2] = ! TARGET_APP_REGS; \ 842 if (fixed_regs[3] == 2) \ 843 fixed_regs[3] = ! TARGET_APP_REGS; \ 844 if (TARGET_ARCH32 && fixed_regs[4] == 2) \ 845 fixed_regs[4] = ! TARGET_APP_REGS; \ 846 else if (TARGET_CM_EMBMEDANY) \ 847 fixed_regs[4] = 1; \ 848 else if (fixed_regs[4] == 2) \ 849 fixed_regs[4] = 0; \ 850 } \ 851 while (0) 852 853 /* Return number of consecutive hard regs needed starting at reg REGNO 854 to hold something of mode MODE. 855 This is ordinarily the length in words of a value of mode MODE 856 but can be less for certain modes in special long registers. 857 858 On SPARC, ordinary registers hold 32 bits worth; 859 this means both integer and floating point registers. 860 On v9, integer regs hold 64 bits worth; floating point regs hold 861 32 bits worth (this includes the new fp regs as even the odd ones are 862 included in the hard register count). */ 863 864 #define HARD_REGNO_NREGS(REGNO, MODE) \ 865 (TARGET_ARCH64 \ 866 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ 867 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 868 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 869 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 870 871 /* Due to the ARCH64 discrepancy above we must override this next 872 macro too. */ 873 #define REGMODE_NATURAL_SIZE(MODE) \ 874 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) 875 876 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 877 See sparc.c for how we initialize this. */ 878 extern const int *hard_regno_mode_classes; 879 extern int sparc_mode_class[]; 880 881 /* ??? Because of the funny way we pass parameters we should allow certain 882 ??? types of float/complex values to be in integer registers during 883 ??? RTL generation. This only matters on arch32. */ 884 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 885 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 886 887 /* Value is 1 if it is OK to rename a hard register FROM to another hard 888 register TO. We cannot rename %g1 as it may be used before the save 889 register window instruction in the prologue. */ 890 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 891 892 /* Value is 1 if it is a good idea to tie two pseudo registers 893 when one has mode MODE1 and one has mode MODE2. 894 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 895 for any hard reg, then this must be 0 for correct output. 896 897 For V9: SFmode can't be combined with other float modes, because they can't 898 be allocated to the %d registers. Also, DFmode won't fit in odd %f 899 registers, but SFmode will. */ 900 #define MODES_TIEABLE_P(MODE1, MODE2) \ 901 ((MODE1) == (MODE2) \ 902 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 903 && (! TARGET_V9 \ 904 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 905 || (MODE1 != SFmode && MODE2 != SFmode))))) 906 907 /* Specify the registers used for certain standard purposes. 908 The values of these macros are register numbers. */ 909 910 /* Register to use for pushing function arguments. */ 911 #define STACK_POINTER_REGNUM 14 912 913 /* The stack bias (amount by which the hardware register is offset by). */ 914 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 915 916 /* Actual top-of-stack address is 92/176 greater than the contents of the 917 stack pointer register for !v9/v9. That is: 918 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 919 address, and 6*4 bytes for the 6 register parameters. 920 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 921 parameter regs. */ 922 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 923 924 /* Base register for access to local variables of the function. */ 925 #define HARD_FRAME_POINTER_REGNUM 30 926 927 /* The soft frame pointer does not have the stack bias applied. */ 928 #define FRAME_POINTER_REGNUM 101 929 930 /* Given the stack bias, the stack pointer isn't actually aligned. */ 931 #define INIT_EXPANDERS \ 932 do { \ 933 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \ 934 { \ 935 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 936 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 937 } \ 938 } while (0) 939 940 /* Value should be nonzero if functions must have frame pointers. 941 Zero means the frame pointer need not be set up (and parms 942 may be accessed via the stack pointer) in functions that seem suitable. 943 Used in flow.c, global.c, ra.c and reload1.c. */ 944 #define FRAME_POINTER_REQUIRED \ 945 (! (leaf_function_p () && only_leaf_regs_used ())) 946 947 /* Base register for access to arguments of the function. */ 948 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 949 950 /* Register in which static-chain is passed to a function. This must 951 not be a register used by the prologue. */ 952 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 953 954 /* Register which holds offset table for position-independent 955 data references. */ 956 957 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) 958 959 /* Pick a default value we can notice from override_options: 960 !v9: Default is on. 961 v9: Default is off. */ 962 963 #define DEFAULT_PCC_STRUCT_RETURN -1 964 965 /* Functions which return large structures get the address 966 to place the wanted value at offset 64 from the frame. 967 Must reserve 64 bytes for the in and local registers. 968 v9: Functions which return large structures get the address to place the 969 wanted value from an invisible first argument. */ 970 #define STRUCT_VALUE_OFFSET 64 971 972 /* Define the classes of registers for register constraints in the 973 machine description. Also define ranges of constants. 974 975 One of the classes must always be named ALL_REGS and include all hard regs. 976 If there is more than one class, another class must be named NO_REGS 977 and contain no registers. 978 979 The name GENERAL_REGS must be the name of a class (or an alias for 980 another name such as ALL_REGS). This is the class of registers 981 that is allowed by "g" or "r" in a register constraint. 982 Also, registers outside this class are allocated only when 983 instructions express preferences for them. 984 985 The classes must be numbered in nondecreasing order; that is, 986 a larger-numbered class must never be contained completely 987 in a smaller-numbered class. 988 989 For any two classes, it is very desirable that there be another 990 class that represents their union. */ 991 992 /* The SPARC has various kinds of registers: general, floating point, 993 and condition codes [well, it has others as well, but none that we 994 care directly about]. 995 996 For v9 we must distinguish between the upper and lower floating point 997 registers because the upper ones can't hold SFmode values. 998 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 999 satisfying a group need for a class will also satisfy a single need for 1000 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 1001 regs. 1002 1003 It is important that one class contains all the general and all the standard 1004 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 1005 because reg_class_record() will bias the selection in favor of fp regs, 1006 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 1007 because FP_REGS > GENERAL_REGS. 1008 1009 It is also important that one class contain all the general and all 1010 the fp regs. Otherwise when spilling a DFmode reg, it may be from 1011 EXTRA_FP_REGS but find_reloads() may use class 1012 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 1013 because the compiler thinks it doesn't have a spill reg when in 1014 fact it does. 1015 1016 v9 also has 4 floating point condition code registers. Since we don't 1017 have a class that is the union of FPCC_REGS with either of the others, 1018 it is important that it appear first. Otherwise the compiler will die 1019 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 1020 constraints. 1021 1022 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 1023 may try to use it to hold an SImode value. See register_operand. 1024 ??? Should %fcc[0123] be handled similarly? 1025 */ 1026 1027 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 1028 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 1029 ALL_REGS, LIM_REG_CLASSES }; 1030 1031 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1032 1033 /* Give names of register classes as strings for dump file. */ 1034 1035 #define REG_CLASS_NAMES \ 1036 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 1037 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 1038 "ALL_REGS" } 1039 1040 /* Define which registers fit in which classes. 1041 This is an initializer for a vector of HARD_REG_SET 1042 of length N_REG_CLASSES. */ 1043 1044 #define REG_CLASS_CONTENTS \ 1045 {{0, 0, 0, 0}, /* NO_REGS */ \ 1046 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 1047 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 1048 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 1049 {0, -1, 0, 0}, /* FP_REGS */ \ 1050 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 1051 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 1052 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 1053 {-1, -1, -1, 0x3f}} /* ALL_REGS */ 1054 1055 /* Defines invalid mode changes. Borrowed from pa64-regs.h. 1056 1057 SImode loads to floating-point registers are not zero-extended. 1058 The definition for LOAD_EXTEND_OP specifies that integer loads 1059 narrower than BITS_PER_WORD will be zero-extended. As a result, 1060 we inhibit changes from SImode unless they are to a mode that is 1061 identical in size. */ 1062 1063 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1064 (TARGET_ARCH64 \ 1065 && (FROM) == SImode \ 1066 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1067 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 1068 1069 /* The same information, inverted: 1070 Return the class number of the smallest class containing 1071 reg number REGNO. This could be a conditional expression 1072 or could index an array. */ 1073 1074 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 1075 1076 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 1077 1078 /* This is the order in which to allocate registers normally. 1079 1080 We put %f0-%f7 last among the float registers, so as to make it more 1081 likely that a pseudo-register which dies in the float return register 1082 area will get allocated to the float return register, thus saving a move 1083 instruction at the end of the function. 1084 1085 Similarly for integer return value registers. 1086 1087 We know in this case that we will not end up with a leaf function. 1088 1089 The register allocator is given the global and out registers first 1090 because these registers are call clobbered and thus less useful to 1091 global register allocation. 1092 1093 Next we list the local and in registers. They are not call clobbered 1094 and thus very useful for global register allocation. We list the input 1095 registers before the locals so that it is more likely the incoming 1096 arguments received in those registers can just stay there and not be 1097 reloaded. */ 1098 1099 #define REG_ALLOC_ORDER \ 1100 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1101 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1102 15, /* %o7 */ \ 1103 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1104 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 1105 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1106 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1107 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1108 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1109 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1110 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1111 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1112 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1113 96, 97, 98, 99, /* %fcc0-3 */ \ 1114 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ 1115 1116 /* This is the order in which to allocate registers for 1117 leaf functions. If all registers can fit in the global and 1118 output registers, then we have the possibility of having a leaf 1119 function. 1120 1121 The macro actually mentioned the input registers first, 1122 because they get renumbered into the output registers once 1123 we know really do have a leaf function. 1124 1125 To be more precise, this register allocation order is used 1126 when %o7 is found to not be clobbered right before register 1127 allocation. Normally, the reason %o7 would be clobbered is 1128 due to a call which could not be transformed into a sibling 1129 call. 1130 1131 As a consequence, it is possible to use the leaf register 1132 allocation order and not end up with a leaf function. We will 1133 not get suboptimal register allocation in that case because by 1134 definition of being potentially leaf, there were no function 1135 calls. Therefore, allocation order within the local register 1136 window is not critical like it is when we do have function calls. */ 1137 1138 #define REG_LEAF_ALLOC_ORDER \ 1139 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1140 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 1141 15, /* %o7 */ \ 1142 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1143 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1144 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1145 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1146 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1147 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1148 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1149 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1150 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1151 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1152 96, 97, 98, 99, /* %fcc0-3 */ \ 1153 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 1154 1155 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 1156 1157 extern char sparc_leaf_regs[]; 1158 #define LEAF_REGISTERS sparc_leaf_regs 1159 1160 extern char leaf_reg_remap[]; 1161 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1162 1163 /* The class value for index registers, and the one for base regs. */ 1164 #define INDEX_REG_CLASS GENERAL_REGS 1165 #define BASE_REG_CLASS GENERAL_REGS 1166 1167 /* Local macro to handle the two v9 classes of FP regs. */ 1168 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1169 1170 /* Get reg_class from a letter such as appears in the machine description. 1171 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the 1172 .md file for v8 and v9. 1173 'd' and 'b' are used for single and double precision VIS operations, 1174 if TARGET_VIS. 1175 'h' is used for V8+ 64 bit global and out registers. */ 1176 1177 #define REG_CLASS_FROM_LETTER(C) \ 1178 (TARGET_V9 \ 1179 ? ((C) == 'f' ? FP_REGS \ 1180 : (C) == 'e' ? EXTRA_FP_REGS \ 1181 : (C) == 'c' ? FPCC_REGS \ 1182 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ 1183 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ 1184 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ 1185 : NO_REGS) \ 1186 : ((C) == 'f' ? FP_REGS \ 1187 : (C) == 'e' ? FP_REGS \ 1188 : (C) == 'c' ? FPCC_REGS \ 1189 : NO_REGS)) 1190 1191 /* The letters I, J, K, L, M, N, O, P in a register constraint string 1192 can be used to stand for particular ranges of CONST_INTs. 1193 This macro defines what the ranges are. 1194 C is the letter, and VALUE is a constant value. 1195 Return 1 if VALUE is in the range specified by C. 1196 1197 `I' is used for the range of constants an insn can actually contain. 1198 `J' is used for the range which is just zero (since that is R0). 1199 `K' is used for constants which can be loaded with a single sethi insn. 1200 `L' is used for the range of constants supported by the movcc insns. 1201 `M' is used for the range of constants supported by the movrcc insns. 1202 `N' is like K, but for constants wider than 32 bits. 1203 `O' is used for the range which is just 4096. 1204 `P' is free. */ 1205 1206 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */ 1207 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1208 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1209 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1210 1211 /* 10- and 11-bit immediates are only used for a few specific insns. 1212 SMALL_INT is used throughout the port so we continue to use it. */ 1213 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1214 1215 /* Predicate for constants that can be loaded with a sethi instruction. 1216 This is the general, 64-bit aware, bitwise version that ensures that 1217 only constants whose representation fits in the mask 1218 1219 0x00000000fffffc00 1220 1221 are accepted. It will reject, for example, negative SImode constants 1222 on 64-bit hosts, so correct handling is to mask the value beforehand 1223 according to the mode of the instruction. */ 1224 #define SPARC_SETHI_P(X) \ 1225 (((unsigned HOST_WIDE_INT) (X) \ 1226 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1227 1228 /* Version of the above predicate for SImode constants and below. */ 1229 #define SPARC_SETHI32_P(X) \ 1230 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1231 1232 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1233 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ 1234 : (C) == 'J' ? (VALUE) == 0 \ 1235 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \ 1236 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ 1237 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ 1238 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ 1239 : (C) == 'O' ? (VALUE) == 4096 \ 1240 : 0) 1241 1242 /* Similar, but for CONST_DOUBLEs, and defining letters G and H. 1243 Here VALUE is the CONST_DOUBLE rtx itself. */ 1244 1245 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1246 ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \ 1247 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1248 : 0) 1249 1250 /* Given an rtx X being reloaded into a reg required to be 1251 in class CLASS, return the class of reg to actually use. 1252 In general this is just CLASS; but on some machines 1253 in some cases it is preferable to use a more restrictive class. */ 1254 /* - We can't load constants into FP registers. 1255 - We can't load FP constants into integer registers when soft-float, 1256 because there is no soft-float pattern with a r/F constraint. 1257 - We can't load FP constants into integer registers for TFmode unless 1258 it is 0.0L, because there is no movtf pattern with a r/F constraint. 1259 - Try and reload integer constants (symbolic or otherwise) back into 1260 registers directly, rather than having them dumped to memory. */ 1261 1262 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1263 (CONSTANT_P (X) \ 1264 ? ((FP_REG_CLASS_P (CLASS) \ 1265 || (CLASS) == GENERAL_OR_FP_REGS \ 1266 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ 1267 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1268 && ! TARGET_FPU) \ 1269 || (GET_MODE (X) == TFmode \ 1270 && ! const_zero_operand (X, TFmode))) \ 1271 ? NO_REGS \ 1272 : (!FP_REG_CLASS_P (CLASS) \ 1273 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ 1274 ? GENERAL_REGS \ 1275 : (CLASS)) \ 1276 : (CLASS)) 1277 1278 /* Return the register class of a scratch register needed to load IN into 1279 a register of class CLASS in MODE. 1280 1281 We need a temporary when loading/storing a HImode/QImode value 1282 between memory and the FPU registers. This can happen when combine puts 1283 a paradoxical subreg in a float/fix conversion insn. 1284 1285 We need a temporary when loading/storing a DFmode value between 1286 unaligned memory and the upper FPU registers. */ 1287 1288 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1289 ((FP_REG_CLASS_P (CLASS) \ 1290 && ((MODE) == HImode || (MODE) == QImode) \ 1291 && (GET_CODE (IN) == MEM \ 1292 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1293 && true_regnum (IN) == -1))) \ 1294 ? GENERAL_REGS \ 1295 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1296 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1297 && ! mem_min_alignment ((IN), 8)) \ 1298 ? FP_REGS \ 1299 : (((TARGET_CM_MEDANY \ 1300 && symbolic_operand ((IN), (MODE))) \ 1301 || (TARGET_CM_EMBMEDANY \ 1302 && text_segment_operand ((IN), (MODE)))) \ 1303 && !flag_pic) \ 1304 ? GENERAL_REGS \ 1305 : NO_REGS) 1306 1307 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1308 ((FP_REG_CLASS_P (CLASS) \ 1309 && ((MODE) == HImode || (MODE) == QImode) \ 1310 && (GET_CODE (IN) == MEM \ 1311 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1312 && true_regnum (IN) == -1))) \ 1313 ? GENERAL_REGS \ 1314 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1315 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1316 && ! mem_min_alignment ((IN), 8)) \ 1317 ? FP_REGS \ 1318 : (((TARGET_CM_MEDANY \ 1319 && symbolic_operand ((IN), (MODE))) \ 1320 || (TARGET_CM_EMBMEDANY \ 1321 && text_segment_operand ((IN), (MODE)))) \ 1322 && !flag_pic) \ 1323 ? GENERAL_REGS \ 1324 : NO_REGS) 1325 1326 /* On SPARC it is not possible to directly move data between 1327 GENERAL_REGS and FP_REGS. */ 1328 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1329 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1330 1331 /* Return the stack location to use for secondary memory needed reloads. 1332 We want to use the reserved location just below the frame pointer. 1333 However, we must ensure that there is a frame, so use assign_stack_local 1334 if the frame size is zero. */ 1335 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1336 (get_frame_size () == 0 \ 1337 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ 1338 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \ 1339 STARTING_FRAME_OFFSET))) 1340 1341 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1342 because the movsi and movsf patterns don't handle r/f moves. 1343 For v8 we copy the default definition. */ 1344 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1345 (TARGET_ARCH64 \ 1346 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1347 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1348 : MODE) \ 1349 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1350 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1351 : MODE)) 1352 1353 /* Return the maximum number of consecutive registers 1354 needed to represent mode MODE in a register of class CLASS. */ 1355 /* On SPARC, this is the size of MODE in words. */ 1356 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1357 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1358 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1359 1360 /* Stack layout; function entry, exit and calling. */ 1361 1362 /* Define this if pushing a word on the stack 1363 makes the stack pointer a smaller address. */ 1364 #define STACK_GROWS_DOWNWARD 1365 1366 /* Define this to nonzero if the nominal address of the stack frame 1367 is at the high-address end of the local variables; 1368 that is, each additional local variable allocated 1369 goes at a more negative offset in the frame. */ 1370 #define FRAME_GROWS_DOWNWARD 1 1371 1372 /* Offset within stack frame to start allocating local variables at. 1373 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1374 first local allocated. Otherwise, it is the offset to the BEGINNING 1375 of the first local allocated. */ 1376 /* This allows space for one TFmode floating point value, which is used 1377 by SECONDARY_MEMORY_NEEDED_RTX. */ 1378 #define STARTING_FRAME_OFFSET \ 1379 (TARGET_ARCH64 ? -16 \ 1380 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1381 1382 /* Offset of first parameter from the argument pointer register value. 1383 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1384 even if this function isn't going to use it. 1385 v9: This is 128 for the ins and locals. */ 1386 #define FIRST_PARM_OFFSET(FNDECL) \ 1387 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1388 1389 /* Offset from the argument pointer register value to the CFA. 1390 This is different from FIRST_PARM_OFFSET because the register window 1391 comes between the CFA and the arguments. */ 1392 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1393 1394 /* When a parameter is passed in a register, stack space is still 1395 allocated for it. 1396 !v9: All 6 possible integer registers have backing store allocated. 1397 v9: Only space for the arguments passed is allocated. */ 1398 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1399 meaning to the backend. Further, we need to be able to detect if a 1400 varargs/unprototyped function is called, as they may want to spill more 1401 registers than we've provided space. Ugly, ugly. So for now we retain 1402 all 6 slots even for v9. */ 1403 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1404 1405 /* Definitions for register elimination. */ 1406 1407 #define ELIMINABLE_REGS \ 1408 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1409 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1410 1411 /* The way this is structured, we can't eliminate SFP in favor of SP 1412 if the frame pointer is required: we want to use the SFP->HFP elimination 1413 in that case. But the test in update_eliminables doesn't know we are 1414 assuming below that we only do the former elimination. */ 1415 #define CAN_ELIMINATE(FROM, TO) \ 1416 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED) 1417 1418 /* We always pretend that this is a leaf function because if it's not, 1419 there's no point in trying to eliminate the frame pointer. If it 1420 is a leaf function, we guessed right! */ 1421 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1422 do { \ 1423 if ((TO) == STACK_POINTER_REGNUM) \ 1424 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \ 1425 else \ 1426 (OFFSET) = 0; \ 1427 (OFFSET) += SPARC_STACK_BIAS; \ 1428 } while (0) 1429 1430 /* Keep the stack pointer constant throughout the function. 1431 This is both an optimization and a necessity: longjmp 1432 doesn't behave itself when the stack pointer moves within 1433 the function! */ 1434 #define ACCUMULATE_OUTGOING_ARGS 1 1435 1436 /* Value is the number of bytes of arguments automatically 1437 popped when returning from a subroutine call. 1438 FUNDECL is the declaration node of the function (as a tree), 1439 FUNTYPE is the data type of the function (as a tree), 1440 or for a library call it is an identifier node for the subroutine name. 1441 SIZE is the number of bytes of arguments passed on the stack. */ 1442 1443 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1444 1445 /* Define this macro if the target machine has "register windows". This 1446 C expression returns the register number as seen by the called function 1447 corresponding to register number OUT as seen by the calling function. 1448 Return OUT if register number OUT is not an outbound register. */ 1449 1450 #define INCOMING_REGNO(OUT) \ 1451 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1452 1453 /* Define this macro if the target machine has "register windows". This 1454 C expression returns the register number as seen by the calling function 1455 corresponding to register number IN as seen by the called function. 1456 Return IN if register number IN is not an inbound register. */ 1457 1458 #define OUTGOING_REGNO(IN) \ 1459 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1460 1461 /* Define this macro if the target machine has register windows. This 1462 C expression returns true if the register is call-saved but is in the 1463 register window. */ 1464 1465 #define LOCAL_REGNO(REGNO) \ 1466 ((REGNO) >= 16 && (REGNO) <= 31) 1467 1468 /* Define how to find the value returned by a function. 1469 VALTYPE is the data type of the value (as a tree). 1470 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1471 otherwise, FUNC is 0. */ 1472 1473 /* On SPARC the value is found in the first "output" register. */ 1474 1475 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1476 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) 1477 1478 /* But the called function leaves it in the first "input" register. */ 1479 1480 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1481 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) 1482 1483 /* Define how to find the value returned by a library function 1484 assuming the value has mode MODE. */ 1485 1486 #define LIBCALL_VALUE(MODE) \ 1487 function_value (NULL_TREE, (MODE), 1) 1488 1489 /* 1 if N is a possible register number for a function value 1490 as seen by the caller. 1491 On SPARC, the first "output" reg is used for integer values, 1492 and the first floating point register is used for floating point values. */ 1493 1494 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1495 1496 /* Define the size of space to allocate for the return value of an 1497 untyped_call. */ 1498 1499 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1500 1501 /* 1 if N is a possible register number for function argument passing. 1502 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1503 1504 #define FUNCTION_ARG_REGNO_P(N) \ 1505 (TARGET_ARCH64 \ 1506 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1507 : ((N) >= 8 && (N) <= 13)) 1508 1509 /* Define a data type for recording info about an argument list 1510 during the scan of that argument list. This data type should 1511 hold all necessary information about the function itself 1512 and about the args processed so far, enough to enable macros 1513 such as FUNCTION_ARG to determine where the next arg should go. 1514 1515 On SPARC (!v9), this is a single integer, which is a number of words 1516 of arguments scanned so far (including the invisible argument, 1517 if any, which holds the structure-value-address). 1518 Thus 7 or more means all following args should go on the stack. 1519 1520 For v9, we also need to know whether a prototype is present. */ 1521 1522 struct sparc_args { 1523 int words; /* number of words passed so far */ 1524 int prototype_p; /* nonzero if a prototype is present */ 1525 int libcall_p; /* nonzero if a library call */ 1526 }; 1527 #define CUMULATIVE_ARGS struct sparc_args 1528 1529 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1530 for a call to a function whose data type is FNTYPE. 1531 For a library call, FNTYPE is 0. */ 1532 1533 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1534 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1535 1536 /* Update the data in CUM to advance over an argument 1537 of mode MODE and data type TYPE. 1538 TYPE is null for libcalls where that information may not be available. */ 1539 1540 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1541 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) 1542 1543 /* Determine where to put an argument to a function. 1544 Value is zero to push the argument on the stack, 1545 or a hard register in which to store the argument. 1546 1547 MODE is the argument's machine mode. 1548 TYPE is the data type of the argument (as a tree). 1549 This is null for libcalls where that information may 1550 not be available. 1551 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1552 the preceding args and about the function being called. 1553 NAMED is nonzero if this argument is a named parameter 1554 (otherwise it is an extra parameter matching an ellipsis). */ 1555 1556 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1557 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) 1558 1559 /* Define where a function finds its arguments. 1560 This is different from FUNCTION_ARG because of register windows. */ 1561 1562 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1563 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) 1564 1565 /* If defined, a C expression which determines whether, and in which direction, 1566 to pad out an argument with extra space. The value should be of type 1567 `enum direction': either `upward' to pad above the argument, 1568 `downward' to pad below, or `none' to inhibit padding. */ 1569 1570 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1571 function_arg_padding ((MODE), (TYPE)) 1572 1573 /* If defined, a C expression that gives the alignment boundary, in bits, 1574 of an argument with the specified mode and type. If it is not defined, 1575 PARM_BOUNDARY is used for all arguments. 1576 For sparc64, objects requiring 16 byte alignment are passed that way. */ 1577 1578 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1579 ((TARGET_ARCH64 \ 1580 && (GET_MODE_ALIGNMENT (MODE) == 128 \ 1581 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ 1582 ? 128 : PARM_BOUNDARY) 1583 1584 /* Define the information needed to generate branch and scc insns. This is 1585 stored from the compare operation. Note that we can't use "rtx" here 1586 since it hasn't been defined! */ 1587 1588 extern GTY(()) rtx sparc_compare_op0; 1589 extern GTY(()) rtx sparc_compare_op1; 1590 extern GTY(()) rtx sparc_compare_emitted; 1591 1592 1593 /* Generate the special assembly code needed to tell the assembler whatever 1594 it might need to know about the return value of a function. 1595 1596 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1597 information to the assembler relating to peephole optimization (done in 1598 the assembler). */ 1599 1600 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1601 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1602 1603 /* Output the special assembly code needed to tell the assembler some 1604 register is used as global register variable. 1605 1606 SPARC 64bit psABI declares registers %g2 and %g3 as application 1607 registers and %g6 and %g7 as OS registers. Any object using them 1608 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1609 and how they are used (scratch or some global variable). 1610 Linker will then refuse to link together objects which use those 1611 registers incompatibly. 1612 1613 Unless the registers are used for scratch, two different global 1614 registers cannot be declared to the same name, so in the unlikely 1615 case of a global register variable occupying more than one register 1616 we prefix the second and following registers with .gnu.part1. etc. */ 1617 1618 extern GTY(()) char sparc_hard_reg_printed[8]; 1619 1620 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 1621 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1622 do { \ 1623 if (TARGET_ARCH64) \ 1624 { \ 1625 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1626 int reg; \ 1627 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1628 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1629 { \ 1630 if (reg == (REGNO)) \ 1631 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1632 else \ 1633 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1634 reg, reg - (REGNO), (NAME)); \ 1635 sparc_hard_reg_printed[reg] = 1; \ 1636 } \ 1637 } \ 1638 } while (0) 1639 #endif 1640 1641 1642 /* Emit rtl for profiling. */ 1643 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1644 1645 /* All the work done in PROFILE_HOOK, but still required. */ 1646 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1647 1648 /* Set the name of the mcount function for the system. */ 1649 #define MCOUNT_FUNCTION "*mcount" 1650 1651 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1652 the stack pointer does not matter. The value is tested only in 1653 functions that have frame pointers. 1654 No definition is equivalent to always zero. */ 1655 1656 #define EXIT_IGNORE_STACK \ 1657 (get_frame_size () != 0 \ 1658 || current_function_calls_alloca || current_function_outgoing_args_size) 1659 1660 /* Define registers used by the epilogue and return instruction. */ 1661 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \ 1662 || (current_function_calls_eh_return && (REGNO) == 1)) 1663 1664 /* Length in units of the trampoline for entering a nested function. */ 1665 1666 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1667 1668 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ 1669 1670 /* Emit RTL insns to initialize the variable parts of a trampoline. 1671 FNADDR is an RTX for the address of the function's pure code. 1672 CXT is an RTX for the static chain value for the function. */ 1673 1674 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1675 if (TARGET_ARCH64) \ 1676 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1677 else \ 1678 sparc_initialize_trampoline (TRAMP, FNADDR, CXT) 1679 1680 /* Implement `va_start' for varargs and stdarg. */ 1681 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1682 sparc_va_start (valist, nextarg) 1683 1684 /* Generate RTL to flush the register windows so as to make arbitrary frames 1685 available. */ 1686 #define SETUP_FRAME_ADDRESSES() \ 1687 emit_insn (gen_flush_register_windows ()) 1688 1689 /* Given an rtx for the address of a frame, 1690 return an rtx for the address of the word in the frame 1691 that holds the dynamic chain--the previous frame's address. */ 1692 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1693 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1694 1695 /* The return address isn't on the stack, it is in a register, so we can't 1696 access it from the current frame pointer. We can access it from the 1697 previous frame pointer though by reading a value from the register window 1698 save area. */ 1699 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1700 1701 /* This is the offset of the return address to the true next instruction to be 1702 executed for the current function. */ 1703 #define RETURN_ADDR_OFFSET \ 1704 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) 1705 1706 /* The current return address is in %i7. The return address of anything 1707 farther back is in the register window save area at [%fp+60]. */ 1708 /* ??? This ignores the fact that the actual return address is +8 for normal 1709 returns, and +12 for structure returns. */ 1710 #define RETURN_ADDR_RTX(count, frame) \ 1711 ((count == -1) \ 1712 ? gen_rtx_REG (Pmode, 31) \ 1713 : gen_rtx_MEM (Pmode, \ 1714 memory_address (Pmode, plus_constant (frame, \ 1715 15 * UNITS_PER_WORD \ 1716 + SPARC_STACK_BIAS)))) 1717 1718 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1719 +12, but always using +8 is close enough for frame unwind purposes. 1720 Actually, just using %o7 is close enough for unwinding, but %o7+8 1721 is something you can return to. */ 1722 #define INCOMING_RETURN_ADDR_RTX \ 1723 plus_constant (gen_rtx_REG (word_mode, 15), 8) 1724 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) 1725 1726 /* The offset from the incoming value of %sp to the top of the stack frame 1727 for the current function. On sparc64, we have to account for the stack 1728 bias if present. */ 1729 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1730 1731 /* Describe how we implement __builtin_eh_return. */ 1732 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1733 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ 1734 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ 1735 1736 /* Select a format to encode pointers in exception handling data. CODE 1737 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1738 true if the symbol may be affected by dynamic relocations. 1739 1740 If assembler and linker properly support .uaword %r_disp32(foo), 1741 then use PC relative 32-bit relocations instead of absolute relocs 1742 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1743 for binaries, to save memory. 1744 1745 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1746 symbol %r_disp32() is against was not local, but .hidden. In that 1747 case, we have to use DW_EH_PE_absptr for pic personality. */ 1748 #ifdef HAVE_AS_SPARC_UA_PCREL 1749 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1750 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1751 (flag_pic \ 1752 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1753 : ((TARGET_ARCH64 && ! GLOBAL) \ 1754 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1755 : DW_EH_PE_absptr)) 1756 #else 1757 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1758 (flag_pic \ 1759 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1760 : ((TARGET_ARCH64 && ! GLOBAL) \ 1761 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1762 : DW_EH_PE_absptr)) 1763 #endif 1764 1765 /* Emit a PC-relative relocation. */ 1766 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1767 do { \ 1768 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1769 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1770 assemble_name (FILE, LABEL); \ 1771 fputc (')', FILE); \ 1772 } while (0) 1773 #endif 1774 1775 /* Addressing modes, and classification of registers for them. */ 1776 1777 /* Macros to check register numbers against specific register classes. */ 1778 1779 /* These assume that REGNO is a hard or pseudo reg number. 1780 They give nonzero only if REGNO is a hard reg of the suitable class 1781 or a pseudo reg currently allocated to a suitable hard reg. 1782 Since they use reg_renumber, they are safe only once reg_renumber 1783 has been allocated, which happens in local-alloc.c. */ 1784 1785 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1786 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ 1787 || (REGNO) == FRAME_POINTER_REGNUM \ 1788 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1789 1790 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1791 1792 #define REGNO_OK_FOR_FP_P(REGNO) \ 1793 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1794 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1795 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1796 (TARGET_V9 \ 1797 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1798 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1799 1800 /* Now macros that check whether X is a register and also, 1801 strictly, whether it is in a specified class. 1802 1803 These macros are specific to the SPARC, and may be used only 1804 in code for printing assembler insns and in conditions for 1805 define_optimization. */ 1806 1807 /* 1 if X is an fp register. */ 1808 1809 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1810 1811 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ 1812 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) 1813 1814 /* Maximum number of registers that can appear in a valid memory address. */ 1815 1816 #define MAX_REGS_PER_ADDRESS 2 1817 1818 /* Recognize any constant value that is a valid address. 1819 When PIC, we do not accept an address that would require a scratch reg 1820 to load into a register. */ 1821 1822 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1823 1824 /* Define this, so that when PIC, reload won't try to reload invalid 1825 addresses which require two reload registers. */ 1826 1827 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1828 1829 /* Nonzero if the constant value X is a legitimate general operand. 1830 Anything can be made to work except floating point constants. 1831 If TARGET_VIS, 0.0 can be made to work as well. */ 1832 1833 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1834 1835 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1836 and check its validity for a certain class. 1837 We have two alternate definitions for each of them. 1838 The usual definition accepts all pseudo regs; the other rejects 1839 them unless they have been allocated suitable hard regs. 1840 The symbol REG_OK_STRICT causes the latter definition to be used. 1841 1842 Most source files want to accept pseudo regs in the hope that 1843 they will get allocated to the class that the insn wants them to be in. 1844 Source files for reload pass need to be strict. 1845 After reload, it makes no difference, since pseudo regs have 1846 been eliminated by then. */ 1847 1848 /* Optional extra constraints for this machine. 1849 1850 'Q' handles floating point constants which can be moved into 1851 an integer register with a single sethi instruction. 1852 1853 'R' handles floating point constants which can be moved into 1854 an integer register with a single mov instruction. 1855 1856 'S' handles floating point constants which can be moved into 1857 an integer register using a high/lo_sum sequence. 1858 1859 'T' handles memory addresses where the alignment is known to 1860 be at least 8 bytes. 1861 1862 `U' handles all pseudo registers or a hard even numbered 1863 integer register, needed for ldd/std instructions. 1864 1865 'W' handles the memory operand when moving operands in/out 1866 of 'e' constraint floating point registers. 1867 1868 'Y' handles the zero vector constant. */ 1869 1870 #ifndef REG_OK_STRICT 1871 1872 /* Nonzero if X is a hard reg that can be used as an index 1873 or if it is a pseudo reg. */ 1874 #define REG_OK_FOR_INDEX_P(X) \ 1875 (REGNO (X) < 32 \ 1876 || REGNO (X) == FRAME_POINTER_REGNUM \ 1877 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1878 1879 /* Nonzero if X is a hard reg that can be used as a base reg 1880 or if it is a pseudo reg. */ 1881 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) 1882 1883 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. 1884 'W' is like 'T' but is assumed true on arch64. 1885 1886 Remember to accept pseudo-registers for memory constraints if reload is 1887 in progress. */ 1888 1889 #define EXTRA_CONSTRAINT(OP, C) \ 1890 sparc_extra_constraint_check(OP, C, 0) 1891 1892 #else 1893 1894 /* Nonzero if X is a hard reg that can be used as an index. */ 1895 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1896 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1897 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1898 1899 #define EXTRA_CONSTRAINT(OP, C) \ 1900 sparc_extra_constraint_check(OP, C, 1) 1901 1902 #endif 1903 1904 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1905 1906 #ifdef HAVE_AS_OFFSETABLE_LO10 1907 #define USE_AS_OFFSETABLE_LO10 1 1908 #else 1909 #define USE_AS_OFFSETABLE_LO10 0 1910 #endif 1911 1912 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1913 that is a valid memory address for an instruction. 1914 The MODE argument is the machine mode for the MEM expression 1915 that wants to use this address. 1916 1917 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 1918 ordinarily. This changes a bit when generating PIC. 1919 1920 If you change this, execute "rm explow.o recog.o reload.o". */ 1921 1922 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) 1923 1924 #define RTX_OK_FOR_BASE_P(X) \ 1925 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1926 || (GET_CODE (X) == SUBREG \ 1927 && GET_CODE (SUBREG_REG (X)) == REG \ 1928 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1929 1930 #define RTX_OK_FOR_INDEX_P(X) \ 1931 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1932 || (GET_CODE (X) == SUBREG \ 1933 && GET_CODE (SUBREG_REG (X)) == REG \ 1934 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1935 1936 #define RTX_OK_FOR_OFFSET_P(X) \ 1937 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) 1938 1939 #define RTX_OK_FOR_OLO10_P(X) \ 1940 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) 1941 1942 #ifdef REG_OK_STRICT 1943 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1944 { \ 1945 if (legitimate_address_p (MODE, X, 1)) \ 1946 goto ADDR; \ 1947 } 1948 #else 1949 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1950 { \ 1951 if (legitimate_address_p (MODE, X, 0)) \ 1952 goto ADDR; \ 1953 } 1954 #endif 1955 1956 /* Go to LABEL if ADDR (a legitimate address expression) 1957 has an effect that depends on the machine mode it is used for. 1958 1959 In PIC mode, 1960 1961 (mem:HI [%l7+a]) 1962 1963 is not equivalent to 1964 1965 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) 1966 1967 because [%l7+a+1] is interpreted as the address of (a+1). */ 1968 1969 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1970 { \ 1971 if (flag_pic == 1) \ 1972 { \ 1973 if (GET_CODE (ADDR) == PLUS) \ 1974 { \ 1975 rtx op0 = XEXP (ADDR, 0); \ 1976 rtx op1 = XEXP (ADDR, 1); \ 1977 if (op0 == pic_offset_table_rtx \ 1978 && SYMBOLIC_CONST (op1)) \ 1979 goto LABEL; \ 1980 } \ 1981 } \ 1982 } 1983 1984 /* Try machine-dependent ways of modifying an illegitimate address 1985 to be legitimate. If we find one, return the new, valid address. 1986 This macro is used in only one place: `memory_address' in explow.c. 1987 1988 OLDX is the address as it was before break_out_memory_refs was called. 1989 In some cases it is useful to look at this to decide what needs to be done. 1990 1991 MODE and WIN are passed so that this macro can use 1992 GO_IF_LEGITIMATE_ADDRESS. 1993 1994 It is always safe for this macro to do nothing. It exists to recognize 1995 opportunities to optimize the output. */ 1996 1997 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 1998 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1999 { \ 2000 (X) = legitimize_address (X, OLDX, MODE); \ 2001 if (memory_address_p (MODE, X)) \ 2002 goto WIN; \ 2003 } 2004 2005 /* Try a machine-dependent way of reloading an illegitimate address 2006 operand. If we find one, push the reload and jump to WIN. This 2007 macro is used in only one place: `find_reloads_address' in reload.c. 2008 2009 For SPARC 32, we wish to handle addresses by splitting them into 2010 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 2011 This cuts the number of extra insns by one. 2012 2013 Do nothing when generating PIC code and the address is a 2014 symbolic operand or requires a scratch register. */ 2015 2016 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2017 do { \ 2018 /* Decompose SImode constants into hi+lo_sum. We do have to \ 2019 rerecognize what we produce, so be careful. */ \ 2020 if (CONSTANT_P (X) \ 2021 && (MODE != TFmode || TARGET_ARCH64) \ 2022 && GET_MODE (X) == SImode \ 2023 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ 2024 && ! (flag_pic \ 2025 && (symbolic_operand (X, Pmode) \ 2026 || pic_address_needs_scratch (X))) \ 2027 && sparc_cmodel <= CM_MEDLOW) \ 2028 { \ 2029 X = gen_rtx_LO_SUM (GET_MODE (X), \ 2030 gen_rtx_HIGH (GET_MODE (X), X), X); \ 2031 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 2032 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 2033 OPNUM, TYPE); \ 2034 goto WIN; \ 2035 } \ 2036 /* ??? 64-bit reloads. */ \ 2037 } while (0) 2038 2039 /* Specify the machine mode that this machine uses 2040 for the index in the tablejump instruction. */ 2041 /* If we ever implement any of the full models (such as CM_FULLANY), 2042 this has to be DImode in that case */ 2043 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2044 #define CASE_VECTOR_MODE \ 2045 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 2046 #else 2047 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 2048 we have to sign extend which slows things down. */ 2049 #define CASE_VECTOR_MODE \ 2050 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 2051 #endif 2052 2053 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2054 #define DEFAULT_SIGNED_CHAR 1 2055 2056 /* Max number of bytes we can move from memory to memory 2057 in one reasonably fast instruction. */ 2058 #define MOVE_MAX 8 2059 2060 /* If a memory-to-memory move would take MOVE_RATIO or more simple 2061 move-instruction pairs, we will do a movmem or libcall instead. */ 2062 2063 #define MOVE_RATIO (optimize_size ? 3 : 8) 2064 2065 /* Define if operations between registers always perform the operation 2066 on the full register even if a narrower mode is specified. */ 2067 #define WORD_REGISTER_OPERATIONS 2068 2069 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2070 will either zero-extend or sign-extend. The value of this macro should 2071 be the code that says which one of the two operations is implicitly 2072 done, UNKNOWN if none. */ 2073 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2074 2075 /* Nonzero if access to memory by bytes is slow and undesirable. 2076 For RISC chips, it means that access to memory by bytes is no 2077 better than access by words when possible, so grab a whole word 2078 and maybe make use of that. */ 2079 #define SLOW_BYTE_ACCESS 1 2080 2081 /* Define this to be nonzero if shift instructions ignore all but the low-order 2082 few bits. */ 2083 #define SHIFT_COUNT_TRUNCATED 1 2084 2085 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2086 is done just by pretending it is already truncated. */ 2087 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2088 2089 /* Specify the machine mode used for addresses. */ 2090 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 2091 2092 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2093 return the mode to be used for the comparison. For floating-point, 2094 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2095 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2096 processing is needed. */ 2097 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 2098 2099 /* Return nonzero if MODE implies a floating point inequality can be 2100 reversed. For SPARC this is always true because we have a full 2101 compliment of ordered and unordered comparisons, but until generic 2102 code knows how to reverse it correctly we keep the old definition. */ 2103 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 2104 2105 /* A function address in a call instruction for indexing purposes. */ 2106 #define FUNCTION_MODE Pmode 2107 2108 /* Define this if addresses of constant functions 2109 shouldn't be put through pseudo regs where they can be cse'd. 2110 Desirable on machines where ordinary constants are expensive 2111 but a CALL with constant address is cheap. */ 2112 #define NO_FUNCTION_CSE 2113 2114 /* alloca should avoid clobbering the old register save area. */ 2115 #define SETJMP_VIA_SAVE_AREA 2116 2117 /* The _Q_* comparison libcalls return booleans. */ 2118 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 2119 2120 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 2121 that the inputs are fully consumed before the output memory is clobbered. */ 2122 2123 #define TARGET_BUGGY_QP_LIB 0 2124 2125 /* Assume by default that we do not have the Solaris-specific conversion 2126 routines nor 64-bit integer multiply and divide routines. */ 2127 2128 #define SUN_CONVERSION_LIBFUNCS 0 2129 #define DITF_CONVERSION_LIBFUNCS 0 2130 #define SUN_INTEGER_MULTIPLY_64 0 2131 2132 /* Compute extra cost of moving data between one register class 2133 and another. */ 2134 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) 2135 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2136 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ 2137 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ 2138 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ 2139 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2140 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2) 2141 2142 /* Provide the cost of a branch. For pre-v9 processors we use 2143 a value of 3 to take into account the potential annulling of 2144 the delay slot (which ends up being a bubble in the pipeline slot) 2145 plus a cycle to take into consideration the instruction cache 2146 effects. 2147 2148 On v9 and later, which have branch prediction facilities, we set 2149 it to the depth of the pipeline as that is the cost of a 2150 mispredicted branch. */ 2151 2152 #define BRANCH_COST \ 2153 ((sparc_cpu == PROCESSOR_V9 \ 2154 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 2155 ? 7 \ 2156 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2157 ? 9 : 3)) 2158 2159 #define PREFETCH_BLOCK \ 2160 ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2161 || sparc_cpu == PROCESSOR_ULTRASPARC3) \ 2162 ? 64 : 32) 2163 2164 #define SIMULTANEOUS_PREFETCHES \ 2165 ((sparc_cpu == PROCESSOR_ULTRASPARC) \ 2166 ? 2 \ 2167 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2168 ? 8 : 3)) 2169 2170 /* Control the assembler format that we output. */ 2171 2172 /* A C string constant describing how to begin a comment in the target 2173 assembler language. The compiler assumes that the comment will end at 2174 the end of the line. */ 2175 2176 #define ASM_COMMENT_START "!" 2177 2178 /* Output to assembler file text saying following lines 2179 may contain character constants, extra white space, comments, etc. */ 2180 2181 #define ASM_APP_ON "" 2182 2183 /* Output to assembler file text saying following lines 2184 no longer contain unusual constructs. */ 2185 2186 #define ASM_APP_OFF "" 2187 2188 /* How to refer to registers in assembler output. 2189 This sequence is indexed by compiler's hard-register-number (see above). */ 2190 2191 #define REGISTER_NAMES \ 2192 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2193 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2194 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2195 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2196 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2197 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2198 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2199 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2200 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2201 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2202 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2203 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2204 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } 2205 2206 /* Define additional names for use in asm clobbers and asm declarations. */ 2207 2208 #define ADDITIONAL_REGISTER_NAMES \ 2209 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 2210 2211 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 2212 can run past this up to a continuation point. Once we used 1500, but 2213 a single entry in C++ can run more than 500 bytes, due to the length of 2214 mangled symbol names. dbxout.c should really be fixed to do 2215 continuations when they are actually needed instead of trying to 2216 guess... */ 2217 #define DBX_CONTIN_LENGTH 1000 2218 2219 /* This is how to output a command to make the user-level label named NAME 2220 defined for reference from other files. */ 2221 2222 /* Globalizing directive for a label. */ 2223 #define GLOBAL_ASM_OP "\t.global " 2224 2225 /* The prefix to add to user-visible assembler symbols. */ 2226 2227 #define USER_LABEL_PREFIX "_" 2228 2229 /* This is how to store into the string LABEL 2230 the symbol_ref name of an internal numbered label where 2231 PREFIX is the class of label and NUM is the number within the class. 2232 This is suitable for output with `assemble_name'. */ 2233 2234 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2235 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 2236 2237 /* This is how we hook in and defer the case-vector until the end of 2238 the function. */ 2239 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 2240 sparc_defer_case_vector ((LAB),(VEC), 0) 2241 2242 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 2243 sparc_defer_case_vector ((LAB),(VEC), 1) 2244 2245 /* This is how to output an element of a case-vector that is absolute. */ 2246 2247 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2248 do { \ 2249 char label[30]; \ 2250 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 2251 if (CASE_VECTOR_MODE == SImode) \ 2252 fprintf (FILE, "\t.word\t"); \ 2253 else \ 2254 fprintf (FILE, "\t.xword\t"); \ 2255 assemble_name (FILE, label); \ 2256 fputc ('\n', FILE); \ 2257 } while (0) 2258 2259 /* This is how to output an element of a case-vector that is relative. 2260 (SPARC uses such vectors only when generating PIC.) */ 2261 2262 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2263 do { \ 2264 char label[30]; \ 2265 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 2266 if (CASE_VECTOR_MODE == SImode) \ 2267 fprintf (FILE, "\t.word\t"); \ 2268 else \ 2269 fprintf (FILE, "\t.xword\t"); \ 2270 assemble_name (FILE, label); \ 2271 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 2272 fputc ('-', FILE); \ 2273 assemble_name (FILE, label); \ 2274 fputc ('\n', FILE); \ 2275 } while (0) 2276 2277 /* This is what to output before and after case-vector (both 2278 relative and absolute). If .subsection -1 works, we put case-vectors 2279 at the beginning of the current section. */ 2280 2281 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2282 2283 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 2284 fprintf(FILE, "\t.subsection\t-1\n") 2285 2286 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 2287 fprintf(FILE, "\t.previous\n") 2288 2289 #endif 2290 2291 /* This is how to output an assembler line 2292 that says to advance the location counter 2293 to a multiple of 2**LOG bytes. */ 2294 2295 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2296 if ((LOG) != 0) \ 2297 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2298 2299 /* This is how to output an assembler line that says to advance 2300 the location counter to a multiple of 2**LOG bytes using the 2301 "nop" instruction as padding. */ 2302 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 2303 if ((LOG) != 0) \ 2304 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) 2305 2306 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2307 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2308 2309 /* This says how to output an assembler line 2310 to define a global common symbol. */ 2311 2312 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 2313 ( fputs ("\t.common ", (FILE)), \ 2314 assemble_name ((FILE), (NAME)), \ 2315 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 2316 2317 /* This says how to output an assembler line to define a local common 2318 symbol. */ 2319 2320 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2321 ( fputs ("\t.reserve ", (FILE)), \ 2322 assemble_name ((FILE), (NAME)), \ 2323 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 2324 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 2325 2326 /* A C statement (sans semicolon) to output to the stdio stream 2327 FILE the assembler definition of uninitialized global DECL named 2328 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 2329 Try to use asm_output_aligned_bss to implement this macro. */ 2330 2331 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2332 do { \ 2333 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 2334 } while (0) 2335 2336 #define IDENT_ASM_OP "\t.ident\t" 2337 2338 /* Output #ident as a .ident. */ 2339 2340 #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2341 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); 2342 2343 /* Prettify the assembly. */ 2344 2345 extern int sparc_indent_opcode; 2346 2347 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 2348 do { \ 2349 if (sparc_indent_opcode) \ 2350 { \ 2351 putc (' ', FILE); \ 2352 sparc_indent_opcode = 0; \ 2353 } \ 2354 } while (0) 2355 2356 #define SPARC_SYMBOL_REF_TLS_P(RTX) \ 2357 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 2358 2359 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2360 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \ 2361 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&') 2362 2363 /* Print operand X (an rtx) in assembler syntax to file FILE. 2364 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2365 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2366 2367 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2368 2369 /* Print a memory address as an operand to reference that memory location. */ 2370 2371 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2372 { register rtx base, index = 0; \ 2373 int offset = 0; \ 2374 register rtx addr = ADDR; \ 2375 if (GET_CODE (addr) == REG) \ 2376 fputs (reg_names[REGNO (addr)], FILE); \ 2377 else if (GET_CODE (addr) == PLUS) \ 2378 { \ 2379 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2380 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2381 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2382 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2383 else \ 2384 base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2385 if (GET_CODE (base) == LO_SUM) \ 2386 { \ 2387 gcc_assert (USE_AS_OFFSETABLE_LO10 \ 2388 && TARGET_ARCH64 \ 2389 && ! TARGET_CM_MEDMID); \ 2390 output_operand (XEXP (base, 0), 0); \ 2391 fputs ("+%lo(", FILE); \ 2392 output_address (XEXP (base, 1)); \ 2393 fprintf (FILE, ")+%d", offset); \ 2394 } \ 2395 else \ 2396 { \ 2397 fputs (reg_names[REGNO (base)], FILE); \ 2398 if (index == 0) \ 2399 fprintf (FILE, "%+d", offset); \ 2400 else if (GET_CODE (index) == REG) \ 2401 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 2402 else if (GET_CODE (index) == SYMBOL_REF \ 2403 || GET_CODE (index) == CONST) \ 2404 fputc ('+', FILE), output_addr_const (FILE, index); \ 2405 else gcc_unreachable (); \ 2406 } \ 2407 } \ 2408 else if (GET_CODE (addr) == MINUS \ 2409 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2410 { \ 2411 output_addr_const (FILE, XEXP (addr, 0)); \ 2412 fputs ("-(", FILE); \ 2413 output_addr_const (FILE, XEXP (addr, 1)); \ 2414 fputs ("-.)", FILE); \ 2415 } \ 2416 else if (GET_CODE (addr) == LO_SUM) \ 2417 { \ 2418 output_operand (XEXP (addr, 0), 0); \ 2419 if (TARGET_CM_MEDMID) \ 2420 fputs ("+%l44(", FILE); \ 2421 else \ 2422 fputs ("+%lo(", FILE); \ 2423 output_address (XEXP (addr, 1)); \ 2424 fputc (')', FILE); \ 2425 } \ 2426 else if (flag_pic && GET_CODE (addr) == CONST \ 2427 && GET_CODE (XEXP (addr, 0)) == MINUS \ 2428 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2429 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2430 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2431 { \ 2432 addr = XEXP (addr, 0); \ 2433 output_addr_const (FILE, XEXP (addr, 0)); \ 2434 /* Group the args of the second CONST in parenthesis. */ \ 2435 fputs ("-(", FILE); \ 2436 /* Skip past the second CONST--it does nothing for us. */\ 2437 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2438 /* Close the parenthesis. */ \ 2439 fputc (')', FILE); \ 2440 } \ 2441 else \ 2442 { \ 2443 output_addr_const (FILE, addr); \ 2444 } \ 2445 } 2446 2447 /* TLS support defaulting to original Sun flavor. GNU extensions 2448 must be activated in separate configuration files. */ 2449 #ifdef HAVE_AS_TLS 2450 #define TARGET_TLS 1 2451 #else 2452 #define TARGET_TLS 0 2453 #endif 2454 2455 #define TARGET_SUN_TLS TARGET_TLS 2456 #define TARGET_GNU_TLS 0 2457 2458 /* The number of Pmode words for the setjmp buffer. */ 2459 #define JMP_BUF_SIZE 12 2460