1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf52.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 06. June 2018 34 * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38 35 * from File 'nrf52.svd', 36 * last modified on Wednesday, 06.06.2018 13:21:34 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf52 47 * @{ 48 */ 49 50 51 #ifndef NRF52_H 52 #define NRF52_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83 /* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ 84 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85 RADIO_IRQn = 1, /*!< 1 RADIO */ 86 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 88 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 89 NFCT_IRQn = 5, /*!< 5 NFCT */ 90 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 91 SAADC_IRQn = 7, /*!< 7 SAADC */ 92 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95 RTC0_IRQn = 11, /*!< 11 RTC0 */ 96 TEMP_IRQn = 12, /*!< 12 TEMP */ 97 RNG_IRQn = 13, /*!< 13 RNG */ 98 ECB_IRQn = 14, /*!< 14 ECB */ 99 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100 WDT_IRQn = 16, /*!< 16 WDT */ 101 RTC1_IRQn = 17, /*!< 17 RTC1 */ 102 QDEC_IRQn = 18, /*!< 18 QDEC */ 103 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 104 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 112 PWM0_IRQn = 28, /*!< 28 PWM0 */ 113 PDM_IRQn = 29, /*!< 29 PDM */ 114 MWU_IRQn = 32, /*!< 32 MWU */ 115 PWM1_IRQn = 33, /*!< 33 PWM1 */ 116 PWM2_IRQn = 34, /*!< 34 PWM2 */ 117 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 118 RTC2_IRQn = 36, /*!< 36 RTC2 */ 119 I2S_IRQn = 37, /*!< 37 I2S */ 120 FPU_IRQn = 38 /*!< 38 FPU */ 121 } IRQn_Type; 122 123 124 125 /* =========================================================================================================================== */ 126 /* ================ Processor and Core Peripheral Section ================ */ 127 /* =========================================================================================================================== */ 128 129 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 130 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 131 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 132 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 133 #define __MPU_PRESENT 1 /*!< MPU present or not */ 134 #define __FPU_PRESENT 1 /*!< FPU present or not */ 135 136 137 /** @} */ /* End of group Configuration_of_CMSIS */ 138 139 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 140 #include "system_nrf52.h" /*!< nrf52 System */ 141 142 #ifndef __IM /*!< Fallback for older CMSIS versions */ 143 #define __IM __I 144 #endif 145 #ifndef __OM /*!< Fallback for older CMSIS versions */ 146 #define __OM __O 147 #endif 148 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 149 #define __IOM __IO 150 #endif 151 152 153 /* ======================================== Start of section using anonymous unions ======================================== */ 154 #if defined (__CC_ARM) 155 #pragma push 156 #pragma anon_unions 157 #elif defined (__ICCARM__) 158 #pragma language=extended 159 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 160 #pragma clang diagnostic push 161 #pragma clang diagnostic ignored "-Wc11-extensions" 162 #pragma clang diagnostic ignored "-Wreserved-id-macro" 163 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 164 #pragma clang diagnostic ignored "-Wnested-anon-types" 165 #elif defined (__GNUC__) 166 /* anonymous unions are enabled by default */ 167 #elif defined (__TMS470__) 168 /* anonymous unions are enabled by default */ 169 #elif defined (__TASKING__) 170 #pragma warning 586 171 #elif defined (__CSMC__) 172 /* anonymous unions are enabled by default */ 173 #else 174 #warning Not supported compiler type 175 #endif 176 177 178 /* =========================================================================================================================== */ 179 /* ================ Device Specific Cluster Section ================ */ 180 /* =========================================================================================================================== */ 181 182 183 /** @addtogroup Device_Peripheral_clusters 184 * @{ 185 */ 186 187 188 /** 189 * @brief FICR_INFO [INFO] (Device info) 190 */ 191 typedef struct { 192 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 193 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production 194 configuration */ 195 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 196 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 197 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 198 __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ 199 } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 200 201 202 /** 203 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 204 */ 205 typedef struct { 206 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ 207 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ 208 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ 209 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ 210 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ 211 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ 212 __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ 213 __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ 214 __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ 215 __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ 216 __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ 217 __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ 218 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ 219 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ 220 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ 221 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ 222 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ 223 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 224 225 226 /** 227 * @brief FICR_NFC [NFC] (Unspecified) 228 */ 229 typedef struct { 230 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 231 these values to populate NFCID1_3RD_LAST, 232 NFCID1_2ND_LAST and NFCID1_LAST. */ 233 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 234 these values to populate NFCID1_3RD_LAST, 235 NFCID1_2ND_LAST and NFCID1_LAST. */ 236 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 237 these values to populate NFCID1_3RD_LAST, 238 NFCID1_2ND_LAST and NFCID1_LAST. */ 239 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 240 these values to populate NFCID1_3RD_LAST, 241 NFCID1_2ND_LAST and NFCID1_LAST. */ 242 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 243 244 245 /** 246 * @brief POWER_RAM [RAM] (Unspecified) 247 */ 248 typedef struct { 249 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ 250 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set 251 register */ 252 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear 253 register */ 254 __IM uint32_t RESERVED; 255 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 256 257 258 /** 259 * @brief UARTE_PSEL [PSEL] (Unspecified) 260 */ 261 typedef struct { 262 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 263 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 264 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 265 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 266 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 267 268 269 /** 270 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 271 */ 272 typedef struct { 273 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 274 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 275 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 276 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 277 278 279 /** 280 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 281 */ 282 typedef struct { 283 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 284 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 285 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 286 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 287 288 289 /** 290 * @brief SPIM_PSEL [PSEL] (Unspecified) 291 */ 292 typedef struct { 293 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 294 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 295 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 296 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 297 298 299 /** 300 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 301 */ 302 typedef struct { 303 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 304 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 305 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 306 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 307 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 308 309 310 /** 311 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 312 */ 313 typedef struct { 314 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 315 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 316 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 317 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 318 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 319 320 321 /** 322 * @brief SPIS_PSEL [PSEL] (Unspecified) 323 */ 324 typedef struct { 325 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 326 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 327 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 328 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 329 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 330 331 332 /** 333 * @brief SPIS_RXD [RXD] (Unspecified) 334 */ 335 typedef struct { 336 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 337 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 338 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 339 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 340 341 342 /** 343 * @brief SPIS_TXD [TXD] (Unspecified) 344 */ 345 typedef struct { 346 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 347 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 348 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 349 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 350 351 352 /** 353 * @brief TWIM_PSEL [PSEL] (Unspecified) 354 */ 355 typedef struct { 356 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 357 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 358 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 359 360 361 /** 362 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 363 */ 364 typedef struct { 365 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 366 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 367 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 368 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 369 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 370 371 372 /** 373 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 374 */ 375 typedef struct { 376 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 377 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 378 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 379 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 380 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 381 382 383 /** 384 * @brief TWIS_PSEL [PSEL] (Unspecified) 385 */ 386 typedef struct { 387 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 388 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 389 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 390 391 392 /** 393 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 394 */ 395 typedef struct { 396 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 397 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 398 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 399 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 400 401 402 /** 403 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 404 */ 405 typedef struct { 406 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 407 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 408 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 409 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 410 411 412 /** 413 * @brief SPI_PSEL [PSEL] (Unspecified) 414 */ 415 typedef struct { 416 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 417 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ 418 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ 419 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 420 421 422 /** 423 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 424 */ 425 typedef struct { 426 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ 427 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 428 429 430 /** 431 * @brief NFCT_TXD [TXD] (Unspecified) 432 */ 433 typedef struct { 434 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 435 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 436 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 437 438 439 /** 440 * @brief NFCT_RXD [RXD] (Unspecified) 441 */ 442 typedef struct { 443 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 444 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 445 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 446 447 448 /** 449 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 450 */ 451 typedef struct { 452 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal 453 or above CH[0].LIMIT.HIGH */ 454 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal 455 or below CH[0].LIMIT.LOW */ 456 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 457 458 459 /** 460 * @brief SAADC_CH [CH] (Unspecified) 461 */ 462 typedef struct { 463 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection 464 for CH[0] */ 465 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection 466 for CH[0] */ 467 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for 468 CH[0] */ 469 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event 470 monitoring a channel */ 471 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 472 473 474 /** 475 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 476 */ 477 typedef struct { 478 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 479 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 480 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 481 START */ 482 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 483 484 485 /** 486 * @brief QDEC_PSEL [PSEL] (Unspecified) 487 */ 488 typedef struct { 489 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 490 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 491 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 492 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 493 494 495 /** 496 * @brief PWM_SEQ [SEQ] (Unspecified) 497 */ 498 typedef struct { 499 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in 500 Data RAM of this sequence */ 501 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty 502 cycles) in this sequence */ 503 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional 504 PWM periods between samples loaded into 505 compare register */ 506 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the 507 sequence */ 508 __IM uint32_t RESERVED[4]; 509 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 510 511 512 /** 513 * @brief PWM_PSEL [PSEL] (Unspecified) 514 */ 515 typedef struct { 516 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select 517 for PWM channel 0 */ 518 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 519 520 521 /** 522 * @brief PDM_PSEL [PSEL] (Unspecified) 523 */ 524 typedef struct { 525 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 526 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 527 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 528 529 530 /** 531 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 532 */ 533 typedef struct { 534 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 535 EasyDMA */ 536 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 537 mode */ 538 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 539 540 541 /** 542 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 543 */ 544 typedef struct { 545 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group 546 0 */ 547 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group 548 0 */ 549 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 550 551 552 /** 553 * @brief PPI_CH [CH] (PPI Channel) 554 */ 555 typedef struct { 556 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ 557 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ 558 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 559 560 561 /** 562 * @brief PPI_FORK [FORK] (Fork) 563 */ 564 typedef struct { 565 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ 566 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 567 568 569 /** 570 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) 571 */ 572 typedef struct { 573 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region 574 0 detected */ 575 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region 576 0 detected */ 577 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 578 579 580 /** 581 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) 582 */ 583 typedef struct { 584 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral 585 region 0 detected */ 586 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral 587 region 0 detected */ 588 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 589 590 591 /** 592 * @brief MWU_PERREGION [PERREGION] (Unspecified) 593 */ 594 typedef struct { 595 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt 596 in region 0, write access detected while 597 corresponding subregion was enabled for 598 watching */ 599 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt 600 in region 0, read access detected while 601 corresponding subregion was enabled for 602 watching */ 603 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 604 605 606 /** 607 * @brief MWU_REGION [REGION] (Unspecified) 608 */ 609 typedef struct { 610 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region 611 0 */ 612 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region 613 0 */ 614 __IM uint32_t RESERVED[2]; 615 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 616 617 618 /** 619 * @brief MWU_PREGION [PREGION] (Unspecified) 620 */ 621 typedef struct { 622 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ 623 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ 624 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region 625 0 */ 626 __IM uint32_t RESERVED; 627 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 628 629 630 /** 631 * @brief I2S_CONFIG [CONFIG] (Unspecified) 632 */ 633 typedef struct { 634 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 635 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 636 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 637 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 638 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 639 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 640 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 641 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 642 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 643 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 644 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 645 646 647 /** 648 * @brief I2S_RXD [RXD] (Unspecified) 649 */ 650 typedef struct { 651 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 652 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 653 654 655 /** 656 * @brief I2S_TXD [TXD] (Unspecified) 657 */ 658 typedef struct { 659 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 660 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 661 662 663 /** 664 * @brief I2S_RXTXD [RXTXD] (Unspecified) 665 */ 666 typedef struct { 667 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 668 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 669 670 671 /** 672 * @brief I2S_PSEL [PSEL] (Unspecified) 673 */ 674 typedef struct { 675 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 676 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 677 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 678 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 679 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 680 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 681 682 683 /** @} */ /* End of group Device_Peripheral_clusters */ 684 685 686 /* =========================================================================================================================== */ 687 /* ================ Device Specific Peripheral Section ================ */ 688 /* =========================================================================================================================== */ 689 690 691 /** @addtogroup Device_Peripheral_peripherals 692 * @{ 693 */ 694 695 696 697 /* =========================================================================================================================== */ 698 /* ================ FICR ================ */ 699 /* =========================================================================================================================== */ 700 701 702 /** 703 * @brief Factory Information Configuration Registers (FICR) 704 */ 705 706 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 707 __IM uint32_t RESERVED[4]; 708 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 709 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 710 __IM uint32_t RESERVED1[18]; 711 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ 712 __IM uint32_t RESERVED2[6]; 713 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word 714 0 */ 715 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word 716 0 */ 717 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 718 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ 719 __IM uint32_t RESERVED3[21]; 720 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 721 __IM uint32_t RESERVED4[185]; 722 __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 723 coefficients */ 724 __IM uint32_t RESERVED5[2]; 725 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 726 } NRF_FICR_Type; /*!< Size = 1120 (0x460) */ 727 728 729 730 /* =========================================================================================================================== */ 731 /* ================ UICR ================ */ 732 /* =========================================================================================================================== */ 733 734 735 /** 736 * @brief User Information Configuration Registers (UICR) 737 */ 738 739 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 740 __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 741 __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 742 __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 743 __IM uint32_t RESERVED; 744 __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 745 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic 746 firmware design */ 747 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic 748 hardware design */ 749 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ 750 __IM uint32_t RESERVED1[64]; 751 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET 752 function (see POWER chapter for details) */ 753 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ 754 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 755 NFC antenna or GPIO */ 756 } NRF_UICR_Type; /*!< Size = 528 (0x210) */ 757 758 759 760 /* =========================================================================================================================== */ 761 /* ================ BPROT ================ */ 762 /* =========================================================================================================================== */ 763 764 765 /** 766 * @brief Block Protect (BPROT) 767 */ 768 769 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 770 __IM uint32_t RESERVED[384]; 771 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 772 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 773 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface 774 mode */ 775 __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ 776 __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ 777 __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ 778 } NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ 779 780 781 782 /* =========================================================================================================================== */ 783 /* ================ POWER ================ */ 784 /* =========================================================================================================================== */ 785 786 787 /** 788 * @brief Power control (POWER) 789 */ 790 791 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 792 __IM uint32_t RESERVED[30]; 793 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 794 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 795 __IM uint32_t RESERVED1[34]; 796 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 797 __IM uint32_t RESERVED2[2]; 798 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 799 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 800 __IM uint32_t RESERVED3[122]; 801 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 802 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 803 __IM uint32_t RESERVED4[61]; 804 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 805 __IM uint32_t RESERVED5[9]; 806 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 807 __IM uint32_t RESERVED6[53]; 808 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 809 __IM uint32_t RESERVED7[3]; 810 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 811 __IM uint32_t RESERVED8[2]; 812 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 813 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 814 __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this 815 register is retained) */ 816 __IM uint32_t RESERVED9[11]; 817 __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this 818 register is retained) */ 819 __IM uint32_t RESERVED10[8]; 820 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 821 __IM uint32_t RESERVED11[225]; 822 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 823 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 824 825 826 827 /* =========================================================================================================================== */ 828 /* ================ CLOCK ================ */ 829 /* =========================================================================================================================== */ 830 831 832 /** 833 * @brief Clock control (CLOCK) 834 */ 835 836 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 837 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 838 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 839 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 840 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 841 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 842 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 843 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 844 __IM uint32_t RESERVED[57]; 845 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 846 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 847 __IM uint32_t RESERVED1; 848 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 849 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 850 __IM uint32_t RESERVED2[124]; 851 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 852 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 853 __IM uint32_t RESERVED3[63]; 854 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 855 triggered */ 856 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 857 __IM uint32_t RESERVED4; 858 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 859 triggered */ 860 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 861 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 862 task was triggered */ 863 __IM uint32_t RESERVED5[62]; 864 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 865 __IM uint32_t RESERVED6[7]; 866 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 867 __IM uint32_t RESERVED7[8]; 868 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ 869 } NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ 870 871 872 873 /* =========================================================================================================================== */ 874 /* ================ RADIO ================ */ 875 /* =========================================================================================================================== */ 876 877 878 /** 879 * @brief 2.4 GHz Radio (RADIO) 880 */ 881 882 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 883 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 884 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 885 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 886 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 887 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 888 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 889 the receive signal strength. */ 890 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 891 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 892 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 893 __IM uint32_t RESERVED[55]; 894 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 895 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 896 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 897 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 898 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 899 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 900 packet */ 901 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 902 received packet */ 903 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 904 __IM uint32_t RESERVED1[2]; 905 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 906 __IM uint32_t RESERVED2; 907 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 908 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 909 __IM uint32_t RESERVED3[50]; 910 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 911 __IM uint32_t RESERVED4[64]; 912 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 913 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 914 __IM uint32_t RESERVED5[61]; 915 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 916 __IM uint32_t RESERVED6; 917 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 918 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 919 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 920 __IM uint32_t RESERVED7[60]; 921 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 922 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 923 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 924 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 925 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 926 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 927 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 928 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 929 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 930 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 931 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 932 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 933 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 934 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 935 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 936 __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ 937 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 938 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 939 __IM uint32_t RESERVED8; 940 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 941 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 942 __IM uint32_t RESERVED9[2]; 943 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 944 __IM uint32_t RESERVED10[39]; 945 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base 946 segment 0 */ 947 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix 948 0 */ 949 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 950 __IM uint32_t RESERVED11[3]; 951 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 952 __IM uint32_t RESERVED12[618]; 953 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 954 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 955 956 957 958 /* =========================================================================================================================== */ 959 /* ================ UARTE0 ================ */ 960 /* =========================================================================================================================== */ 961 962 963 /** 964 * @brief UART with EasyDMA (UARTE0) 965 */ 966 967 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 968 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 969 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 970 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 971 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 972 __IM uint32_t RESERVED[7]; 973 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 974 __IM uint32_t RESERVED1[52]; 975 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 976 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 977 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 978 transferred to Data RAM) */ 979 __IM uint32_t RESERVED2; 980 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 981 __IM uint32_t RESERVED3[2]; 982 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 983 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 984 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 985 __IM uint32_t RESERVED4[7]; 986 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 987 __IM uint32_t RESERVED5; 988 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 989 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 990 __IM uint32_t RESERVED6; 991 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 992 __IM uint32_t RESERVED7[41]; 993 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 994 __IM uint32_t RESERVED8[63]; 995 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 996 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 997 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 998 __IM uint32_t RESERVED9[93]; 999 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1000 __IM uint32_t RESERVED10[31]; 1001 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1002 __IM uint32_t RESERVED11; 1003 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1004 __IM uint32_t RESERVED12[3]; 1005 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1006 selected. */ 1007 __IM uint32_t RESERVED13[3]; 1008 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1009 __IM uint32_t RESERVED14; 1010 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1011 __IM uint32_t RESERVED15[7]; 1012 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1013 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1014 1015 1016 1017 /* =========================================================================================================================== */ 1018 /* ================ UART0 ================ */ 1019 /* =========================================================================================================================== */ 1020 1021 1022 /** 1023 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1024 */ 1025 1026 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1027 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1028 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1029 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1030 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1031 __IM uint32_t RESERVED[3]; 1032 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1033 __IM uint32_t RESERVED1[56]; 1034 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1035 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1036 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1037 __IM uint32_t RESERVED2[4]; 1038 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1039 __IM uint32_t RESERVED3; 1040 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1041 __IM uint32_t RESERVED4[7]; 1042 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1043 __IM uint32_t RESERVED5[46]; 1044 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1045 __IM uint32_t RESERVED6[64]; 1046 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1047 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1048 __IM uint32_t RESERVED7[93]; 1049 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1050 __IM uint32_t RESERVED8[31]; 1051 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1052 __IM uint32_t RESERVED9; 1053 __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ 1054 __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ 1055 __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ 1056 __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ 1057 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1058 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1059 __IM uint32_t RESERVED10; 1060 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ 1061 __IM uint32_t RESERVED11[17]; 1062 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1063 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1064 1065 1066 1067 /* =========================================================================================================================== */ 1068 /* ================ SPIM0 ================ */ 1069 /* =========================================================================================================================== */ 1070 1071 1072 /** 1073 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1074 */ 1075 1076 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1077 __IM uint32_t RESERVED[4]; 1078 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1079 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1080 __IM uint32_t RESERVED1; 1081 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1082 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1083 __IM uint32_t RESERVED2[56]; 1084 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1085 __IM uint32_t RESERVED3[2]; 1086 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1087 __IM uint32_t RESERVED4; 1088 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1089 __IM uint32_t RESERVED5; 1090 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1091 __IM uint32_t RESERVED6[10]; 1092 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1093 __IM uint32_t RESERVED7[44]; 1094 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1095 __IM uint32_t RESERVED8[64]; 1096 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1097 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1098 __IM uint32_t RESERVED9[125]; 1099 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1100 __IM uint32_t RESERVED10; 1101 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1102 __IM uint32_t RESERVED11[4]; 1103 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1104 source selected. */ 1105 __IM uint32_t RESERVED12[3]; 1106 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1107 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1108 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1109 __IM uint32_t RESERVED13[26]; 1110 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1111 case and over-read of the TXD buffer. */ 1112 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1113 1114 1115 1116 /* =========================================================================================================================== */ 1117 /* ================ SPIS0 ================ */ 1118 /* =========================================================================================================================== */ 1119 1120 1121 /** 1122 * @brief SPI Slave 0 (SPIS0) 1123 */ 1124 1125 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1126 __IM uint32_t RESERVED[9]; 1127 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1128 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1129 to acquire it */ 1130 __IM uint32_t RESERVED1[54]; 1131 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1132 __IM uint32_t RESERVED2[2]; 1133 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1134 __IM uint32_t RESERVED3[5]; 1135 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1136 __IM uint32_t RESERVED4[53]; 1137 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1138 __IM uint32_t RESERVED5[64]; 1139 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1140 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1141 __IM uint32_t RESERVED6[61]; 1142 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1143 __IM uint32_t RESERVED7[15]; 1144 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1145 __IM uint32_t RESERVED8[47]; 1146 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1147 __IM uint32_t RESERVED9; 1148 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1149 __IM uint32_t RESERVED10[7]; 1150 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1151 __IM uint32_t RESERVED11; 1152 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1153 __IM uint32_t RESERVED12; 1154 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1155 __IM uint32_t RESERVED13; 1156 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1157 of an ignored transaction. */ 1158 __IM uint32_t RESERVED14[24]; 1159 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1160 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1161 1162 1163 1164 /* =========================================================================================================================== */ 1165 /* ================ TWIM0 ================ */ 1166 /* =========================================================================================================================== */ 1167 1168 1169 /** 1170 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1171 */ 1172 1173 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1174 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1175 __IM uint32_t RESERVED; 1176 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1177 __IM uint32_t RESERVED1[2]; 1178 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1179 TWI master is not suspended. */ 1180 __IM uint32_t RESERVED2; 1181 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1182 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1183 __IM uint32_t RESERVED3[56]; 1184 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1185 __IM uint32_t RESERVED4[7]; 1186 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1187 __IM uint32_t RESERVED5[8]; 1188 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1189 task has been issued, TWI traffic is now 1190 suspended. */ 1191 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1192 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1193 __IM uint32_t RESERVED6[2]; 1194 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1195 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1196 byte */ 1197 __IM uint32_t RESERVED7[39]; 1198 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1199 __IM uint32_t RESERVED8[63]; 1200 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1201 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1202 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1203 __IM uint32_t RESERVED9[110]; 1204 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1205 __IM uint32_t RESERVED10[14]; 1206 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1207 __IM uint32_t RESERVED11; 1208 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1209 __IM uint32_t RESERVED12[5]; 1210 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1211 __IM uint32_t RESERVED13[3]; 1212 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1213 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1214 __IM uint32_t RESERVED14[13]; 1215 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1216 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1217 1218 1219 1220 /* =========================================================================================================================== */ 1221 /* ================ TWIS0 ================ */ 1222 /* =========================================================================================================================== */ 1223 1224 1225 /** 1226 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1227 */ 1228 1229 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1230 __IM uint32_t RESERVED[5]; 1231 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1232 __IM uint32_t RESERVED1; 1233 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1234 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1235 __IM uint32_t RESERVED2[3]; 1236 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1237 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1238 __IM uint32_t RESERVED3[51]; 1239 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1240 __IM uint32_t RESERVED4[7]; 1241 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1242 __IM uint32_t RESERVED5[9]; 1243 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1244 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1245 __IM uint32_t RESERVED6[4]; 1246 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1247 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1248 __IM uint32_t RESERVED7[37]; 1249 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1250 __IM uint32_t RESERVED8[63]; 1251 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1252 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1253 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1254 __IM uint32_t RESERVED9[113]; 1255 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1256 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1257 a match */ 1258 __IM uint32_t RESERVED10[10]; 1259 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1260 __IM uint32_t RESERVED11; 1261 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1262 __IM uint32_t RESERVED12[9]; 1263 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1264 __IM uint32_t RESERVED13; 1265 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1266 __IM uint32_t RESERVED14[14]; 1267 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address 1268 0 */ 1269 __IM uint32_t RESERVED15; 1270 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1271 mechanism */ 1272 __IM uint32_t RESERVED16[10]; 1273 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1274 of an over-read of the transmit buffer. */ 1275 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1276 1277 1278 1279 /* =========================================================================================================================== */ 1280 /* ================ SPI0 ================ */ 1281 /* =========================================================================================================================== */ 1282 1283 1284 /** 1285 * @brief Serial Peripheral Interface 0 (SPI0) 1286 */ 1287 1288 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1289 __IM uint32_t RESERVED[66]; 1290 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1291 __IM uint32_t RESERVED1[126]; 1292 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1293 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1294 __IM uint32_t RESERVED2[125]; 1295 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1296 __IM uint32_t RESERVED3; 1297 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1298 __IM uint32_t RESERVED4; 1299 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1300 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1301 __IM uint32_t RESERVED5; 1302 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 1303 __IM uint32_t RESERVED6[11]; 1304 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1305 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1306 1307 1308 1309 /* =========================================================================================================================== */ 1310 /* ================ TWI0 ================ */ 1311 /* =========================================================================================================================== */ 1312 1313 1314 /** 1315 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1316 */ 1317 1318 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1319 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1320 __IM uint32_t RESERVED; 1321 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1322 __IM uint32_t RESERVED1[2]; 1323 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1324 __IM uint32_t RESERVED2; 1325 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1326 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1327 __IM uint32_t RESERVED3[56]; 1328 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1329 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1330 __IM uint32_t RESERVED4[4]; 1331 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1332 __IM uint32_t RESERVED5; 1333 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1334 __IM uint32_t RESERVED6[4]; 1335 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1336 that is sent or received */ 1337 __IM uint32_t RESERVED7[3]; 1338 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1339 __IM uint32_t RESERVED8[45]; 1340 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1341 __IM uint32_t RESERVED9[64]; 1342 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1343 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1344 __IM uint32_t RESERVED10[110]; 1345 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1346 __IM uint32_t RESERVED11[14]; 1347 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1348 __IM uint32_t RESERVED12; 1349 __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ 1350 __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ 1351 __IM uint32_t RESERVED13[2]; 1352 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1353 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1354 __IM uint32_t RESERVED14; 1355 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1356 __IM uint32_t RESERVED15[24]; 1357 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1358 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1359 1360 1361 1362 /* =========================================================================================================================== */ 1363 /* ================ NFCT ================ */ 1364 /* =========================================================================================================================== */ 1365 1366 1367 /** 1368 * @brief NFC-A compatible radio (NFCT) 1369 */ 1370 1371 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1372 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing 1373 frames, change state to activated */ 1374 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ 1375 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1376 sense mode */ 1377 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change 1378 state to transmit */ 1379 __IM uint32_t RESERVED[3]; 1380 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1381 __IM uint32_t RESERVED1; 1382 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1383 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1384 __IM uint32_t RESERVED2[53]; 1385 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send 1386 frames */ 1387 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1388 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1389 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1390 frame */ 1391 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1392 symbol of a frame */ 1393 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1394 frame */ 1395 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) 1396 and transferred to RAM, and EasyDMA has 1397 ended accessing the RX buffer */ 1398 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1399 contains details on the source of the error. */ 1400 __IM uint32_t RESERVED3[2]; 1401 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1402 register contains details on the source 1403 of the error. */ 1404 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1405 in Data RAM full. */ 1406 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1407 has ended accessing the TX buffer */ 1408 __IM uint32_t RESERVED4; 1409 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1410 __IM uint32_t RESERVED5[3]; 1411 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ 1412 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ 1413 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1414 __IM uint32_t RESERVED6[43]; 1415 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1416 __IM uint32_t RESERVED7[63]; 1417 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1418 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1419 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1420 __IM uint32_t RESERVED8[62]; 1421 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1422 __IM uint32_t RESERVED9; 1423 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1424 __IM uint32_t RESERVED10[8]; 1425 __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ 1426 __IM uint32_t RESERVED11[2]; 1427 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1428 __IM uint32_t RESERVED12[49]; 1429 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1430 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1431 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1432 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1433 Data RAM */ 1434 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage 1435 buffer in Data RAM */ 1436 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1437 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1438 __IM uint32_t RESERVED13[26]; 1439 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1440 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1441 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1442 __IM uint32_t RESERVED14; 1443 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1444 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1445 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1446 1447 1448 1449 /* =========================================================================================================================== */ 1450 /* ================ GPIOTE ================ */ 1451 /* =========================================================================================================================== */ 1452 1453 1454 /** 1455 * @brief GPIO Tasks and Events (GPIOTE) 1456 */ 1457 1458 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1459 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to 1460 pin specified in CONFIG[0].PSEL. Action 1461 on pin is configured in CONFIG[0].POLARITY. */ 1462 __IM uint32_t RESERVED[4]; 1463 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to 1464 pin specified in CONFIG[0].PSEL. Action 1465 on pin is to set it high. */ 1466 __IM uint32_t RESERVED1[4]; 1467 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to 1468 pin specified in CONFIG[0].PSEL. Action 1469 on pin is to set it low. */ 1470 __IM uint32_t RESERVED2[32]; 1471 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from 1472 pin specified in CONFIG[0].PSEL */ 1473 __IM uint32_t RESERVED3[23]; 1474 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1475 with SENSE mechanism enabled */ 1476 __IM uint32_t RESERVED4[97]; 1477 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1478 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1479 __IM uint32_t RESERVED5[129]; 1480 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for 1481 OUT[n], SET[n] and CLR[n] tasks and IN[n] 1482 event */ 1483 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1484 1485 1486 1487 /* =========================================================================================================================== */ 1488 /* ================ SAADC ================ */ 1489 /* =========================================================================================================================== */ 1490 1491 1492 /** 1493 * @brief Analog to Digital Converter (SAADC) 1494 */ 1495 1496 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1497 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1498 RAM */ 1499 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1500 are sampled */ 1501 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1502 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1503 __IM uint32_t RESERVED[60]; 1504 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1505 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1506 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1507 on the mode, multiple conversions might 1508 be needed for a result to be transferred 1509 to RAM. */ 1510 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1511 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1512 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1513 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1514 __IM uint32_t RESERVED1[106]; 1515 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1516 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1517 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1518 __IM uint32_t RESERVED2[61]; 1519 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1520 __IM uint32_t RESERVED3[63]; 1521 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1522 __IM uint32_t RESERVED4[3]; 1523 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1524 __IM uint32_t RESERVED5[24]; 1525 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1526 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1527 not be combined with SCAN. The RESOLUTION 1528 is applied before averaging, thus for high 1529 OVERSAMPLE a higher RESOLUTION should be 1530 used. */ 1531 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1532 __IM uint32_t RESERVED6[12]; 1533 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1534 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1535 1536 1537 1538 /* =========================================================================================================================== */ 1539 /* ================ TIMER0 ================ */ 1540 /* =========================================================================================================================== */ 1541 1542 1543 /** 1544 * @brief Timer/Counter 0 (TIMER0) 1545 */ 1546 1547 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1548 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1549 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1550 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1551 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1552 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1553 __IM uint32_t RESERVED[11]; 1554 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value 1555 to CC[0] register */ 1556 __IM uint32_t RESERVED1[58]; 1557 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] 1558 match */ 1559 __IM uint32_t RESERVED2[42]; 1560 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1561 __IM uint32_t RESERVED3[64]; 1562 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1563 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1564 __IM uint32_t RESERVED4[126]; 1565 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1566 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1567 __IM uint32_t RESERVED5; 1568 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1569 __IM uint32_t RESERVED6[11]; 1570 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register 1571 0 */ 1572 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1573 1574 1575 1576 /* =========================================================================================================================== */ 1577 /* ================ RTC0 ================ */ 1578 /* =========================================================================================================================== */ 1579 1580 1581 /** 1582 * @brief Real time counter 0 (RTC0) 1583 */ 1584 1585 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1586 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1587 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1588 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1589 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1590 __IM uint32_t RESERVED[60]; 1591 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1592 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1593 __IM uint32_t RESERVED1[14]; 1594 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] 1595 match */ 1596 __IM uint32_t RESERVED2[109]; 1597 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1598 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1599 __IM uint32_t RESERVED3[13]; 1600 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1601 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1602 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1603 __IM uint32_t RESERVED4[110]; 1604 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1605 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1606 t be written when RTC is stopped */ 1607 __IM uint32_t RESERVED5[13]; 1608 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ 1609 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1610 1611 1612 1613 /* =========================================================================================================================== */ 1614 /* ================ TEMP ================ */ 1615 /* =========================================================================================================================== */ 1616 1617 1618 /** 1619 * @brief Temperature Sensor (TEMP) 1620 */ 1621 1622 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1623 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1624 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1625 __IM uint32_t RESERVED[62]; 1626 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1627 __IM uint32_t RESERVED1[128]; 1628 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1629 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1630 __IM uint32_t RESERVED2[127]; 1631 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1632 __IM uint32_t RESERVED3[5]; 1633 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1634 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1635 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1636 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1637 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1638 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1639 __IM uint32_t RESERVED4[2]; 1640 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1641 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1642 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1643 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1644 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1645 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1646 __IM uint32_t RESERVED5[2]; 1647 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1648 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1649 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1650 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1651 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1652 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1653 1654 1655 1656 /* =========================================================================================================================== */ 1657 /* ================ RNG ================ */ 1658 /* =========================================================================================================================== */ 1659 1660 1661 /** 1662 * @brief Random Number Generator (RNG) 1663 */ 1664 1665 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1666 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1667 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1668 __IM uint32_t RESERVED[62]; 1669 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1670 written to the VALUE register */ 1671 __IM uint32_t RESERVED1[63]; 1672 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1673 __IM uint32_t RESERVED2[64]; 1674 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1675 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1676 __IM uint32_t RESERVED3[126]; 1677 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1678 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1679 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1680 1681 1682 1683 /* =========================================================================================================================== */ 1684 /* ================ ECB ================ */ 1685 /* =========================================================================================================================== */ 1686 1687 1688 /** 1689 * @brief AES ECB Mode Encryption (ECB) 1690 */ 1691 1692 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1693 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1694 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1695 __IM uint32_t RESERVED[62]; 1696 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1697 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1698 task or due to an error */ 1699 __IM uint32_t RESERVED1[127]; 1700 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1701 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1702 __IM uint32_t RESERVED2[126]; 1703 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1704 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1705 1706 1707 1708 /* =========================================================================================================================== */ 1709 /* ================ CCM ================ */ 1710 /* =========================================================================================================================== */ 1711 1712 1713 /** 1714 * @brief AES CCM Mode Encryption (CCM) 1715 */ 1716 1717 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1718 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1719 will stop by itself when completed. */ 1720 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1721 stop by itself when completed. */ 1722 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1723 __IM uint32_t RESERVED[61]; 1724 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1725 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1726 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ 1727 __IM uint32_t RESERVED1[61]; 1728 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1729 __IM uint32_t RESERVED2[64]; 1730 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1731 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1732 __IM uint32_t RESERVED3[61]; 1733 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1734 __IM uint32_t RESERVED4[63]; 1735 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1736 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1737 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1738 NONCE vector */ 1739 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1740 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1741 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1742 } NRF_CCM_Type; /*!< Size = 1304 (0x518) */ 1743 1744 1745 1746 /* =========================================================================================================================== */ 1747 /* ================ AAR ================ */ 1748 /* =========================================================================================================================== */ 1749 1750 1751 /** 1752 * @brief Accelerated Address Resolver (AAR) 1753 */ 1754 1755 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1756 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1757 in the IRK data structure */ 1758 __IM uint32_t RESERVED; 1759 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1760 __IM uint32_t RESERVED1[61]; 1761 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1762 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1763 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1764 __IM uint32_t RESERVED2[126]; 1765 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1766 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1767 __IM uint32_t RESERVED3[61]; 1768 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1769 __IM uint32_t RESERVED4[63]; 1770 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1771 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1772 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1773 __IM uint32_t RESERVED5; 1774 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1775 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1776 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1777 1778 1779 1780 /* =========================================================================================================================== */ 1781 /* ================ WDT ================ */ 1782 /* =========================================================================================================================== */ 1783 1784 1785 /** 1786 * @brief Watchdog Timer (WDT) 1787 */ 1788 1789 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1790 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1791 __IM uint32_t RESERVED[63]; 1792 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1793 __IM uint32_t RESERVED1[128]; 1794 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1795 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1796 __IM uint32_t RESERVED2[61]; 1797 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1798 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1799 __IM uint32_t RESERVED3[63]; 1800 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1801 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1802 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1803 __IM uint32_t RESERVED4[60]; 1804 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ 1805 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1806 1807 1808 1809 /* =========================================================================================================================== */ 1810 /* ================ QDEC ================ */ 1811 /* =========================================================================================================================== */ 1812 1813 1814 /** 1815 * @brief Quadrature Decoder (QDEC) 1816 */ 1817 1818 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1819 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1820 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1821 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1822 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1823 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1824 __IM uint32_t RESERVED[59]; 1825 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1826 written to the SAMPLE register */ 1827 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1828 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1829 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1830 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1831 __IM uint32_t RESERVED1[59]; 1832 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1833 __IM uint32_t RESERVED2[64]; 1834 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1835 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1836 __IM uint32_t RESERVED3[125]; 1837 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1838 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1839 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1840 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1841 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1842 and DBLRDY events can be generated */ 1843 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1844 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1845 READCLRACC or RDCLRACC task */ 1846 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1847 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1848 __IM uint32_t RESERVED4[5]; 1849 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1850 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1851 double transitions */ 1852 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1853 or RDCLRDBL task */ 1854 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1855 1856 1857 1858 /* =========================================================================================================================== */ 1859 /* ================ COMP ================ */ 1860 /* =========================================================================================================================== */ 1861 1862 1863 /** 1864 * @brief Comparator (COMP) 1865 */ 1866 1867 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1868 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1869 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1870 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1871 __IM uint32_t RESERVED[61]; 1872 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1873 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1874 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1875 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1876 __IM uint32_t RESERVED1[60]; 1877 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1878 __IM uint32_t RESERVED2[63]; 1879 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1880 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1881 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1882 __IM uint32_t RESERVED3[61]; 1883 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1884 __IM uint32_t RESERVED4[63]; 1885 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1886 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1887 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1888 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1889 __IM uint32_t RESERVED5[8]; 1890 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1891 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1892 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1893 __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ 1894 } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ 1895 1896 1897 1898 /* =========================================================================================================================== */ 1899 /* ================ LPCOMP ================ */ 1900 /* =========================================================================================================================== */ 1901 1902 1903 /** 1904 * @brief Low Power Comparator (LPCOMP) 1905 */ 1906 1907 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 1908 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1909 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1910 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1911 __IM uint32_t RESERVED[61]; 1912 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 1913 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1914 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1915 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1916 __IM uint32_t RESERVED1[60]; 1917 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1918 __IM uint32_t RESERVED2[64]; 1919 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1920 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1921 __IM uint32_t RESERVED3[61]; 1922 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1923 __IM uint32_t RESERVED4[63]; 1924 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 1925 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 1926 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 1927 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1928 __IM uint32_t RESERVED5[4]; 1929 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 1930 __IM uint32_t RESERVED6[5]; 1931 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1932 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 1933 1934 1935 1936 /* =========================================================================================================================== */ 1937 /* ================ SWI0 ================ */ 1938 /* =========================================================================================================================== */ 1939 1940 1941 /** 1942 * @brief Software interrupt 0 (SWI0) 1943 */ 1944 1945 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1946 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1947 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1948 1949 1950 1951 /* =========================================================================================================================== */ 1952 /* ================ EGU0 ================ */ 1953 /* =========================================================================================================================== */ 1954 1955 1956 /** 1957 * @brief Event Generator Unit 0 (EGU0) 1958 */ 1959 1960 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1961 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering 1962 the corresponding TRIGGERED[0] event */ 1963 __IM uint32_t RESERVED[48]; 1964 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated 1965 by triggering the corresponding TRIGGER[0] 1966 task */ 1967 __IM uint32_t RESERVED1[112]; 1968 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1969 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1970 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1971 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1972 1973 1974 1975 /* =========================================================================================================================== */ 1976 /* ================ PWM0 ================ */ 1977 /* =========================================================================================================================== */ 1978 1979 1980 /** 1981 * @brief Pulse Width Modulation Unit 0 (PWM0) 1982 */ 1983 1984 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1985 __IM uint32_t RESERVED; 1986 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1987 the end of current PWM period, and stops 1988 sequence playback */ 1989 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM 1990 value on all enabled channels from sequence 1991 0, and starts playing that sequence at the 1992 rate defined in SEQ[0]REFRESH and/or DECODER.MODE. 1993 Causes PWM generation to start it was not 1994 running. */ 1995 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1996 all enabled channels if DECODER.MODE=NextStep. 1997 Does not cause PWM generation to start it 1998 was not running. */ 1999 __IM uint32_t RESERVED1[60]; 2000 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2001 are no longer generated */ 2002 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started 2003 on sequence 0 */ 2004 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of 2005 every sequence 0, when last value from RAM 2006 has been applied to wave counter */ 2007 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2008 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2009 of times defined in LOOP.CNT */ 2010 __IM uint32_t RESERVED2[56]; 2011 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2012 __IM uint32_t RESERVED3[63]; 2013 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2014 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2015 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2016 __IM uint32_t RESERVED4[125]; 2017 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2018 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2019 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2020 counts */ 2021 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2022 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2023 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ 2024 __IM uint32_t RESERVED5[2]; 2025 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2026 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2027 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2028 2029 2030 2031 /* =========================================================================================================================== */ 2032 /* ================ PDM ================ */ 2033 /* =========================================================================================================================== */ 2034 2035 2036 /** 2037 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2038 */ 2039 2040 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2041 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2042 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2043 __IM uint32_t RESERVED[62]; 2044 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2045 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2046 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2047 by SAMPLE.MAXCNT (or the last sample after 2048 a STOP task has been received) to Data RAM */ 2049 __IM uint32_t RESERVED1[125]; 2050 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2051 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2052 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2053 __IM uint32_t RESERVED2[125]; 2054 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2055 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2056 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2057 signals */ 2058 __IM uint32_t RESERVED3[3]; 2059 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2060 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2061 __IM uint32_t RESERVED4[8]; 2062 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2063 __IM uint32_t RESERVED5[6]; 2064 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2065 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2066 2067 2068 2069 /* =========================================================================================================================== */ 2070 /* ================ NVMC ================ */ 2071 /* =========================================================================================================================== */ 2072 2073 2074 /** 2075 * @brief Non Volatile Memory Controller (NVMC) 2076 */ 2077 2078 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2079 __IM uint32_t RESERVED[256]; 2080 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2081 __IM uint32_t RESERVED1[64]; 2082 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2083 2084 union { 2085 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ 2086 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2087 page in Code area. Equivalent to ERASEPAGE. */ 2088 }; 2089 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2090 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2091 page in Code area. Equivalent to ERASEPAGE. */ 2092 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration 2093 Registers */ 2094 __IM uint32_t RESERVED2[10]; 2095 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ 2096 __IM uint32_t RESERVED3; 2097 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ 2098 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ 2099 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2100 2101 2102 2103 /* =========================================================================================================================== */ 2104 /* ================ PPI ================ */ 2105 /* =========================================================================================================================== */ 2106 2107 2108 /** 2109 * @brief Programmable Peripheral Interconnect (PPI) 2110 */ 2111 2112 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2113 __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2114 __IM uint32_t RESERVED[308]; 2115 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2116 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2117 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2118 __IM uint32_t RESERVED1; 2119 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2120 __IM uint32_t RESERVED2[148]; 2121 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ 2122 __IM uint32_t RESERVED3[62]; 2123 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2124 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2125 2126 2127 2128 /* =========================================================================================================================== */ 2129 /* ================ MWU ================ */ 2130 /* =========================================================================================================================== */ 2131 2132 2133 /** 2134 * @brief Memory Watch Unit (MWU) 2135 */ 2136 2137 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2138 __IM uint32_t RESERVED[64]; 2139 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ 2140 __IM uint32_t RESERVED1[16]; 2141 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ 2142 __IM uint32_t RESERVED2[100]; 2143 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2144 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2145 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2146 __IM uint32_t RESERVED3[5]; 2147 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ 2148 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ 2149 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ 2150 __IM uint32_t RESERVED4[53]; 2151 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2152 __IM uint32_t RESERVED5[64]; 2153 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2154 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2155 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2156 __IM uint32_t RESERVED6[57]; 2157 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2158 __IM uint32_t RESERVED7[32]; 2159 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2160 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2161 2162 2163 2164 /* =========================================================================================================================== */ 2165 /* ================ I2S ================ */ 2166 /* =========================================================================================================================== */ 2167 2168 2169 /** 2170 * @brief Inter-IC Sound (I2S) 2171 */ 2172 2173 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2174 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2175 generator when this is enabled. */ 2176 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2177 Triggering this task will cause the {event:STOPPED} 2178 event to be generated. */ 2179 __IM uint32_t RESERVED[63]; 2180 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2181 double-buffers. When the I2S module is started 2182 and RX is enabled, this event will be generated 2183 for every RXTXD.MAXCNT words that are received 2184 on the SDIN pin. */ 2185 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2186 __IM uint32_t RESERVED1[2]; 2187 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2188 double-buffers. When the I2S module is started 2189 and TX is enabled, this event will be generated 2190 for every RXTXD.MAXCNT words that are sent 2191 on the SDOUT pin. */ 2192 __IM uint32_t RESERVED2[122]; 2193 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2194 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2195 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2196 __IM uint32_t RESERVED3[125]; 2197 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2198 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2199 __IM uint32_t RESERVED4[3]; 2200 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2201 __IM uint32_t RESERVED5; 2202 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2203 __IM uint32_t RESERVED6[3]; 2204 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2205 __IM uint32_t RESERVED7[3]; 2206 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2207 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2208 2209 2210 2211 /* =========================================================================================================================== */ 2212 /* ================ FPU ================ */ 2213 /* =========================================================================================================================== */ 2214 2215 2216 /** 2217 * @brief FPU (FPU) 2218 */ 2219 2220 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2221 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2222 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2223 2224 2225 2226 /* =========================================================================================================================== */ 2227 /* ================ P0 ================ */ 2228 /* =========================================================================================================================== */ 2229 2230 2231 /** 2232 * @brief GPIO Port 1 (P0) 2233 */ 2234 2235 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 2236 __IM uint32_t RESERVED[321]; 2237 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 2238 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 2239 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 2240 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 2241 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 2242 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 2243 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 2244 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 2245 have met the criteria set in the PIN_CNF[n].SENSE 2246 registers */ 2247 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 2248 and LDETECT mode */ 2249 __IM uint32_t RESERVED1[118]; 2250 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO 2251 pins */ 2252 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 2253 2254 2255 /** @} */ /* End of group Device_Peripheral_peripherals */ 2256 2257 2258 /* =========================================================================================================================== */ 2259 /* ================ Device Specific Peripheral Address Map ================ */ 2260 /* =========================================================================================================================== */ 2261 2262 2263 /** @addtogroup Device_Peripheral_peripheralAddr 2264 * @{ 2265 */ 2266 2267 #define NRF_FICR_BASE 0x10000000UL 2268 #define NRF_UICR_BASE 0x10001000UL 2269 #define NRF_BPROT_BASE 0x40000000UL 2270 #define NRF_POWER_BASE 0x40000000UL 2271 #define NRF_CLOCK_BASE 0x40000000UL 2272 #define NRF_RADIO_BASE 0x40001000UL 2273 #define NRF_UARTE0_BASE 0x40002000UL 2274 #define NRF_UART0_BASE 0x40002000UL 2275 #define NRF_SPIM0_BASE 0x40003000UL 2276 #define NRF_SPIS0_BASE 0x40003000UL 2277 #define NRF_TWIM0_BASE 0x40003000UL 2278 #define NRF_TWIS0_BASE 0x40003000UL 2279 #define NRF_SPI0_BASE 0x40003000UL 2280 #define NRF_TWI0_BASE 0x40003000UL 2281 #define NRF_SPIM1_BASE 0x40004000UL 2282 #define NRF_SPIS1_BASE 0x40004000UL 2283 #define NRF_TWIM1_BASE 0x40004000UL 2284 #define NRF_TWIS1_BASE 0x40004000UL 2285 #define NRF_SPI1_BASE 0x40004000UL 2286 #define NRF_TWI1_BASE 0x40004000UL 2287 #define NRF_NFCT_BASE 0x40005000UL 2288 #define NRF_GPIOTE_BASE 0x40006000UL 2289 #define NRF_SAADC_BASE 0x40007000UL 2290 #define NRF_TIMER0_BASE 0x40008000UL 2291 #define NRF_TIMER1_BASE 0x40009000UL 2292 #define NRF_TIMER2_BASE 0x4000A000UL 2293 #define NRF_RTC0_BASE 0x4000B000UL 2294 #define NRF_TEMP_BASE 0x4000C000UL 2295 #define NRF_RNG_BASE 0x4000D000UL 2296 #define NRF_ECB_BASE 0x4000E000UL 2297 #define NRF_CCM_BASE 0x4000F000UL 2298 #define NRF_AAR_BASE 0x4000F000UL 2299 #define NRF_WDT_BASE 0x40010000UL 2300 #define NRF_RTC1_BASE 0x40011000UL 2301 #define NRF_QDEC_BASE 0x40012000UL 2302 #define NRF_COMP_BASE 0x40013000UL 2303 #define NRF_LPCOMP_BASE 0x40013000UL 2304 #define NRF_SWI0_BASE 0x40014000UL 2305 #define NRF_EGU0_BASE 0x40014000UL 2306 #define NRF_SWI1_BASE 0x40015000UL 2307 #define NRF_EGU1_BASE 0x40015000UL 2308 #define NRF_SWI2_BASE 0x40016000UL 2309 #define NRF_EGU2_BASE 0x40016000UL 2310 #define NRF_SWI3_BASE 0x40017000UL 2311 #define NRF_EGU3_BASE 0x40017000UL 2312 #define NRF_SWI4_BASE 0x40018000UL 2313 #define NRF_EGU4_BASE 0x40018000UL 2314 #define NRF_SWI5_BASE 0x40019000UL 2315 #define NRF_EGU5_BASE 0x40019000UL 2316 #define NRF_TIMER3_BASE 0x4001A000UL 2317 #define NRF_TIMER4_BASE 0x4001B000UL 2318 #define NRF_PWM0_BASE 0x4001C000UL 2319 #define NRF_PDM_BASE 0x4001D000UL 2320 #define NRF_NVMC_BASE 0x4001E000UL 2321 #define NRF_PPI_BASE 0x4001F000UL 2322 #define NRF_MWU_BASE 0x40020000UL 2323 #define NRF_PWM1_BASE 0x40021000UL 2324 #define NRF_PWM2_BASE 0x40022000UL 2325 #define NRF_SPIM2_BASE 0x40023000UL 2326 #define NRF_SPIS2_BASE 0x40023000UL 2327 #define NRF_SPI2_BASE 0x40023000UL 2328 #define NRF_RTC2_BASE 0x40024000UL 2329 #define NRF_I2S_BASE 0x40025000UL 2330 #define NRF_FPU_BASE 0x40026000UL 2331 #define NRF_P0_BASE 0x50000000UL 2332 2333 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2334 2335 2336 /* =========================================================================================================================== */ 2337 /* ================ Peripheral declaration ================ */ 2338 /* =========================================================================================================================== */ 2339 2340 2341 /** @addtogroup Device_Peripheral_declaration 2342 * @{ 2343 */ 2344 2345 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2346 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2347 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 2348 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2349 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2350 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2351 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2352 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2353 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2354 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2355 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2356 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2357 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2358 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2359 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2360 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2361 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2362 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2363 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2364 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2365 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2366 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2367 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2368 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2369 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2370 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2371 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2372 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2373 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2374 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2375 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2376 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2377 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2378 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2379 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2380 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2381 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2382 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2383 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2384 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2385 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2386 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2387 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2388 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2389 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2390 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2391 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2392 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2393 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2394 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2395 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2396 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2397 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2398 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2399 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2400 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2401 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2402 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2403 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2404 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2405 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2406 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2407 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2408 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2409 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2410 2411 /** @} */ /* End of group Device_Peripheral_declaration */ 2412 2413 2414 /* ========================================= End of section using anonymous unions ========================================= */ 2415 #if defined (__CC_ARM) 2416 #pragma pop 2417 #elif defined (__ICCARM__) 2418 /* leave anonymous unions enabled */ 2419 #elif (__ARMCC_VERSION >= 6010050) 2420 #pragma clang diagnostic pop 2421 #elif defined (__GNUC__) 2422 /* anonymous unions are enabled by default */ 2423 #elif defined (__TMS470__) 2424 /* anonymous unions are enabled by default */ 2425 #elif defined (__TASKING__) 2426 #pragma warning restore 2427 #elif defined (__CSMC__) 2428 /* anonymous unions are enabled by default */ 2429 #endif 2430 2431 2432 #ifdef __cplusplus 2433 } 2434 #endif 2435 2436 #endif /* NRF52_H */ 2437 2438 2439 /** @} */ /* End of group nrf52 */ 2440 2441 /** @} */ /* End of group Nordic Semiconductor */ 2442