1; Test sequences that can use ROSBG.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test the simple case.
6define i32 @f1(i32 %a, i32 %b) {
7; CHECK-LABEL: f1:
8; CHECK: rosbg %r2, %r3, 59, 59, 0
9; CHECK: br %r14
10  %andb = and i32 %b, 16
11  %or = or i32 %a, %andb
12  ret i32 %or
13}
14
15; ...and again with i64.
16define i64 @f2(i64 %a, i64 %b) {
17; CHECK-LABEL: f2:
18; CHECK: rosbg %r2, %r3, 59, 59, 0
19; CHECK: br %r14
20  %andb = and i64 %b, 16
21  %or = or i64 %a, %andb
22  ret i64 %or
23}
24
25; Test a case where wraparound is needed.
26define i32 @f3(i32 %a, i32 %b) {
27; CHECK-LABEL: f3:
28; CHECK: rosbg %r2, %r3, 63, 60, 0
29; CHECK: br %r14
30  %andb = and i32 %b, -7
31  %or = or i32 %a, %andb
32  ret i32 %or
33}
34
35; ...and again with i64.
36define i64 @f4(i64 %a, i64 %b) {
37; CHECK-LABEL: f4:
38; CHECK: rosbg %r2, %r3, 63, 60, 0
39; CHECK: br %r14
40  %andb = and i64 %b, -7
41  %or = or i64 %a, %andb
42  ret i64 %or
43}
44
45; Test a case with just a shift.
46define i32 @f6(i32 %a, i32 %b) {
47; CHECK-LABEL: f6:
48; CHECK: rosbg %r2, %r3, 32, 51, 12
49; CHECK: br %r14
50  %shrb = shl i32 %b, 12
51  %or = or i32 %a, %shrb
52  ret i32 %or
53}
54
55; ...and again with i64.
56define i64 @f7(i64 %a, i64 %b) {
57; CHECK-LABEL: f7:
58; CHECK: rosbg %r2, %r3, 0, 51, 12
59; CHECK: br %r14
60  %shrb = shl i64 %b, 12
61  %or = or i64 %a, %shrb
62  ret i64 %or
63}
64
65; Test a case with just a rotate.  This can't use ROSBG.
66define i32 @f8(i32 %a, i32 %b) {
67; CHECK-LABEL: f8:
68; CHECK: rll {{%r[0-5]}}
69; CHECK: or {{%r[0-5]}}
70; CHECK: br %r14
71  %shlb = shl i32 %b, 30
72  %shrb = lshr i32 %b, 2
73  %rotlb = or i32 %shlb, %shrb
74  %or = or i32 %a, %rotlb
75  ret i32 %or
76}
77
78; ...and again with i64, which can.
79define i64 @f9(i64 %a, i64 %b) {
80; CHECK-LABEL: f9:
81; CHECK: rosbg %r2, %r3, 0, 63, 47
82; CHECK: br %r14
83  %shlb = shl i64 %b, 47
84  %shrb = lshr i64 %b, 17
85  %rotlb = or i64 %shlb, %shrb
86  %or = or i64 %a, %rotlb
87  ret i64 %or
88}
89
90; Test a case with a shift and AND.
91define i32 @f10(i32 %a, i32 %b) {
92; CHECK-LABEL: f10:
93; CHECK: rosbg %r2, %r3, 56, 59, 4
94; CHECK: br %r14
95  %shrb = shl i32 %b, 4
96  %andb = and i32 %shrb, 240
97  %or = or i32 %a, %andb
98  ret i32 %or
99}
100
101; ...and again with i64.
102define i64 @f11(i64 %a, i64 %b) {
103; CHECK-LABEL: f11:
104; CHECK: rosbg %r2, %r3, 56, 59, 4
105; CHECK: br %r14
106  %shrb = shl i64 %b, 4
107  %andb = and i64 %shrb, 240
108  %or = or i64 %a, %andb
109  ret i64 %or
110}
111
112; Check the handling of zext and OR, which can use ROSBG.
113define i64 @f12(i64 %a, i32 %b) {
114; CHECK-LABEL: f12:
115; CHECK: rosbg %r2, %r3, 32, 63, 0
116; CHECK: br %r14
117  %add = add i32 %b, 1
118  %ext = zext i32 %add to i64
119  %or = or i64 %a, %ext
120  ret i64 %or
121}
122