1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
3; RUN:     -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
4; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
5; RUN:     -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
6
7; Function Attrs: nounwind
8define zeroext i8 @_Z6testcff(float %arg) {
9; CHECK-LABEL: _Z6testcff:
10; CHECK:       # %bb.0: # %entry
11; CHECK-NEXT:    xscvdpsxws f0, f1
12; CHECK-NEXT:    stfs f1, -4(r1)
13; CHECK-NEXT:    mffprwz r3, f0
14; CHECK-NEXT:    clrldi r3, r3, 32
15; CHECK-NEXT:    blr
16entry:
17  %arg.addr = alloca float, align 4
18  store float %arg, float* %arg.addr, align 4
19  %0 = load float, float* %arg.addr, align 4
20  %conv = fptoui float %0 to i8
21  ret i8 %conv
22}
23
24; Function Attrs: nounwind
25define float @_Z6testfcc(i8 zeroext %arg) {
26; CHECK-LABEL: _Z6testfcc:
27; CHECK:       # %bb.0: # %entry
28; CHECK-NEXT:    mtfprwz f0, r3
29; CHECK-NEXT:    stb r3, -1(r1)
30; CHECK-NEXT:    xscvuxdsp f1, f0
31; CHECK-NEXT:    blr
32entry:
33  %arg.addr = alloca i8, align 1
34  store i8 %arg, i8* %arg.addr, align 1
35  %0 = load i8, i8* %arg.addr, align 1
36  %conv = uitofp i8 %0 to float
37  ret float %conv
38}
39
40; Function Attrs: nounwind
41define zeroext i8 @_Z6testcdd(double %arg) {
42; CHECK-LABEL: _Z6testcdd:
43; CHECK:       # %bb.0: # %entry
44; CHECK-NEXT:    xscvdpsxws f0, f1
45; CHECK-NEXT:    stfd f1, -8(r1)
46; CHECK-NEXT:    mffprwz r3, f0
47; CHECK-NEXT:    clrldi r3, r3, 32
48; CHECK-NEXT:    blr
49entry:
50  %arg.addr = alloca double, align 8
51  store double %arg, double* %arg.addr, align 8
52  %0 = load double, double* %arg.addr, align 8
53  %conv = fptoui double %0 to i8
54  ret i8 %conv
55}
56
57; Function Attrs: nounwind
58define double @_Z6testdcc(i8 zeroext %arg) {
59; CHECK-LABEL: _Z6testdcc:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    mtfprwz f0, r3
62; CHECK-NEXT:    stb r3, -1(r1)
63; CHECK-NEXT:    xscvuxddp f1, f0
64; CHECK-NEXT:    blr
65entry:
66  %arg.addr = alloca i8, align 1
67  store i8 %arg, i8* %arg.addr, align 1
68  %0 = load i8, i8* %arg.addr, align 1
69  %conv = uitofp i8 %0 to double
70  ret double %conv
71}
72
73; Function Attrs: nounwind
74define zeroext i8 @_Z7testucff(float %arg) {
75; CHECK-LABEL: _Z7testucff:
76; CHECK:       # %bb.0: # %entry
77; CHECK-NEXT:    xscvdpsxws f0, f1
78; CHECK-NEXT:    stfs f1, -4(r1)
79; CHECK-NEXT:    mffprwz r3, f0
80; CHECK-NEXT:    clrldi r3, r3, 32
81; CHECK-NEXT:    blr
82entry:
83  %arg.addr = alloca float, align 4
84  store float %arg, float* %arg.addr, align 4
85  %0 = load float, float* %arg.addr, align 4
86  %conv = fptoui float %0 to i8
87  ret i8 %conv
88}
89
90; Function Attrs: nounwind
91define float @_Z7testfuch(i8 zeroext %arg) {
92; CHECK-LABEL: _Z7testfuch:
93; CHECK:       # %bb.0: # %entry
94; CHECK-NEXT:    mtfprwz f0, r3
95; CHECK-NEXT:    stb r3, -1(r1)
96; CHECK-NEXT:    xscvuxdsp f1, f0
97; CHECK-NEXT:    blr
98entry:
99  %arg.addr = alloca i8, align 1
100  store i8 %arg, i8* %arg.addr, align 1
101  %0 = load i8, i8* %arg.addr, align 1
102  %conv = uitofp i8 %0 to float
103  ret float %conv
104}
105
106; Function Attrs: nounwind
107define zeroext i8 @_Z7testucdd(double %arg) {
108; CHECK-LABEL: _Z7testucdd:
109; CHECK:       # %bb.0: # %entry
110; CHECK-NEXT:    xscvdpsxws f0, f1
111; CHECK-NEXT:    stfd f1, -8(r1)
112; CHECK-NEXT:    mffprwz r3, f0
113; CHECK-NEXT:    clrldi r3, r3, 32
114; CHECK-NEXT:    blr
115entry:
116  %arg.addr = alloca double, align 8
117  store double %arg, double* %arg.addr, align 8
118  %0 = load double, double* %arg.addr, align 8
119  %conv = fptoui double %0 to i8
120  ret i8 %conv
121}
122
123; Function Attrs: nounwind
124define double @_Z7testduch(i8 zeroext %arg) {
125; CHECK-LABEL: _Z7testduch:
126; CHECK:       # %bb.0: # %entry
127; CHECK-NEXT:    mtfprwz f0, r3
128; CHECK-NEXT:    stb r3, -1(r1)
129; CHECK-NEXT:    xscvuxddp f1, f0
130; CHECK-NEXT:    blr
131entry:
132  %arg.addr = alloca i8, align 1
133  store i8 %arg, i8* %arg.addr, align 1
134  %0 = load i8, i8* %arg.addr, align 1
135  %conv = uitofp i8 %0 to double
136  ret double %conv
137}
138
139; Function Attrs: nounwind
140define signext i16 @_Z6testsff(float %arg) {
141; CHECK-LABEL: _Z6testsff:
142; CHECK:       # %bb.0: # %entry
143; CHECK-NEXT:    xscvdpsxws f0, f1
144; CHECK-NEXT:    stfs f1, -4(r1)
145; CHECK-NEXT:    mffprwz r3, f0
146; CHECK-NEXT:    extsw r3, r3
147; CHECK-NEXT:    blr
148entry:
149  %arg.addr = alloca float, align 4
150  store float %arg, float* %arg.addr, align 4
151  %0 = load float, float* %arg.addr, align 4
152  %conv = fptosi float %0 to i16
153  ret i16 %conv
154}
155
156; Function Attrs: nounwind
157define float @_Z6testfss(i16 signext %arg) {
158; CHECK-LABEL: _Z6testfss:
159; CHECK:       # %bb.0: # %entry
160; CHECK-NEXT:    mtfprwa f0, r3
161; CHECK-NEXT:    sth r3, -2(r1)
162; CHECK-NEXT:    xscvsxdsp f1, f0
163; CHECK-NEXT:    blr
164entry:
165  %arg.addr = alloca i16, align 2
166  store i16 %arg, i16* %arg.addr, align 2
167  %0 = load i16, i16* %arg.addr, align 2
168  %conv = sitofp i16 %0 to float
169  ret float %conv
170}
171
172; Function Attrs: nounwind
173define signext i16 @_Z6testsdd(double %arg) {
174; CHECK-LABEL: _Z6testsdd:
175; CHECK:       # %bb.0: # %entry
176; CHECK-NEXT:    xscvdpsxws f0, f1
177; CHECK-NEXT:    stfd f1, -8(r1)
178; CHECK-NEXT:    mffprwz r3, f0
179; CHECK-NEXT:    extsw r3, r3
180; CHECK-NEXT:    blr
181entry:
182  %arg.addr = alloca double, align 8
183  store double %arg, double* %arg.addr, align 8
184  %0 = load double, double* %arg.addr, align 8
185  %conv = fptosi double %0 to i16
186  ret i16 %conv
187}
188
189; Function Attrs: nounwind
190define double @_Z6testdss(i16 signext %arg) {
191; CHECK-LABEL: _Z6testdss:
192; CHECK:       # %bb.0: # %entry
193; CHECK-NEXT:    mtfprwa f0, r3
194; CHECK-NEXT:    sth r3, -2(r1)
195; CHECK-NEXT:    xscvsxddp f1, f0
196; CHECK-NEXT:    blr
197entry:
198  %arg.addr = alloca i16, align 2
199  store i16 %arg, i16* %arg.addr, align 2
200  %0 = load i16, i16* %arg.addr, align 2
201  %conv = sitofp i16 %0 to double
202  ret double %conv
203}
204
205; Function Attrs: nounwind
206define zeroext i16 @_Z7testusff(float %arg) {
207; CHECK-LABEL: _Z7testusff:
208; CHECK:       # %bb.0: # %entry
209; CHECK-NEXT:    xscvdpsxws f0, f1
210; CHECK-NEXT:    stfs f1, -4(r1)
211; CHECK-NEXT:    mffprwz r3, f0
212; CHECK-NEXT:    clrldi r3, r3, 32
213; CHECK-NEXT:    blr
214entry:
215  %arg.addr = alloca float, align 4
216  store float %arg, float* %arg.addr, align 4
217  %0 = load float, float* %arg.addr, align 4
218  %conv = fptoui float %0 to i16
219  ret i16 %conv
220}
221
222; Function Attrs: nounwind
223define float @_Z7testfust(i16 zeroext %arg) {
224; CHECK-LABEL: _Z7testfust:
225; CHECK:       # %bb.0: # %entry
226; CHECK-NEXT:    mtfprwz f0, r3
227; CHECK-NEXT:    sth r3, -2(r1)
228; CHECK-NEXT:    xscvuxdsp f1, f0
229; CHECK-NEXT:    blr
230entry:
231  %arg.addr = alloca i16, align 2
232  store i16 %arg, i16* %arg.addr, align 2
233  %0 = load i16, i16* %arg.addr, align 2
234  %conv = uitofp i16 %0 to float
235  ret float %conv
236}
237
238; Function Attrs: nounwind
239define zeroext i16 @_Z7testusdd(double %arg) {
240; CHECK-LABEL: _Z7testusdd:
241; CHECK:       # %bb.0: # %entry
242; CHECK-NEXT:    xscvdpsxws f0, f1
243; CHECK-NEXT:    stfd f1, -8(r1)
244; CHECK-NEXT:    mffprwz r3, f0
245; CHECK-NEXT:    clrldi r3, r3, 32
246; CHECK-NEXT:    blr
247entry:
248  %arg.addr = alloca double, align 8
249  store double %arg, double* %arg.addr, align 8
250  %0 = load double, double* %arg.addr, align 8
251  %conv = fptoui double %0 to i16
252  ret i16 %conv
253}
254
255; Function Attrs: nounwind
256define double @_Z7testdust(i16 zeroext %arg) {
257; CHECK-LABEL: _Z7testdust:
258; CHECK:       # %bb.0: # %entry
259; CHECK-NEXT:    mtfprwz f0, r3
260; CHECK-NEXT:    sth r3, -2(r1)
261; CHECK-NEXT:    xscvuxddp f1, f0
262; CHECK-NEXT:    blr
263entry:
264  %arg.addr = alloca i16, align 2
265  store i16 %arg, i16* %arg.addr, align 2
266  %0 = load i16, i16* %arg.addr, align 2
267  %conv = uitofp i16 %0 to double
268  ret double %conv
269}
270
271; Function Attrs: nounwind
272define signext i32 @_Z6testiff(float %arg) {
273; CHECK-LABEL: _Z6testiff:
274; CHECK:       # %bb.0: # %entry
275; CHECK-NEXT:    xscvdpsxws f0, f1
276; CHECK-NEXT:    stfs f1, -4(r1)
277; CHECK-NEXT:    mffprwz r3, f0
278; CHECK-NEXT:    extsw r3, r3
279; CHECK-NEXT:    blr
280entry:
281  %arg.addr = alloca float, align 4
282  store float %arg, float* %arg.addr, align 4
283  %0 = load float, float* %arg.addr, align 4
284  %conv = fptosi float %0 to i32
285  ret i32 %conv
286}
287
288; Function Attrs: nounwind
289define float @_Z6testfii(i32 signext %arg) {
290; CHECK-LABEL: _Z6testfii:
291; CHECK:       # %bb.0: # %entry
292; CHECK-NEXT:    mtfprwa f0, r3
293; CHECK-NEXT:    stw r3, -4(r1)
294; CHECK-NEXT:    xscvsxdsp f1, f0
295; CHECK-NEXT:    blr
296entry:
297  %arg.addr = alloca i32, align 4
298  store i32 %arg, i32* %arg.addr, align 4
299  %0 = load i32, i32* %arg.addr, align 4
300  %conv = sitofp i32 %0 to float
301  ret float %conv
302}
303
304; Function Attrs: nounwind
305define signext i32 @_Z6testidd(double %arg) {
306; CHECK-LABEL: _Z6testidd:
307; CHECK:       # %bb.0: # %entry
308; CHECK-NEXT:    xscvdpsxws f0, f1
309; CHECK-NEXT:    stfd f1, -8(r1)
310; CHECK-NEXT:    mffprwz r3, f0
311; CHECK-NEXT:    extsw r3, r3
312; CHECK-NEXT:    blr
313entry:
314  %arg.addr = alloca double, align 8
315  store double %arg, double* %arg.addr, align 8
316  %0 = load double, double* %arg.addr, align 8
317  %conv = fptosi double %0 to i32
318  ret i32 %conv
319}
320
321; Function Attrs: nounwind
322define double @_Z6testdii(i32 signext %arg) {
323; CHECK-LABEL: _Z6testdii:
324; CHECK:       # %bb.0: # %entry
325; CHECK-NEXT:    mtfprwa f0, r3
326; CHECK-NEXT:    stw r3, -4(r1)
327; CHECK-NEXT:    xscvsxddp f1, f0
328; CHECK-NEXT:    blr
329entry:
330  %arg.addr = alloca i32, align 4
331  store i32 %arg, i32* %arg.addr, align 4
332  %0 = load i32, i32* %arg.addr, align 4
333  %conv = sitofp i32 %0 to double
334  ret double %conv
335}
336
337; Function Attrs: nounwind
338define zeroext i32 @_Z7testuiff(float %arg) {
339; CHECK-LABEL: _Z7testuiff:
340; CHECK:       # %bb.0: # %entry
341; CHECK-NEXT:    xscvdpuxws f0, f1
342; CHECK-NEXT:    stfs f1, -4(r1)
343; CHECK-NEXT:    mffprwz r3, f0
344; CHECK-NEXT:    clrldi r3, r3, 32
345; CHECK-NEXT:    blr
346entry:
347  %arg.addr = alloca float, align 4
348  store float %arg, float* %arg.addr, align 4
349  %0 = load float, float* %arg.addr, align 4
350  %conv = fptoui float %0 to i32
351  ret i32 %conv
352}
353
354; Function Attrs: nounwind
355define float @_Z7testfuij(i32 zeroext %arg) {
356; CHECK-LABEL: _Z7testfuij:
357; CHECK:       # %bb.0: # %entry
358; CHECK-NEXT:    mtfprwz f0, r3
359; CHECK-NEXT:    stw r3, -4(r1)
360; CHECK-NEXT:    xscvuxdsp f1, f0
361; CHECK-NEXT:    blr
362entry:
363  %arg.addr = alloca i32, align 4
364  store i32 %arg, i32* %arg.addr, align 4
365  %0 = load i32, i32* %arg.addr, align 4
366  %conv = uitofp i32 %0 to float
367  ret float %conv
368}
369
370; Function Attrs: nounwind
371define zeroext i32 @_Z7testuidd(double %arg) {
372; CHECK-LABEL: _Z7testuidd:
373; CHECK:       # %bb.0: # %entry
374; CHECK-NEXT:    xscvdpuxws f0, f1
375; CHECK-NEXT:    stfd f1, -8(r1)
376; CHECK-NEXT:    mffprwz r3, f0
377; CHECK-NEXT:    clrldi r3, r3, 32
378; CHECK-NEXT:    blr
379entry:
380  %arg.addr = alloca double, align 8
381  store double %arg, double* %arg.addr, align 8
382  %0 = load double, double* %arg.addr, align 8
383  %conv = fptoui double %0 to i32
384  ret i32 %conv
385}
386
387; Function Attrs: nounwind
388define double @_Z7testduij(i32 zeroext %arg) {
389; CHECK-LABEL: _Z7testduij:
390; CHECK:       # %bb.0: # %entry
391; CHECK-NEXT:    mtfprwz f0, r3
392; CHECK-NEXT:    stw r3, -4(r1)
393; CHECK-NEXT:    xscvuxddp f1, f0
394; CHECK-NEXT:    blr
395entry:
396  %arg.addr = alloca i32, align 4
397  store i32 %arg, i32* %arg.addr, align 4
398  %0 = load i32, i32* %arg.addr, align 4
399  %conv = uitofp i32 %0 to double
400  ret double %conv
401}
402
403; Function Attrs: nounwind
404define i64 @_Z7testllff(float %arg) {
405; CHECK-LABEL: _Z7testllff:
406; CHECK:       # %bb.0: # %entry
407; CHECK-NEXT:    xscvdpsxds f0, f1
408; CHECK-NEXT:    stfs f1, -4(r1)
409; CHECK-NEXT:    mffprd r3, f0
410; CHECK-NEXT:    blr
411entry:
412  %arg.addr = alloca float, align 4
413  store float %arg, float* %arg.addr, align 4
414  %0 = load float, float* %arg.addr, align 4
415  %conv = fptosi float %0 to i64
416  ret i64 %conv
417}
418
419; Function Attrs: nounwind
420define float @_Z7testfllx(i64 %arg) {
421; CHECK-LABEL: _Z7testfllx:
422; CHECK:       # %bb.0: # %entry
423; CHECK-NEXT:    mtfprd f0, r3
424; CHECK-NEXT:    std r3, -8(r1)
425; CHECK-NEXT:    xscvsxdsp f1, f0
426; CHECK-NEXT:    blr
427entry:
428  %arg.addr = alloca i64, align 8
429  store i64 %arg, i64* %arg.addr, align 8
430  %0 = load i64, i64* %arg.addr, align 8
431  %conv = sitofp i64 %0 to float
432  ret float %conv
433}
434
435; Function Attrs: nounwind
436define i64 @_Z7testlldd(double %arg) {
437; CHECK-LABEL: _Z7testlldd:
438; CHECK:       # %bb.0: # %entry
439; CHECK-NEXT:    xscvdpsxds f0, f1
440; CHECK-NEXT:    stfd f1, -8(r1)
441; CHECK-NEXT:    mffprd r3, f0
442; CHECK-NEXT:    blr
443entry:
444  %arg.addr = alloca double, align 8
445  store double %arg, double* %arg.addr, align 8
446  %0 = load double, double* %arg.addr, align 8
447  %conv = fptosi double %0 to i64
448  ret i64 %conv
449}
450
451; Function Attrs: nounwind
452define double @_Z7testdllx(i64 %arg) {
453; CHECK-LABEL: _Z7testdllx:
454; CHECK:       # %bb.0: # %entry
455; CHECK-NEXT:    mtfprd f0, r3
456; CHECK-NEXT:    std r3, -8(r1)
457; CHECK-NEXT:    xscvsxddp f1, f0
458; CHECK-NEXT:    blr
459entry:
460  %arg.addr = alloca i64, align 8
461  store i64 %arg, i64* %arg.addr, align 8
462  %0 = load i64, i64* %arg.addr, align 8
463  %conv = sitofp i64 %0 to double
464  ret double %conv
465}
466
467; Function Attrs: nounwind
468define i64 @_Z8testullff(float %arg) {
469; CHECK-LABEL: _Z8testullff:
470; CHECK:       # %bb.0: # %entry
471; CHECK-NEXT:    xscvdpuxds f0, f1
472; CHECK-NEXT:    stfs f1, -4(r1)
473; CHECK-NEXT:    mffprd r3, f0
474; CHECK-NEXT:    blr
475entry:
476  %arg.addr = alloca float, align 4
477  store float %arg, float* %arg.addr, align 4
478  %0 = load float, float* %arg.addr, align 4
479  %conv = fptoui float %0 to i64
480  ret i64 %conv
481}
482
483; Function Attrs: nounwind
484define float @_Z8testfully(i64 %arg) {
485; CHECK-LABEL: _Z8testfully:
486; CHECK:       # %bb.0: # %entry
487; CHECK-NEXT:    mtfprd f0, r3
488; CHECK-NEXT:    std r3, -8(r1)
489; CHECK-NEXT:    xscvuxdsp f1, f0
490; CHECK-NEXT:    blr
491entry:
492  %arg.addr = alloca i64, align 8
493  store i64 %arg, i64* %arg.addr, align 8
494  %0 = load i64, i64* %arg.addr, align 8
495  %conv = uitofp i64 %0 to float
496  ret float %conv
497}
498
499; Function Attrs: nounwind
500define i64 @_Z8testulldd(double %arg) {
501; CHECK-LABEL: _Z8testulldd:
502; CHECK:       # %bb.0: # %entry
503; CHECK-NEXT:    xscvdpuxds f0, f1
504; CHECK-NEXT:    stfd f1, -8(r1)
505; CHECK-NEXT:    mffprd r3, f0
506; CHECK-NEXT:    blr
507entry:
508  %arg.addr = alloca double, align 8
509  store double %arg, double* %arg.addr, align 8
510  %0 = load double, double* %arg.addr, align 8
511  %conv = fptoui double %0 to i64
512  ret i64 %conv
513}
514
515; Function Attrs: nounwind
516define double @_Z8testdully(i64 %arg) {
517; CHECK-LABEL: _Z8testdully:
518; CHECK:       # %bb.0: # %entry
519; CHECK-NEXT:    mtfprd f0, r3
520; CHECK-NEXT:    std r3, -8(r1)
521; CHECK-NEXT:    xscvuxddp f1, f0
522; CHECK-NEXT:    blr
523entry:
524  %arg.addr = alloca i64, align 8
525  store i64 %arg, i64* %arg.addr, align 8
526  %0 = load i64, i64* %arg.addr, align 8
527  %conv = uitofp i64 %0 to double
528  ret double %conv
529}
530