1; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5define zeroext i32 @test1() {
6entry:
7  %0 = tail call i32 @llvm.ppc.tbegin(i32 0)
8  ret i32 %0
9
10; CHECK-LABEL: @test1
11; CHECK: tbegin. 0
12; CHECK: mfocrf  [[REGISTER1:[0-9]+]], 128
13; CHECK: rlwinm  [[REGISTER2:[0-9]+]], [[REGISTER1]], 3, 31, 31
14; CHECK: xori    {{[0-9]+}}, [[REGISTER2]], 1
15}
16
17declare i32 @llvm.ppc.tbegin(i32) #1
18
19
20define zeroext i32 @test2() {
21entry:
22  %0 = tail call i32 @llvm.ppc.tend(i32 0)
23  ret i32 %0
24; CHECK-LABEL: @test2
25; CHECK: tend.
26; CHECK: mfocrf  {{[0-9]+}}, 128
27}
28
29declare i32 @llvm.ppc.tend(i32)
30
31
32define void @test3() {
33entry:
34  %0 = tail call i32 @llvm.ppc.tabort(i32 0)
35  %1 = tail call i32 @llvm.ppc.tabortdc(i32 0, i32 1, i32 2)
36  %2 = tail call i32 @llvm.ppc.tabortdci(i32 0, i32 1, i32 2)
37  %3 = tail call i32 @llvm.ppc.tabortwc(i32 0, i32 1, i32 2)
38  %4 = tail call i32 @llvm.ppc.tabortwci(i32 0, i32 1, i32 2)
39  ret void
40; CHECK-LABEL: @test3
41; CHECK: tabort.    {{[0-9]+}}
42; CHECK: tabortdc.  0, {{[0-9]+}}, {{[0-9]+}}
43; CHECK: tabortdci. 0, {{[0-9]+}}, 2
44; CHECK: tabortwc.  0, {{[0-9]+}}, {{[0-9]+}}
45; CHECK: tabortwci. 0, {{[0-9]+}}, 2
46}
47
48declare i32 @llvm.ppc.tabort(i32)
49declare i32 @llvm.ppc.tabortdc(i32, i32, i32)
50declare i32 @llvm.ppc.tabortdci(i32, i32, i32)
51declare i32 @llvm.ppc.tabortwc(i32, i32, i32)
52declare i32 @llvm.ppc.tabortwci(i32, i32, i32)
53
54
55define void @test4() {
56entry:
57  %0 = tail call i32 @llvm.ppc.tendall()
58  %1 = tail call i32 @llvm.ppc.tresume()
59  %2 = tail call i32 @llvm.ppc.tsuspend()
60  %3 = tail call i64 @llvm.ppc.ttest()
61  ret void
62; CHECK-LABEL: @test4
63; CHECK: tendall.
64; CHECK: tresume.
65; CHECK: tsuspend.
66; CHECK: tabortwci. 0, {{[0-9]+}}, 0
67}
68
69declare i32 @llvm.ppc.tendall()
70declare i32 @llvm.ppc.tresume()
71declare i32 @llvm.ppc.tsuspend()
72declare i64 @llvm.ppc.ttest()
73
74
75define void @test5(i64 %v) {
76entry:
77  tail call void @llvm.ppc.set.texasr(i64 %v)
78  tail call void @llvm.ppc.set.texasru(i64 %v)
79  tail call void @llvm.ppc.set.tfhar(i64 %v)
80  tail call void @llvm.ppc.set.tfiar(i64 %v)
81  ret void
82; CHECK-LABEL: @test5
83; CHECK: mtspr 130, [[REG1:[0-9]+]]
84; CHECK: mtspr 131, [[REG2:[0-9]+]]
85; CHECK: mtspr 128, [[REG3:[0-9]+]]
86; CHECK: mtspr 129, [[REG4:[0-9]+]]
87}
88
89define i64 @test6() {
90entry:
91  %0 = tail call i64 @llvm.ppc.get.texasr()
92  ret i64 %0
93; CHECK-LABEL: @test6
94; CHECK: mfspr [[REG1:[0-9]+]], 130
95}
96
97define i64 @test7() {
98entry:
99  %0 = tail call i64 @llvm.ppc.get.texasru()
100  ret i64 %0
101; CHECK-LABEL: @test7
102; CHECK: mfspr [[REG1:[0-9]+]], 131
103}
104
105define i64 @test8() {
106entry:
107  %0 = tail call i64 @llvm.ppc.get.tfhar()
108  ret i64 %0
109; CHECK-LABEL: @test8
110; CHECK: mfspr [[REG1:[0-9]+]], 128
111}
112
113define i64 @test9() {
114entry:
115  %0 = tail call i64 @llvm.ppc.get.tfiar()
116  ret i64 %0
117; CHECK-LABEL: @test9
118; CHECK: mfspr [[REG1:[0-9]+]], 129
119}
120
121declare void @llvm.ppc.set.texasr(i64)
122declare void @llvm.ppc.set.texasru(i64)
123declare void @llvm.ppc.set.tfhar(i64)
124declare void @llvm.ppc.set.tfiar(i64)
125declare i64 @llvm.ppc.get.texasr()
126declare i64 @llvm.ppc.get.texasru()
127declare i64 @llvm.ppc.get.tfhar()
128declare i64 @llvm.ppc.get.tfiar()
129
130define void @test10() {
131entry:
132  %0 = tail call i32 @llvm.ppc.tcheck()
133  %1 = tail call i32 @llvm.ppc.treclaim(i32 5)
134  %2 = tail call i32 @llvm.ppc.trechkpt()
135  %3 = tail call i32 @llvm.ppc.tsr(i32 1)
136  ret void
137; CHECK-LABEL: @test10
138; CHECK: tcheck [[REG1:[0-9]+]]
139; CHECK: treclaim. [[REG2:[0-9]+]]
140; CHECK: trechkpt.
141; CHECK: tresume.
142}
143
144declare i32 @llvm.ppc.tcheck()
145declare i32 @llvm.ppc.treclaim(i32)
146declare i32 @llvm.ppc.trechkpt()
147declare i32 @llvm.ppc.tsr(i32)
148
149