1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=medium <%s | FileCheck %s
2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=large <%s | FileCheck -check-prefix=LARGE  %s
3
4; Test correct code generation for medium and large code model
5; for loading the address of a jump table from the TOC.
6
7target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
8target triple = "powerpc64-unknown-linux-gnu"
9
10define signext i32 @test_jump_table(i32 signext %i) nounwind {
11entry:
12  %i.addr = alloca i32, align 4
13  store i32 %i, i32* %i.addr, align 4
14  %0 = load i32, i32* %i.addr, align 4
15  switch i32 %0, label %sw.default [
16    i32 3, label %sw.bb
17    i32 4, label %sw.bb1
18    i32 5, label %sw.bb2
19    i32 6, label %sw.bb3
20  ]
21
22sw.default:                                       ; preds = %entry
23  br label %sw.epilog
24
25sw.bb:                                            ; preds = %entry
26  %1 = load i32, i32* %i.addr, align 4
27  %mul = mul nsw i32 %1, 7
28  store i32 %mul, i32* %i.addr, align 4
29  br label %sw.bb1
30
31sw.bb1:                                           ; preds = %entry, %sw.bb
32  %2 = load i32, i32* %i.addr, align 4
33  %dec = add nsw i32 %2, -1
34  store i32 %dec, i32* %i.addr, align 4
35  br label %sw.bb2
36
37sw.bb2:                                           ; preds = %entry, %sw.bb1
38  %3 = load i32, i32* %i.addr, align 4
39  %add = add nsw i32 %3, 3
40  store i32 %add, i32* %i.addr, align 4
41  br label %sw.bb3
42
43sw.bb3:                                           ; preds = %entry, %sw.bb2
44  %4 = load i32, i32* %i.addr, align 4
45  %shl = shl i32 %4, 1
46  store i32 %shl, i32* %i.addr, align 4
47  br label %sw.epilog
48
49sw.epilog:                                        ; preds = %sw.bb3, %sw.default
50  %5 = load i32, i32* %i.addr, align 4
51  ret i32 %5
52}
53; CHECK-LABEL: test_jump_table:
54; CHECK-NOT:       bl .L0$pb
55
56; CHECK:       addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
57; CHECK:       ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
58; CHECK:       lwax [[REG3:[0-9]+]], {{[0-9]+}}, [[REG2]]
59; CHECK-NEXT:  add  [[REG4:[0-9]+]], [[REG3]], [[REG2]]
60; CHECK-NEXT:  mtctr [[REG4]]
61; CHECK-NEXT:  bctr
62
63; CHECK-LABEL: .LJTI0_0:
64; CHECK-NEXT: .long	.LBB0_{{[0-9]+}}-.LJTI0_0
65
66; LARGE-LABEL: test_jump_table:
67; LARGE:       bl .L0$pb
68; LARGE-NEXT:  .L0$pb:
69; LARGE:       mflr [[REGBASE:[0-9]+]]
70
71; LARGE:       addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
72; LARGE:       ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
73; LARGE:       lwax [[REG3:[0-9]+]], {{[0-9]+}}, [[REG2]]
74; LARGE-NEXT:  add  [[REG4:[0-9]+]], [[REG3]], [[REGBASE]]
75; LARGE-NEXT:  mtctr [[REG4]]
76; LARGE-NEXT:  bctr
77
78; LARGE-LABEL: .LJTI0_0:
79; LARGE-NEXT: .long	.LBB0_{{[0-9]+}}-.L0$pb
80