1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr8 < %s |\ 3; RUN: FileCheck %s --check-prefix=32BIT 4 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64 -mcpu=pwr8 < %s |\ 6; RUN: FileCheck %s --check-prefix=64BIT 7 8define dso_local fastcc void @BuildVectorICE() unnamed_addr { 9; 32BIT-LABEL: BuildVectorICE: 10; 32BIT: # %bb.0: # %entry 11; 32BIT-NEXT: stwu 1, -64(1) 12; 32BIT-NEXT: .cfi_def_cfa_offset 64 13; 32BIT-NEXT: lxvw4x 34, 0, 3 14; 32BIT-NEXT: li 3, 0 15; 32BIT-NEXT: addi 4, 1, 16 16; 32BIT-NEXT: addi 5, 1, 32 17; 32BIT-NEXT: addi 6, 1, 48 18; 32BIT-NEXT: li 7, 0 19; 32BIT-NEXT: .p2align 4 20; 32BIT-NEXT: .LBB0_1: # %while.body 21; 32BIT-NEXT: # 22; 32BIT-NEXT: stw 7, 16(1) 23; 32BIT-NEXT: stw 3, 32(1) 24; 32BIT-NEXT: lxvw4x 0, 0, 4 25; 32BIT-NEXT: lxvw4x 1, 0, 5 26; 32BIT-NEXT: xxsldwi 0, 1, 0, 1 27; 32BIT-NEXT: xxspltw 1, 1, 0 28; 32BIT-NEXT: xxsldwi 35, 0, 1, 3 29; 32BIT-NEXT: vadduwm 3, 2, 3 30; 32BIT-NEXT: xxspltw 36, 35, 1 31; 32BIT-NEXT: vadduwm 3, 3, 4 32; 32BIT-NEXT: stxvw4x 35, 0, 6 33; 32BIT-NEXT: lwz 7, 48(1) 34; 32BIT-NEXT: b .LBB0_1 35; 36; 64BIT-LABEL: BuildVectorICE: 37; 64BIT: # %bb.0: # %entry 38; 64BIT-NEXT: li 3, 0 39; 64BIT-NEXT: lxvw4x 34, 0, 3 40; 64BIT-NEXT: rldimi 3, 3, 32, 0 41; 64BIT-NEXT: mtfprd 0, 3 42; 64BIT-NEXT: li 3, 0 43; 64BIT-NEXT: .p2align 4 44; 64BIT-NEXT: .LBB0_1: # %while.body 45; 64BIT-NEXT: # 46; 64BIT-NEXT: li 4, 0 47; 64BIT-NEXT: rldimi 4, 3, 32, 0 48; 64BIT-NEXT: mtfprd 1, 4 49; 64BIT-NEXT: xxmrghd 35, 1, 0 50; 64BIT-NEXT: vadduwm 3, 2, 3 51; 64BIT-NEXT: xxspltw 36, 35, 1 52; 64BIT-NEXT: vadduwm 3, 3, 4 53; 64BIT-NEXT: xxsldwi 1, 35, 35, 3 54; 64BIT-NEXT: mffprwz 3, 1 55; 64BIT-NEXT: b .LBB0_1 56 entry: 57 br label %while.body 58 while.body: ; preds = %while.body, %entry 59 %newelement = phi i32 [ 0, %entry ], [ %5, %while.body ] 60 %0 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %newelement, i32 0 61 %1 = load <4 x i32>, <4 x i32>* undef, align 1 62 %2 = add <4 x i32> %1, %0 63 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 64 %4 = add <4 x i32> %2, %3 65 %5 = extractelement <4 x i32> %4, i32 0 66 br label %while.body 67} 68