1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
4; RUN:   -check-prefix=P9BE
5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
7; RUN:   -check-prefix=P9LE
8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
10; RUN:   -check-prefix=P8BE
11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
13; RUN:   -check-prefix=P8LE
14define dso_local <2 x double> @test1(<8 x i16> %a) {
15; P9BE-LABEL: test1:
16; P9BE:       # %bb.0: # %entry
17; P9BE-NEXT:    li r3, 0
18; P9BE-NEXT:    vextuhlx r3, r3, v2
19; P9BE-NEXT:    clrlwi r3, r3, 16
20; P9BE-NEXT:    mtfprwz f0, r3
21; P9BE-NEXT:    li r3, 2
22; P9BE-NEXT:    vextuhlx r3, r3, v2
23; P9BE-NEXT:    xscvuxddp f0, f0
24; P9BE-NEXT:    clrlwi r3, r3, 16
25; P9BE-NEXT:    mtfprwz f1, r3
26; P9BE-NEXT:    xscvuxddp f1, f1
27; P9BE-NEXT:    xxmrghd v2, vs0, vs1
28; P9BE-NEXT:    blr
29;
30; P9LE-LABEL: test1:
31; P9LE:       # %bb.0: # %entry
32; P9LE-NEXT:    li r3, 0
33; P9LE-NEXT:    vextuhrx r3, r3, v2
34; P9LE-NEXT:    clrlwi r3, r3, 16
35; P9LE-NEXT:    mtfprwz f0, r3
36; P9LE-NEXT:    li r3, 2
37; P9LE-NEXT:    vextuhrx r3, r3, v2
38; P9LE-NEXT:    xscvuxddp f0, f0
39; P9LE-NEXT:    clrlwi r3, r3, 16
40; P9LE-NEXT:    mtfprwz f1, r3
41; P9LE-NEXT:    xscvuxddp f1, f1
42; P9LE-NEXT:    xxmrghd v2, vs1, vs0
43; P9LE-NEXT:    blr
44;
45; P8BE-LABEL: test1:
46; P8BE:       # %bb.0: # %entry
47; P8BE-NEXT:    mfvsrd r3, v2
48; P8BE-NEXT:    rldicl r4, r3, 16, 48
49; P8BE-NEXT:    rldicl r3, r3, 32, 48
50; P8BE-NEXT:    clrlwi r4, r4, 16
51; P8BE-NEXT:    clrlwi r3, r3, 16
52; P8BE-NEXT:    mtfprwz f0, r4
53; P8BE-NEXT:    mtfprwz f1, r3
54; P8BE-NEXT:    xscvuxddp f0, f0
55; P8BE-NEXT:    xscvuxddp f1, f1
56; P8BE-NEXT:    xxmrghd v2, vs0, vs1
57; P8BE-NEXT:    blr
58;
59; P8LE-LABEL: test1:
60; P8LE:       # %bb.0: # %entry
61; P8LE-NEXT:    xxswapd vs0, v2
62; P8LE-NEXT:    mffprd r3, f0
63; P8LE-NEXT:    clrldi r4, r3, 48
64; P8LE-NEXT:    rldicl r3, r3, 48, 48
65; P8LE-NEXT:    clrlwi r4, r4, 16
66; P8LE-NEXT:    clrlwi r3, r3, 16
67; P8LE-NEXT:    mtfprwz f0, r4
68; P8LE-NEXT:    mtfprwz f1, r3
69; P8LE-NEXT:    xscvuxddp f0, f0
70; P8LE-NEXT:    xscvuxddp f1, f1
71; P8LE-NEXT:    xxmrghd v2, vs1, vs0
72; P8LE-NEXT:    blr
73entry:
74  %vecext = extractelement <8 x i16> %a, i32 0
75  %conv = uitofp i16 %vecext to double
76  %vecinit = insertelement <2 x double> undef, double %conv, i32 0
77  %vecext1 = extractelement <8 x i16> %a, i32 1
78  %conv2 = uitofp i16 %vecext1 to double
79  %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
80  ret <2 x double> %vecinit3
81}
82
83define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
84; P9BE-LABEL: test2:
85; P9BE:       # %bb.0: # %entry
86; P9BE-NEXT:    xxextractuw f0, v2, 0
87; P9BE-NEXT:    xxextractuw f1, v3, 4
88; P9BE-NEXT:    xscvuxddp f0, f0
89; P9BE-NEXT:    xscvuxddp f1, f1
90; P9BE-NEXT:    xxmrghd v2, vs0, vs1
91; P9BE-NEXT:    blr
92;
93; P9LE-LABEL: test2:
94; P9LE:       # %bb.0: # %entry
95; P9LE-NEXT:    xxextractuw f0, v2, 12
96; P9LE-NEXT:    xxextractuw f1, v3, 8
97; P9LE-NEXT:    xscvuxddp f0, f0
98; P9LE-NEXT:    xscvuxddp f1, f1
99; P9LE-NEXT:    xxmrghd v2, vs1, vs0
100; P9LE-NEXT:    blr
101;
102; P8BE-LABEL: test2:
103; P8BE:       # %bb.0: # %entry
104; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
105; P8BE-NEXT:    mfvsrwz r4, v3
106; P8BE-NEXT:    mtfprwz f1, r4
107; P8BE-NEXT:    mffprwz r3, f0
108; P8BE-NEXT:    xscvuxddp f1, f1
109; P8BE-NEXT:    mtfprwz f0, r3
110; P8BE-NEXT:    xscvuxddp f0, f0
111; P8BE-NEXT:    xxmrghd v2, vs0, vs1
112; P8BE-NEXT:    blr
113;
114; P8LE-LABEL: test2:
115; P8LE:       # %bb.0: # %entry
116; P8LE-NEXT:    xxswapd vs0, v2
117; P8LE-NEXT:    xxsldwi vs1, v3, v3, 1
118; P8LE-NEXT:    mffprwz r3, f0
119; P8LE-NEXT:    mffprwz r4, f1
120; P8LE-NEXT:    mtfprwz f0, r3
121; P8LE-NEXT:    mtfprwz f1, r4
122; P8LE-NEXT:    xscvuxddp f0, f0
123; P8LE-NEXT:    xscvuxddp f1, f1
124; P8LE-NEXT:    xxmrghd v2, vs1, vs0
125; P8LE-NEXT:    blr
126entry:
127  %vecext = extractelement <4 x i32> %a, i32 0
128  %conv = uitofp i32 %vecext to double
129  %vecinit = insertelement <2 x double> undef, double %conv, i32 0
130  %vecext1 = extractelement <4 x i32> %b, i32 1
131  %conv2 = uitofp i32 %vecext1 to double
132  %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
133  ret <2 x double> %vecinit3
134}
135