1; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu  < %s | FileCheck %s
2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
3
4; Check the vabsd* instructions that were added in PowerISA V3.0
5
6; Function Attrs: nounwind readnone
7declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)
8
9; Function Attrs: nounwind readnone
10declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
11
12; Function Attrs: nounwind readnone
13declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)
14
15define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {
16entry:
17  %res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)
18  ret <16 x i8> %res
19; CHECK-LABEL: @test_byte
20; CHECK: vabsdub 2, 2, 3
21; CHECK: blr
22}
23
24define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
25entry:
26  %res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)
27  ret <8 x i16> %res
28; CHECK-LABEL: @test_half
29; CHECK: vabsduh 2, 2, 3
30; CHECK: blr
31}
32
33define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {
34entry:
35  %res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)
36  ret <4 x i32> %res
37; CHECK-LABEL: @test_word
38; CHECK: vabsduw 2, 2, 3
39; CHECK: blr
40}
41
42define <16 x i8> @test_vabsdub(<16 x i8> %0, <16 x i8> %1) {
43entry:
44  %2 = zext <16 x i8> %0 to <16 x i32>
45  %3 = zext <16 x i8> %1 to <16 x i32>
46  %4 = sub nsw <16 x i32> %2, %3
47  %5 = icmp slt <16 x i32> %4, zeroinitializer
48  %6 = sub nsw <16 x i32> zeroinitializer, %4
49  %7 = select <16 x i1> %5, <16 x i32> %6, <16 x i32> %4
50  %8 = trunc <16 x i32> %7 to <16 x i8>
51  ret <16 x i8> %8
52; CHECK-LABEL: @test_vabsdub
53; CHECK: vabsdub 2, 2, 3
54; CHECK: blr
55}
56
57define <8 x i16> @test_vabsduh(<8 x i16> %0, <8 x i16> %1) {
58entry:
59  %2 = zext <8 x i16> %0 to <8 x i32>
60  %3 = zext <8 x i16> %1 to <8 x i32>
61  %4 = sub nsw <8 x i32> %2, %3
62  %5 = icmp slt <8 x i32> %4, zeroinitializer
63  %6 = sub nsw <8 x i32> zeroinitializer, %4
64  %7 = select <8 x i1> %5, <8 x i32> %6, <8 x i32> %4
65  %8 = trunc <8 x i32> %7 to <8 x i16>
66  ret <8 x i16> %8
67; CHECK-LABEL: @test_vabsduh
68; CHECK: vabsduh 2, 2, 3
69; CHECK: blr
70}
71
72define <4 x i32> @test_vabsduw(<4 x i32> %0, <4 x i32> %1) {
73entry:
74  %2 = sub nsw <4 x i32> %0, %1
75  %3 = icmp slt <4 x i32> %2, zeroinitializer
76  %4 = sub nsw <4 x i32> zeroinitializer, %2
77  %5 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %2
78  ret <4 x i32> %5
79; CHECK-LABEL: @test_vabsduw
80; CHECK: vabsduw 2, 2, 3
81; CHECK: blr
82}
83