1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
12
13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23
24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)
25 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
26 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13
27 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
28 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14
29 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
30 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15
31 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
32 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16
33
34 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
35 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17
36
37 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
38 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
39 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
40 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
41 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
42 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
43 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
44 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
45
46 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
47 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
48
49 // expected-no-diagnostics
50 #ifndef HEADER
51 #define HEADER
52
53 struct St {
54 int a, b;
StSt55 St() : a(0), b(0) {}
StSt56 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt57 ~St() {}
58 };
59
60 volatile int g = 1212;
61 volatile int &g1 = g;
62
63 template <class T>
64 struct S {
65 T f;
SS66 S(T a) : f(a + g) {}
SS67 S() : f(g) {}
SS68 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS69 operator T() { return T(); }
~SS70 ~S() {}
71 };
72
73
74 template <typename T>
tmain()75 T tmain() {
76 S<T> test;
77 T t_var = T();
78 T vec[] = {1, 2};
79 S<T> s_arr[] = {1, 2};
80 S<T> &var = test;
81 #pragma omp target teams distribute parallel for firstprivate(t_var, vec, s_arr, var)
82 for (int i = 0; i < 2; ++i) {
83 vec[i] = t_var;
84 s_arr[i] = var;
85 }
86 return T();
87 }
88
89 S<float> test;
90 int t_var = 333;
91 int vec[] = {1, 2};
92 S<float> s_arr[] = {1, 2};
93 S<float> var(3);
94
main()95 int main() {
96 static int sivar;
97 #ifdef LAMBDA
98 [&]() {
99 #pragma omp target teams distribute parallel for firstprivate(g, g1, sivar)
100 for (int i = 0; i < 2; ++i) {
101
102 // Skip global and bound tid vars
103 // skip loop vars
104 g = 1;
105 g1 = 1;
106 sivar = 2;
107
108 // Skip global and bound tid vars, and prev lb and ub vars
109 // skip loop vars
110
111 // use of private vars
112 [&]() {
113 g = 2;
114 g1 = 2;
115 sivar = 4;
116
117 }();
118 }
119 }();
120 return 0;
121 #else
122 #pragma omp target teams distribute parallel for firstprivate(t_var, vec, s_arr, var, sivar)
123 for (int i = 0; i < 2; ++i) {
124 vec[i] = t_var;
125 s_arr[i] = var;
126 sivar += i;
127 }
128 return tmain<int>();
129 #endif
130 }
131
132
133
134
135
136 // Skip global and bound tid vars
137 // Skip temp vars for loop
138
139 // param copy
140
141 // T_VAR and SIVAR
142
143 // preparation vars
144
145 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
146
147 // firstprivate(s_arr)
148
149 // firstprivate(var)
150
151
152 // Skip global and bound tid vars, and prev lb ub vars
153 // Skip temp vars for loop
154
155 // param copy
156
157 // T_VAR and SIVAR
158
159 // preparation vars
160
161 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
162
163 // firstprivate(s_arr)
164
165 // firstprivate(var)
166
167
168
169
170
171
172 // Skip global and bound tid vars
173 // Skip temp vars for loop
174
175 // param copy
176
177 // T_VAR and preparation variables
178
179
180 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
181
182 // firstprivate(s_arr)
183
184 // firstprivate(var)
185
186
187 // Skip global and bound tid vars
188 // Skip temp vars for loop
189
190 // param copy
191
192 // T_VAR and preparation variables
193
194
195 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
196
197 // firstprivate(s_arr)
198
199 // firstprivate(var)
200
201
202 #endif
203 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
204 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
205 // CHECK1-NEXT: entry:
206 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
207 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
208 // CHECK1-NEXT: ret void
209 //
210 //
211 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
212 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
213 // CHECK1-NEXT: entry:
214 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
216 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
217 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
218 // CHECK1-NEXT: ret void
219 //
220 //
221 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
222 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
223 // CHECK1-NEXT: entry:
224 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
225 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
226 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
227 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
228 // CHECK1-NEXT: ret void
229 //
230 //
231 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
232 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
233 // CHECK1-NEXT: entry:
234 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
235 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
236 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
237 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
238 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
239 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
240 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
241 // CHECK1-NEXT: ret void
242 //
243 //
244 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
245 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
246 // CHECK1-NEXT: entry:
247 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
248 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
249 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
250 // CHECK1-NEXT: ret void
251 //
252 //
253 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
254 // CHECK1-SAME: () #[[ATTR0]] {
255 // CHECK1-NEXT: entry:
256 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
257 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
258 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
259 // CHECK1-NEXT: ret void
260 //
261 //
262 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
263 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
264 // CHECK1-NEXT: entry:
265 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
266 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
267 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
268 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
269 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
270 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
271 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
272 // CHECK1-NEXT: ret void
273 //
274 //
275 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
276 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
277 // CHECK1-NEXT: entry:
278 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
279 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
280 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
281 // CHECK1: arraydestroy.body:
282 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
283 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
284 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
285 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
286 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
287 // CHECK1: arraydestroy.done1:
288 // CHECK1-NEXT: ret void
289 //
290 //
291 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
292 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
293 // CHECK1-NEXT: entry:
294 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
295 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
296 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
297 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
298 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
299 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
300 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
301 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
302 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
303 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
304 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
305 // CHECK1-NEXT: ret void
306 //
307 //
308 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
309 // CHECK1-SAME: () #[[ATTR0]] {
310 // CHECK1-NEXT: entry:
311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
312 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
313 // CHECK1-NEXT: ret void
314 //
315 //
316 // CHECK1-LABEL: define {{[^@]+}}@main
317 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
318 // CHECK1-NEXT: entry:
319 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
320 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
321 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
325 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
326 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
327 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
328 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
329 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
330 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
331 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
332 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
333 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
334 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
335 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
336 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]**
337 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8
338 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
339 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]**
340 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8
341 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
342 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
343 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
344 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
345 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
346 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
347 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
348 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8
349 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
350 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
351 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
352 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
353 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
354 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
355 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
356 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
357 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
358 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
359 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
360 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
361 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
362 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
363 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
364 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
365 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
366 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
367 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
368 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
369 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
370 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
371 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
372 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
373 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
374 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8
375 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
376 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
377 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
378 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
379 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
380 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
381 // CHECK1: omp_offload.failed:
382 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
383 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
384 // CHECK1: omp_offload.cont:
385 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
386 // CHECK1-NEXT: ret i32 [[CALL]]
387 //
388 //
389 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
390 // CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
391 // CHECK1-NEXT: entry:
392 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
393 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
394 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
395 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
396 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
397 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
398 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
399 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
400 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
401 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
402 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
403 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
404 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
405 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
406 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
407 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
408 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
409 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
410 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
411 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
412 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
413 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
414 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
415 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
416 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
417 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
418 // CHECK1-NEXT: ret void
419 //
420 //
421 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
422 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
423 // CHECK1-NEXT: entry:
424 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
425 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
426 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
427 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
428 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
429 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
430 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
431 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
432 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
433 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
434 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
435 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
436 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
437 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
438 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
439 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
440 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
441 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
442 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
443 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
444 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
445 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
446 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
447 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
448 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
449 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
450 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
451 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
452 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
453 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
454 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
455 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
456 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
457 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
458 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
459 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
460 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
461 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
462 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
463 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
464 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
465 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
466 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
467 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
468 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
469 // CHECK1: omp.arraycpy.body:
470 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
471 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
472 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
473 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
474 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
475 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
476 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
477 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
478 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
479 // CHECK1: omp.arraycpy.done4:
480 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
481 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
482 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
483 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
484 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
485 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
486 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
487 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
488 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
489 // CHECK1: cond.true:
490 // CHECK1-NEXT: br label [[COND_END:%.*]]
491 // CHECK1: cond.false:
492 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
493 // CHECK1-NEXT: br label [[COND_END]]
494 // CHECK1: cond.end:
495 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
496 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
497 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
498 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
499 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
500 // CHECK1: omp.inner.for.cond:
501 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
502 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
503 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
504 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
505 // CHECK1: omp.inner.for.cond.cleanup:
506 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
507 // CHECK1: omp.inner.for.body:
508 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
509 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
510 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
511 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
512 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
513 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
514 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
515 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
516 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
517 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
518 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
519 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
520 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
521 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
522 // CHECK1: omp.inner.for.inc:
523 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
524 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
525 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
526 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
527 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
528 // CHECK1: omp.inner.for.end:
529 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
530 // CHECK1: omp.loop.exit:
531 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
532 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
533 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
534 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
535 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
536 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
537 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
538 // CHECK1: arraydestroy.body:
539 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
540 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
541 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
542 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
543 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
544 // CHECK1: arraydestroy.done11:
545 // CHECK1-NEXT: ret void
546 //
547 //
548 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
549 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
550 // CHECK1-NEXT: entry:
551 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
552 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
553 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
554 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
555 // CHECK1-NEXT: ret void
556 //
557 //
558 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
559 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
560 // CHECK1-NEXT: entry:
561 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
562 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
563 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
564 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
565 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
566 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
567 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
568 // CHECK1-NEXT: ret void
569 //
570 //
571 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
572 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
573 // CHECK1-NEXT: entry:
574 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
575 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
576 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
577 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
578 // CHECK1-NEXT: ret void
579 //
580 //
581 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
582 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
583 // CHECK1-NEXT: entry:
584 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
585 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
586 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
587 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
588 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
589 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
590 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
591 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
592 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
593 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
594 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
595 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
596 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
597 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
598 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
599 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
600 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
601 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
602 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
603 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
604 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
605 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
606 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
607 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
608 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
609 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
610 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
611 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
612 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
613 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
614 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
615 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
616 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
617 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
618 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
619 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
620 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
621 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
622 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
623 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
624 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
625 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
626 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
627 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
628 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
629 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
630 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
631 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
632 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
633 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
634 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
635 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
636 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
637 // CHECK1: omp.arraycpy.body:
638 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
639 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
640 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
641 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
642 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
643 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
644 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
645 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
646 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
647 // CHECK1: omp.arraycpy.done6:
648 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
649 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]])
650 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
651 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
652 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
653 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
654 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
655 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
656 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
657 // CHECK1: cond.true:
658 // CHECK1-NEXT: br label [[COND_END:%.*]]
659 // CHECK1: cond.false:
660 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
661 // CHECK1-NEXT: br label [[COND_END]]
662 // CHECK1: cond.end:
663 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
664 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
665 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
666 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
667 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
668 // CHECK1: omp.inner.for.cond:
669 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
670 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
671 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
672 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
673 // CHECK1: omp.inner.for.cond.cleanup:
674 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
675 // CHECK1: omp.inner.for.body:
676 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
677 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
678 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
679 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
680 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
681 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
682 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
683 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
684 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
685 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
686 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
687 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
688 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
689 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
690 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
691 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
692 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
693 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
694 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
695 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
696 // CHECK1: omp.body.continue:
697 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
698 // CHECK1: omp.inner.for.inc:
699 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
700 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
701 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
702 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
703 // CHECK1: omp.inner.for.end:
704 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
705 // CHECK1: omp.loop.exit:
706 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
707 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
708 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
709 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
710 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
711 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
712 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
713 // CHECK1: arraydestroy.body:
714 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
715 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
716 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
717 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
718 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
719 // CHECK1: arraydestroy.done15:
720 // CHECK1-NEXT: ret void
721 //
722 //
723 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
724 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
725 // CHECK1-NEXT: entry:
726 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
727 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
728 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
729 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
730 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
731 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
732 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
733 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
734 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
735 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
736 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
737 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
738 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
739 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
740 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
741 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
742 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
743 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
744 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
745 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
746 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
747 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
748 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
749 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
750 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
751 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
752 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
753 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
754 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
755 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
756 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8
757 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
758 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
759 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
760 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
761 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8
762 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
763 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
764 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
765 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
766 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
767 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
768 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
769 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8
770 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
771 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
772 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8
773 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
774 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
775 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
776 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
777 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
778 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
779 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
780 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8
781 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
782 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
783 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8
784 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
785 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8
786 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
787 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
788 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
789 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
790 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
791 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
792 // CHECK1: omp_offload.failed:
793 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
794 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
795 // CHECK1: omp_offload.cont:
796 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
797 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
798 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
799 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
800 // CHECK1: arraydestroy.body:
801 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
802 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
803 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
804 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
805 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
806 // CHECK1: arraydestroy.done2:
807 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
808 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
809 // CHECK1-NEXT: ret i32 [[TMP30]]
810 //
811 //
812 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
813 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
814 // CHECK1-NEXT: entry:
815 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
816 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
817 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
818 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
819 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
820 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
821 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4
822 // CHECK1-NEXT: ret void
823 //
824 //
825 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
826 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
827 // CHECK1-NEXT: entry:
828 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
829 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
830 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
831 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
832 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
833 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
834 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
835 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
836 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
837 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
838 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
839 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
840 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
841 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
842 // CHECK1-NEXT: ret void
843 //
844 //
845 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
846 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
847 // CHECK1-NEXT: entry:
848 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
849 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
850 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
851 // CHECK1-NEXT: ret void
852 //
853 //
854 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
855 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
856 // CHECK1-NEXT: entry:
857 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
858 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
859 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
860 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
861 // CHECK1-NEXT: ret void
862 //
863 //
864 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
865 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
866 // CHECK1-NEXT: entry:
867 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
868 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
869 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
870 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
871 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
872 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
873 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
874 // CHECK1-NEXT: ret void
875 //
876 //
877 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
878 // CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
879 // CHECK1-NEXT: entry:
880 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
881 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
882 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
883 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
884 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
885 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
886 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
887 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
888 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
889 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
890 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
891 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
892 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
893 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
894 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
895 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
896 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
897 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
898 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
899 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
900 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
901 // CHECK1-NEXT: ret void
902 //
903 //
904 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
905 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
906 // CHECK1-NEXT: entry:
907 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
908 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
909 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
910 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
911 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
912 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
913 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
914 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
915 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
916 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
917 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
918 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
919 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
920 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
921 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
922 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
923 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
924 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
925 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
926 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
927 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
928 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
929 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
930 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
931 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
932 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
933 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
934 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
935 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
936 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
937 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
938 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
939 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
940 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
941 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
942 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
943 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
944 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
945 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
946 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
947 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
948 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
949 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
950 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
951 // CHECK1: omp.arraycpy.body:
952 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
953 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
954 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
955 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
956 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
957 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
958 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
959 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
960 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
961 // CHECK1: omp.arraycpy.done4:
962 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
963 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
964 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
965 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
966 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
967 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
968 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
969 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
970 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
971 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
972 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
973 // CHECK1: cond.true:
974 // CHECK1-NEXT: br label [[COND_END:%.*]]
975 // CHECK1: cond.false:
976 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
977 // CHECK1-NEXT: br label [[COND_END]]
978 // CHECK1: cond.end:
979 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
980 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
981 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
982 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
983 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
984 // CHECK1: omp.inner.for.cond:
985 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
986 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
987 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
988 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
989 // CHECK1: omp.inner.for.cond.cleanup:
990 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
991 // CHECK1: omp.inner.for.body:
992 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
993 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
994 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
995 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
996 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
997 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
998 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
999 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1000 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
1001 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
1002 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1003 // CHECK1: omp.inner.for.inc:
1004 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1005 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1006 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1007 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1008 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1009 // CHECK1: omp.inner.for.end:
1010 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1011 // CHECK1: omp.loop.exit:
1012 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1013 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
1014 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
1015 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1016 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
1017 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1018 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1019 // CHECK1: arraydestroy.body:
1020 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1021 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1022 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1023 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1024 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1025 // CHECK1: arraydestroy.done11:
1026 // CHECK1-NEXT: ret void
1027 //
1028 //
1029 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1030 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1031 // CHECK1-NEXT: entry:
1032 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1033 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1034 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1035 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1036 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1037 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1038 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1039 // CHECK1-NEXT: ret void
1040 //
1041 //
1042 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
1043 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1044 // CHECK1-NEXT: entry:
1045 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1046 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1047 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1048 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1049 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1050 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1051 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1052 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1053 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1054 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1055 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1056 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1057 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1058 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1059 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1060 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1061 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1062 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1063 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1064 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
1065 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
1066 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1067 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1068 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1069 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1070 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1071 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1072 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1073 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1074 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1075 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1076 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1077 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1078 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1079 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1080 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1081 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1082 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1083 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1084 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1085 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1086 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1087 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1088 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1089 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1090 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1091 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1092 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
1093 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1094 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
1095 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1096 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
1097 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1098 // CHECK1: omp.arraycpy.body:
1099 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1100 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1101 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1102 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1103 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1104 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1105 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1106 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1107 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1108 // CHECK1: omp.arraycpy.done6:
1109 // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1110 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
1111 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]])
1112 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
1113 // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
1114 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1115 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
1116 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1117 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1118 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
1119 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1120 // CHECK1: cond.true:
1121 // CHECK1-NEXT: br label [[COND_END:%.*]]
1122 // CHECK1: cond.false:
1123 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1124 // CHECK1-NEXT: br label [[COND_END]]
1125 // CHECK1: cond.end:
1126 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1127 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1128 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1129 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1130 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1131 // CHECK1: omp.inner.for.cond:
1132 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1133 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1134 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1135 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1136 // CHECK1: omp.inner.for.cond.cleanup:
1137 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1138 // CHECK1: omp.inner.for.body:
1139 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1140 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1141 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1142 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1143 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
1144 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1145 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
1146 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
1147 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
1148 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
1149 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
1150 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
1151 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
1152 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
1153 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
1154 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
1155 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1156 // CHECK1: omp.body.continue:
1157 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1158 // CHECK1: omp.inner.for.inc:
1159 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1160 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
1161 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
1162 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1163 // CHECK1: omp.inner.for.end:
1164 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1165 // CHECK1: omp.loop.exit:
1166 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1167 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1168 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1169 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
1170 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1171 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
1172 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1173 // CHECK1: arraydestroy.body:
1174 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1175 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1176 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1177 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1178 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1179 // CHECK1: arraydestroy.done15:
1180 // CHECK1-NEXT: ret void
1181 //
1182 //
1183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1184 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1185 // CHECK1-NEXT: entry:
1186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1187 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1189 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1190 // CHECK1-NEXT: ret void
1191 //
1192 //
1193 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1194 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1195 // CHECK1-NEXT: entry:
1196 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1197 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1198 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1199 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1200 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1201 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1202 // CHECK1-NEXT: ret void
1203 //
1204 //
1205 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1206 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1207 // CHECK1-NEXT: entry:
1208 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1209 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1210 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1211 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1212 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1213 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1214 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1215 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1216 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1217 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1218 // CHECK1-NEXT: ret void
1219 //
1220 //
1221 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1222 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1223 // CHECK1-NEXT: entry:
1224 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1225 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1226 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1227 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1228 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1229 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1230 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1231 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
1232 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
1233 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1234 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1235 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1236 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1237 // CHECK1-NEXT: ret void
1238 //
1239 //
1240 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1241 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1242 // CHECK1-NEXT: entry:
1243 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1244 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1245 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1246 // CHECK1-NEXT: ret void
1247 //
1248 //
1249 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
1250 // CHECK1-SAME: () #[[ATTR0]] {
1251 // CHECK1-NEXT: entry:
1252 // CHECK1-NEXT: call void @__cxx_global_var_init()
1253 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
1254 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
1255 // CHECK1-NEXT: ret void
1256 //
1257 //
1258 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1259 // CHECK1-SAME: () #[[ATTR0]] {
1260 // CHECK1-NEXT: entry:
1261 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1262 // CHECK1-NEXT: ret void
1263 //
1264 //
1265 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
1266 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
1267 // CHECK2-NEXT: entry:
1268 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1269 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1270 // CHECK2-NEXT: ret void
1271 //
1272 //
1273 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1274 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1275 // CHECK2-NEXT: entry:
1276 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1277 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1278 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1279 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1280 // CHECK2-NEXT: ret void
1281 //
1282 //
1283 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1284 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1285 // CHECK2-NEXT: entry:
1286 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1287 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1288 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1289 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1290 // CHECK2-NEXT: ret void
1291 //
1292 //
1293 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1294 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1295 // CHECK2-NEXT: entry:
1296 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1297 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1298 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1299 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1300 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1301 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1302 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
1303 // CHECK2-NEXT: ret void
1304 //
1305 //
1306 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1307 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1308 // CHECK2-NEXT: entry:
1309 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1310 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1311 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1312 // CHECK2-NEXT: ret void
1313 //
1314 //
1315 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1316 // CHECK2-SAME: () #[[ATTR0]] {
1317 // CHECK2-NEXT: entry:
1318 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
1319 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
1320 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1321 // CHECK2-NEXT: ret void
1322 //
1323 //
1324 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1325 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1326 // CHECK2-NEXT: entry:
1327 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1328 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1329 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1330 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1331 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1332 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1333 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1334 // CHECK2-NEXT: ret void
1335 //
1336 //
1337 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1338 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1339 // CHECK2-NEXT: entry:
1340 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1341 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1342 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1343 // CHECK2: arraydestroy.body:
1344 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1345 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1346 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1347 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1348 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1349 // CHECK2: arraydestroy.done1:
1350 // CHECK2-NEXT: ret void
1351 //
1352 //
1353 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1354 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1355 // CHECK2-NEXT: entry:
1356 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1357 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1358 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1359 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1360 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1361 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1362 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1363 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1364 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1365 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1366 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
1367 // CHECK2-NEXT: ret void
1368 //
1369 //
1370 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1371 // CHECK2-SAME: () #[[ATTR0]] {
1372 // CHECK2-NEXT: entry:
1373 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1374 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1375 // CHECK2-NEXT: ret void
1376 //
1377 //
1378 // CHECK2-LABEL: define {{[^@]+}}@main
1379 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
1380 // CHECK2-NEXT: entry:
1381 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1382 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1383 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1384 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1385 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1386 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1387 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1388 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1389 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
1390 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1391 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1392 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1393 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1394 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1395 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
1396 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1397 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1398 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]**
1399 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8
1400 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1401 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]**
1402 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8
1403 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1404 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1405 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1406 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1407 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
1408 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1409 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
1410 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8
1411 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1412 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1413 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1414 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
1415 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
1416 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1417 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
1418 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
1419 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1420 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
1421 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1422 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
1423 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
1424 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1425 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
1426 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
1427 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1428 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
1429 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1430 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1431 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
1432 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1433 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1434 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
1435 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1436 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8
1437 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1438 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1439 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
1440 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1441 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1442 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1443 // CHECK2: omp_offload.failed:
1444 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
1445 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1446 // CHECK2: omp_offload.cont:
1447 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
1448 // CHECK2-NEXT: ret i32 [[CALL]]
1449 //
1450 //
1451 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
1452 // CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1453 // CHECK2-NEXT: entry:
1454 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1455 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1456 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1457 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1458 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1459 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1460 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1461 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1462 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1463 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1464 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1465 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1466 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1467 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1468 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1469 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1470 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1471 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1472 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1473 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
1474 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1475 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
1476 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1477 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
1478 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1479 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
1480 // CHECK2-NEXT: ret void
1481 //
1482 //
1483 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1484 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
1485 // CHECK2-NEXT: entry:
1486 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1487 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1488 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1489 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1490 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1491 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1492 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1493 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1494 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1495 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1496 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1497 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1498 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1499 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1500 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
1501 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1502 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1503 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1504 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1505 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1506 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1507 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1508 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1509 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1510 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1511 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1512 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1513 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1514 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1515 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1516 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1517 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1518 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1519 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1520 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1521 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1522 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1523 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
1524 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1525 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
1526 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1527 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1528 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1529 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
1530 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1531 // CHECK2: omp.arraycpy.body:
1532 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1533 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1534 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1535 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1536 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1537 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1538 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1539 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1540 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
1541 // CHECK2: omp.arraycpy.done4:
1542 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
1543 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
1544 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
1545 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1546 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1547 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1548 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1549 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1550 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1551 // CHECK2: cond.true:
1552 // CHECK2-NEXT: br label [[COND_END:%.*]]
1553 // CHECK2: cond.false:
1554 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1555 // CHECK2-NEXT: br label [[COND_END]]
1556 // CHECK2: cond.end:
1557 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1558 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1559 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1560 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1561 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1562 // CHECK2: omp.inner.for.cond:
1563 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1564 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1565 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1566 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1567 // CHECK2: omp.inner.for.cond.cleanup:
1568 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1569 // CHECK2: omp.inner.for.body:
1570 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1571 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1572 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1573 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1574 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
1575 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1576 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
1577 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1578 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
1579 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1580 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
1581 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1582 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
1583 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1584 // CHECK2: omp.inner.for.inc:
1585 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1586 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1587 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1588 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1589 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1590 // CHECK2: omp.inner.for.end:
1591 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1592 // CHECK2: omp.loop.exit:
1593 // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1594 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
1595 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
1596 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1597 // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1598 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
1599 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1600 // CHECK2: arraydestroy.body:
1601 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1602 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1603 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1604 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1605 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1606 // CHECK2: arraydestroy.done11:
1607 // CHECK2-NEXT: ret void
1608 //
1609 //
1610 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1611 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1612 // CHECK2-NEXT: entry:
1613 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1614 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1615 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1616 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
1617 // CHECK2-NEXT: ret void
1618 //
1619 //
1620 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1621 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1622 // CHECK2-NEXT: entry:
1623 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1624 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1625 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1626 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1627 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1628 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1629 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1630 // CHECK2-NEXT: ret void
1631 //
1632 //
1633 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1634 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1635 // CHECK2-NEXT: entry:
1636 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1637 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1638 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1639 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1640 // CHECK2-NEXT: ret void
1641 //
1642 //
1643 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1644 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
1645 // CHECK2-NEXT: entry:
1646 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1647 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1648 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1649 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1650 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1651 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1652 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1653 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1654 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1655 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1656 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1657 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1658 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1659 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1660 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1661 // CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1662 // CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1663 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1664 // CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1665 // CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
1666 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1667 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1668 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1669 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1670 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1671 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1672 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1673 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1674 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1675 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1676 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1677 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1678 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1679 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1680 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1681 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1682 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1683 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1684 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1685 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1686 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1687 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1688 // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1689 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1690 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1691 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1692 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1693 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
1694 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1695 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1696 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1697 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
1698 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1699 // CHECK2: omp.arraycpy.body:
1700 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1701 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1702 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1703 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1704 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1705 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1706 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1707 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1708 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1709 // CHECK2: omp.arraycpy.done6:
1710 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
1711 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]])
1712 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
1713 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1714 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1715 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1716 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1717 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
1718 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1719 // CHECK2: cond.true:
1720 // CHECK2-NEXT: br label [[COND_END:%.*]]
1721 // CHECK2: cond.false:
1722 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1723 // CHECK2-NEXT: br label [[COND_END]]
1724 // CHECK2: cond.end:
1725 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1726 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1727 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1728 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1729 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1730 // CHECK2: omp.inner.for.cond:
1731 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1732 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1733 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1734 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1735 // CHECK2: omp.inner.for.cond.cleanup:
1736 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1737 // CHECK2: omp.inner.for.body:
1738 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1739 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
1740 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1741 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1742 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
1743 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
1744 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
1745 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
1746 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
1747 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1748 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
1749 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
1750 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
1751 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
1752 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
1753 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
1754 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
1755 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
1756 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
1757 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1758 // CHECK2: omp.body.continue:
1759 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1760 // CHECK2: omp.inner.for.inc:
1761 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1762 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
1763 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
1764 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1765 // CHECK2: omp.inner.for.end:
1766 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1767 // CHECK2: omp.loop.exit:
1768 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1769 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1770 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1771 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
1772 // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1773 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
1774 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1775 // CHECK2: arraydestroy.body:
1776 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1777 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1778 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1779 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1780 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1781 // CHECK2: arraydestroy.done15:
1782 // CHECK2-NEXT: ret void
1783 //
1784 //
1785 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1786 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat {
1787 // CHECK2-NEXT: entry:
1788 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1789 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1790 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1791 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1792 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1793 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1794 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1795 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1796 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1797 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1798 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1799 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1800 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1801 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
1802 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1803 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1804 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1805 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
1806 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1807 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
1808 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1809 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
1810 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
1811 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1812 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1813 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
1814 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1815 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1816 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1817 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
1818 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8
1819 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1820 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
1821 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
1822 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1823 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8
1824 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1825 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1826 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
1827 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1828 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1829 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1830 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1831 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8
1832 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1833 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
1834 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8
1835 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1836 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1837 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
1838 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1839 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8
1840 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1841 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
1842 // CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8
1843 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1844 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1845 // CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8
1846 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1847 // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8
1848 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1849 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1850 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1851 // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1852 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1853 // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1854 // CHECK2: omp_offload.failed:
1855 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
1856 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1857 // CHECK2: omp_offload.cont:
1858 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1859 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1860 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1861 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1862 // CHECK2: arraydestroy.body:
1863 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1864 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1865 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1866 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1867 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1868 // CHECK2: arraydestroy.done2:
1869 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1870 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
1871 // CHECK2-NEXT: ret i32 [[TMP30]]
1872 //
1873 //
1874 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1875 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1876 // CHECK2-NEXT: entry:
1877 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1878 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1879 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1880 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1881 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
1882 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1883 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4
1884 // CHECK2-NEXT: ret void
1885 //
1886 //
1887 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1888 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1889 // CHECK2-NEXT: entry:
1890 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1891 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1892 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1893 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1894 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1895 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1896 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1897 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
1898 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
1899 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1900 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1901 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1902 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1903 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
1904 // CHECK2-NEXT: ret void
1905 //
1906 //
1907 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1908 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1909 // CHECK2-NEXT: entry:
1910 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1911 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1912 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1913 // CHECK2-NEXT: ret void
1914 //
1915 //
1916 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1917 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1918 // CHECK2-NEXT: entry:
1919 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1920 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1921 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1922 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1923 // CHECK2-NEXT: ret void
1924 //
1925 //
1926 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1927 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1928 // CHECK2-NEXT: entry:
1929 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1930 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1931 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1932 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1933 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1934 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1935 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
1936 // CHECK2-NEXT: ret void
1937 //
1938 //
1939 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
1940 // CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1941 // CHECK2-NEXT: entry:
1942 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1943 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1944 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1945 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1946 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1947 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1948 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1949 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1950 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1951 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1952 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1953 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1954 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1955 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1956 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1957 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1958 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1959 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
1960 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1961 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1962 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
1963 // CHECK2-NEXT: ret void
1964 //
1965 //
1966 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1967 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1968 // CHECK2-NEXT: entry:
1969 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1970 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1971 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1972 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1973 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1974 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1975 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1976 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1977 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1978 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1979 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1980 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1981 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1982 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1983 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
1984 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1985 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1986 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1987 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
1988 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1989 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1990 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1991 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1992 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1993 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1994 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1995 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1996 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1997 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1998 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1999 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2000 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
2001 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2002 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2003 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2004 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2005 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2006 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2007 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
2008 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2009 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2010 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2011 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
2012 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2013 // CHECK2: omp.arraycpy.body:
2014 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2015 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2016 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2017 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2018 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2019 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2020 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2021 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2022 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2023 // CHECK2: omp.arraycpy.done4:
2024 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2025 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2026 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
2027 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2028 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
2029 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2030 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
2031 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2032 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2033 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
2034 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2035 // CHECK2: cond.true:
2036 // CHECK2-NEXT: br label [[COND_END:%.*]]
2037 // CHECK2: cond.false:
2038 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2039 // CHECK2-NEXT: br label [[COND_END]]
2040 // CHECK2: cond.end:
2041 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2042 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2043 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2044 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
2045 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2046 // CHECK2: omp.inner.for.cond:
2047 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2048 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2049 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2050 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2051 // CHECK2: omp.inner.for.cond.cleanup:
2052 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2053 // CHECK2: omp.inner.for.body:
2054 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2055 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
2056 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2057 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
2058 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
2059 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2060 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
2061 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2062 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
2063 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
2064 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2065 // CHECK2: omp.inner.for.inc:
2066 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2067 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2068 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
2069 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2070 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
2071 // CHECK2: omp.inner.for.end:
2072 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2073 // CHECK2: omp.loop.exit:
2074 // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2075 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
2076 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
2077 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2078 // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2079 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
2080 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2081 // CHECK2: arraydestroy.body:
2082 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2083 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2084 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2085 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2086 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2087 // CHECK2: arraydestroy.done11:
2088 // CHECK2-NEXT: ret void
2089 //
2090 //
2091 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2092 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2093 // CHECK2-NEXT: entry:
2094 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2095 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
2096 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2097 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
2098 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2099 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
2100 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2101 // CHECK2-NEXT: ret void
2102 //
2103 //
2104 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
2105 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2106 // CHECK2-NEXT: entry:
2107 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2108 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2109 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2110 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2111 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2112 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2113 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
2114 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
2115 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
2116 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2117 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2118 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2119 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2120 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2121 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2122 // CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
2123 // CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
2124 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2125 // CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2126 // CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
2127 // CHECK2-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
2128 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
2129 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2130 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2131 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2132 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2133 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2134 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2135 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2136 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
2137 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2138 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2139 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2140 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2141 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
2142 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2143 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2144 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2145 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
2146 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2147 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
2148 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
2149 // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
2150 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2151 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2152 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
2153 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2154 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
2155 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
2156 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2157 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2158 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
2159 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2160 // CHECK2: omp.arraycpy.body:
2161 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2162 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2163 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2164 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2165 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2166 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2167 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2168 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2169 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
2170 // CHECK2: omp.arraycpy.done6:
2171 // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2172 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
2173 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]])
2174 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
2175 // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
2176 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2177 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2178 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2179 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2180 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
2181 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2182 // CHECK2: cond.true:
2183 // CHECK2-NEXT: br label [[COND_END:%.*]]
2184 // CHECK2: cond.false:
2185 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2186 // CHECK2-NEXT: br label [[COND_END]]
2187 // CHECK2: cond.end:
2188 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2189 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2190 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2191 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
2192 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2193 // CHECK2: omp.inner.for.cond:
2194 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2195 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2196 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2197 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2198 // CHECK2: omp.inner.for.cond.cleanup:
2199 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2200 // CHECK2: omp.inner.for.body:
2201 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2202 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
2203 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2204 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2205 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
2206 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2207 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
2208 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
2209 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
2210 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
2211 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
2212 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
2213 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
2214 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
2215 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
2216 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
2217 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2218 // CHECK2: omp.body.continue:
2219 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2220 // CHECK2: omp.inner.for.inc:
2221 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2222 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
2223 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
2224 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
2225 // CHECK2: omp.inner.for.end:
2226 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2227 // CHECK2: omp.loop.exit:
2228 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2229 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2230 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2231 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
2232 // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
2233 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
2234 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2235 // CHECK2: arraydestroy.body:
2236 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2237 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2238 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2239 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
2240 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
2241 // CHECK2: arraydestroy.done15:
2242 // CHECK2-NEXT: ret void
2243 //
2244 //
2245 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2246 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2247 // CHECK2-NEXT: entry:
2248 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2249 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2250 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2251 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2252 // CHECK2-NEXT: ret void
2253 //
2254 //
2255 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2256 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2257 // CHECK2-NEXT: entry:
2258 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2259 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2260 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2261 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2262 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2263 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2264 // CHECK2-NEXT: ret void
2265 //
2266 //
2267 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2268 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2269 // CHECK2-NEXT: entry:
2270 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2271 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2272 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2273 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2274 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2275 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2276 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2277 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2278 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2279 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2280 // CHECK2-NEXT: ret void
2281 //
2282 //
2283 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2284 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2285 // CHECK2-NEXT: entry:
2286 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2287 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
2288 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2289 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
2290 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2291 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2292 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
2293 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
2294 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
2295 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2296 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2297 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2298 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2299 // CHECK2-NEXT: ret void
2300 //
2301 //
2302 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2303 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2304 // CHECK2-NEXT: entry:
2305 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2306 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2307 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2308 // CHECK2-NEXT: ret void
2309 //
2310 //
2311 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
2312 // CHECK2-SAME: () #[[ATTR0]] {
2313 // CHECK2-NEXT: entry:
2314 // CHECK2-NEXT: call void @__cxx_global_var_init()
2315 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
2316 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
2317 // CHECK2-NEXT: ret void
2318 //
2319 //
2320 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2321 // CHECK2-SAME: () #[[ATTR0]] {
2322 // CHECK2-NEXT: entry:
2323 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
2324 // CHECK2-NEXT: ret void
2325 //
2326 //
2327 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
2328 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
2329 // CHECK3-NEXT: entry:
2330 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2331 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2332 // CHECK3-NEXT: ret void
2333 //
2334 //
2335 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2336 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2337 // CHECK3-NEXT: entry:
2338 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2339 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2340 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2341 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2342 // CHECK3-NEXT: ret void
2343 //
2344 //
2345 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2346 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2347 // CHECK3-NEXT: entry:
2348 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2349 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2350 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2351 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2352 // CHECK3-NEXT: ret void
2353 //
2354 //
2355 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2356 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2357 // CHECK3-NEXT: entry:
2358 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2359 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2360 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2361 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2362 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2363 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2364 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
2365 // CHECK3-NEXT: ret void
2366 //
2367 //
2368 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2369 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2370 // CHECK3-NEXT: entry:
2371 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2372 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2373 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2374 // CHECK3-NEXT: ret void
2375 //
2376 //
2377 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2378 // CHECK3-SAME: () #[[ATTR0]] {
2379 // CHECK3-NEXT: entry:
2380 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2381 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2382 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2383 // CHECK3-NEXT: ret void
2384 //
2385 //
2386 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2387 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2388 // CHECK3-NEXT: entry:
2389 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2390 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2391 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2392 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2393 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2394 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2395 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2396 // CHECK3-NEXT: ret void
2397 //
2398 //
2399 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2400 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2401 // CHECK3-NEXT: entry:
2402 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2403 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2404 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2405 // CHECK3: arraydestroy.body:
2406 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2407 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2408 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2409 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2410 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2411 // CHECK3: arraydestroy.done1:
2412 // CHECK3-NEXT: ret void
2413 //
2414 //
2415 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2416 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2417 // CHECK3-NEXT: entry:
2418 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2419 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2420 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2421 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2422 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2423 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2424 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2425 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2426 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2427 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2428 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
2429 // CHECK3-NEXT: ret void
2430 //
2431 //
2432 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2433 // CHECK3-SAME: () #[[ATTR0]] {
2434 // CHECK3-NEXT: entry:
2435 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2436 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2437 // CHECK3-NEXT: ret void
2438 //
2439 //
2440 // CHECK3-LABEL: define {{[^@]+}}@main
2441 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
2442 // CHECK3-NEXT: entry:
2443 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2444 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2445 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2446 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
2447 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
2448 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
2449 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2450 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
2451 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
2452 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
2453 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2454 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
2455 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
2456 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2457 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2458 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]**
2459 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4
2460 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2461 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]**
2462 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4
2463 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2464 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
2465 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2466 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
2467 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
2468 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2469 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
2470 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4
2471 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2472 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
2473 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2474 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
2475 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
2476 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2477 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
2478 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
2479 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2480 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
2481 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2482 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
2483 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
2484 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2485 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
2486 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
2487 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2488 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
2489 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2490 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
2491 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
2492 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2493 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
2494 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
2495 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2496 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
2497 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2498 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2499 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
2500 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2501 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2502 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2503 // CHECK3: omp_offload.failed:
2504 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
2505 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2506 // CHECK3: omp_offload.cont:
2507 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
2508 // CHECK3-NEXT: ret i32 [[CALL]]
2509 //
2510 //
2511 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
2512 // CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
2513 // CHECK3-NEXT: entry:
2514 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2515 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2516 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2517 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2518 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2519 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2520 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2521 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2522 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2523 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2524 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2525 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2526 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2527 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2528 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2529 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2530 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
2531 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2532 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2533 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
2534 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2535 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
2536 // CHECK3-NEXT: ret void
2537 //
2538 //
2539 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2540 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
2541 // CHECK3-NEXT: entry:
2542 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2543 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2544 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2545 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2546 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2547 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2548 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2549 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2550 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2551 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2552 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2553 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2554 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2555 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
2556 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
2557 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2558 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2559 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
2560 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2561 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2562 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2563 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2564 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2565 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2566 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2567 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2568 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2569 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2570 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2571 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2572 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2573 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2574 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2575 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2576 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2577 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
2578 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2579 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2580 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2581 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
2582 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2583 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
2584 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2585 // CHECK3: omp.arraycpy.body:
2586 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2587 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2588 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2589 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2590 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2591 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2592 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2593 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2594 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
2595 // CHECK3: omp.arraycpy.done3:
2596 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
2597 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
2598 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
2599 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2600 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2601 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2602 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2603 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2604 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2605 // CHECK3: cond.true:
2606 // CHECK3-NEXT: br label [[COND_END:%.*]]
2607 // CHECK3: cond.false:
2608 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2609 // CHECK3-NEXT: br label [[COND_END]]
2610 // CHECK3: cond.end:
2611 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2612 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2613 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2614 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
2615 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2616 // CHECK3: omp.inner.for.cond:
2617 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2618 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2619 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2620 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2621 // CHECK3: omp.inner.for.cond.cleanup:
2622 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2623 // CHECK3: omp.inner.for.body:
2624 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2625 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2626 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2627 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
2628 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2629 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2630 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
2631 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2632 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
2633 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2634 // CHECK3: omp.inner.for.inc:
2635 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2636 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2637 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2638 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2639 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2640 // CHECK3: omp.inner.for.end:
2641 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2642 // CHECK3: omp.loop.exit:
2643 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2644 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
2645 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
2646 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
2647 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2648 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
2649 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2650 // CHECK3: arraydestroy.body:
2651 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2652 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2653 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2654 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
2655 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
2656 // CHECK3: arraydestroy.done8:
2657 // CHECK3-NEXT: ret void
2658 //
2659 //
2660 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
2661 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2662 // CHECK3-NEXT: entry:
2663 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2664 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2665 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2666 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
2667 // CHECK3-NEXT: ret void
2668 //
2669 //
2670 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
2671 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2672 // CHECK3-NEXT: entry:
2673 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2674 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2675 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2676 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2677 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2678 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2679 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2680 // CHECK3-NEXT: ret void
2681 //
2682 //
2683 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
2684 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2685 // CHECK3-NEXT: entry:
2686 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2687 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2688 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2689 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
2690 // CHECK3-NEXT: ret void
2691 //
2692 //
2693 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
2694 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
2695 // CHECK3-NEXT: entry:
2696 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2697 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2698 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2699 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2700 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2701 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2702 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2703 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2704 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2705 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2706 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2707 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2708 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2709 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2710 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2711 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
2712 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
2713 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2714 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2715 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
2716 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2717 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2718 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2719 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2720 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2721 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2722 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2723 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2724 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2725 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2726 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2727 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2728 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2729 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2730 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2731 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2732 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2733 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
2734 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
2735 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2736 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2737 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
2738 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2739 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
2740 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2741 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
2742 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2743 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
2744 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2745 // CHECK3: omp.arraycpy.body:
2746 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2747 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2748 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2749 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2750 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2751 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2752 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2753 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2754 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
2755 // CHECK3: omp.arraycpy.done3:
2756 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
2757 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
2758 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
2759 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2760 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2761 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2762 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2763 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
2764 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2765 // CHECK3: cond.true:
2766 // CHECK3-NEXT: br label [[COND_END:%.*]]
2767 // CHECK3: cond.false:
2768 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2769 // CHECK3-NEXT: br label [[COND_END]]
2770 // CHECK3: cond.end:
2771 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2772 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2773 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2774 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2775 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2776 // CHECK3: omp.inner.for.cond:
2777 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2778 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2779 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2780 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2781 // CHECK3: omp.inner.for.cond.cleanup:
2782 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2783 // CHECK3: omp.inner.for.body:
2784 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2785 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
2786 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2787 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2788 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2789 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
2790 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
2791 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
2792 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2793 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
2794 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
2795 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
2796 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
2797 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
2798 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2799 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
2800 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
2801 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2802 // CHECK3: omp.body.continue:
2803 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2804 // CHECK3: omp.inner.for.inc:
2805 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2806 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
2807 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
2808 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2809 // CHECK3: omp.inner.for.end:
2810 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2811 // CHECK3: omp.loop.exit:
2812 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2813 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2814 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2815 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
2816 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2817 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
2818 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2819 // CHECK3: arraydestroy.body:
2820 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2821 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2822 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2823 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2824 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2825 // CHECK3: arraydestroy.done11:
2826 // CHECK3-NEXT: ret void
2827 //
2828 //
2829 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2830 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
2831 // CHECK3-NEXT: entry:
2832 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2833 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2834 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2835 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2836 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2837 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2838 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2839 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2840 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2841 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2842 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2843 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2844 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2845 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
2846 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2847 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2848 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2849 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
2850 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2851 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
2852 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2853 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
2854 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
2855 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2856 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
2857 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2858 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2859 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2860 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
2861 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4
2862 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2863 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
2864 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
2865 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2866 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4
2867 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2868 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
2869 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
2870 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2871 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
2872 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
2873 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2874 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4
2875 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2876 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
2877 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4
2878 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2879 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
2880 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
2881 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2882 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
2883 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2884 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
2885 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4
2886 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2887 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
2888 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4
2889 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2890 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4
2891 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2892 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2893 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
2894 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2895 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2896 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2897 // CHECK3: omp_offload.failed:
2898 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
2899 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2900 // CHECK3: omp_offload.cont:
2901 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
2902 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2903 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2904 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2905 // CHECK3: arraydestroy.body:
2906 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2907 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2908 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2909 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2910 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2911 // CHECK3: arraydestroy.done2:
2912 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2913 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
2914 // CHECK3-NEXT: ret i32 [[TMP30]]
2915 //
2916 //
2917 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
2918 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2919 // CHECK3-NEXT: entry:
2920 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2921 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2922 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2923 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
2924 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
2925 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
2926 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4
2927 // CHECK3-NEXT: ret void
2928 //
2929 //
2930 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
2931 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2932 // CHECK3-NEXT: entry:
2933 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2934 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2935 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2936 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2937 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2938 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2939 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2940 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
2941 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
2942 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2943 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2944 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
2945 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
2946 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
2947 // CHECK3-NEXT: ret void
2948 //
2949 //
2950 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
2951 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2952 // CHECK3-NEXT: entry:
2953 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2954 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2955 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2956 // CHECK3-NEXT: ret void
2957 //
2958 //
2959 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2960 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2961 // CHECK3-NEXT: entry:
2962 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2963 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2964 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2965 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2966 // CHECK3-NEXT: ret void
2967 //
2968 //
2969 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2970 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2971 // CHECK3-NEXT: entry:
2972 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2973 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2974 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2975 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2976 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2977 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2978 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2979 // CHECK3-NEXT: ret void
2980 //
2981 //
2982 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
2983 // CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2984 // CHECK3-NEXT: entry:
2985 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2986 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2987 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2988 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2989 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2990 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2991 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2992 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2993 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2994 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2995 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2996 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2997 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2998 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2999 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3000 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
3001 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3002 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3003 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
3004 // CHECK3-NEXT: ret void
3005 //
3006 //
3007 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
3008 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3009 // CHECK3-NEXT: entry:
3010 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3011 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3012 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3013 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3014 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3015 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3016 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3017 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3018 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3019 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3020 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3021 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3022 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3023 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
3024 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
3025 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3026 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3027 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3028 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
3029 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3030 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3031 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3032 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3033 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3034 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3035 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3036 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3037 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3038 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3039 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3040 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3041 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3042 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3043 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3044 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3045 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3046 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3047 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
3048 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3049 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
3050 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3051 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
3052 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3053 // CHECK3: omp.arraycpy.body:
3054 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3055 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3056 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3057 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3058 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3059 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3060 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3061 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
3062 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
3063 // CHECK3: omp.arraycpy.done4:
3064 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3065 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
3066 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
3067 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
3068 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
3069 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3070 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
3071 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3072 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3073 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
3074 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3075 // CHECK3: cond.true:
3076 // CHECK3-NEXT: br label [[COND_END:%.*]]
3077 // CHECK3: cond.false:
3078 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3079 // CHECK3-NEXT: br label [[COND_END]]
3080 // CHECK3: cond.end:
3081 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
3082 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3083 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3084 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
3085 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3086 // CHECK3: omp.inner.for.cond:
3087 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3088 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3089 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
3090 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3091 // CHECK3: omp.inner.for.cond.cleanup:
3092 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3093 // CHECK3: omp.inner.for.body:
3094 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3095 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3096 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3097 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
3098 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3099 // CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
3100 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
3101 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3102 // CHECK3: omp.inner.for.inc:
3103 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3104 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3105 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
3106 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3107 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3108 // CHECK3: omp.inner.for.end:
3109 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3110 // CHECK3: omp.loop.exit:
3111 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3112 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
3113 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
3114 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3115 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3116 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
3117 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3118 // CHECK3: arraydestroy.body:
3119 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3120 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3121 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3122 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
3123 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
3124 // CHECK3: arraydestroy.done10:
3125 // CHECK3-NEXT: ret void
3126 //
3127 //
3128 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
3129 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3130 // CHECK3-NEXT: entry:
3131 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3132 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
3133 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3134 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
3135 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3136 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
3137 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
3138 // CHECK3-NEXT: ret void
3139 //
3140 //
3141 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
3142 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3143 // CHECK3-NEXT: entry:
3144 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3145 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3146 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3147 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3148 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3149 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3150 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3151 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3152 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3153 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3154 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3155 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3156 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3157 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3158 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3159 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
3160 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
3161 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3162 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3163 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3164 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
3165 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3166 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3167 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3168 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3169 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3170 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3171 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3172 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3173 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3174 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3175 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3176 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3177 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3178 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3179 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3180 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3181 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3182 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
3183 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
3184 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3185 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3186 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3187 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3188 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
3189 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3190 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
3191 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3192 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
3193 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3194 // CHECK3: omp.arraycpy.body:
3195 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3196 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3197 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3198 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3199 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3200 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3201 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3202 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
3203 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
3204 // CHECK3: omp.arraycpy.done4:
3205 // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3206 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
3207 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]])
3208 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
3209 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
3210 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3211 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
3212 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3213 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3214 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
3215 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3216 // CHECK3: cond.true:
3217 // CHECK3-NEXT: br label [[COND_END:%.*]]
3218 // CHECK3: cond.false:
3219 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3220 // CHECK3-NEXT: br label [[COND_END]]
3221 // CHECK3: cond.end:
3222 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
3223 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3224 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3225 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
3226 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3227 // CHECK3: omp.inner.for.cond:
3228 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3229 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3230 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
3231 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3232 // CHECK3: omp.inner.for.cond.cleanup:
3233 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3234 // CHECK3: omp.inner.for.body:
3235 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3236 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
3237 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3238 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3239 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3240 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3241 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
3242 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
3243 // CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
3244 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
3245 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
3246 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
3247 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
3248 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
3249 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3250 // CHECK3: omp.body.continue:
3251 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3252 // CHECK3: omp.inner.for.inc:
3253 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3254 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
3255 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
3256 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3257 // CHECK3: omp.inner.for.end:
3258 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3259 // CHECK3: omp.loop.exit:
3260 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3261 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3262 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3263 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3264 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3265 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3266 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3267 // CHECK3: arraydestroy.body:
3268 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3269 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3270 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3271 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
3272 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
3273 // CHECK3: arraydestroy.done12:
3274 // CHECK3-NEXT: ret void
3275 //
3276 //
3277 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3278 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3279 // CHECK3-NEXT: entry:
3280 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3281 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3282 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3283 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3284 // CHECK3-NEXT: ret void
3285 //
3286 //
3287 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3288 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3289 // CHECK3-NEXT: entry:
3290 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3291 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3292 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3293 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3294 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3295 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3296 // CHECK3-NEXT: ret void
3297 //
3298 //
3299 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3300 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3301 // CHECK3-NEXT: entry:
3302 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3303 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3304 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3305 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3306 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3307 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3308 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3309 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3310 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3311 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3312 // CHECK3-NEXT: ret void
3313 //
3314 //
3315 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
3316 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3317 // CHECK3-NEXT: entry:
3318 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3319 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
3320 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3321 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
3322 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3323 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3324 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
3325 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
3326 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
3327 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
3328 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3329 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
3330 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3331 // CHECK3-NEXT: ret void
3332 //
3333 //
3334 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3335 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3336 // CHECK3-NEXT: entry:
3337 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3338 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3339 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3340 // CHECK3-NEXT: ret void
3341 //
3342 //
3343 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
3344 // CHECK3-SAME: () #[[ATTR0]] {
3345 // CHECK3-NEXT: entry:
3346 // CHECK3-NEXT: call void @__cxx_global_var_init()
3347 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
3348 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
3349 // CHECK3-NEXT: ret void
3350 //
3351 //
3352 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3353 // CHECK3-SAME: () #[[ATTR0]] {
3354 // CHECK3-NEXT: entry:
3355 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
3356 // CHECK3-NEXT: ret void
3357 //
3358 //
3359 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
3360 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
3361 // CHECK4-NEXT: entry:
3362 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3363 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3364 // CHECK4-NEXT: ret void
3365 //
3366 //
3367 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3368 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3369 // CHECK4-NEXT: entry:
3370 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3371 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3372 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3373 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3374 // CHECK4-NEXT: ret void
3375 //
3376 //
3377 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3378 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3379 // CHECK4-NEXT: entry:
3380 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3381 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3382 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3383 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3384 // CHECK4-NEXT: ret void
3385 //
3386 //
3387 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3388 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3389 // CHECK4-NEXT: entry:
3390 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3391 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3392 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3393 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3394 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3395 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3396 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
3397 // CHECK4-NEXT: ret void
3398 //
3399 //
3400 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3401 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3402 // CHECK4-NEXT: entry:
3403 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3404 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3405 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3406 // CHECK4-NEXT: ret void
3407 //
3408 //
3409 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3410 // CHECK4-SAME: () #[[ATTR0]] {
3411 // CHECK4-NEXT: entry:
3412 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
3413 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
3414 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3415 // CHECK4-NEXT: ret void
3416 //
3417 //
3418 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3419 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3420 // CHECK4-NEXT: entry:
3421 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3422 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3423 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3424 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3425 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3426 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3427 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3428 // CHECK4-NEXT: ret void
3429 //
3430 //
3431 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3432 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3433 // CHECK4-NEXT: entry:
3434 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
3435 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
3436 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3437 // CHECK4: arraydestroy.body:
3438 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3439 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3440 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3441 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3442 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3443 // CHECK4: arraydestroy.done1:
3444 // CHECK4-NEXT: ret void
3445 //
3446 //
3447 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3448 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3449 // CHECK4-NEXT: entry:
3450 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3451 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3452 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3453 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3454 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3455 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3456 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3457 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3458 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3459 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3460 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
3461 // CHECK4-NEXT: ret void
3462 //
3463 //
3464 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3465 // CHECK4-SAME: () #[[ATTR0]] {
3466 // CHECK4-NEXT: entry:
3467 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3468 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3469 // CHECK4-NEXT: ret void
3470 //
3471 //
3472 // CHECK4-LABEL: define {{[^@]+}}@main
3473 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
3474 // CHECK4-NEXT: entry:
3475 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3476 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3477 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
3478 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3479 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3480 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3481 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3482 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
3483 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
3484 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
3485 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3486 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
3487 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
3488 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
3489 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3490 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]**
3491 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4
3492 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3493 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]**
3494 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4
3495 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3496 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
3497 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3498 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3499 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
3500 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3501 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
3502 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4
3503 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3504 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
3505 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3506 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
3507 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
3508 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3509 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
3510 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
3511 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3512 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
3513 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3514 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
3515 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
3516 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3517 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
3518 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
3519 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3520 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
3521 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3522 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
3523 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
3524 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3525 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
3526 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
3527 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3528 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4
3529 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3530 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3531 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
3532 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3533 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3534 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3535 // CHECK4: omp_offload.failed:
3536 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
3537 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3538 // CHECK4: omp_offload.cont:
3539 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3540 // CHECK4-NEXT: ret i32 [[CALL]]
3541 //
3542 //
3543 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
3544 // CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
3545 // CHECK4-NEXT: entry:
3546 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3547 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3548 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3549 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3550 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
3551 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3552 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
3553 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3554 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3555 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3556 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3557 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
3558 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3559 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3560 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3561 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3562 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
3563 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3564 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
3565 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
3566 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
3567 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
3568 // CHECK4-NEXT: ret void
3569 //
3570 //
3571 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
3572 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
3573 // CHECK4-NEXT: entry:
3574 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3575 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3576 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3577 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3578 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3579 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3580 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
3581 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3582 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3583 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3584 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3585 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3586 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3587 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
3588 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
3589 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3590 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3591 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
3592 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3593 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3594 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
3595 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3596 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3597 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3598 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3599 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3600 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3601 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
3602 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3603 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3604 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3605 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3606 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3607 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3608 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3609 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
3610 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3611 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
3612 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3613 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
3614 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3615 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
3616 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3617 // CHECK4: omp.arraycpy.body:
3618 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3619 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3620 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3621 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3622 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3623 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3624 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3625 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
3626 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
3627 // CHECK4: omp.arraycpy.done3:
3628 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
3629 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
3630 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
3631 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3632 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
3633 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3634 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3635 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
3636 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3637 // CHECK4: cond.true:
3638 // CHECK4-NEXT: br label [[COND_END:%.*]]
3639 // CHECK4: cond.false:
3640 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3641 // CHECK4-NEXT: br label [[COND_END]]
3642 // CHECK4: cond.end:
3643 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3644 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3645 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3646 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
3647 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3648 // CHECK4: omp.inner.for.cond:
3649 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3650 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3651 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
3652 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3653 // CHECK4: omp.inner.for.cond.cleanup:
3654 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3655 // CHECK4: omp.inner.for.body:
3656 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3657 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3658 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3659 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
3660 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3661 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
3662 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
3663 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
3664 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
3665 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3666 // CHECK4: omp.inner.for.inc:
3667 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3668 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3669 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
3670 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3671 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
3672 // CHECK4: omp.inner.for.end:
3673 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3674 // CHECK4: omp.loop.exit:
3675 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3676 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
3677 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
3678 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
3679 // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3680 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
3681 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3682 // CHECK4: arraydestroy.body:
3683 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3684 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3685 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3686 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
3687 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
3688 // CHECK4: arraydestroy.done8:
3689 // CHECK4-NEXT: ret void
3690 //
3691 //
3692 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev
3693 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3694 // CHECK4-NEXT: entry:
3695 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3696 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3697 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3698 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
3699 // CHECK4-NEXT: ret void
3700 //
3701 //
3702 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
3703 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3704 // CHECK4-NEXT: entry:
3705 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3706 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
3707 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3708 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
3709 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3710 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
3711 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
3712 // CHECK4-NEXT: ret void
3713 //
3714 //
3715 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev
3716 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3717 // CHECK4-NEXT: entry:
3718 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3719 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3720 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3721 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
3722 // CHECK4-NEXT: ret void
3723 //
3724 //
3725 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
3726 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
3727 // CHECK4-NEXT: entry:
3728 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3729 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3730 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3731 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3732 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3733 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3734 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3735 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3736 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
3737 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3738 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3739 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3740 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3741 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3742 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3743 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
3744 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
3745 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3746 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3747 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
3748 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3749 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3750 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3751 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3752 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3753 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3754 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3755 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3756 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3757 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
3758 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3759 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3760 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3761 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3762 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3763 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3764 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3765 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
3766 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
3767 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3768 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3769 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
3770 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3771 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
3772 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3773 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
3774 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3775 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
3776 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3777 // CHECK4: omp.arraycpy.body:
3778 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3779 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3780 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3781 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3782 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3783 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3784 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3785 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
3786 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
3787 // CHECK4: omp.arraycpy.done3:
3788 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
3789 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
3790 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
3791 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3792 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3793 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3794 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3795 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
3796 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3797 // CHECK4: cond.true:
3798 // CHECK4-NEXT: br label [[COND_END:%.*]]
3799 // CHECK4: cond.false:
3800 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3801 // CHECK4-NEXT: br label [[COND_END]]
3802 // CHECK4: cond.end:
3803 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3804 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3805 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3806 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
3807 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3808 // CHECK4: omp.inner.for.cond:
3809 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3810 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3811 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
3812 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3813 // CHECK4: omp.inner.for.cond.cleanup:
3814 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3815 // CHECK4: omp.inner.for.body:
3816 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3817 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
3818 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3819 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3820 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3821 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
3822 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
3823 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
3824 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3825 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
3826 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
3827 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
3828 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
3829 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
3830 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
3831 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
3832 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
3833 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3834 // CHECK4: omp.body.continue:
3835 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3836 // CHECK4: omp.inner.for.inc:
3837 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3838 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
3839 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
3840 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
3841 // CHECK4: omp.inner.for.end:
3842 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3843 // CHECK4: omp.loop.exit:
3844 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3845 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3846 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3847 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
3848 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3849 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
3850 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3851 // CHECK4: arraydestroy.body:
3852 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3853 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3854 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3855 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
3856 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
3857 // CHECK4: arraydestroy.done11:
3858 // CHECK4-NEXT: ret void
3859 //
3860 //
3861 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3862 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat {
3863 // CHECK4-NEXT: entry:
3864 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3865 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3866 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3867 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3868 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3869 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3870 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3871 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3872 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3873 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3874 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3875 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3876 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3877 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
3878 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3879 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3880 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3881 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3882 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3883 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3884 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3885 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3886 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
3887 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
3888 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
3889 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3890 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3891 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3892 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
3893 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4
3894 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3895 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
3896 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
3897 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3898 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4
3899 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3900 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
3901 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
3902 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3903 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3904 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
3905 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3906 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4
3907 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3908 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
3909 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4
3910 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3911 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
3912 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
3913 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3914 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4
3915 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3916 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
3917 // CHECK4-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4
3918 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3919 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
3920 // CHECK4-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4
3921 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3922 // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4
3923 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3924 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3925 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
3926 // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3927 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3928 // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3929 // CHECK4: omp_offload.failed:
3930 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
3931 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3932 // CHECK4: omp_offload.cont:
3933 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
3934 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3935 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3936 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3937 // CHECK4: arraydestroy.body:
3938 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3939 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3940 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3941 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3942 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
3943 // CHECK4: arraydestroy.done2:
3944 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3945 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
3946 // CHECK4-NEXT: ret i32 [[TMP30]]
3947 //
3948 //
3949 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev
3950 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3951 // CHECK4-NEXT: entry:
3952 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3953 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3954 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3955 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
3956 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
3957 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
3958 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4
3959 // CHECK4-NEXT: ret void
3960 //
3961 //
3962 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
3963 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3964 // CHECK4-NEXT: entry:
3965 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3966 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
3967 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3968 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
3969 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3970 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3971 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
3972 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
3973 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
3974 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
3975 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3976 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
3977 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
3978 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
3979 // CHECK4-NEXT: ret void
3980 //
3981 //
3982 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev
3983 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3984 // CHECK4-NEXT: entry:
3985 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3986 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3987 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3988 // CHECK4-NEXT: ret void
3989 //
3990 //
3991 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3992 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3993 // CHECK4-NEXT: entry:
3994 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3995 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3996 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3997 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3998 // CHECK4-NEXT: ret void
3999 //
4000 //
4001 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4002 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4003 // CHECK4-NEXT: entry:
4004 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4005 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4006 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4007 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4008 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4009 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4010 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4011 // CHECK4-NEXT: ret void
4012 //
4013 //
4014 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
4015 // CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
4016 // CHECK4-NEXT: entry:
4017 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4018 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4019 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4020 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4021 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4022 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4023 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4024 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4025 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4026 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4027 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4028 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4029 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4030 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4031 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4032 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
4033 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4034 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4035 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
4036 // CHECK4-NEXT: ret void
4037 //
4038 //
4039 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
4040 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
4041 // CHECK4-NEXT: entry:
4042 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4043 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4044 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4045 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4046 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4047 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4048 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4049 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4050 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4051 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4052 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4053 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4054 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4055 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
4056 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
4057 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4058 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4059 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
4060 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
4061 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
4062 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4063 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4064 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4065 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4066 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4067 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4068 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4069 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4070 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4071 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4072 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4073 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4074 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4075 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4076 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4077 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
4078 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4079 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
4080 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4081 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4082 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4083 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
4084 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4085 // CHECK4: omp.arraycpy.body:
4086 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4087 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4088 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
4089 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
4090 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
4091 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4092 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4093 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
4094 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4095 // CHECK4: omp.arraycpy.done4:
4096 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4097 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
4098 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
4099 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
4100 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
4101 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4102 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
4103 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4104 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4105 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
4106 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4107 // CHECK4: cond.true:
4108 // CHECK4-NEXT: br label [[COND_END:%.*]]
4109 // CHECK4: cond.false:
4110 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4111 // CHECK4-NEXT: br label [[COND_END]]
4112 // CHECK4: cond.end:
4113 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4114 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4115 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4116 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
4117 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4118 // CHECK4: omp.inner.for.cond:
4119 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4120 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4121 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4122 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4123 // CHECK4: omp.inner.for.cond.cleanup:
4124 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4125 // CHECK4: omp.inner.for.body:
4126 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4127 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4128 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4129 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
4130 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4131 // CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
4132 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
4133 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4134 // CHECK4: omp.inner.for.inc:
4135 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4136 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4137 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
4138 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4139 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
4140 // CHECK4: omp.inner.for.end:
4141 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4142 // CHECK4: omp.loop.exit:
4143 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4144 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
4145 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
4146 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
4147 // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4148 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
4149 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4150 // CHECK4: arraydestroy.body:
4151 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4152 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4153 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4154 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
4155 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
4156 // CHECK4: arraydestroy.done10:
4157 // CHECK4-NEXT: ret void
4158 //
4159 //
4160 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
4161 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4162 // CHECK4-NEXT: entry:
4163 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4164 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
4165 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4166 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
4167 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4168 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
4169 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
4170 // CHECK4-NEXT: ret void
4171 //
4172 //
4173 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5
4174 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
4175 // CHECK4-NEXT: entry:
4176 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4177 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4178 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4179 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4180 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4181 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4182 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4183 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4184 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4185 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4186 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4187 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4188 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4189 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4190 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4191 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
4192 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
4193 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4194 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4195 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
4196 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
4197 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
4198 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4199 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4200 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4201 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4202 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4203 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4204 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4205 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4206 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4207 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4208 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4209 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4210 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4211 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4212 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4213 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4214 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
4215 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
4216 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4217 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4218 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
4219 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4220 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
4221 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4222 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4223 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4224 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
4225 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4226 // CHECK4: omp.arraycpy.body:
4227 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4228 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4229 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
4230 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
4231 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
4232 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4233 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4234 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
4235 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4236 // CHECK4: omp.arraycpy.done4:
4237 // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4238 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
4239 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]])
4240 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
4241 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
4242 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4243 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
4244 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4245 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4246 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
4247 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4248 // CHECK4: cond.true:
4249 // CHECK4-NEXT: br label [[COND_END:%.*]]
4250 // CHECK4: cond.false:
4251 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4252 // CHECK4-NEXT: br label [[COND_END]]
4253 // CHECK4: cond.end:
4254 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
4255 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4256 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4257 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
4258 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4259 // CHECK4: omp.inner.for.cond:
4260 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4261 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4262 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
4263 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4264 // CHECK4: omp.inner.for.cond.cleanup:
4265 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4266 // CHECK4: omp.inner.for.body:
4267 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4268 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
4269 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4270 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4271 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4272 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
4273 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
4274 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
4275 // CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
4276 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
4277 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
4278 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
4279 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
4280 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
4281 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4282 // CHECK4: omp.body.continue:
4283 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4284 // CHECK4: omp.inner.for.inc:
4285 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4286 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
4287 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
4288 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
4289 // CHECK4: omp.inner.for.end:
4290 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4291 // CHECK4: omp.loop.exit:
4292 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4293 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
4294 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
4295 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
4296 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4297 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
4298 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4299 // CHECK4: arraydestroy.body:
4300 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4301 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4302 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4303 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
4304 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
4305 // CHECK4: arraydestroy.done12:
4306 // CHECK4-NEXT: ret void
4307 //
4308 //
4309 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4310 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4311 // CHECK4-NEXT: entry:
4312 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4313 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4314 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4315 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4316 // CHECK4-NEXT: ret void
4317 //
4318 //
4319 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4320 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4321 // CHECK4-NEXT: entry:
4322 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4323 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4324 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4325 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4326 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4327 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4328 // CHECK4-NEXT: ret void
4329 //
4330 //
4331 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4332 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4333 // CHECK4-NEXT: entry:
4334 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4335 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4336 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4337 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4338 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4339 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4340 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4341 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4342 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4343 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4344 // CHECK4-NEXT: ret void
4345 //
4346 //
4347 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
4348 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4349 // CHECK4-NEXT: entry:
4350 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4351 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
4352 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4353 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
4354 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4355 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4356 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
4357 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
4358 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
4359 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
4360 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4361 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
4362 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4363 // CHECK4-NEXT: ret void
4364 //
4365 //
4366 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4367 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4368 // CHECK4-NEXT: entry:
4369 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4370 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4371 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4372 // CHECK4-NEXT: ret void
4373 //
4374 //
4375 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
4376 // CHECK4-SAME: () #[[ATTR0]] {
4377 // CHECK4-NEXT: entry:
4378 // CHECK4-NEXT: call void @__cxx_global_var_init()
4379 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
4380 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
4381 // CHECK4-NEXT: ret void
4382 //
4383 //
4384 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4385 // CHECK4-SAME: () #[[ATTR0]] {
4386 // CHECK4-NEXT: entry:
4387 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
4388 // CHECK4-NEXT: ret void
4389 //
4390 //
4391 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
4392 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
4393 // CHECK5-NEXT: entry:
4394 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4395 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4396 // CHECK5-NEXT: ret void
4397 //
4398 //
4399 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4400 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4401 // CHECK5-NEXT: entry:
4402 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4403 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4404 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4405 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4406 // CHECK5-NEXT: ret void
4407 //
4408 //
4409 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4410 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4411 // CHECK5-NEXT: entry:
4412 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4413 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4414 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4415 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4416 // CHECK5-NEXT: ret void
4417 //
4418 //
4419 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4420 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4421 // CHECK5-NEXT: entry:
4422 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4423 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4424 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4425 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4426 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4427 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4428 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
4429 // CHECK5-NEXT: ret void
4430 //
4431 //
4432 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4433 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4434 // CHECK5-NEXT: entry:
4435 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4436 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4437 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4438 // CHECK5-NEXT: ret void
4439 //
4440 //
4441 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4442 // CHECK5-SAME: () #[[ATTR0]] {
4443 // CHECK5-NEXT: entry:
4444 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4445 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4446 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4447 // CHECK5-NEXT: ret void
4448 //
4449 //
4450 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4451 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4452 // CHECK5-NEXT: entry:
4453 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4454 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4455 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4456 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4457 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4458 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4459 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4460 // CHECK5-NEXT: ret void
4461 //
4462 //
4463 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4464 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4465 // CHECK5-NEXT: entry:
4466 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4467 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4468 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4469 // CHECK5: arraydestroy.body:
4470 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4471 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4472 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4473 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4474 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4475 // CHECK5: arraydestroy.done1:
4476 // CHECK5-NEXT: ret void
4477 //
4478 //
4479 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4480 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4481 // CHECK5-NEXT: entry:
4482 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4483 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4484 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4485 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4486 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4487 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4488 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4489 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4490 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4491 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4492 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
4493 // CHECK5-NEXT: ret void
4494 //
4495 //
4496 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4497 // CHECK5-SAME: () #[[ATTR0]] {
4498 // CHECK5-NEXT: entry:
4499 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4500 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4501 // CHECK5-NEXT: ret void
4502 //
4503 //
4504 // CHECK5-LABEL: define {{[^@]+}}@main
4505 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
4506 // CHECK5-NEXT: entry:
4507 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4508 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4509 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
4510 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4511 // CHECK5-NEXT: ret i32 0
4512 //
4513 //
4514 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
4515 // CHECK5-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
4516 // CHECK5-NEXT: entry:
4517 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4518 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4519 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4520 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4521 // CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
4522 // CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
4523 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
4524 // CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4525 // CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4526 // CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4527 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4528 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4529 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4530 // CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
4531 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
4532 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
4533 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
4534 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
4535 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
4536 // CHECK5-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
4537 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
4538 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
4539 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
4540 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
4541 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
4542 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
4543 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
4544 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
4545 // CHECK5-NEXT: ret void
4546 //
4547 //
4548 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
4549 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
4550 // CHECK5-NEXT: entry:
4551 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4552 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4553 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4554 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4555 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4556 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4557 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4558 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
4559 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4560 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4561 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4562 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4563 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
4564 // CHECK5-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
4565 // CHECK5-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
4566 // CHECK5-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
4567 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4568 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4569 // CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4570 // CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4571 // CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4572 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4573 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4574 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4575 // CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
4576 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4577 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4578 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4579 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4580 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4581 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4582 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4583 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4584 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
4585 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4586 // CHECK5: cond.true:
4587 // CHECK5-NEXT: br label [[COND_END:%.*]]
4588 // CHECK5: cond.false:
4589 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4590 // CHECK5-NEXT: br label [[COND_END]]
4591 // CHECK5: cond.end:
4592 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4593 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4594 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4595 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4596 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4597 // CHECK5: omp.inner.for.cond:
4598 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4599 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4600 // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4601 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4602 // CHECK5: omp.inner.for.body:
4603 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4604 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
4605 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4606 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
4607 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
4608 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
4609 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
4610 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
4611 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
4612 // CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
4613 // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
4614 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
4615 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
4616 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
4617 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
4618 // CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
4619 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
4620 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
4621 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4622 // CHECK5: omp.inner.for.inc:
4623 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4624 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4625 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
4626 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4627 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
4628 // CHECK5: omp.inner.for.end:
4629 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4630 // CHECK5: omp.loop.exit:
4631 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4632 // CHECK5-NEXT: ret void
4633 //
4634 //
4635 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
4636 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
4637 // CHECK5-NEXT: entry:
4638 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4639 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4640 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
4641 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
4642 // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4643 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4644 // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4645 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4646 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4647 // CHECK5-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
4648 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4649 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4650 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4651 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4652 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
4653 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
4654 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4655 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4656 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
4657 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
4658 // CHECK5-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4659 // CHECK5-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4660 // CHECK5-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4661 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4662 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4663 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4664 // CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
4665 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4666 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4667 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
4668 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
4669 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
4670 // CHECK5-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
4671 // CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
4672 // CHECK5-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
4673 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4674 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4675 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4676 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4677 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4678 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4679 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
4680 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4681 // CHECK5: cond.true:
4682 // CHECK5-NEXT: br label [[COND_END:%.*]]
4683 // CHECK5: cond.false:
4684 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4685 // CHECK5-NEXT: br label [[COND_END]]
4686 // CHECK5: cond.end:
4687 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4688 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4689 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4690 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
4691 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4692 // CHECK5: omp.inner.for.cond:
4693 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4694 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4695 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4696 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4697 // CHECK5: omp.inner.for.body:
4698 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4699 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
4700 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4701 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4702 // CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8
4703 // CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
4704 // CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
4705 // CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8
4706 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
4707 // CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
4708 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
4709 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
4710 // CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
4711 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
4712 // CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
4713 // CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
4714 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4715 // CHECK5: omp.body.continue:
4716 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4717 // CHECK5: omp.inner.for.inc:
4718 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4719 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
4720 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
4721 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
4722 // CHECK5: omp.inner.for.end:
4723 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4724 // CHECK5: omp.loop.exit:
4725 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4726 // CHECK5-NEXT: ret void
4727 //
4728 //
4729 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
4730 // CHECK5-SAME: () #[[ATTR0]] {
4731 // CHECK5-NEXT: entry:
4732 // CHECK5-NEXT: call void @__cxx_global_var_init()
4733 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
4734 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
4735 // CHECK5-NEXT: ret void
4736 //
4737 //
4738 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4739 // CHECK5-SAME: () #[[ATTR0]] {
4740 // CHECK5-NEXT: entry:
4741 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
4742 // CHECK5-NEXT: ret void
4743 //
4744 //
4745 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
4746 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
4747 // CHECK6-NEXT: entry:
4748 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4749 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4750 // CHECK6-NEXT: ret void
4751 //
4752 //
4753 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4754 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4755 // CHECK6-NEXT: entry:
4756 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4757 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4758 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4759 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4760 // CHECK6-NEXT: ret void
4761 //
4762 //
4763 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4764 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4765 // CHECK6-NEXT: entry:
4766 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4767 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4768 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4769 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4770 // CHECK6-NEXT: ret void
4771 //
4772 //
4773 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4774 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4775 // CHECK6-NEXT: entry:
4776 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4777 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4778 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4779 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4780 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4781 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4782 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4
4783 // CHECK6-NEXT: ret void
4784 //
4785 //
4786 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4787 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4788 // CHECK6-NEXT: entry:
4789 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4790 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4791 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4792 // CHECK6-NEXT: ret void
4793 //
4794 //
4795 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4796 // CHECK6-SAME: () #[[ATTR0]] {
4797 // CHECK6-NEXT: entry:
4798 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4799 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4800 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4801 // CHECK6-NEXT: ret void
4802 //
4803 //
4804 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4805 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4806 // CHECK6-NEXT: entry:
4807 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4808 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4809 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4810 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4811 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4812 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4813 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4814 // CHECK6-NEXT: ret void
4815 //
4816 //
4817 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4818 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4819 // CHECK6-NEXT: entry:
4820 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4821 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4822 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4823 // CHECK6: arraydestroy.body:
4824 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4825 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4826 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4827 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4828 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4829 // CHECK6: arraydestroy.done1:
4830 // CHECK6-NEXT: ret void
4831 //
4832 //
4833 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4834 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4835 // CHECK6-NEXT: entry:
4836 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4837 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4838 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4839 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4840 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4841 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4842 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4843 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4844 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4845 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4846 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4
4847 // CHECK6-NEXT: ret void
4848 //
4849 //
4850 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4851 // CHECK6-SAME: () #[[ATTR0]] {
4852 // CHECK6-NEXT: entry:
4853 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4854 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4855 // CHECK6-NEXT: ret void
4856 //
4857 //
4858 // CHECK6-LABEL: define {{[^@]+}}@main
4859 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
4860 // CHECK6-NEXT: entry:
4861 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4862 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4863 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
4864 // CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4865 // CHECK6-NEXT: ret i32 0
4866 //
4867 //
4868 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
4869 // CHECK6-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
4870 // CHECK6-NEXT: entry:
4871 // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4872 // CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4873 // CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4874 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4875 // CHECK6-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
4876 // CHECK6-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
4877 // CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
4878 // CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4879 // CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4880 // CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4881 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4882 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4883 // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4884 // CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
4885 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
4886 // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
4887 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
4888 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
4889 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
4890 // CHECK6-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
4891 // CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
4892 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
4893 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
4894 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
4895 // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
4896 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
4897 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
4898 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
4899 // CHECK6-NEXT: ret void
4900 //
4901 //
4902 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
4903 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
4904 // CHECK6-NEXT: entry:
4905 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4906 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4907 // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4908 // CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4909 // CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4910 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4911 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4912 // CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
4913 // CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4914 // CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4915 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4916 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4917 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
4918 // CHECK6-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
4919 // CHECK6-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
4920 // CHECK6-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
4921 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4922 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4923 // CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4924 // CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4925 // CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4926 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4927 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4928 // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4929 // CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
4930 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4931 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4932 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4933 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4934 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4935 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4936 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4937 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4938 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
4939 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4940 // CHECK6: cond.true:
4941 // CHECK6-NEXT: br label [[COND_END:%.*]]
4942 // CHECK6: cond.false:
4943 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4944 // CHECK6-NEXT: br label [[COND_END]]
4945 // CHECK6: cond.end:
4946 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4947 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4948 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4949 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4950 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4951 // CHECK6: omp.inner.for.cond:
4952 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4953 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4954 // CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4955 // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4956 // CHECK6: omp.inner.for.body:
4957 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4958 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
4959 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4960 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
4961 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
4962 // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
4963 // CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
4964 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
4965 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
4966 // CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
4967 // CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
4968 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
4969 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
4970 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
4971 // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
4972 // CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
4973 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
4974 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
4975 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4976 // CHECK6: omp.inner.for.inc:
4977 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4978 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4979 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
4980 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4981 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
4982 // CHECK6: omp.inner.for.end:
4983 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4984 // CHECK6: omp.loop.exit:
4985 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4986 // CHECK6-NEXT: ret void
4987 //
4988 //
4989 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
4990 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
4991 // CHECK6-NEXT: entry:
4992 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4993 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4994 // CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
4995 // CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
4996 // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4997 // CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4998 // CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4999 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8
5000 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5001 // CHECK6-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
5002 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5003 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5004 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5005 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5006 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
5007 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
5008 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5009 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5010 // CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5011 // CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5012 // CHECK6-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
5013 // CHECK6-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
5014 // CHECK6-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5015 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5016 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5017 // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5018 // CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
5019 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5020 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5021 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5022 // CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
5023 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5024 // CHECK6-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
5025 // CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
5026 // CHECK6-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
5027 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5028 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5029 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5030 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5031 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5032 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5033 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
5034 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5035 // CHECK6: cond.true:
5036 // CHECK6-NEXT: br label [[COND_END:%.*]]
5037 // CHECK6: cond.false:
5038 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5039 // CHECK6-NEXT: br label [[COND_END]]
5040 // CHECK6: cond.end:
5041 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5042 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5043 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5044 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
5045 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5046 // CHECK6: omp.inner.for.cond:
5047 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5048 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5049 // CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
5050 // CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5051 // CHECK6: omp.inner.for.body:
5052 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5053 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
5054 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5055 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5056 // CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8
5057 // CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
5058 // CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
5059 // CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8
5060 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
5061 // CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
5062 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
5063 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
5064 // CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
5065 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
5066 // CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
5067 // CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
5068 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5069 // CHECK6: omp.body.continue:
5070 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5071 // CHECK6: omp.inner.for.inc:
5072 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5073 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
5074 // CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
5075 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
5076 // CHECK6: omp.inner.for.end:
5077 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5078 // CHECK6: omp.loop.exit:
5079 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
5080 // CHECK6-NEXT: ret void
5081 //
5082 //
5083 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_parallel_for_firstprivate_codegen.cpp
5084 // CHECK6-SAME: () #[[ATTR0]] {
5085 // CHECK6-NEXT: entry:
5086 // CHECK6-NEXT: call void @__cxx_global_var_init()
5087 // CHECK6-NEXT: call void @__cxx_global_var_init.1()
5088 // CHECK6-NEXT: call void @__cxx_global_var_init.2()
5089 // CHECK6-NEXT: ret void
5090 //
5091 //
5092 // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5093 // CHECK6-SAME: () #[[ATTR0]] {
5094 // CHECK6-NEXT: entry:
5095 // CHECK6-NEXT: call void @__tgt_register_requires(i64 1)
5096 // CHECK6-NEXT: ret void
5097 //
5098 //
5099 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
5100 // CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
5101 // CHECK13-NEXT: entry:
5102 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5103 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5104 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
5105 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
5106 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5107 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
5108 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5109 // CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5110 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5111 // CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5112 // CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
5113 // CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5114 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5115 // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5116 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5117 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
5118 // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5119 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
5120 // CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
5121 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
5122 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
5123 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
5124 // CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5125 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
5126 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5127 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
5128 // CHECK13-NEXT: ret void
5129 //
5130 //
5131 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
5132 // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] {
5133 // CHECK13-NEXT: entry:
5134 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5135 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5136 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5137 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5138 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
5139 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
5140 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5141 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5142 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
5143 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
5144 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
5145 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5146 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5147 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
5148 // CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
5149 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
5150 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
5151 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
5152 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
5153 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
5154 // CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5155 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5156 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5157 // CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5158 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5159 // CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5160 // CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
5161 // CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5162 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5163 // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5164 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5165 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
5166 // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5167 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5168 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5169 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5170 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5171 // CHECK13-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
5172 // CHECK13-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5173 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
5174 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
5175 // CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
5176 // CHECK13-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
5177 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
5178 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5179 // CHECK13: omp.arraycpy.body:
5180 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5181 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5182 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]]
5183 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
5184 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]]
5185 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5186 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5187 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
5188 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
5189 // CHECK13: omp.arraycpy.done4:
5190 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
5191 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
5192 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
5193 // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5194 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
5195 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5196 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5197 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
5198 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5199 // CHECK13: cond.true:
5200 // CHECK13-NEXT: br label [[COND_END:%.*]]
5201 // CHECK13: cond.false:
5202 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5203 // CHECK13-NEXT: br label [[COND_END]]
5204 // CHECK13: cond.end:
5205 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
5206 // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
5207 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5208 // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
5209 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5210 // CHECK13: omp.inner.for.cond:
5211 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5212 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5213 // CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
5214 // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5215 // CHECK13: omp.inner.for.cond.cleanup:
5216 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5217 // CHECK13: omp.inner.for.body:
5218 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5219 // CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
5220 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5221 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
5222 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
5223 // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
5224 // CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
5225 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
5226 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
5227 // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5228 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
5229 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5230 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
5231 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5232 // CHECK13: omp.inner.for.inc:
5233 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5234 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5235 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
5236 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5237 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]
5238 // CHECK13: omp.inner.for.end:
5239 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5240 // CHECK13: omp.loop.exit:
5241 // CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5242 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
5243 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
5244 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
5245 // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
5246 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
5247 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5248 // CHECK13: arraydestroy.body:
5249 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5250 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5251 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
5252 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
5253 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
5254 // CHECK13: arraydestroy.done11:
5255 // CHECK13-NEXT: ret void
5256 //
5257 //
5258 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev
5259 // CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
5260 // CHECK13-NEXT: entry:
5261 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
5262 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
5263 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
5264 // CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
5265 // CHECK13-NEXT: ret void
5266 //
5267 //
5268 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
5269 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5270 // CHECK13-NEXT: entry:
5271 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5272 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
5273 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5274 // CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
5275 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5276 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
5277 // CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
5278 // CHECK13-NEXT: ret void
5279 //
5280 //
5281 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev
5282 // CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5283 // CHECK13-NEXT: entry:
5284 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
5285 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
5286 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
5287 // CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
5288 // CHECK13-NEXT: ret void
5289 //
5290 //
5291 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1
5292 // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] {
5293 // CHECK13-NEXT: entry:
5294 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5295 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5296 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
5297 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
5298 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5299 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5300 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
5301 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
5302 // CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5303 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5304 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
5305 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5306 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5307 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5308 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5309 // CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
5310 // CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
5311 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
5312 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
5313 // CHECK13-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
5314 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
5315 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5316 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5317 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5318 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5319 // CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5320 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5321 // CHECK13-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5322 // CHECK13-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
5323 // CHECK13-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5324 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5325 // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5326 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5327 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
5328 // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5329 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5330 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5331 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5332 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
5333 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5334 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
5335 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
5336 // CHECK13-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
5337 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5338 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5339 // CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
5340 // CHECK13-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5341 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
5342 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
5343 // CHECK13-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
5344 // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
5345 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
5346 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5347 // CHECK13: omp.arraycpy.body:
5348 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5349 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5350 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
5351 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
5352 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
5353 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5354 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5355 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
5356 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
5357 // CHECK13: omp.arraycpy.done6:
5358 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]]
5359 // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]]
5360 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]]
5361 // CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5362 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
5363 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5364 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5365 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
5366 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5367 // CHECK13: cond.true:
5368 // CHECK13-NEXT: br label [[COND_END:%.*]]
5369 // CHECK13: cond.false:
5370 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5371 // CHECK13-NEXT: br label [[COND_END]]
5372 // CHECK13: cond.end:
5373 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
5374 // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5375 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5376 // CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
5377 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5378 // CHECK13: omp.inner.for.cond:
5379 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5380 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5381 // CHECK13-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
5382 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5383 // CHECK13: omp.inner.for.cond.cleanup:
5384 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5385 // CHECK13: omp.inner.for.body:
5386 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5387 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
5388 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5389 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5390 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
5391 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
5392 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
5393 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
5394 // CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
5395 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
5396 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
5397 // CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
5398 // CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
5399 // CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
5400 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
5401 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
5402 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
5403 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
5404 // CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
5405 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5406 // CHECK13: omp.body.continue:
5407 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5408 // CHECK13: omp.inner.for.inc:
5409 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5410 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
5411 // CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
5412 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]
5413 // CHECK13: omp.inner.for.end:
5414 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5415 // CHECK13: omp.loop.exit:
5416 // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5417 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
5418 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
5419 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]]
5420 // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
5421 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
5422 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5423 // CHECK13: arraydestroy.body:
5424 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5425 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5426 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
5427 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
5428 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
5429 // CHECK13: arraydestroy.done15:
5430 // CHECK13-NEXT: ret void
5431 //
5432 //
5433 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5434 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5435 // CHECK13-NEXT: entry:
5436 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5437 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5438 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5439 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
5440 // CHECK13-NEXT: ret void
5441 //
5442 //
5443 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
5444 // CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
5445 // CHECK13-NEXT: entry:
5446 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5447 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5448 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
5449 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
5450 // CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
5451 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
5452 // CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5453 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5454 // CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
5455 // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
5456 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5457 // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5458 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
5459 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
5460 // CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
5461 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
5462 // CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
5463 // CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
5464 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
5465 // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
5466 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
5467 // CHECK13-NEXT: ret void
5468 //
5469 //
5470 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2
5471 // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
5472 // CHECK13-NEXT: entry:
5473 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5474 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5475 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5476 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5477 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
5478 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
5479 // CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
5480 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5481 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
5482 // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
5483 // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
5484 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5485 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5486 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
5487 // CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
5488 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
5489 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
5490 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
5491 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
5492 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
5493 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
5494 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5495 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5496 // CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5497 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5498 // CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
5499 // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
5500 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5501 // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5502 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
5503 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
5504 // CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
5505 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5506 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5507 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5508 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5509 // CHECK13-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
5510 // CHECK13-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5511 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
5512 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
5513 // CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
5514 // CHECK13-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
5515 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
5516 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5517 // CHECK13: omp.arraycpy.body:
5518 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5519 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5520 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
5521 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
5522 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
5523 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5524 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5525 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
5526 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
5527 // CHECK13: omp.arraycpy.done4:
5528 // CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
5529 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
5530 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
5531 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
5532 // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
5533 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5534 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
5535 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5536 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5537 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
5538 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5539 // CHECK13: cond.true:
5540 // CHECK13-NEXT: br label [[COND_END:%.*]]
5541 // CHECK13: cond.false:
5542 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5543 // CHECK13-NEXT: br label [[COND_END]]
5544 // CHECK13: cond.end:
5545 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
5546 // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
5547 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5548 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
5549 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5550 // CHECK13: omp.inner.for.cond:
5551 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5552 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5553 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
5554 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5555 // CHECK13: omp.inner.for.cond.cleanup:
5556 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5557 // CHECK13: omp.inner.for.body:
5558 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5559 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
5560 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5561 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
5562 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
5563 // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
5564 // CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
5565 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
5566 // CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
5567 // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
5568 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5569 // CHECK13: omp.inner.for.inc:
5570 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5571 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5572 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
5573 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5574 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]
5575 // CHECK13: omp.inner.for.end:
5576 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5577 // CHECK13: omp.loop.exit:
5578 // CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5579 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
5580 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
5581 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
5582 // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
5583 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
5584 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5585 // CHECK13: arraydestroy.body:
5586 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5587 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5588 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
5589 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
5590 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
5591 // CHECK13: arraydestroy.done11:
5592 // CHECK13-NEXT: ret void
5593 //
5594 //
5595 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
5596 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5597 // CHECK13-NEXT: entry:
5598 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5599 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
5600 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5601 // CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
5602 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5603 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
5604 // CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
5605 // CHECK13-NEXT: ret void
5606 //
5607 //
5608 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3
5609 // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
5610 // CHECK13-NEXT: entry:
5611 // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5612 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5613 // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
5614 // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
5615 // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5616 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5617 // CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
5618 // CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
5619 // CHECK13-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
5620 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5621 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
5622 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5623 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5624 // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5625 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5626 // CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
5627 // CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
5628 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
5629 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
5630 // CHECK13-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
5631 // CHECK13-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
5632 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
5633 // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5634 // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5635 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5636 // CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5637 // CHECK13-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5638 // CHECK13-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5639 // CHECK13-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
5640 // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
5641 // CHECK13-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5642 // CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5643 // CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
5644 // CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
5645 // CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
5646 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5647 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5648 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5649 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
5650 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5651 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
5652 // CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
5653 // CHECK13-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
5654 // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5655 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5656 // CHECK13-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
5657 // CHECK13-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5658 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
5659 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
5660 // CHECK13-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
5661 // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
5662 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
5663 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5664 // CHECK13: omp.arraycpy.body:
5665 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5666 // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5667 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
5668 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
5669 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
5670 // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5671 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5672 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
5673 // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
5674 // CHECK13: omp.arraycpy.done6:
5675 // CHECK13-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
5676 // CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]]
5677 // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]]
5678 // CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]]
5679 // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
5680 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5681 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
5682 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5683 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5684 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
5685 // CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5686 // CHECK13: cond.true:
5687 // CHECK13-NEXT: br label [[COND_END:%.*]]
5688 // CHECK13: cond.false:
5689 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5690 // CHECK13-NEXT: br label [[COND_END]]
5691 // CHECK13: cond.end:
5692 // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
5693 // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5694 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5695 // CHECK13-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
5696 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5697 // CHECK13: omp.inner.for.cond:
5698 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5699 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5700 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
5701 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5702 // CHECK13: omp.inner.for.cond.cleanup:
5703 // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5704 // CHECK13: omp.inner.for.body:
5705 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5706 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
5707 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5708 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5709 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
5710 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
5711 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
5712 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
5713 // CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
5714 // CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
5715 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
5716 // CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
5717 // CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
5718 // CHECK13-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
5719 // CHECK13-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
5720 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
5721 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5722 // CHECK13: omp.body.continue:
5723 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5724 // CHECK13: omp.inner.for.inc:
5725 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5726 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
5727 // CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
5728 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]
5729 // CHECK13: omp.inner.for.end:
5730 // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5731 // CHECK13: omp.loop.exit:
5732 // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5733 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
5734 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
5735 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]]
5736 // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
5737 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
5738 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5739 // CHECK13: arraydestroy.body:
5740 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5741 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5742 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
5743 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
5744 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
5745 // CHECK13: arraydestroy.done15:
5746 // CHECK13-NEXT: ret void
5747 //
5748 //
5749 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
5750 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5751 // CHECK13-NEXT: entry:
5752 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5753 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5754 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5755 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
5756 // CHECK13-NEXT: ret void
5757 //
5758 //
5759 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev
5760 // CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5761 // CHECK13-NEXT: entry:
5762 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
5763 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
5764 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
5765 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
5766 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4
5767 // CHECK13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
5768 // CHECK13-NEXT: store i32 0, i32* [[B]], align 4
5769 // CHECK13-NEXT: ret void
5770 //
5771 //
5772 // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev
5773 // CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5774 // CHECK13-NEXT: entry:
5775 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
5776 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
5777 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
5778 // CHECK13-NEXT: ret void
5779 //
5780 //
5781 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5782 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5783 // CHECK13-NEXT: entry:
5784 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5785 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5786 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5787 // CHECK13-NEXT: ret void
5788 //
5789 //
5790 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
5791 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5792 // CHECK13-NEXT: entry:
5793 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5794 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
5795 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5796 // CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
5797 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5798 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5799 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
5800 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
5801 // CHECK13-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
5802 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
5803 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
5804 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
5805 // CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
5806 // CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4
5807 // CHECK13-NEXT: ret void
5808 //
5809 //
5810 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
5811 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5812 // CHECK13-NEXT: entry:
5813 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5814 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5815 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5816 // CHECK13-NEXT: ret void
5817 //
5818 //
5819 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
5820 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5821 // CHECK13-NEXT: entry:
5822 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5823 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
5824 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5825 // CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
5826 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5827 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5828 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
5829 // CHECK13-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
5830 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
5831 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
5832 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
5833 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
5834 // CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4
5835 // CHECK13-NEXT: ret void
5836 //
5837 //
5838 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
5839 // CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
5840 // CHECK14-NEXT: entry:
5841 // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5842 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5843 // CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
5844 // CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
5845 // CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5846 // CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
5847 // CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5848 // CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5849 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5850 // CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5851 // CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
5852 // CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5853 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5854 // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5855 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5856 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
5857 // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5858 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
5859 // CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
5860 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
5861 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
5862 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
5863 // CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5864 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
5865 // CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5866 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
5867 // CHECK14-NEXT: ret void
5868 //
5869 //
5870 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
5871 // CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] {
5872 // CHECK14-NEXT: entry:
5873 // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5874 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5875 // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
5876 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
5877 // CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
5878 // CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
5879 // CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5880 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5881 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
5882 // CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
5883 // CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
5884 // CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5885 // CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5886 // CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
5887 // CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
5888 // CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
5889 // CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
5890 // CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
5891 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
5892 // CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
5893 // CHECK14-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5894 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5895 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5896 // CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
5897 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
5898 // CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5899 // CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
5900 // CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5901 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
5902 // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
5903 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
5904 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
5905 // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5906 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5907 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5908 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5909 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5910 // CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
5911 // CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5912 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
5913 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
5914 // CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
5915 // CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
5916 // CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
5917 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5918 // CHECK14: omp.arraycpy.body:
5919 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5920 // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5921 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]]
5922 // CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
5923 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]]
5924 // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5925 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5926 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
5927 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
5928 // CHECK14: omp.arraycpy.done4:
5929 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
5930 // CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
5931 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
5932 // CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5933 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
5934 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5935 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5936 // CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
5937 // CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5938 // CHECK14: cond.true:
5939 // CHECK14-NEXT: br label [[COND_END:%.*]]
5940 // CHECK14: cond.false:
5941 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5942 // CHECK14-NEXT: br label [[COND_END]]
5943 // CHECK14: cond.end:
5944 // CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
5945 // CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
5946 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5947 // CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
5948 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5949 // CHECK14: omp.inner.for.cond:
5950 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5951 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5952 // CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
5953 // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5954 // CHECK14: omp.inner.for.cond.cleanup:
5955 // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5956 // CHECK14: omp.inner.for.body:
5957 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5958 // CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
5959 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5960 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
5961 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
5962 // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
5963 // CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
5964 // CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
5965 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
5966 // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5967 // CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
5968 // CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5969 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
5970 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5971 // CHECK14: omp.inner.for.inc:
5972 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5973 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5974 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
5975 // CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5976 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]]
5977 // CHECK14: omp.inner.for.end:
5978 // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5979 // CHECK14: omp.loop.exit:
5980 // CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5981 // CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
5982 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
5983 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
5984 // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
5985 // CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
5986 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5987 // CHECK14: arraydestroy.body:
5988 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5989 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5990 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
5991 // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
5992 // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
5993 // CHECK14: arraydestroy.done11:
5994 // CHECK14-NEXT: ret void
5995 //
5996 //
5997 // CHECK14-LABEL: define {{[^@]+}}@_ZN2StC1Ev
5998 // CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
5999 // CHECK14-NEXT: entry:
6000 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
6001 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
6002 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
6003 // CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
6004 // CHECK14-NEXT: ret void
6005 //
6006 //
6007 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
6008 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6009 // CHECK14-NEXT: entry:
6010 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6011 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
6012 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6013 // CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
6014 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6015 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
6016 // CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
6017 // CHECK14-NEXT: ret void
6018 //
6019 //
6020 // CHECK14-LABEL: define {{[^@]+}}@_ZN2StD1Ev
6021 // CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6022 // CHECK14-NEXT: entry:
6023 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
6024 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
6025 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
6026 // CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
6027 // CHECK14-NEXT: ret void
6028 //
6029 //
6030 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1
6031 // CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] {
6032 // CHECK14-NEXT: entry:
6033 // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6034 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6035 // CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
6036 // CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
6037 // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
6038 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
6039 // CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
6040 // CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
6041 // CHECK14-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
6042 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6043 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
6044 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6045 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6046 // CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6047 // CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6048 // CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
6049 // CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
6050 // CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
6051 // CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
6052 // CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
6053 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
6054 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6055 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6056 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6057 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6058 // CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
6059 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
6060 // CHECK14-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
6061 // CHECK14-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
6062 // CHECK14-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
6063 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
6064 // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
6065 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
6066 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
6067 // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
6068 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6069 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
6070 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6071 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
6072 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6073 // CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
6074 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
6075 // CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
6076 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6077 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6078 // CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
6079 // CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
6080 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
6081 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
6082 // CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
6083 // CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
6084 // CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
6085 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
6086 // CHECK14: omp.arraycpy.body:
6087 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6088 // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6089 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
6090 // CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
6091 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
6092 // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
6093 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
6094 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
6095 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
6096 // CHECK14: omp.arraycpy.done6:
6097 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]]
6098 // CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]]
6099 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]]
6100 // CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6101 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6102 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6103 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6104 // CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
6105 // CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6106 // CHECK14: cond.true:
6107 // CHECK14-NEXT: br label [[COND_END:%.*]]
6108 // CHECK14: cond.false:
6109 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6110 // CHECK14-NEXT: br label [[COND_END]]
6111 // CHECK14: cond.end:
6112 // CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6113 // CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6114 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6115 // CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6116 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6117 // CHECK14: omp.inner.for.cond:
6118 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6119 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6120 // CHECK14-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6121 // CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
6122 // CHECK14: omp.inner.for.cond.cleanup:
6123 // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
6124 // CHECK14: omp.inner.for.body:
6125 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6126 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
6127 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6128 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4
6129 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
6130 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
6131 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
6132 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
6133 // CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
6134 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
6135 // CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
6136 // CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
6137 // CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
6138 // CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
6139 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
6140 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
6141 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
6142 // CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
6143 // CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
6144 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6145 // CHECK14: omp.body.continue:
6146 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6147 // CHECK14: omp.inner.for.inc:
6148 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6149 // CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
6150 // CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
6151 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]]
6152 // CHECK14: omp.inner.for.end:
6153 // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6154 // CHECK14: omp.loop.exit:
6155 // CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6156 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
6157 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
6158 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]]
6159 // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
6160 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
6161 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6162 // CHECK14: arraydestroy.body:
6163 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6164 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
6165 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
6166 // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
6167 // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
6168 // CHECK14: arraydestroy.done15:
6169 // CHECK14-NEXT: ret void
6170 //
6171 //
6172 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
6173 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6174 // CHECK14-NEXT: entry:
6175 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6176 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6177 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6178 // CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
6179 // CHECK14-NEXT: ret void
6180 //
6181 //
6182 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
6183 // CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
6184 // CHECK14-NEXT: entry:
6185 // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
6186 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
6187 // CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
6188 // CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
6189 // CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
6190 // CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
6191 // CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
6192 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
6193 // CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
6194 // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
6195 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
6196 // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
6197 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
6198 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
6199 // CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
6200 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
6201 // CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
6202 // CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
6203 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
6204 // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
6205 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
6206 // CHECK14-NEXT: ret void
6207 //
6208 //
6209 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2
6210 // CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
6211 // CHECK14-NEXT: entry:
6212 // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6213 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6214 // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
6215 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
6216 // CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
6217 // CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
6218 // CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
6219 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6220 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
6221 // CHECK14-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
6222 // CHECK14-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
6223 // CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6224 // CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6225 // CHECK14-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
6226 // CHECK14-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
6227 // CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
6228 // CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
6229 // CHECK14-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
6230 // CHECK14-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
6231 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
6232 // CHECK14-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
6233 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6234 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6235 // CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
6236 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
6237 // CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
6238 // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
6239 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
6240 // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
6241 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
6242 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
6243 // CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
6244 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
6245 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
6246 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6247 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6248 // CHECK14-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
6249 // CHECK14-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
6250 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
6251 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
6252 // CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
6253 // CHECK14-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
6254 // CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
6255 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
6256 // CHECK14: omp.arraycpy.body:
6257 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6258 // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6259 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
6260 // CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
6261 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
6262 // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
6263 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
6264 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
6265 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
6266 // CHECK14: omp.arraycpy.done4:
6267 // CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
6268 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
6269 // CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
6270 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
6271 // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
6272 // CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6273 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
6274 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6275 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6276 // CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
6277 // CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6278 // CHECK14: cond.true:
6279 // CHECK14-NEXT: br label [[COND_END:%.*]]
6280 // CHECK14: cond.false:
6281 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6282 // CHECK14-NEXT: br label [[COND_END]]
6283 // CHECK14: cond.end:
6284 // CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
6285 // CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
6286 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6287 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
6288 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6289 // CHECK14: omp.inner.for.cond:
6290 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6291 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6292 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
6293 // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
6294 // CHECK14: omp.inner.for.cond.cleanup:
6295 // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
6296 // CHECK14: omp.inner.for.body:
6297 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6298 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
6299 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6300 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
6301 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
6302 // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
6303 // CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
6304 // CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
6305 // CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
6306 // CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
6307 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6308 // CHECK14: omp.inner.for.inc:
6309 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6310 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6311 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
6312 // CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6313 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]]
6314 // CHECK14: omp.inner.for.end:
6315 // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6316 // CHECK14: omp.loop.exit:
6317 // CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6318 // CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
6319 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
6320 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
6321 // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
6322 // CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
6323 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6324 // CHECK14: arraydestroy.body:
6325 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6326 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
6327 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
6328 // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
6329 // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
6330 // CHECK14: arraydestroy.done11:
6331 // CHECK14-NEXT: ret void
6332 //
6333 //
6334 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
6335 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6336 // CHECK14-NEXT: entry:
6337 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
6338 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
6339 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
6340 // CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
6341 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
6342 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
6343 // CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
6344 // CHECK14-NEXT: ret void
6345 //
6346 //
6347 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3
6348 // CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
6349 // CHECK14-NEXT: entry:
6350 // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6351 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6352 // CHECK14-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
6353 // CHECK14-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
6354 // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
6355 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
6356 // CHECK14-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
6357 // CHECK14-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
6358 // CHECK14-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
6359 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6360 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
6361 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6362 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6363 // CHECK14-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6364 // CHECK14-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6365 // CHECK14-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
6366 // CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
6367 // CHECK14-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
6368 // CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
6369 // CHECK14-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
6370 // CHECK14-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
6371 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
6372 // CHECK14-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6373 // CHECK14-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6374 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6375 // CHECK14-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6376 // CHECK14-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
6377 // CHECK14-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
6378 // CHECK14-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
6379 // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
6380 // CHECK14-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
6381 // CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
6382 // CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
6383 // CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
6384 // CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
6385 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6386 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
6387 // CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6388 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
6389 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6390 // CHECK14-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
6391 // CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
6392 // CHECK14-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
6393 // CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6394 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6395 // CHECK14-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
6396 // CHECK14-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
6397 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
6398 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
6399 // CHECK14-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
6400 // CHECK14-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
6401 // CHECK14-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
6402 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
6403 // CHECK14: omp.arraycpy.body:
6404 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6405 // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6406 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
6407 // CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
6408 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
6409 // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
6410 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
6411 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
6412 // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
6413 // CHECK14: omp.arraycpy.done6:
6414 // CHECK14-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
6415 // CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]]
6416 // CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]]
6417 // CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]]
6418 // CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
6419 // CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6420 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
6421 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6422 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6423 // CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
6424 // CHECK14-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6425 // CHECK14: cond.true:
6426 // CHECK14-NEXT: br label [[COND_END:%.*]]
6427 // CHECK14: cond.false:
6428 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6429 // CHECK14-NEXT: br label [[COND_END]]
6430 // CHECK14: cond.end:
6431 // CHECK14-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
6432 // CHECK14-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6433 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6434 // CHECK14-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
6435 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6436 // CHECK14: omp.inner.for.cond:
6437 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6438 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6439 // CHECK14-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
6440 // CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
6441 // CHECK14: omp.inner.for.cond.cleanup:
6442 // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
6443 // CHECK14: omp.inner.for.body:
6444 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6445 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
6446 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6447 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4
6448 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
6449 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
6450 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
6451 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
6452 // CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
6453 // CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
6454 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
6455 // CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
6456 // CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
6457 // CHECK14-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
6458 // CHECK14-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
6459 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
6460 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6461 // CHECK14: omp.body.continue:
6462 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6463 // CHECK14: omp.inner.for.inc:
6464 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6465 // CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
6466 // CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
6467 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]]
6468 // CHECK14: omp.inner.for.end:
6469 // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6470 // CHECK14: omp.loop.exit:
6471 // CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6472 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
6473 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
6474 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]]
6475 // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
6476 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
6477 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6478 // CHECK14: arraydestroy.body:
6479 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6480 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
6481 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
6482 // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
6483 // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
6484 // CHECK14: arraydestroy.done15:
6485 // CHECK14-NEXT: ret void
6486 //
6487 //
6488 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
6489 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6490 // CHECK14-NEXT: entry:
6491 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
6492 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
6493 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
6494 // CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
6495 // CHECK14-NEXT: ret void
6496 //
6497 //
6498 // CHECK14-LABEL: define {{[^@]+}}@_ZN2StC2Ev
6499 // CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6500 // CHECK14-NEXT: entry:
6501 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
6502 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
6503 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
6504 // CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
6505 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4
6506 // CHECK14-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
6507 // CHECK14-NEXT: store i32 0, i32* [[B]], align 4
6508 // CHECK14-NEXT: ret void
6509 //
6510 //
6511 // CHECK14-LABEL: define {{[^@]+}}@_ZN2StD2Ev
6512 // CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6513 // CHECK14-NEXT: entry:
6514 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
6515 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
6516 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
6517 // CHECK14-NEXT: ret void
6518 //
6519 //
6520 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
6521 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6522 // CHECK14-NEXT: entry:
6523 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6524 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6525 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6526 // CHECK14-NEXT: ret void
6527 //
6528 //
6529 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
6530 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6531 // CHECK14-NEXT: entry:
6532 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6533 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
6534 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6535 // CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
6536 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6537 // CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6538 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
6539 // CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
6540 // CHECK14-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
6541 // CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
6542 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6543 // CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
6544 // CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
6545 // CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4
6546 // CHECK14-NEXT: ret void
6547 //
6548 //
6549 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
6550 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6551 // CHECK14-NEXT: entry:
6552 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
6553 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
6554 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
6555 // CHECK14-NEXT: ret void
6556 //
6557 //
6558 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
6559 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6560 // CHECK14-NEXT: entry:
6561 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
6562 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
6563 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
6564 // CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
6565 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
6566 // CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
6567 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
6568 // CHECK14-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
6569 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
6570 // CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
6571 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6572 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
6573 // CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4
6574 // CHECK14-NEXT: ret void
6575 //
6576 //
6577 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
6578 // CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
6579 // CHECK15-NEXT: entry:
6580 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
6581 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
6582 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
6583 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
6584 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
6585 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
6586 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
6587 // CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
6588 // CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
6589 // CHECK15-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
6590 // CHECK15-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
6591 // CHECK15-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
6592 // CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
6593 // CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
6594 // CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
6595 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
6596 // CHECK15-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
6597 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
6598 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
6599 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
6600 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
6601 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
6602 // CHECK15-NEXT: ret void
6603 //
6604 //
6605 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined.
6606 // CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] {
6607 // CHECK15-NEXT: entry:
6608 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6609 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6610 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
6611 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
6612 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
6613 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
6614 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
6615 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6616 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
6617 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
6618 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
6619 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6620 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6621 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
6622 // CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
6623 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
6624 // CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
6625 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
6626 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
6627 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
6628 // CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
6629 // CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6630 // CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6631 // CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
6632 // CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
6633 // CHECK15-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
6634 // CHECK15-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
6635 // CHECK15-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
6636 // CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
6637 // CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
6638 // CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
6639 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
6640 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
6641 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6642 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6643 // CHECK15-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
6644 // CHECK15-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
6645 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
6646 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
6647 // CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
6648 // CHECK15-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
6649 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
6650 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
6651 // CHECK15: omp.arraycpy.body:
6652 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6653 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6654 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]]
6655 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
6656 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]]
6657 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
6658 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
6659 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
6660 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
6661 // CHECK15: omp.arraycpy.done3:
6662 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
6663 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]]
6664 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]]
6665 // CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6666 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
6667 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6668 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6669 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
6670 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6671 // CHECK15: cond.true:
6672 // CHECK15-NEXT: br label [[COND_END:%.*]]
6673 // CHECK15: cond.false:
6674 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6675 // CHECK15-NEXT: br label [[COND_END]]
6676 // CHECK15: cond.end:
6677 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
6678 // CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
6679 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6680 // CHECK15-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
6681 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6682 // CHECK15: omp.inner.for.cond:
6683 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6684 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6685 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
6686 // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
6687 // CHECK15: omp.inner.for.cond.cleanup:
6688 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
6689 // CHECK15: omp.inner.for.body:
6690 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6691 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6692 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
6693 // CHECK15-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
6694 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
6695 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
6696 // CHECK15-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
6697 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
6698 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
6699 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6700 // CHECK15: omp.inner.for.inc:
6701 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6702 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6703 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
6704 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6705 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]]
6706 // CHECK15: omp.inner.for.end:
6707 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6708 // CHECK15: omp.loop.exit:
6709 // CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6710 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
6711 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
6712 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]]
6713 // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
6714 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
6715 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6716 // CHECK15: arraydestroy.body:
6717 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6718 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
6719 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
6720 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
6721 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
6722 // CHECK15: arraydestroy.done8:
6723 // CHECK15-NEXT: ret void
6724 //
6725 //
6726 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev
6727 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
6728 // CHECK15-NEXT: entry:
6729 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
6730 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
6731 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
6732 // CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
6733 // CHECK15-NEXT: ret void
6734 //
6735 //
6736 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
6737 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6738 // CHECK15-NEXT: entry:
6739 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
6740 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
6741 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
6742 // CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
6743 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
6744 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
6745 // CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
6746 // CHECK15-NEXT: ret void
6747 //
6748 //
6749 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev
6750 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6751 // CHECK15-NEXT: entry:
6752 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
6753 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
6754 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
6755 // CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
6756 // CHECK15-NEXT: ret void
6757 //
6758 //
6759 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1
6760 // CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] {
6761 // CHECK15-NEXT: entry:
6762 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6763 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6764 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
6765 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
6766 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
6767 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
6768 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
6769 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
6770 // CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
6771 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6772 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
6773 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6774 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6775 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6776 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6777 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
6778 // CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
6779 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
6780 // CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
6781 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
6782 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
6783 // CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6784 // CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6785 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
6786 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
6787 // CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
6788 // CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
6789 // CHECK15-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
6790 // CHECK15-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
6791 // CHECK15-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
6792 // CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
6793 // CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
6794 // CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
6795 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6796 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
6797 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
6798 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
6799 // CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
6800 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
6801 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6802 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6803 // CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
6804 // CHECK15-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
6805 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
6806 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
6807 // CHECK15-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
6808 // CHECK15-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
6809 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
6810 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
6811 // CHECK15: omp.arraycpy.body:
6812 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6813 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6814 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
6815 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
6816 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
6817 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
6818 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
6819 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
6820 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
6821 // CHECK15: omp.arraycpy.done3:
6822 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
6823 // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]]
6824 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]]
6825 // CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6826 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6827 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6828 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6829 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
6830 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6831 // CHECK15: cond.true:
6832 // CHECK15-NEXT: br label [[COND_END:%.*]]
6833 // CHECK15: cond.false:
6834 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6835 // CHECK15-NEXT: br label [[COND_END]]
6836 // CHECK15: cond.end:
6837 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6838 // CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6839 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6840 // CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6841 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6842 // CHECK15: omp.inner.for.cond:
6843 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6844 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6845 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6846 // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
6847 // CHECK15: omp.inner.for.cond.cleanup:
6848 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
6849 // CHECK15: omp.inner.for.body:
6850 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6851 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
6852 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6853 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4
6854 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
6855 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
6856 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
6857 // CHECK15-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
6858 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
6859 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
6860 // CHECK15-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
6861 // CHECK15-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
6862 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
6863 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
6864 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
6865 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
6866 // CHECK15-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
6867 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6868 // CHECK15: omp.body.continue:
6869 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6870 // CHECK15: omp.inner.for.inc:
6871 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6872 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
6873 // CHECK15-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
6874 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]]
6875 // CHECK15: omp.inner.for.end:
6876 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6877 // CHECK15: omp.loop.exit:
6878 // CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6879 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
6880 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
6881 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]]
6882 // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
6883 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
6884 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6885 // CHECK15: arraydestroy.body:
6886 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6887 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
6888 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
6889 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
6890 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
6891 // CHECK15: arraydestroy.done11:
6892 // CHECK15-NEXT: ret void
6893 //
6894 //
6895 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
6896 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
6897 // CHECK15-NEXT: entry:
6898 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
6899 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
6900 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
6901 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
6902 // CHECK15-NEXT: ret void
6903 //
6904 //
6905 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
6906 // CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
6907 // CHECK15-NEXT: entry:
6908 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
6909 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
6910 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
6911 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
6912 // CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
6913 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
6914 // CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
6915 // CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
6916 // CHECK15-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
6917 // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
6918 // CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
6919 // CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
6920 // CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
6921 // CHECK15-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
6922 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
6923 // CHECK15-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
6924 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
6925 // CHECK15-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
6926 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
6927 // CHECK15-NEXT: ret void
6928 //
6929 //
6930 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2
6931 // CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
6932 // CHECK15-NEXT: entry:
6933 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6934 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6935 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
6936 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
6937 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
6938 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
6939 // CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
6940 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6941 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
6942 // CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
6943 // CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
6944 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6945 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6946 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
6947 // CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
6948 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
6949 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
6950 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
6951 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
6952 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
6953 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
6954 // CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6955 // CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6956 // CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
6957 // CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
6958 // CHECK15-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
6959 // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
6960 // CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
6961 // CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
6962 // CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
6963 // CHECK15-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
6964 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
6965 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
6966 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6967 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6968 // CHECK15-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
6969 // CHECK15-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
6970 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
6971 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
6972 // CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
6973 // CHECK15-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
6974 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
6975 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
6976 // CHECK15: omp.arraycpy.body:
6977 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6978 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
6979 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
6980 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
6981 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
6982 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
6983 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
6984 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
6985 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
6986 // CHECK15: omp.arraycpy.done4:
6987 // CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
6988 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
6989 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
6990 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
6991 // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
6992 // CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6993 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
6994 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6995 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6996 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
6997 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6998 // CHECK15: cond.true:
6999 // CHECK15-NEXT: br label [[COND_END:%.*]]
7000 // CHECK15: cond.false:
7001 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7002 // CHECK15-NEXT: br label [[COND_END]]
7003 // CHECK15: cond.end:
7004 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
7005 // CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
7006 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
7007 // CHECK15-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
7008 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7009 // CHECK15: omp.inner.for.cond:
7010 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7011 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7012 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
7013 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
7014 // CHECK15: omp.inner.for.cond.cleanup:
7015 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
7016 // CHECK15: omp.inner.for.body:
7017 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
7018 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7019 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7020 // CHECK15-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
7021 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
7022 // CHECK15-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
7023 // CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
7024 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7025 // CHECK15: omp.inner.for.inc:
7026 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7027 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7028 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
7029 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
7030 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]]
7031 // CHECK15: omp.inner.for.end:
7032 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7033 // CHECK15: omp.loop.exit:
7034 // CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7035 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
7036 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
7037 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
7038 // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7039 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
7040 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
7041 // CHECK15: arraydestroy.body:
7042 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
7043 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
7044 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
7045 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
7046 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
7047 // CHECK15: arraydestroy.done10:
7048 // CHECK15-NEXT: ret void
7049 //
7050 //
7051 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
7052 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7053 // CHECK15-NEXT: entry:
7054 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7055 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
7056 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7057 // CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
7058 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7059 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
7060 // CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
7061 // CHECK15-NEXT: ret void
7062 //
7063 //
7064 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3
7065 // CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
7066 // CHECK15-NEXT: entry:
7067 // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7068 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7069 // CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
7070 // CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
7071 // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7072 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7073 // CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
7074 // CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
7075 // CHECK15-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
7076 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7077 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
7078 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7079 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7080 // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7081 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7082 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
7083 // CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
7084 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
7085 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
7086 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
7087 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
7088 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
7089 // CHECK15-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7090 // CHECK15-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7091 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
7092 // CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
7093 // CHECK15-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7094 // CHECK15-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7095 // CHECK15-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7096 // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
7097 // CHECK15-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7098 // CHECK15-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7099 // CHECK15-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
7100 // CHECK15-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
7101 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7102 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
7103 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
7104 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
7105 // CHECK15-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
7106 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
7107 // CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7108 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7109 // CHECK15-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
7110 // CHECK15-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
7111 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
7112 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7113 // CHECK15-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
7114 // CHECK15-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
7115 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
7116 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
7117 // CHECK15: omp.arraycpy.body:
7118 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7119 // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7120 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
7121 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
7122 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
7123 // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
7124 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
7125 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
7126 // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
7127 // CHECK15: omp.arraycpy.done4:
7128 // CHECK15-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
7129 // CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
7130 // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
7131 // CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
7132 // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
7133 // CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7134 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
7135 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7136 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7137 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
7138 // CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7139 // CHECK15: cond.true:
7140 // CHECK15-NEXT: br label [[COND_END:%.*]]
7141 // CHECK15: cond.false:
7142 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7143 // CHECK15-NEXT: br label [[COND_END]]
7144 // CHECK15: cond.end:
7145 // CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
7146 // CHECK15-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7147 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7148 // CHECK15-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
7149 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7150 // CHECK15: omp.inner.for.cond:
7151 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7152 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7153 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7154 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
7155 // CHECK15: omp.inner.for.cond.cleanup:
7156 // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
7157 // CHECK15: omp.inner.for.body:
7158 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7159 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
7160 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7161 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4
7162 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7163 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
7164 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
7165 // CHECK15-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
7166 // CHECK15-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
7167 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
7168 // CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
7169 // CHECK15-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
7170 // CHECK15-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
7171 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
7172 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7173 // CHECK15: omp.body.continue:
7174 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7175 // CHECK15: omp.inner.for.inc:
7176 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7177 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
7178 // CHECK15-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
7179 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]]
7180 // CHECK15: omp.inner.for.end:
7181 // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7182 // CHECK15: omp.loop.exit:
7183 // CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7184 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7185 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7186 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
7187 // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7188 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
7189 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
7190 // CHECK15: arraydestroy.body:
7191 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
7192 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
7193 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
7194 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
7195 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
7196 // CHECK15: arraydestroy.done12:
7197 // CHECK15-NEXT: ret void
7198 //
7199 //
7200 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
7201 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7202 // CHECK15-NEXT: entry:
7203 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7204 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7205 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7206 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
7207 // CHECK15-NEXT: ret void
7208 //
7209 //
7210 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev
7211 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7212 // CHECK15-NEXT: entry:
7213 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
7214 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
7215 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
7216 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
7217 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4
7218 // CHECK15-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
7219 // CHECK15-NEXT: store i32 0, i32* [[B]], align 4
7220 // CHECK15-NEXT: ret void
7221 //
7222 //
7223 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev
7224 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7225 // CHECK15-NEXT: entry:
7226 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
7227 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
7228 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
7229 // CHECK15-NEXT: ret void
7230 //
7231 //
7232 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
7233 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7234 // CHECK15-NEXT: entry:
7235 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
7236 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
7237 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
7238 // CHECK15-NEXT: ret void
7239 //
7240 //
7241 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
7242 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7243 // CHECK15-NEXT: entry:
7244 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
7245 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
7246 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
7247 // CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
7248 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
7249 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
7250 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
7251 // CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
7252 // CHECK15-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
7253 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
7254 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7255 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
7256 // CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
7257 // CHECK15-NEXT: store float [[ADD]], float* [[F]], align 4
7258 // CHECK15-NEXT: ret void
7259 //
7260 //
7261 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
7262 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7263 // CHECK15-NEXT: entry:
7264 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7265 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7266 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7267 // CHECK15-NEXT: ret void
7268 //
7269 //
7270 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
7271 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7272 // CHECK15-NEXT: entry:
7273 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7274 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
7275 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7276 // CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
7277 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7278 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
7279 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
7280 // CHECK15-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
7281 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
7282 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
7283 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7284 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
7285 // CHECK15-NEXT: store i32 [[ADD]], i32* [[F]], align 4
7286 // CHECK15-NEXT: ret void
7287 //
7288 //
7289 // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
7290 // CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
7291 // CHECK16-NEXT: entry:
7292 // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7293 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7294 // CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
7295 // CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
7296 // CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
7297 // CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
7298 // CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
7299 // CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7300 // CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7301 // CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
7302 // CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
7303 // CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
7304 // CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7305 // CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
7306 // CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
7307 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7308 // CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
7309 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
7310 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
7311 // CHECK16-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
7312 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
7313 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
7314 // CHECK16-NEXT: ret void
7315 //
7316 //
7317 // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined.
7318 // CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] {
7319 // CHECK16-NEXT: entry:
7320 // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7321 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7322 // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7323 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7324 // CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
7325 // CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
7326 // CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
7327 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7328 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
7329 // CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
7330 // CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
7331 // CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7332 // CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7333 // CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
7334 // CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
7335 // CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
7336 // CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
7337 // CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
7338 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
7339 // CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
7340 // CHECK16-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
7341 // CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7342 // CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7343 // CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7344 // CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7345 // CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
7346 // CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
7347 // CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
7348 // CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7349 // CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
7350 // CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
7351 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
7352 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
7353 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7354 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7355 // CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
7356 // CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
7357 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
7358 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
7359 // CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
7360 // CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
7361 // CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
7362 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
7363 // CHECK16: omp.arraycpy.body:
7364 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7365 // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7366 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]]
7367 // CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
7368 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]]
7369 // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
7370 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
7371 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
7372 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
7373 // CHECK16: omp.arraycpy.done3:
7374 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
7375 // CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]]
7376 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]]
7377 // CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7378 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
7379 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7380 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7381 // CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
7382 // CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7383 // CHECK16: cond.true:
7384 // CHECK16-NEXT: br label [[COND_END:%.*]]
7385 // CHECK16: cond.false:
7386 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7387 // CHECK16-NEXT: br label [[COND_END]]
7388 // CHECK16: cond.end:
7389 // CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
7390 // CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
7391 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
7392 // CHECK16-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
7393 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7394 // CHECK16: omp.inner.for.cond:
7395 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7396 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7397 // CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
7398 // CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
7399 // CHECK16: omp.inner.for.cond.cleanup:
7400 // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
7401 // CHECK16: omp.inner.for.body:
7402 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
7403 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7404 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7405 // CHECK16-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
7406 // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
7407 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
7408 // CHECK16-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
7409 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
7410 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
7411 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7412 // CHECK16: omp.inner.for.inc:
7413 // CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7414 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7415 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
7416 // CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
7417 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]]
7418 // CHECK16: omp.inner.for.end:
7419 // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7420 // CHECK16: omp.loop.exit:
7421 // CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7422 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
7423 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
7424 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]]
7425 // CHECK16-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
7426 // CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
7427 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
7428 // CHECK16: arraydestroy.body:
7429 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
7430 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
7431 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
7432 // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
7433 // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
7434 // CHECK16: arraydestroy.done8:
7435 // CHECK16-NEXT: ret void
7436 //
7437 //
7438 // CHECK16-LABEL: define {{[^@]+}}@_ZN2StC1Ev
7439 // CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
7440 // CHECK16-NEXT: entry:
7441 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
7442 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
7443 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
7444 // CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
7445 // CHECK16-NEXT: ret void
7446 //
7447 //
7448 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
7449 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7450 // CHECK16-NEXT: entry:
7451 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
7452 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
7453 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
7454 // CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
7455 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
7456 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
7457 // CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
7458 // CHECK16-NEXT: ret void
7459 //
7460 //
7461 // CHECK16-LABEL: define {{[^@]+}}@_ZN2StD1Ev
7462 // CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7463 // CHECK16-NEXT: entry:
7464 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
7465 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
7466 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
7467 // CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]]
7468 // CHECK16-NEXT: ret void
7469 //
7470 //
7471 // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1
7472 // CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] {
7473 // CHECK16-NEXT: entry:
7474 // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7475 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7476 // CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
7477 // CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
7478 // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7479 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7480 // CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
7481 // CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
7482 // CHECK16-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
7483 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7484 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
7485 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7486 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7487 // CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7488 // CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7489 // CHECK16-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
7490 // CHECK16-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
7491 // CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
7492 // CHECK16-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
7493 // CHECK16-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
7494 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
7495 // CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7496 // CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7497 // CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
7498 // CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
7499 // CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7500 // CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7501 // CHECK16-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
7502 // CHECK16-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
7503 // CHECK16-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
7504 // CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7505 // CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
7506 // CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
7507 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7508 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
7509 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
7510 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
7511 // CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
7512 // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
7513 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7514 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7515 // CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
7516 // CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
7517 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
7518 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
7519 // CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
7520 // CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
7521 // CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
7522 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
7523 // CHECK16: omp.arraycpy.body:
7524 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7525 // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7526 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
7527 // CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
7528 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
7529 // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
7530 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
7531 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
7532 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
7533 // CHECK16: omp.arraycpy.done3:
7534 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
7535 // CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]]
7536 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]]
7537 // CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7538 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
7539 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7540 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7541 // CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
7542 // CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7543 // CHECK16: cond.true:
7544 // CHECK16-NEXT: br label [[COND_END:%.*]]
7545 // CHECK16: cond.false:
7546 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7547 // CHECK16-NEXT: br label [[COND_END]]
7548 // CHECK16: cond.end:
7549 // CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7550 // CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7551 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7552 // CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
7553 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7554 // CHECK16: omp.inner.for.cond:
7555 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7556 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7557 // CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
7558 // CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
7559 // CHECK16: omp.inner.for.cond.cleanup:
7560 // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
7561 // CHECK16: omp.inner.for.body:
7562 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7563 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
7564 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7565 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4
7566 // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7567 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
7568 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
7569 // CHECK16-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
7570 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
7571 // CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
7572 // CHECK16-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
7573 // CHECK16-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
7574 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
7575 // CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
7576 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
7577 // CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
7578 // CHECK16-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
7579 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7580 // CHECK16: omp.body.continue:
7581 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7582 // CHECK16: omp.inner.for.inc:
7583 // CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7584 // CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
7585 // CHECK16-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
7586 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]]
7587 // CHECK16: omp.inner.for.end:
7588 // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7589 // CHECK16: omp.loop.exit:
7590 // CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7591 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7592 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7593 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]]
7594 // CHECK16-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
7595 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
7596 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
7597 // CHECK16: arraydestroy.body:
7598 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
7599 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
7600 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
7601 // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
7602 // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
7603 // CHECK16: arraydestroy.done11:
7604 // CHECK16-NEXT: ret void
7605 //
7606 //
7607 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
7608 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7609 // CHECK16-NEXT: entry:
7610 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
7611 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
7612 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
7613 // CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
7614 // CHECK16-NEXT: ret void
7615 //
7616 //
7617 // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
7618 // CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
7619 // CHECK16-NEXT: entry:
7620 // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7621 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7622 // CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
7623 // CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
7624 // CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
7625 // CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
7626 // CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7627 // CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7628 // CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7629 // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
7630 // CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7631 // CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7632 // CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
7633 // CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
7634 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7635 // CHECK16-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
7636 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
7637 // CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
7638 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
7639 // CHECK16-NEXT: ret void
7640 //
7641 //
7642 // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2
7643 // CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
7644 // CHECK16-NEXT: entry:
7645 // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7646 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7647 // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7648 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7649 // CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
7650 // CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
7651 // CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
7652 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7653 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
7654 // CHECK16-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
7655 // CHECK16-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
7656 // CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7657 // CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7658 // CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
7659 // CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
7660 // CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
7661 // CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
7662 // CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
7663 // CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
7664 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
7665 // CHECK16-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
7666 // CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7667 // CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7668 // CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7669 // CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7670 // CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7671 // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
7672 // CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7673 // CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7674 // CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
7675 // CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
7676 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
7677 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
7678 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7679 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7680 // CHECK16-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
7681 // CHECK16-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
7682 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
7683 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7684 // CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
7685 // CHECK16-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
7686 // CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
7687 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
7688 // CHECK16: omp.arraycpy.body:
7689 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7690 // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7691 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
7692 // CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
7693 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
7694 // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
7695 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
7696 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
7697 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
7698 // CHECK16: omp.arraycpy.done4:
7699 // CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
7700 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
7701 // CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
7702 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
7703 // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
7704 // CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7705 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
7706 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7707 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7708 // CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
7709 // CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7710 // CHECK16: cond.true:
7711 // CHECK16-NEXT: br label [[COND_END:%.*]]
7712 // CHECK16: cond.false:
7713 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7714 // CHECK16-NEXT: br label [[COND_END]]
7715 // CHECK16: cond.end:
7716 // CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
7717 // CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
7718 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
7719 // CHECK16-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
7720 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7721 // CHECK16: omp.inner.for.cond:
7722 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7723 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7724 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
7725 // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
7726 // CHECK16: omp.inner.for.cond.cleanup:
7727 // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
7728 // CHECK16: omp.inner.for.body:
7729 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
7730 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
7731 // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7732 // CHECK16-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
7733 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
7734 // CHECK16-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
7735 // CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
7736 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7737 // CHECK16: omp.inner.for.inc:
7738 // CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7739 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7740 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
7741 // CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
7742 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]]
7743 // CHECK16: omp.inner.for.end:
7744 // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7745 // CHECK16: omp.loop.exit:
7746 // CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7747 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
7748 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
7749 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
7750 // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7751 // CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
7752 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
7753 // CHECK16: arraydestroy.body:
7754 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
7755 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
7756 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
7757 // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
7758 // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
7759 // CHECK16: arraydestroy.done10:
7760 // CHECK16-NEXT: ret void
7761 //
7762 //
7763 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
7764 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7765 // CHECK16-NEXT: entry:
7766 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7767 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
7768 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7769 // CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
7770 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7771 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
7772 // CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]]
7773 // CHECK16-NEXT: ret void
7774 //
7775 //
7776 // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3
7777 // CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] {
7778 // CHECK16-NEXT: entry:
7779 // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7780 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7781 // CHECK16-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
7782 // CHECK16-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
7783 // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
7784 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
7785 // CHECK16-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
7786 // CHECK16-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
7787 // CHECK16-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
7788 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7789 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
7790 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7791 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7792 // CHECK16-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7793 // CHECK16-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7794 // CHECK16-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
7795 // CHECK16-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
7796 // CHECK16-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
7797 // CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
7798 // CHECK16-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
7799 // CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
7800 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
7801 // CHECK16-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7802 // CHECK16-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7803 // CHECK16-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
7804 // CHECK16-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
7805 // CHECK16-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
7806 // CHECK16-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
7807 // CHECK16-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7808 // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
7809 // CHECK16-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
7810 // CHECK16-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
7811 // CHECK16-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
7812 // CHECK16-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
7813 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7814 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
7815 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
7816 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
7817 // CHECK16-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
7818 // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
7819 // CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7820 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7821 // CHECK16-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
7822 // CHECK16-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
7823 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
7824 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7825 // CHECK16-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
7826 // CHECK16-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
7827 // CHECK16-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
7828 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
7829 // CHECK16: omp.arraycpy.body:
7830 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7831 // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
7832 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
7833 // CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]]
7834 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]]
7835 // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
7836 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
7837 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
7838 // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
7839 // CHECK16: omp.arraycpy.done4:
7840 // CHECK16-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
7841 // CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
7842 // CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]]
7843 // CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]]
7844 // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
7845 // CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7846 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
7847 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7848 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7849 // CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
7850 // CHECK16-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7851 // CHECK16: cond.true:
7852 // CHECK16-NEXT: br label [[COND_END:%.*]]
7853 // CHECK16: cond.false:
7854 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7855 // CHECK16-NEXT: br label [[COND_END]]
7856 // CHECK16: cond.end:
7857 // CHECK16-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
7858 // CHECK16-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7859 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7860 // CHECK16-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
7861 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7862 // CHECK16: omp.inner.for.cond:
7863 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7864 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7865 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7866 // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
7867 // CHECK16: omp.inner.for.cond.cleanup:
7868 // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
7869 // CHECK16: omp.inner.for.body:
7870 // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7871 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
7872 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7873 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4
7874 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
7875 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
7876 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
7877 // CHECK16-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
7878 // CHECK16-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
7879 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
7880 // CHECK16-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
7881 // CHECK16-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
7882 // CHECK16-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
7883 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
7884 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7885 // CHECK16: omp.body.continue:
7886 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7887 // CHECK16: omp.inner.for.inc:
7888 // CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7889 // CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
7890 // CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
7891 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]]
7892 // CHECK16: omp.inner.for.end:
7893 // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7894 // CHECK16: omp.loop.exit:
7895 // CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7896 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7897 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7898 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]]
7899 // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
7900 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
7901 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
7902 // CHECK16: arraydestroy.body:
7903 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
7904 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
7905 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
7906 // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
7907 // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
7908 // CHECK16: arraydestroy.done12:
7909 // CHECK16-NEXT: ret void
7910 //
7911 //
7912 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
7913 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7914 // CHECK16-NEXT: entry:
7915 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7916 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7917 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7918 // CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
7919 // CHECK16-NEXT: ret void
7920 //
7921 //
7922 // CHECK16-LABEL: define {{[^@]+}}@_ZN2StC2Ev
7923 // CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7924 // CHECK16-NEXT: entry:
7925 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
7926 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
7927 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
7928 // CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
7929 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4
7930 // CHECK16-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
7931 // CHECK16-NEXT: store i32 0, i32* [[B]], align 4
7932 // CHECK16-NEXT: ret void
7933 //
7934 //
7935 // CHECK16-LABEL: define {{[^@]+}}@_ZN2StD2Ev
7936 // CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7937 // CHECK16-NEXT: entry:
7938 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
7939 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
7940 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
7941 // CHECK16-NEXT: ret void
7942 //
7943 //
7944 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
7945 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7946 // CHECK16-NEXT: entry:
7947 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
7948 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
7949 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
7950 // CHECK16-NEXT: ret void
7951 //
7952 //
7953 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
7954 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7955 // CHECK16-NEXT: entry:
7956 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
7957 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
7958 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
7959 // CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
7960 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
7961 // CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
7962 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
7963 // CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
7964 // CHECK16-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
7965 // CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
7966 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7967 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
7968 // CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
7969 // CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4
7970 // CHECK16-NEXT: ret void
7971 //
7972 //
7973 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
7974 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7975 // CHECK16-NEXT: entry:
7976 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7977 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7978 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7979 // CHECK16-NEXT: ret void
7980 //
7981 //
7982 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
7983 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
7984 // CHECK16-NEXT: entry:
7985 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
7986 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
7987 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
7988 // CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
7989 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
7990 // CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
7991 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
7992 // CHECK16-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
7993 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
7994 // CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
7995 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7996 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
7997 // CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4
7998 // CHECK16-NEXT: ret void
7999 //
8000 //
8001 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
8002 // CHECK17-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] {
8003 // CHECK17-NEXT: entry:
8004 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
8005 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
8006 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
8007 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32*, align 8
8008 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
8009 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
8010 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
8011 // CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
8012 // CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
8013 // CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
8014 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
8015 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
8016 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
8017 // CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
8018 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8019 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
8020 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
8021 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
8022 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
8023 // CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
8024 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
8025 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
8026 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
8027 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
8028 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
8029 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
8030 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
8031 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
8032 // CHECK17-NEXT: ret void
8033 //
8034 //
8035 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
8036 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] {
8037 // CHECK17-NEXT: entry:
8038 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8039 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8040 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
8041 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
8042 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
8043 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32*, align 8
8044 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8045 // CHECK17-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
8046 // CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
8047 // CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
8048 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8049 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8050 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
8051 // CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
8052 // CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
8053 // CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
8054 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8055 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8056 // CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
8057 // CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
8058 // CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
8059 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
8060 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
8061 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
8062 // CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
8063 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
8064 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
8065 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8066 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8067 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8068 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8069 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8070 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
8071 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
8072 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8073 // CHECK17: cond.true:
8074 // CHECK17-NEXT: br label [[COND_END:%.*]]
8075 // CHECK17: cond.false:
8076 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
8077 // CHECK17-NEXT: br label [[COND_END]]
8078 // CHECK17: cond.end:
8079 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8080 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
8081 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
8082 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8083 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8084 // CHECK17: omp.inner.for.cond:
8085 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8086 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
8087 // CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8088 // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8089 // CHECK17: omp.inner.for.body:
8090 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
8091 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
8092 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
8093 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
8094 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
8095 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
8096 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
8097 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
8098 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
8099 // CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
8100 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
8101 // CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
8102 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
8103 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
8104 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
8105 // CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
8106 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
8107 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
8108 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8109 // CHECK17: omp.inner.for.inc:
8110 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8111 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8112 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
8113 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
8114 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
8115 // CHECK17: omp.inner.for.end:
8116 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
8117 // CHECK17: omp.loop.exit:
8118 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8119 // CHECK17-NEXT: ret void
8120 //
8121 //
8122 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
8123 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] {
8124 // CHECK17-NEXT: entry:
8125 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8126 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8127 // CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
8128 // CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
8129 // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
8130 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
8131 // CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
8132 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32*, align 8
8133 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8134 // CHECK17-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
8135 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8136 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8137 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8138 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8139 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
8140 // CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
8141 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8142 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8143 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
8144 // CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
8145 // CHECK17-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
8146 // CHECK17-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
8147 // CHECK17-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
8148 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
8149 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
8150 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
8151 // CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
8152 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8153 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
8154 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
8155 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
8156 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
8157 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
8158 // CHECK17-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
8159 // CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
8160 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8161 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8162 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8163 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
8164 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8165 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8166 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
8167 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8168 // CHECK17: cond.true:
8169 // CHECK17-NEXT: br label [[COND_END:%.*]]
8170 // CHECK17: cond.false:
8171 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8172 // CHECK17-NEXT: br label [[COND_END]]
8173 // CHECK17: cond.end:
8174 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
8175 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8176 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8177 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
8178 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8179 // CHECK17: omp.inner.for.cond:
8180 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8181 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8182 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
8183 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8184 // CHECK17: omp.inner.for.body:
8185 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8186 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
8187 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8188 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
8189 // CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8
8190 // CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
8191 // CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
8192 // CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8
8193 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
8194 // CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
8195 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
8196 // CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
8197 // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
8198 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2
8199 // CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
8200 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
8201 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8202 // CHECK17: omp.body.continue:
8203 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8204 // CHECK17: omp.inner.for.inc:
8205 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8206 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
8207 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
8208 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
8209 // CHECK17: omp.inner.for.end:
8210 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
8211 // CHECK17: omp.loop.exit:
8212 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
8213 // CHECK17-NEXT: ret void
8214 //
8215 //