1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // expected-no-diagnostics
3 #ifndef HEADER
4 #define HEADER
5
6 // Test host codegen.
7 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
10 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
13
14 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
17 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8
20 #ifdef CK1
21
22 template <typename T, int X, long long Y>
23 struct SS{
24 T a[X][Y];
25
fooSS26 int foo(void) {
27
28 #pragma omp target teams distribute parallel for simd collapse(2)
29 for(int i = 0; i < X; i++) {
30 for(int j = 0; j < Y; j++) {
31 a[i][j] = (T)0;
32 }
33 }
34
35 // discard loop variables not needed here
36
37
38 return a[0][0];
39 }
40 };
41
teams_template_struct(void)42 int teams_template_struct(void) {
43 SS<int, 123, 456> V;
44 return V.foo();
45
46 }
47 #endif // CK1
48
49 // Test host codegen.
50 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
51 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
52 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
53 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
54 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
55 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
56
57 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13
58 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
59 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14
60 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15
61 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
62 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16
63 #ifdef CK2
64
65 template <typename T, int n, int m>
tmain(T argc)66 int tmain(T argc) {
67 T a[n][m];
68 #pragma omp target teams distribute parallel for simd collapse(2)
69 for(int i = 0; i < n; i++) {
70 for(int j = 0; j < m; j++) {
71 a[i][j] = (T)0;
72 }
73 }
74 return 0;
75 }
76
main(int argc,char ** argv)77 int main (int argc, char **argv) {
78 int n = 100;
79 int m = 2;
80 int a[n][m];
81 #pragma omp target teams distribute parallel for simd collapse(2)
82 for(int i = 0; i < n; i++) {
83 for(int j = 0; j < m; j++) {
84 a[i][j] = 0;
85 }
86 }
87 return tmain<int, 10, 2>(argc);
88 }
89
90
91
92
93
94
95
96
97 // discard loop variables not needed here
98
99
100 #endif // CK2
101 #endif // #ifndef HEADER
102 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv
103 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
104 // CHECK1-NEXT: entry:
105 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
106 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
107 // CHECK1-NEXT: ret i32 [[CALL]]
108 //
109 //
110 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
111 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
112 // CHECK1-NEXT: entry:
113 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
114 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
115 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
116 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
117 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
118 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
119 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
120 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
121 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
122 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
123 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
124 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8
125 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
126 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
127 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8
128 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
129 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8
130 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
131 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
132 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 56088)
133 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
134 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
135 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
136 // CHECK1: omp_offload.failed:
137 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
138 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
139 // CHECK1: omp_offload.cont:
140 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
141 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0
142 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0
143 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
144 // CHECK1-NEXT: ret i32 [[TMP9]]
145 //
146 //
147 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
148 // CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
149 // CHECK1-NEXT: entry:
150 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
151 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
152 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
153 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
154 // CHECK1-NEXT: ret void
155 //
156 //
157 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
158 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
159 // CHECK1-NEXT: entry:
160 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
161 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
162 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
163 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
164 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
165 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
166 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
167 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
168 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
169 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
170 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
171 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
172 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
173 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
174 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
175 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
176 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
177 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_COMB_UB]], align 4
178 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
179 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
180 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
181 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
182 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
183 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
184 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
185 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
186 // CHECK1: cond.true:
187 // CHECK1-NEXT: br label [[COND_END:%.*]]
188 // CHECK1: cond.false:
189 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
190 // CHECK1-NEXT: br label [[COND_END]]
191 // CHECK1: cond.end:
192 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
193 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
194 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
195 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
196 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
197 // CHECK1: omp.inner.for.cond:
198 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
199 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
200 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
201 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
202 // CHECK1: omp.inner.for.body:
203 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
204 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
205 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
206 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
207 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]])
208 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
209 // CHECK1: omp.inner.for.inc:
210 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
211 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
212 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
213 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
214 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
215 // CHECK1: omp.inner.for.end:
216 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
217 // CHECK1: omp.loop.exit:
218 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
219 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
220 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
221 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
222 // CHECK1: .omp.final.then:
223 // CHECK1-NEXT: store i32 123, i32* [[I]], align 4
224 // CHECK1-NEXT: store i32 456, i32* [[J]], align 4
225 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
226 // CHECK1: .omp.final.done:
227 // CHECK1-NEXT: ret void
228 //
229 //
230 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
231 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
232 // CHECK1-NEXT: entry:
233 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
234 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
235 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
236 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
237 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
238 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
241 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
242 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
243 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
245 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
246 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
247 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
248 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
249 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
250 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
251 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
252 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
253 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
254 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
255 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
256 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
257 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
258 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
259 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
260 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
261 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
262 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
263 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
264 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
265 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
266 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
267 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087
268 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
269 // CHECK1: cond.true:
270 // CHECK1-NEXT: br label [[COND_END:%.*]]
271 // CHECK1: cond.false:
272 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
273 // CHECK1-NEXT: br label [[COND_END]]
274 // CHECK1: cond.end:
275 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
276 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
277 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
278 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
279 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
280 // CHECK1: omp.inner.for.cond:
281 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
282 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
283 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
284 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
285 // CHECK1: omp.inner.for.body:
286 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
287 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
288 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
289 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
290 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
291 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
292 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
293 // CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456
294 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456
295 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
296 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
297 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
298 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4
299 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
300 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
301 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
302 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
303 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
304 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
305 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
306 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4
307 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
308 // CHECK1: omp.body.continue:
309 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
310 // CHECK1: omp.inner.for.inc:
311 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
312 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
313 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
314 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
315 // CHECK1: omp.inner.for.end:
316 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
317 // CHECK1: omp.loop.exit:
318 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
319 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
320 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
321 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
322 // CHECK1: .omp.final.then:
323 // CHECK1-NEXT: store i32 123, i32* [[I]], align 4
324 // CHECK1-NEXT: store i32 456, i32* [[J]], align 4
325 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
326 // CHECK1: .omp.final.done:
327 // CHECK1-NEXT: ret void
328 //
329 //
330 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
331 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
332 // CHECK1-NEXT: entry:
333 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
334 // CHECK1-NEXT: ret void
335 //
336 //
337 // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv
338 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
339 // CHECK2-NEXT: entry:
340 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
341 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
342 // CHECK2-NEXT: ret i32 [[CALL]]
343 //
344 //
345 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
346 // CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
347 // CHECK2-NEXT: entry:
348 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
349 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
350 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
351 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
352 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
353 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
354 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
355 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
356 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
357 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
358 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
359 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8
360 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
361 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
362 // CHECK2-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8
363 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
364 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8
365 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
366 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
367 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 56088)
368 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
369 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
370 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
371 // CHECK2: omp_offload.failed:
372 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
373 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
374 // CHECK2: omp_offload.cont:
375 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
376 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0
377 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0
378 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
379 // CHECK2-NEXT: ret i32 [[TMP9]]
380 //
381 //
382 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
383 // CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
384 // CHECK2-NEXT: entry:
385 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
386 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
387 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
388 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
389 // CHECK2-NEXT: ret void
390 //
391 //
392 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
393 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
394 // CHECK2-NEXT: entry:
395 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
396 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
397 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
398 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
399 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
400 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
401 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
402 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
403 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
404 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
405 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
406 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
407 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
408 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
409 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
410 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
411 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
412 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_COMB_UB]], align 4
413 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
414 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
415 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
416 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
417 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
418 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
419 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
420 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
421 // CHECK2: cond.true:
422 // CHECK2-NEXT: br label [[COND_END:%.*]]
423 // CHECK2: cond.false:
424 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
425 // CHECK2-NEXT: br label [[COND_END]]
426 // CHECK2: cond.end:
427 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
428 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
429 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
430 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
431 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
432 // CHECK2: omp.inner.for.cond:
433 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
434 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
435 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
436 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
437 // CHECK2: omp.inner.for.body:
438 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
439 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
440 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
441 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
442 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]])
443 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
444 // CHECK2: omp.inner.for.inc:
445 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
446 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
447 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
448 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
449 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
450 // CHECK2: omp.inner.for.end:
451 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
452 // CHECK2: omp.loop.exit:
453 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
454 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
455 // CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
456 // CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
457 // CHECK2: .omp.final.then:
458 // CHECK2-NEXT: store i32 123, i32* [[I]], align 4
459 // CHECK2-NEXT: store i32 456, i32* [[J]], align 4
460 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
461 // CHECK2: .omp.final.done:
462 // CHECK2-NEXT: ret void
463 //
464 //
465 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
466 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
467 // CHECK2-NEXT: entry:
468 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
469 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
470 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
471 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
472 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
473 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
474 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
475 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
476 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
477 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
478 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
479 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
480 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
481 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
482 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
483 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
484 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
485 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
486 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
487 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
488 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
489 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
490 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
491 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
492 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
493 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
494 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
495 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
496 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
497 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
498 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
499 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
500 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
501 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
502 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087
503 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
504 // CHECK2: cond.true:
505 // CHECK2-NEXT: br label [[COND_END:%.*]]
506 // CHECK2: cond.false:
507 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
508 // CHECK2-NEXT: br label [[COND_END]]
509 // CHECK2: cond.end:
510 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
511 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
512 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
513 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
514 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
515 // CHECK2: omp.inner.for.cond:
516 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
517 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
518 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
519 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
520 // CHECK2: omp.inner.for.body:
521 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
522 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
523 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
524 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
525 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
526 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
527 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
528 // CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456
529 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456
530 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
531 // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
532 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
533 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4
534 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
535 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
536 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
537 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
538 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
539 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
540 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
541 // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4
542 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
543 // CHECK2: omp.body.continue:
544 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
545 // CHECK2: omp.inner.for.inc:
546 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
547 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
548 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
549 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
550 // CHECK2: omp.inner.for.end:
551 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
552 // CHECK2: omp.loop.exit:
553 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
554 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
555 // CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
556 // CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
557 // CHECK2: .omp.final.then:
558 // CHECK2-NEXT: store i32 123, i32* [[I]], align 4
559 // CHECK2-NEXT: store i32 456, i32* [[J]], align 4
560 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
561 // CHECK2: .omp.final.done:
562 // CHECK2-NEXT: ret void
563 //
564 //
565 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
566 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
567 // CHECK2-NEXT: entry:
568 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
569 // CHECK2-NEXT: ret void
570 //
571 //
572 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv
573 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
574 // CHECK3-NEXT: entry:
575 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
576 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
577 // CHECK3-NEXT: ret i32 [[CALL]]
578 //
579 //
580 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
581 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
582 // CHECK3-NEXT: entry:
583 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
584 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
585 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
586 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
587 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
588 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
589 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
590 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
591 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
592 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
593 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
594 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4
595 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
596 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
597 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4
598 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
599 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4
600 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
601 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
602 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 56088)
603 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
604 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
605 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
606 // CHECK3: omp_offload.failed:
607 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
608 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
609 // CHECK3: omp_offload.cont:
610 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
611 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0
612 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0
613 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
614 // CHECK3-NEXT: ret i32 [[TMP9]]
615 //
616 //
617 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
618 // CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
619 // CHECK3-NEXT: entry:
620 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
621 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
622 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
623 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
624 // CHECK3-NEXT: ret void
625 //
626 //
627 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
628 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
629 // CHECK3-NEXT: entry:
630 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
631 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
632 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
633 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
634 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
635 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
636 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
637 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
638 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
639 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
640 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
641 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4
642 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
643 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
644 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
645 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
646 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
647 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_COMB_UB]], align 4
648 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
649 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
650 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
651 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
652 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
653 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
654 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
655 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
656 // CHECK3: cond.true:
657 // CHECK3-NEXT: br label [[COND_END:%.*]]
658 // CHECK3: cond.false:
659 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
660 // CHECK3-NEXT: br label [[COND_END]]
661 // CHECK3: cond.end:
662 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
663 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
664 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
665 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
666 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
667 // CHECK3: omp.inner.for.cond:
668 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
669 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
670 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
671 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
672 // CHECK3: omp.inner.for.body:
673 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
674 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
675 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]])
676 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
677 // CHECK3: omp.inner.for.inc:
678 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
679 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
680 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
681 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
682 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
683 // CHECK3: omp.inner.for.end:
684 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
685 // CHECK3: omp.loop.exit:
686 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
687 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
688 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
689 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
690 // CHECK3: .omp.final.then:
691 // CHECK3-NEXT: store i32 123, i32* [[I]], align 4
692 // CHECK3-NEXT: store i32 456, i32* [[J]], align 4
693 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
694 // CHECK3: .omp.final.done:
695 // CHECK3-NEXT: ret void
696 //
697 //
698 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
699 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
700 // CHECK3-NEXT: entry:
701 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
702 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
703 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
704 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
705 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
706 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
707 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
708 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
709 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
710 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
711 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
712 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
713 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
714 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4
715 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
716 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
717 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
718 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
719 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
720 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
721 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
722 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
723 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
724 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
725 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
726 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
727 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
728 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
729 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
730 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
731 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
732 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
733 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087
734 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
735 // CHECK3: cond.true:
736 // CHECK3-NEXT: br label [[COND_END:%.*]]
737 // CHECK3: cond.false:
738 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
739 // CHECK3-NEXT: br label [[COND_END]]
740 // CHECK3: cond.end:
741 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
742 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
743 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
744 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
745 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
746 // CHECK3: omp.inner.for.cond:
747 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
748 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
749 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
750 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
751 // CHECK3: omp.inner.for.body:
752 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
753 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
754 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
755 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
756 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
757 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
758 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
759 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456
760 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
761 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
762 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
763 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
764 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
765 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
766 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
767 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]]
768 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
769 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]]
770 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
771 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
772 // CHECK3: omp.body.continue:
773 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
774 // CHECK3: omp.inner.for.inc:
775 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
776 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
777 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
778 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
779 // CHECK3: omp.inner.for.end:
780 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
781 // CHECK3: omp.loop.exit:
782 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
783 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
784 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
785 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
786 // CHECK3: .omp.final.then:
787 // CHECK3-NEXT: store i32 123, i32* [[I]], align 4
788 // CHECK3-NEXT: store i32 456, i32* [[J]], align 4
789 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
790 // CHECK3: .omp.final.done:
791 // CHECK3-NEXT: ret void
792 //
793 //
794 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
795 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
796 // CHECK3-NEXT: entry:
797 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
798 // CHECK3-NEXT: ret void
799 //
800 //
801 // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv
802 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
803 // CHECK4-NEXT: entry:
804 // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
805 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
806 // CHECK4-NEXT: ret i32 [[CALL]]
807 //
808 //
809 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
810 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
811 // CHECK4-NEXT: entry:
812 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
813 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
814 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
815 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
816 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
817 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
818 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
819 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
820 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
821 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
822 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
823 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4
824 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
825 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
826 // CHECK4-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4
827 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
828 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4
829 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
830 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
831 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 56088)
832 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
833 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
834 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
835 // CHECK4: omp_offload.failed:
836 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
837 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
838 // CHECK4: omp_offload.cont:
839 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
840 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0
841 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0
842 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
843 // CHECK4-NEXT: ret i32 [[TMP9]]
844 //
845 //
846 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
847 // CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
848 // CHECK4-NEXT: entry:
849 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
850 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
851 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
852 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
853 // CHECK4-NEXT: ret void
854 //
855 //
856 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
857 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
858 // CHECK4-NEXT: entry:
859 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
860 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
861 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
862 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
863 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
864 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
865 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
866 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
867 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
868 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
869 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
870 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4
871 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
872 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
873 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
874 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
875 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
876 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_COMB_UB]], align 4
877 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
878 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
879 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
880 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
881 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
882 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
883 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
884 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
885 // CHECK4: cond.true:
886 // CHECK4-NEXT: br label [[COND_END:%.*]]
887 // CHECK4: cond.false:
888 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
889 // CHECK4-NEXT: br label [[COND_END]]
890 // CHECK4: cond.end:
891 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
892 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
893 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
894 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
895 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
896 // CHECK4: omp.inner.for.cond:
897 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
898 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
899 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
900 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
901 // CHECK4: omp.inner.for.body:
902 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
903 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
904 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]])
905 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
906 // CHECK4: omp.inner.for.inc:
907 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
908 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
909 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
910 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
911 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
912 // CHECK4: omp.inner.for.end:
913 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
914 // CHECK4: omp.loop.exit:
915 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
916 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
917 // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
918 // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
919 // CHECK4: .omp.final.then:
920 // CHECK4-NEXT: store i32 123, i32* [[I]], align 4
921 // CHECK4-NEXT: store i32 456, i32* [[J]], align 4
922 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
923 // CHECK4: .omp.final.done:
924 // CHECK4-NEXT: ret void
925 //
926 //
927 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
928 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
929 // CHECK4-NEXT: entry:
930 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
931 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
932 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
933 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
934 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
935 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
936 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
937 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
938 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
939 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
940 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
941 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
942 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
943 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4
944 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
945 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
946 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
947 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
948 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
949 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
950 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
951 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
952 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
953 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
954 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
955 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
956 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
957 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
958 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
959 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
960 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
961 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
962 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087
963 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
964 // CHECK4: cond.true:
965 // CHECK4-NEXT: br label [[COND_END:%.*]]
966 // CHECK4: cond.false:
967 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
968 // CHECK4-NEXT: br label [[COND_END]]
969 // CHECK4: cond.end:
970 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
971 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
972 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
973 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
974 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
975 // CHECK4: omp.inner.for.cond:
976 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
977 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
978 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
979 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
980 // CHECK4: omp.inner.for.body:
981 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
982 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456
983 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
984 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
985 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
986 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
987 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
988 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456
989 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
990 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
991 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
992 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
993 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
994 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
995 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
996 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]]
997 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
998 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]]
999 // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
1000 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1001 // CHECK4: omp.body.continue:
1002 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1003 // CHECK4: omp.inner.for.inc:
1004 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1005 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
1006 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
1007 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1008 // CHECK4: omp.inner.for.end:
1009 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1010 // CHECK4: omp.loop.exit:
1011 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1012 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1013 // CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1014 // CHECK4-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1015 // CHECK4: .omp.final.then:
1016 // CHECK4-NEXT: store i32 123, i32* [[I]], align 4
1017 // CHECK4-NEXT: store i32 456, i32* [[J]], align 4
1018 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
1019 // CHECK4: .omp.final.done:
1020 // CHECK4-NEXT: ret void
1021 //
1022 //
1023 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1024 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
1025 // CHECK4-NEXT: entry:
1026 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
1027 // CHECK4-NEXT: ret void
1028 //
1029 //
1030 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv
1031 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1032 // CHECK5-NEXT: entry:
1033 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
1034 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
1035 // CHECK5-NEXT: ret i32 [[CALL]]
1036 //
1037 //
1038 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
1039 // CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
1040 // CHECK5-NEXT: entry:
1041 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
1042 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1043 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1044 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1045 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1046 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1047 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1048 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4
1049 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
1050 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
1051 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1052 // CHECK5-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
1053 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1054 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1055 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1056 // CHECK5: omp.inner.for.cond:
1057 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1058 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1059 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1060 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1061 // CHECK5: omp.inner.for.body:
1062 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1063 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
1064 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1065 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1066 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1067 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1068 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1069 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
1070 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
1071 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
1072 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1073 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1074 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2
1075 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
1076 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1077 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1078 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
1079 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2
1080 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
1081 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
1082 // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2
1083 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1084 // CHECK5: omp.body.continue:
1085 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1086 // CHECK5: omp.inner.for.inc:
1087 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1088 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
1089 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1090 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1091 // CHECK5: omp.inner.for.end:
1092 // CHECK5-NEXT: store i32 123, i32* [[I]], align 4
1093 // CHECK5-NEXT: store i32 456, i32* [[J]], align 4
1094 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
1095 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0
1096 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0
1097 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4
1098 // CHECK5-NEXT: ret i32 [[TMP9]]
1099 //
1100 //
1101 // CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv
1102 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
1103 // CHECK6-NEXT: entry:
1104 // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
1105 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
1106 // CHECK6-NEXT: ret i32 [[CALL]]
1107 //
1108 //
1109 // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
1110 // CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
1111 // CHECK6-NEXT: entry:
1112 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
1113 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
1114 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1115 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1116 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1117 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1118 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
1119 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4
1120 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
1121 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
1122 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1123 // CHECK6-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
1124 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1125 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1126 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1127 // CHECK6: omp.inner.for.cond:
1128 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1129 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
1130 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1131 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1132 // CHECK6: omp.inner.for.body:
1133 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1134 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
1135 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1136 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1137 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
1138 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1139 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1140 // CHECK6-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
1141 // CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
1142 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
1143 // CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1144 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1145 // CHECK6-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2
1146 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
1147 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
1148 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1149 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
1150 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2
1151 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
1152 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
1153 // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2
1154 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1155 // CHECK6: omp.body.continue:
1156 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1157 // CHECK6: omp.inner.for.inc:
1158 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1159 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
1160 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
1161 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1162 // CHECK6: omp.inner.for.end:
1163 // CHECK6-NEXT: store i32 123, i32* [[I]], align 4
1164 // CHECK6-NEXT: store i32 456, i32* [[J]], align 4
1165 // CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
1166 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0
1167 // CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0
1168 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4
1169 // CHECK6-NEXT: ret i32 [[TMP9]]
1170 //
1171 //
1172 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv
1173 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1174 // CHECK7-NEXT: entry:
1175 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
1176 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
1177 // CHECK7-NEXT: ret i32 [[CALL]]
1178 //
1179 //
1180 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
1181 // CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
1182 // CHECK7-NEXT: entry:
1183 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1184 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1185 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1186 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1187 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1188 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1189 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1190 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4
1191 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1192 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1193 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1194 // CHECK7-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
1195 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1196 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1197 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1198 // CHECK7: omp.inner.for.cond:
1199 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1200 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
1201 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1202 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1203 // CHECK7: omp.inner.for.body:
1204 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1205 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
1206 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1207 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1208 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
1209 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1210 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1211 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
1212 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
1213 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
1214 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1215 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1216 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3
1217 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
1218 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1219 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]]
1220 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3
1221 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]]
1222 // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3
1223 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1224 // CHECK7: omp.body.continue:
1225 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1226 // CHECK7: omp.inner.for.inc:
1227 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1228 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
1229 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1230 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1231 // CHECK7: omp.inner.for.end:
1232 // CHECK7-NEXT: store i32 123, i32* [[I]], align 4
1233 // CHECK7-NEXT: store i32 456, i32* [[J]], align 4
1234 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
1235 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0
1236 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0
1237 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4
1238 // CHECK7-NEXT: ret i32 [[TMP9]]
1239 //
1240 //
1241 // CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv
1242 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
1243 // CHECK8-NEXT: entry:
1244 // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
1245 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
1246 // CHECK8-NEXT: ret i32 [[CALL]]
1247 //
1248 //
1249 // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
1250 // CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
1251 // CHECK8-NEXT: entry:
1252 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
1253 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
1254 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1255 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1256 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1257 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1258 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
1259 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4
1260 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
1261 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
1262 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1263 // CHECK8-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
1264 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1265 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
1266 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1267 // CHECK8: omp.inner.for.cond:
1268 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1269 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
1270 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1271 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1272 // CHECK8: omp.inner.for.body:
1273 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1274 // CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
1275 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1276 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1277 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
1278 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1279 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1280 // CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
1281 // CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
1282 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
1283 // CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1284 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1285 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3
1286 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
1287 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
1288 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]]
1289 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3
1290 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]]
1291 // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3
1292 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1293 // CHECK8: omp.body.continue:
1294 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1295 // CHECK8: omp.inner.for.inc:
1296 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1297 // CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
1298 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
1299 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1300 // CHECK8: omp.inner.for.end:
1301 // CHECK8-NEXT: store i32 123, i32* [[I]], align 4
1302 // CHECK8-NEXT: store i32 456, i32* [[J]], align 4
1303 // CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
1304 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0
1305 // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0
1306 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4
1307 // CHECK8-NEXT: ret i32 [[TMP9]]
1308 //
1309 //
1310 // CHECK9-LABEL: define {{[^@]+}}@main
1311 // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1312 // CHECK9-NEXT: entry:
1313 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1314 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1315 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
1316 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
1317 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4
1318 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
1319 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1320 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1321 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
1322 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
1323 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1324 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1325 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1326 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1327 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1328 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1329 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1330 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
1331 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
1332 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
1333 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1334 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
1335 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4
1336 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4
1337 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
1338 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1339 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4
1340 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
1341 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
1342 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
1343 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
1344 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
1345 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
1346 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
1347 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4
1348 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1349 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
1350 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
1351 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4
1352 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32*
1353 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4
1354 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8
1355 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
1356 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4
1357 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1358 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1359 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8
1360 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1361 // CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1362 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8
1363 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1364 // CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8
1365 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1366 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8
1367 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1368 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1369 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8
1370 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1371 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
1372 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8
1373 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1374 // CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8
1375 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1376 // CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8
1377 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1378 // CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1379 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8
1380 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1381 // CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1382 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8
1383 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1384 // CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8
1385 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1386 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8
1387 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1388 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1389 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8
1390 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1391 // CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
1392 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8
1393 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1394 // CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8
1395 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1396 // CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8
1397 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1398 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32**
1399 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8
1400 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1401 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32**
1402 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8
1403 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1404 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8
1405 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1406 // CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8
1407 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1408 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1409 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1410 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4
1411 // CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4
1412 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4
1413 // CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4
1414 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1415 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0
1416 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1417 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64
1418 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1419 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0
1420 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
1421 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
1422 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]]
1423 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
1424 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8
1425 // CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8
1426 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1
1427 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]])
1428 // CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1429 // CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
1430 // CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1431 // CHECK9: omp_offload.failed:
1432 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
1433 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
1434 // CHECK9: omp_offload.cont:
1435 // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1436 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]])
1437 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
1438 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1439 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]])
1440 // CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4
1441 // CHECK9-NEXT: ret i32 [[TMP54]]
1442 //
1443 //
1444 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
1445 // CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
1446 // CHECK9-NEXT: entry:
1447 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
1448 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
1449 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1450 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1451 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
1452 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
1453 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
1454 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
1455 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
1456 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1457 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1458 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
1459 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1460 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
1461 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1462 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1463 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
1464 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1465 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1466 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
1467 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
1468 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
1469 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
1470 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
1471 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
1472 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
1473 // CHECK9-NEXT: ret void
1474 //
1475 //
1476 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
1477 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
1478 // CHECK9-NEXT: entry:
1479 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1480 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1481 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
1482 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
1483 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1484 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1485 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
1486 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1487 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1488 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
1489 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1490 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1491 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8
1492 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1493 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
1494 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
1495 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
1496 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1497 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1498 // CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4
1499 // CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4
1500 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
1501 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
1502 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1503 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1504 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
1505 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
1506 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1507 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1508 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
1509 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1510 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
1511 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1512 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1513 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
1514 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1515 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
1516 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
1517 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1518 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1519 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
1520 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1521 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
1522 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1523 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
1524 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
1525 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64
1526 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]]
1527 // CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1
1528 // CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8
1529 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
1530 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4
1531 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1532 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
1533 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1534 // CHECK9: land.lhs.true:
1535 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1536 // CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]]
1537 // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1538 // CHECK9: omp.precond.then:
1539 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8
1540 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
1541 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8
1542 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1543 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1544 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1545 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
1546 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1547 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
1548 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
1549 // CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
1550 // CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1551 // CHECK9: cond.true:
1552 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
1553 // CHECK9-NEXT: br label [[COND_END:%.*]]
1554 // CHECK9: cond.false:
1555 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
1556 // CHECK9-NEXT: br label [[COND_END]]
1557 // CHECK9: cond.end:
1558 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
1559 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
1560 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
1561 // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
1562 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1563 // CHECK9: omp.inner.for.cond:
1564 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1565 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
1566 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
1567 // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1568 // CHECK9: omp.inner.for.body:
1569 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
1570 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
1571 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
1572 // CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1573 // CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4
1574 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
1575 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8
1576 // CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
1577 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4
1578 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8
1579 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
1580 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1581 // CHECK9: omp.inner.for.inc:
1582 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1583 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8
1584 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
1585 // CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8
1586 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1587 // CHECK9: omp.inner.for.end:
1588 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1589 // CHECK9: omp.loop.exit:
1590 // CHECK9-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1591 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4
1592 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]])
1593 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1594 // CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1595 // CHECK9-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1596 // CHECK9: .omp.final.then:
1597 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1598 // CHECK9-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP31]], 0
1599 // CHECK9-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1600 // CHECK9-NEXT: [[MUL21:%.*]] = mul nsw i32 [[DIV20]], 1
1601 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]]
1602 // CHECK9-NEXT: store i32 [[ADD22]], i32* [[I13]], align 4
1603 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1604 // CHECK9-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP32]], 0
1605 // CHECK9-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1
1606 // CHECK9-NEXT: [[MUL25:%.*]] = mul nsw i32 [[DIV24]], 1
1607 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]]
1608 // CHECK9-NEXT: store i32 [[ADD26]], i32* [[J14]], align 4
1609 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
1610 // CHECK9: .omp.final.done:
1611 // CHECK9-NEXT: br label [[OMP_PRECOND_END]]
1612 // CHECK9: omp.precond.end:
1613 // CHECK9-NEXT: ret void
1614 //
1615 //
1616 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
1617 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
1618 // CHECK9-NEXT: entry:
1619 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1620 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1621 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1622 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1623 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
1624 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
1625 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1626 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1627 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
1628 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1629 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1630 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
1631 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1632 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1633 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8
1634 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1635 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
1636 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1637 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1638 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1639 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1640 // CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4
1641 // CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4
1642 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1643 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1644 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1645 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1646 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
1647 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
1648 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1649 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1650 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
1651 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1652 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
1653 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1654 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1655 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
1656 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1657 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
1658 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
1659 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1660 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1661 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
1662 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1663 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
1664 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1665 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
1666 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
1667 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64
1668 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]]
1669 // CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1
1670 // CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8
1671 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
1672 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4
1673 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1674 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
1675 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1676 // CHECK9: land.lhs.true:
1677 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1678 // CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]]
1679 // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1680 // CHECK9: omp.precond.then:
1681 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
1682 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
1683 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8
1684 // CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1685 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1686 // CHECK9-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_LB]], align 8
1687 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8
1688 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1689 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1690 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1691 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
1692 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1693 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1694 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
1695 // CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
1696 // CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1697 // CHECK9: cond.true:
1698 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
1699 // CHECK9-NEXT: br label [[COND_END:%.*]]
1700 // CHECK9: cond.false:
1701 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1702 // CHECK9-NEXT: br label [[COND_END]]
1703 // CHECK9: cond.end:
1704 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
1705 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1706 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1707 // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
1708 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1709 // CHECK9: omp.inner.for.cond:
1710 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1711 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1712 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
1713 // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1714 // CHECK9: omp.inner.for.body:
1715 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1716 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1717 // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0
1718 // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1
1719 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]
1720 // CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64
1721 // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]]
1722 // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1
1723 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]
1724 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32
1725 // CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4
1726 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1727 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1728 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1729 // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0
1730 // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1731 // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1732 // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1733 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]]
1734 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1735 // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0
1736 // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1
1737 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]
1738 // CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64
1739 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]
1740 // CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]]
1741 // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1
1742 // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
1743 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
1744 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4
1745 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4
1746 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
1747 // CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]]
1748 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]]
1749 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4
1750 // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64
1751 // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]]
1752 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4
1753 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1754 // CHECK9: omp.body.continue:
1755 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1756 // CHECK9: omp.inner.for.inc:
1757 // CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1758 // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1
1759 // CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8
1760 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1761 // CHECK9: omp.inner.for.end:
1762 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1763 // CHECK9: omp.loop.exit:
1764 // CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1765 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
1766 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
1767 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1768 // CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1769 // CHECK9-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1770 // CHECK9: .omp.final.then:
1771 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1772 // CHECK9-NEXT: [[SUB41:%.*]] = sub nsw i32 [[TMP35]], 0
1773 // CHECK9-NEXT: [[DIV42:%.*]] = sdiv i32 [[SUB41]], 1
1774 // CHECK9-NEXT: [[MUL43:%.*]] = mul nsw i32 [[DIV42]], 1
1775 // CHECK9-NEXT: [[ADD44:%.*]] = add nsw i32 0, [[MUL43]]
1776 // CHECK9-NEXT: store i32 [[ADD44]], i32* [[I13]], align 4
1777 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1778 // CHECK9-NEXT: [[SUB45:%.*]] = sub nsw i32 [[TMP36]], 0
1779 // CHECK9-NEXT: [[DIV46:%.*]] = sdiv i32 [[SUB45]], 1
1780 // CHECK9-NEXT: [[MUL47:%.*]] = mul nsw i32 [[DIV46]], 1
1781 // CHECK9-NEXT: [[ADD48:%.*]] = add nsw i32 0, [[MUL47]]
1782 // CHECK9-NEXT: store i32 [[ADD48]], i32* [[J14]], align 4
1783 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
1784 // CHECK9: .omp.final.done:
1785 // CHECK9-NEXT: br label [[OMP_PRECOND_END]]
1786 // CHECK9: omp.precond.end:
1787 // CHECK9-NEXT: ret void
1788 //
1789 //
1790 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1791 // CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
1792 // CHECK9-NEXT: entry:
1793 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1794 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1795 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1796 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1797 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1798 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1799 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1800 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1801 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1802 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
1803 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8
1804 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1805 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
1806 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8
1807 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1808 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8
1809 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1810 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1811 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20)
1812 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1813 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
1814 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1815 // CHECK9: omp_offload.failed:
1816 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
1817 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
1818 // CHECK9: omp_offload.cont:
1819 // CHECK9-NEXT: ret i32 0
1820 //
1821 //
1822 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
1823 // CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1824 // CHECK9-NEXT: entry:
1825 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1826 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1827 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1828 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
1829 // CHECK9-NEXT: ret void
1830 //
1831 //
1832 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
1833 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1834 // CHECK9-NEXT: entry:
1835 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1836 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1837 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1838 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1839 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1840 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1841 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1842 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1843 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1844 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1845 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1846 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
1847 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1848 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1849 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1850 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1851 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1852 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4
1853 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1854 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1855 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1856 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1857 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1858 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1859 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1860 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1861 // CHECK9: cond.true:
1862 // CHECK9-NEXT: br label [[COND_END:%.*]]
1863 // CHECK9: cond.false:
1864 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1865 // CHECK9-NEXT: br label [[COND_END]]
1866 // CHECK9: cond.end:
1867 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1868 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1869 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1870 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1871 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1872 // CHECK9: omp.inner.for.cond:
1873 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1874 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1875 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1876 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1877 // CHECK9: omp.inner.for.body:
1878 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1879 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
1880 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1881 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
1882 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]])
1883 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1884 // CHECK9: omp.inner.for.inc:
1885 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1886 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1887 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
1888 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1889 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
1890 // CHECK9: omp.inner.for.end:
1891 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1892 // CHECK9: omp.loop.exit:
1893 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1894 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1895 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1896 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1897 // CHECK9: .omp.final.then:
1898 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4
1899 // CHECK9-NEXT: store i32 2, i32* [[J]], align 4
1900 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
1901 // CHECK9: .omp.final.done:
1902 // CHECK9-NEXT: ret void
1903 //
1904 //
1905 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
1906 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1907 // CHECK9-NEXT: entry:
1908 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1909 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1910 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1911 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1912 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1913 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1914 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1915 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1916 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1917 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1918 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1919 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1920 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1921 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
1922 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1923 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1924 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1925 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1926 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1927 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1928 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1929 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
1930 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1931 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
1932 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1933 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
1934 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1935 // CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
1936 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1937 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1938 // CHECK9-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1939 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1940 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1941 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1942 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19
1943 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1944 // CHECK9: cond.true:
1945 // CHECK9-NEXT: br label [[COND_END:%.*]]
1946 // CHECK9: cond.false:
1947 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1948 // CHECK9-NEXT: br label [[COND_END]]
1949 // CHECK9: cond.end:
1950 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1951 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1952 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1953 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
1954 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1955 // CHECK9: omp.inner.for.cond:
1956 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1957 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1958 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1959 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1960 // CHECK9: omp.inner.for.body:
1961 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1962 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
1963 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1964 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1965 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1966 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1967 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1968 // CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2
1969 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2
1970 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
1971 // CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
1972 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
1973 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4
1974 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1975 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
1976 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
1977 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
1978 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
1979 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
1980 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4
1981 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1982 // CHECK9: omp.body.continue:
1983 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1984 // CHECK9: omp.inner.for.inc:
1985 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1986 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
1987 // CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
1988 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1989 // CHECK9: omp.inner.for.end:
1990 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1991 // CHECK9: omp.loop.exit:
1992 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1993 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1994 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1995 // CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1996 // CHECK9: .omp.final.then:
1997 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4
1998 // CHECK9-NEXT: store i32 2, i32* [[J]], align 4
1999 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
2000 // CHECK9: .omp.final.done:
2001 // CHECK9-NEXT: ret void
2002 //
2003 //
2004 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2005 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
2006 // CHECK9-NEXT: entry:
2007 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
2008 // CHECK9-NEXT: ret void
2009 //
2010 //
2011 // CHECK10-LABEL: define {{[^@]+}}@main
2012 // CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
2013 // CHECK10-NEXT: entry:
2014 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2015 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
2016 // CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
2017 // CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
2018 // CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4
2019 // CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
2020 // CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2021 // CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2022 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
2023 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
2024 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
2025 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
2026 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
2027 // CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
2028 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2029 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
2030 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2031 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2032 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
2033 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
2034 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
2035 // CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
2036 // CHECK10-NEXT: store i32 100, i32* [[N]], align 4
2037 // CHECK10-NEXT: store i32 2, i32* [[M]], align 4
2038 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
2039 // CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2040 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4
2041 // CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
2042 // CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
2043 // CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
2044 // CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
2045 // CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
2046 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
2047 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
2048 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4
2049 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
2050 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
2051 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
2052 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4
2053 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32*
2054 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4
2055 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8
2056 // CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
2057 // CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4
2058 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2059 // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2060 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8
2061 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2062 // CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
2063 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8
2064 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2065 // CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8
2066 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2067 // CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8
2068 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2069 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
2070 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8
2071 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2072 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
2073 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8
2074 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2075 // CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8
2076 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2077 // CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8
2078 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2079 // CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
2080 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8
2081 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2082 // CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
2083 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8
2084 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2085 // CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8
2086 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2087 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8
2088 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2089 // CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
2090 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8
2091 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2092 // CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
2093 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8
2094 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2095 // CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8
2096 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2097 // CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8
2098 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2099 // CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32**
2100 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8
2101 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2102 // CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32**
2103 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8
2104 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2105 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8
2106 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
2107 // CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8
2108 // CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2109 // CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2110 // CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2111 // CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4
2112 // CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4
2113 // CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4
2114 // CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4
2115 // CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2116 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0
2117 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2118 // CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64
2119 // CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
2120 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0
2121 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
2122 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
2123 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]]
2124 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
2125 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8
2126 // CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8
2127 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1
2128 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]])
2129 // CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2130 // CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
2131 // CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2132 // CHECK10: omp_offload.failed:
2133 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
2134 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
2135 // CHECK10: omp_offload.cont:
2136 // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
2137 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]])
2138 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
2139 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2140 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]])
2141 // CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4
2142 // CHECK10-NEXT: ret i32 [[TMP54]]
2143 //
2144 //
2145 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
2146 // CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
2147 // CHECK10-NEXT: entry:
2148 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
2149 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
2150 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2151 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2152 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
2153 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
2154 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
2155 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
2156 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
2157 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2158 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2159 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
2160 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
2161 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
2162 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2163 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2164 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
2165 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
2166 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
2167 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
2168 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
2169 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
2170 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
2171 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
2172 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
2173 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
2174 // CHECK10-NEXT: ret void
2175 //
2176 //
2177 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
2178 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
2179 // CHECK10-NEXT: entry:
2180 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2181 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2182 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
2183 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
2184 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2185 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2186 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
2187 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
2188 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2189 // CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
2190 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2191 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
2192 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8
2193 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
2194 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4
2195 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
2196 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
2197 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2198 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2199 // CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4
2200 // CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4
2201 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
2202 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
2203 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2204 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2205 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
2206 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
2207 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2208 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2209 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
2210 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
2211 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
2212 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2213 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2214 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
2215 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
2216 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
2217 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
2218 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
2219 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2220 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
2221 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2222 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
2223 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2224 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
2225 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
2226 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64
2227 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]]
2228 // CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1
2229 // CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8
2230 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
2231 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4
2232 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2233 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
2234 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2235 // CHECK10: land.lhs.true:
2236 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2237 // CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]]
2238 // CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2239 // CHECK10: omp.precond.then:
2240 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8
2241 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
2242 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8
2243 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2244 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2245 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2246 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2247 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2248 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2249 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
2250 // CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
2251 // CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2252 // CHECK10: cond.true:
2253 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
2254 // CHECK10-NEXT: br label [[COND_END:%.*]]
2255 // CHECK10: cond.false:
2256 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2257 // CHECK10-NEXT: br label [[COND_END]]
2258 // CHECK10: cond.end:
2259 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
2260 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
2261 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
2262 // CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
2263 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2264 // CHECK10: omp.inner.for.cond:
2265 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2266 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2267 // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
2268 // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2269 // CHECK10: omp.inner.for.body:
2270 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
2271 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2272 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
2273 // CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
2274 // CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4
2275 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
2276 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8
2277 // CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
2278 // CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4
2279 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8
2280 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
2281 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2282 // CHECK10: omp.inner.for.inc:
2283 // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2284 // CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8
2285 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
2286 // CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8
2287 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2288 // CHECK10: omp.inner.for.end:
2289 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2290 // CHECK10: omp.loop.exit:
2291 // CHECK10-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2292 // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4
2293 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]])
2294 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2295 // CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2296 // CHECK10-NEXT: br i1 [[TMP30]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2297 // CHECK10: .omp.final.then:
2298 // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2299 // CHECK10-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP31]], 0
2300 // CHECK10-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
2301 // CHECK10-NEXT: [[MUL21:%.*]] = mul nsw i32 [[DIV20]], 1
2302 // CHECK10-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]]
2303 // CHECK10-NEXT: store i32 [[ADD22]], i32* [[I13]], align 4
2304 // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2305 // CHECK10-NEXT: [[SUB23:%.*]] = sub nsw i32 [[TMP32]], 0
2306 // CHECK10-NEXT: [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1
2307 // CHECK10-NEXT: [[MUL25:%.*]] = mul nsw i32 [[DIV24]], 1
2308 // CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]]
2309 // CHECK10-NEXT: store i32 [[ADD26]], i32* [[J14]], align 4
2310 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
2311 // CHECK10: .omp.final.done:
2312 // CHECK10-NEXT: br label [[OMP_PRECOND_END]]
2313 // CHECK10: omp.precond.end:
2314 // CHECK10-NEXT: ret void
2315 //
2316 //
2317 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
2318 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
2319 // CHECK10-NEXT: entry:
2320 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2321 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2322 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2323 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2324 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
2325 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
2326 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
2327 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
2328 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
2329 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
2330 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2331 // CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
2332 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2333 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
2334 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8
2335 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
2336 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4
2337 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2338 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2339 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2340 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2341 // CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4
2342 // CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4
2343 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2344 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2345 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2346 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2347 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
2348 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
2349 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2350 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2351 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
2352 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
2353 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
2354 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2355 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2356 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
2357 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
2358 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
2359 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
2360 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
2361 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2362 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
2363 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2364 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64
2365 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2366 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0
2367 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
2368 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64
2369 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]]
2370 // CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1
2371 // CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8
2372 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
2373 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4
2374 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2375 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
2376 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2377 // CHECK10: land.lhs.true:
2378 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2379 // CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]]
2380 // CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2381 // CHECK10: omp.precond.then:
2382 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
2383 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
2384 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8
2385 // CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2386 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2387 // CHECK10-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_LB]], align 8
2388 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8
2389 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2390 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2391 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2392 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
2393 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2394 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2395 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
2396 // CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
2397 // CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2398 // CHECK10: cond.true:
2399 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8
2400 // CHECK10-NEXT: br label [[COND_END:%.*]]
2401 // CHECK10: cond.false:
2402 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2403 // CHECK10-NEXT: br label [[COND_END]]
2404 // CHECK10: cond.end:
2405 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
2406 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
2407 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
2408 // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
2409 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2410 // CHECK10: omp.inner.for.cond:
2411 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2412 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2413 // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
2414 // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2415 // CHECK10: omp.inner.for.body:
2416 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2417 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2418 // CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0
2419 // CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1
2420 // CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]
2421 // CHECK10-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64
2422 // CHECK10-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]]
2423 // CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1
2424 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]
2425 // CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32
2426 // CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4
2427 // CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2428 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2429 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2430 // CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0
2431 // CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
2432 // CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
2433 // CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
2434 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]]
2435 // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2436 // CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0
2437 // CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1
2438 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]
2439 // CHECK10-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64
2440 // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]
2441 // CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]]
2442 // CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1
2443 // CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
2444 // CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
2445 // CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4
2446 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4
2447 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
2448 // CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]]
2449 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]]
2450 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4
2451 // CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64
2452 // CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]]
2453 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4
2454 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2455 // CHECK10: omp.body.continue:
2456 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2457 // CHECK10: omp.inner.for.inc:
2458 // CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2459 // CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1
2460 // CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8
2461 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
2462 // CHECK10: omp.inner.for.end:
2463 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2464 // CHECK10: omp.loop.exit:
2465 // CHECK10-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2466 // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
2467 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
2468 // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2469 // CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
2470 // CHECK10-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2471 // CHECK10: .omp.final.then:
2472 // CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2473 // CHECK10-NEXT: [[SUB41:%.*]] = sub nsw i32 [[TMP35]], 0
2474 // CHECK10-NEXT: [[DIV42:%.*]] = sdiv i32 [[SUB41]], 1
2475 // CHECK10-NEXT: [[MUL43:%.*]] = mul nsw i32 [[DIV42]], 1
2476 // CHECK10-NEXT: [[ADD44:%.*]] = add nsw i32 0, [[MUL43]]
2477 // CHECK10-NEXT: store i32 [[ADD44]], i32* [[I13]], align 4
2478 // CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
2479 // CHECK10-NEXT: [[SUB45:%.*]] = sub nsw i32 [[TMP36]], 0
2480 // CHECK10-NEXT: [[DIV46:%.*]] = sdiv i32 [[SUB45]], 1
2481 // CHECK10-NEXT: [[MUL47:%.*]] = mul nsw i32 [[DIV46]], 1
2482 // CHECK10-NEXT: [[ADD48:%.*]] = add nsw i32 0, [[MUL47]]
2483 // CHECK10-NEXT: store i32 [[ADD48]], i32* [[J14]], align 4
2484 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
2485 // CHECK10: .omp.final.done:
2486 // CHECK10-NEXT: br label [[OMP_PRECOND_END]]
2487 // CHECK10: omp.precond.end:
2488 // CHECK10-NEXT: ret void
2489 //
2490 //
2491 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
2492 // CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
2493 // CHECK10-NEXT: entry:
2494 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
2495 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
2496 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
2497 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
2498 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
2499 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2500 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2501 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
2502 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2503 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
2504 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8
2505 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2506 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
2507 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8
2508 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2509 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8
2510 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2511 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2512 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20)
2513 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2514 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
2515 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2516 // CHECK10: omp_offload.failed:
2517 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
2518 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
2519 // CHECK10: omp_offload.cont:
2520 // CHECK10-NEXT: ret i32 0
2521 //
2522 //
2523 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
2524 // CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
2525 // CHECK10-NEXT: entry:
2526 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
2527 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
2528 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
2529 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
2530 // CHECK10-NEXT: ret void
2531 //
2532 //
2533 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
2534 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
2535 // CHECK10-NEXT: entry:
2536 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2537 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2538 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
2539 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2540 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2541 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2542 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2543 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2544 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2545 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2546 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
2547 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4
2548 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2549 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2550 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
2551 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
2552 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2553 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4
2554 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2555 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2556 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2557 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2558 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2559 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2560 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
2561 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2562 // CHECK10: cond.true:
2563 // CHECK10-NEXT: br label [[COND_END:%.*]]
2564 // CHECK10: cond.false:
2565 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2566 // CHECK10-NEXT: br label [[COND_END]]
2567 // CHECK10: cond.end:
2568 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2569 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2570 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2571 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
2572 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2573 // CHECK10: omp.inner.for.cond:
2574 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2575 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2576 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2577 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2578 // CHECK10: omp.inner.for.body:
2579 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2580 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
2581 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2582 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
2583 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]])
2584 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2585 // CHECK10: omp.inner.for.inc:
2586 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2587 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2588 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
2589 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2590 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2591 // CHECK10: omp.inner.for.end:
2592 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2593 // CHECK10: omp.loop.exit:
2594 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
2595 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2596 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2597 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2598 // CHECK10: .omp.final.then:
2599 // CHECK10-NEXT: store i32 10, i32* [[I]], align 4
2600 // CHECK10-NEXT: store i32 2, i32* [[J]], align 4
2601 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
2602 // CHECK10: .omp.final.done:
2603 // CHECK10-NEXT: ret void
2604 //
2605 //
2606 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
2607 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
2608 // CHECK10-NEXT: entry:
2609 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2610 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2611 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2612 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2613 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
2614 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2615 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2616 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2617 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2618 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2619 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2620 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2621 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
2622 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4
2623 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2624 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2625 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2626 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2627 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
2628 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
2629 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2630 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
2631 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2632 // CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
2633 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2634 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
2635 // CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
2636 // CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
2637 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2638 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2639 // CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2640 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
2641 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2642 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2643 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19
2644 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2645 // CHECK10: cond.true:
2646 // CHECK10-NEXT: br label [[COND_END:%.*]]
2647 // CHECK10: cond.false:
2648 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2649 // CHECK10-NEXT: br label [[COND_END]]
2650 // CHECK10: cond.end:
2651 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
2652 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2653 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2654 // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
2655 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2656 // CHECK10: omp.inner.for.cond:
2657 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2658 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2659 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
2660 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2661 // CHECK10: omp.inner.for.body:
2662 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2663 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
2664 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
2665 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2666 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2667 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2668 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2669 // CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2
2670 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2
2671 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]]
2672 // CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
2673 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
2674 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4
2675 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2676 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
2677 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
2678 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
2679 // CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64
2680 // CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]]
2681 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4
2682 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2683 // CHECK10: omp.body.continue:
2684 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2685 // CHECK10: omp.inner.for.inc:
2686 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2687 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1
2688 // CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
2689 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2690 // CHECK10: omp.inner.for.end:
2691 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2692 // CHECK10: omp.loop.exit:
2693 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
2694 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2695 // CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
2696 // CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2697 // CHECK10: .omp.final.then:
2698 // CHECK10-NEXT: store i32 10, i32* [[I]], align 4
2699 // CHECK10-NEXT: store i32 2, i32* [[J]], align 4
2700 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
2701 // CHECK10: .omp.final.done:
2702 // CHECK10-NEXT: ret void
2703 //
2704 //
2705 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2706 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] {
2707 // CHECK10-NEXT: entry:
2708 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
2709 // CHECK10-NEXT: ret void
2710 //
2711 //
2712 // CHECK11-LABEL: define {{[^@]+}}@main
2713 // CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
2714 // CHECK11-NEXT: entry:
2715 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2716 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
2717 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
2718 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
2719 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4
2720 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
2721 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2722 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2723 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
2724 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
2725 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
2726 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
2727 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
2728 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
2729 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
2730 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2731 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2732 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2733 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
2734 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
2735 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
2736 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
2737 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4
2738 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4
2739 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
2740 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4
2741 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
2742 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
2743 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
2744 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
2745 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
2746 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4
2747 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
2748 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4
2749 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4
2750 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4
2751 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4
2752 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4
2753 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
2754 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
2755 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
2756 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2757 // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
2758 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4
2759 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2760 // CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
2761 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4
2762 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2763 // CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4
2764 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2765 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4
2766 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2767 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
2768 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4
2769 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2770 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
2771 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4
2772 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2773 // CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4
2774 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2775 // CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4
2776 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2777 // CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
2778 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4
2779 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2780 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
2781 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4
2782 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2783 // CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4
2784 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2785 // CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4
2786 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2787 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
2788 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4
2789 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2790 // CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
2791 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4
2792 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2793 // CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4
2794 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2795 // CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4
2796 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2797 // CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32**
2798 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4
2799 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2800 // CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32**
2801 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4
2802 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2803 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4
2804 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2805 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4
2806 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2807 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2808 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2809 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4
2810 // CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
2811 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4
2812 // CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2813 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2814 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0
2815 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2816 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
2817 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2818 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0
2819 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
2820 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
2821 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
2822 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
2823 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
2824 // CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
2825 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1
2826 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]])
2827 // CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2828 // CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
2829 // CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2830 // CHECK11: omp_offload.failed:
2831 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
2832 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
2833 // CHECK11: omp_offload.cont:
2834 // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
2835 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]])
2836 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
2837 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
2838 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]])
2839 // CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4
2840 // CHECK11-NEXT: ret i32 [[TMP53]]
2841 //
2842 //
2843 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
2844 // CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
2845 // CHECK11-NEXT: entry:
2846 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2847 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
2848 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2849 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2850 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
2851 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
2852 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
2853 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2854 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
2855 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2856 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2857 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
2858 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2859 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2860 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
2861 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
2862 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
2863 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
2864 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4
2865 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4
2866 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4
2867 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]])
2868 // CHECK11-NEXT: ret void
2869 //
2870 //
2871 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
2872 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
2873 // CHECK11-NEXT: entry:
2874 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2875 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2876 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2877 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
2878 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2879 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2880 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
2881 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
2882 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
2883 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
2884 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2885 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
2886 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
2887 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
2888 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
2889 // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
2890 // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
2891 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2892 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2893 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4
2894 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4
2895 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
2896 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
2897 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2898 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2899 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2900 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
2901 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2902 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2903 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
2904 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2905 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2906 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
2907 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
2908 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
2909 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4
2910 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4
2911 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2912 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
2913 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2914 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
2915 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2916 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0
2917 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
2918 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
2919 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
2920 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
2921 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
2922 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
2923 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4
2924 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2925 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
2926 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2927 // CHECK11: land.lhs.true:
2928 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2929 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]
2930 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2931 // CHECK11: omp.precond.then:
2932 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8
2933 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
2934 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8
2935 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2936 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2937 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2938 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2939 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2940 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2941 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
2942 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
2943 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2944 // CHECK11: cond.true:
2945 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
2946 // CHECK11-NEXT: br label [[COND_END:%.*]]
2947 // CHECK11: cond.false:
2948 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2949 // CHECK11-NEXT: br label [[COND_END]]
2950 // CHECK11: cond.end:
2951 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
2952 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
2953 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
2954 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
2955 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2956 // CHECK11: omp.inner.for.cond:
2957 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2958 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2959 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
2960 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2961 // CHECK11: omp.inner.for.body:
2962 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
2963 // CHECK11-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
2964 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
2965 // CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
2966 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4
2967 // CHECK11-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4
2968 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4
2969 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4
2970 // CHECK11-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4
2971 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4
2972 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]])
2973 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2974 // CHECK11: omp.inner.for.inc:
2975 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2976 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8
2977 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]]
2978 // CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8
2979 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2980 // CHECK11: omp.inner.for.end:
2981 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2982 // CHECK11: omp.loop.exit:
2983 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2984 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
2985 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
2986 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2987 // CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2988 // CHECK11-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2989 // CHECK11: .omp.final.then:
2990 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2991 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP33]], 0
2992 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
2993 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
2994 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
2995 // CHECK11-NEXT: store i32 [[ADD18]], i32* [[I11]], align 4
2996 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2997 // CHECK11-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP34]], 0
2998 // CHECK11-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
2999 // CHECK11-NEXT: [[MUL21:%.*]] = mul nsw i32 [[DIV20]], 1
3000 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]]
3001 // CHECK11-NEXT: store i32 [[ADD22]], i32* [[J12]], align 4
3002 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]
3003 // CHECK11: .omp.final.done:
3004 // CHECK11-NEXT: br label [[OMP_PRECOND_END]]
3005 // CHECK11: omp.precond.end:
3006 // CHECK11-NEXT: ret void
3007 //
3008 //
3009 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
3010 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
3011 // CHECK11-NEXT: entry:
3012 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3013 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3014 // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3015 // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3016 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3017 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
3018 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3019 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3020 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
3021 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
3022 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
3023 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
3024 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3025 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3026 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
3027 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
3028 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
3029 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
3030 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
3031 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3032 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3033 // CHECK11-NEXT: [[I13:%.*]] = alloca i32, align 4
3034 // CHECK11-NEXT: [[J14:%.*]] = alloca i32, align 4
3035 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3036 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3037 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3038 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3039 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3040 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
3041 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3042 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3043 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
3044 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3045 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3046 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
3047 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3048 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
3049 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4
3050 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3051 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3052 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
3053 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3054 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
3055 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3056 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0
3057 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
3058 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
3059 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
3060 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
3061 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
3062 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
3063 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4
3064 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3065 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
3066 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
3067 // CHECK11: land.lhs.true:
3068 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3069 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]
3070 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
3071 // CHECK11: omp.precond.then:
3072 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
3073 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3074 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8
3075 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3076 // CHECK11-NEXT: [[CONV11:%.*]] = zext i32 [[TMP10]] to i64
3077 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3078 // CHECK11-NEXT: [[CONV12:%.*]] = zext i32 [[TMP11]] to i64
3079 // CHECK11-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8
3080 // CHECK11-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8
3081 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3082 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3083 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3084 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
3085 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3086 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3087 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3088 // CHECK11-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
3089 // CHECK11-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3090 // CHECK11: cond.true:
3091 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3092 // CHECK11-NEXT: br label [[COND_END:%.*]]
3093 // CHECK11: cond.false:
3094 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3095 // CHECK11-NEXT: br label [[COND_END]]
3096 // CHECK11: cond.end:
3097 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
3098 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3099 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3100 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
3101 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3102 // CHECK11: omp.inner.for.cond:
3103 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3104 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3105 // CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
3106 // CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3107 // CHECK11: omp.inner.for.body:
3108 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3109 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3110 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0
3111 // CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1
3112 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]
3113 // CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64
3114 // CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]]
3115 // CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1
3116 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]
3117 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32
3118 // CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4
3119 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3120 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3121 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3122 // CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0
3123 // CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
3124 // CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
3125 // CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
3126 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]]
3127 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3128 // CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0
3129 // CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1
3130 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]
3131 // CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64
3132 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]
3133 // CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]]
3134 // CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1
3135 // CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
3136 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
3137 // CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4
3138 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4
3139 // CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]]
3140 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]]
3141 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4
3142 // CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]]
3143 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4
3144 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3145 // CHECK11: omp.body.continue:
3146 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3147 // CHECK11: omp.inner.for.inc:
3148 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3149 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1
3150 // CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8
3151 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3152 // CHECK11: omp.inner.for.end:
3153 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3154 // CHECK11: omp.loop.exit:
3155 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3156 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
3157 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
3158 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3159 // CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
3160 // CHECK11-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3161 // CHECK11: .omp.final.then:
3162 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3163 // CHECK11-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP35]], 0
3164 // CHECK11-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
3165 // CHECK11-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
3166 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
3167 // CHECK11-NEXT: store i32 [[ADD43]], i32* [[I13]], align 4
3168 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3169 // CHECK11-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP36]], 0
3170 // CHECK11-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1
3171 // CHECK11-NEXT: [[MUL46:%.*]] = mul nsw i32 [[DIV45]], 1
3172 // CHECK11-NEXT: [[ADD47:%.*]] = add nsw i32 0, [[MUL46]]
3173 // CHECK11-NEXT: store i32 [[ADD47]], i32* [[J14]], align 4
3174 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]
3175 // CHECK11: .omp.final.done:
3176 // CHECK11-NEXT: br label [[OMP_PRECOND_END]]
3177 // CHECK11: omp.precond.end:
3178 // CHECK11-NEXT: ret void
3179 //
3180 //
3181 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
3182 // CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
3183 // CHECK11-NEXT: entry:
3184 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
3185 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
3186 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
3187 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
3188 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
3189 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
3190 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3191 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
3192 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3193 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
3194 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4
3195 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3196 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
3197 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4
3198 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3199 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4
3200 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3201 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3202 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20)
3203 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3204 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
3205 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3206 // CHECK11: omp_offload.failed:
3207 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
3208 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
3209 // CHECK11: omp_offload.cont:
3210 // CHECK11-NEXT: ret i32 0
3211 //
3212 //
3213 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
3214 // CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
3215 // CHECK11-NEXT: entry:
3216 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
3217 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
3218 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
3219 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
3220 // CHECK11-NEXT: ret void
3221 //
3222 //
3223 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
3224 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
3225 // CHECK11-NEXT: entry:
3226 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3227 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3228 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
3229 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3230 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
3231 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3232 // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3233 // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3234 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3235 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3236 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
3237 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
3238 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3239 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3240 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
3241 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
3242 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3243 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4
3244 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3245 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3246 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3247 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3248 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3249 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3250 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
3251 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3252 // CHECK11: cond.true:
3253 // CHECK11-NEXT: br label [[COND_END:%.*]]
3254 // CHECK11: cond.false:
3255 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3256 // CHECK11-NEXT: br label [[COND_END]]
3257 // CHECK11: cond.end:
3258 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3259 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3260 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3261 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3262 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3263 // CHECK11: omp.inner.for.cond:
3264 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3265 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3266 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3267 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3268 // CHECK11: omp.inner.for.body:
3269 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3270 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3271 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]])
3272 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3273 // CHECK11: omp.inner.for.inc:
3274 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3275 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3276 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
3277 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3278 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
3279 // CHECK11: omp.inner.for.end:
3280 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3281 // CHECK11: omp.loop.exit:
3282 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3283 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3284 // CHECK11-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
3285 // CHECK11-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3286 // CHECK11: .omp.final.then:
3287 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4
3288 // CHECK11-NEXT: store i32 2, i32* [[J]], align 4
3289 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]
3290 // CHECK11: .omp.final.done:
3291 // CHECK11-NEXT: ret void
3292 //
3293 //
3294 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
3295 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
3296 // CHECK11-NEXT: entry:
3297 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3298 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3299 // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3300 // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3301 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
3302 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3303 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
3304 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3305 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3306 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3307 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3308 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3309 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
3310 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
3311 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3312 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3313 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3314 // CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3315 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
3316 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
3317 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3318 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
3319 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3320 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3321 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
3322 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
3323 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3324 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3325 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3326 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
3327 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3328 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3329 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19
3330 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3331 // CHECK11: cond.true:
3332 // CHECK11-NEXT: br label [[COND_END:%.*]]
3333 // CHECK11: cond.false:
3334 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3335 // CHECK11-NEXT: br label [[COND_END]]
3336 // CHECK11: cond.end:
3337 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
3338 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3339 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3340 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
3341 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3342 // CHECK11: omp.inner.for.cond:
3343 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3344 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3345 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
3346 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3347 // CHECK11: omp.inner.for.body:
3348 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3349 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
3350 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
3351 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3352 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3353 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3354 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3355 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2
3356 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
3357 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
3358 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
3359 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
3360 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
3361 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
3362 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]]
3363 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
3364 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]]
3365 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
3366 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3367 // CHECK11: omp.body.continue:
3368 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3369 // CHECK11: omp.inner.for.inc:
3370 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3371 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
3372 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
3373 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
3374 // CHECK11: omp.inner.for.end:
3375 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3376 // CHECK11: omp.loop.exit:
3377 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
3378 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3379 // CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
3380 // CHECK11-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3381 // CHECK11: .omp.final.then:
3382 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4
3383 // CHECK11-NEXT: store i32 2, i32* [[J]], align 4
3384 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]
3385 // CHECK11: .omp.final.done:
3386 // CHECK11-NEXT: ret void
3387 //
3388 //
3389 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3390 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] {
3391 // CHECK11-NEXT: entry:
3392 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1)
3393 // CHECK11-NEXT: ret void
3394 //
3395 //
3396 // CHECK12-LABEL: define {{[^@]+}}@main
3397 // CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
3398 // CHECK12-NEXT: entry:
3399 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3400 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
3401 // CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
3402 // CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
3403 // CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4
3404 // CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
3405 // CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3406 // CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3407 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
3408 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
3409 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3410 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3411 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3412 // CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3413 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
3414 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3415 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3416 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3417 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
3418 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
3419 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
3420 // CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
3421 // CHECK12-NEXT: store i32 100, i32* [[N]], align 4
3422 // CHECK12-NEXT: store i32 2, i32* [[M]], align 4
3423 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
3424 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4
3425 // CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
3426 // CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3427 // CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
3428 // CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
3429 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
3430 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4
3431 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
3432 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4
3433 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4
3434 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4
3435 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4
3436 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4
3437 // CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
3438 // CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
3439 // CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
3440 // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3441 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
3442 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4
3443 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3444 // CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
3445 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4
3446 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3447 // CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4
3448 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3449 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4
3450 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3451 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
3452 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4
3453 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3454 // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3455 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4
3456 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3457 // CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4
3458 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3459 // CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4
3460 // CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3461 // CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
3462 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4
3463 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3464 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
3465 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4
3466 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3467 // CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4
3468 // CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3469 // CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4
3470 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3471 // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
3472 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4
3473 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3474 // CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
3475 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4
3476 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3477 // CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4
3478 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3479 // CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4
3480 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3481 // CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32**
3482 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4
3483 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3484 // CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32**
3485 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4
3486 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3487 // CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4
3488 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3489 // CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4
3490 // CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3491 // CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3492 // CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3493 // CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4
3494 // CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
3495 // CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4
3496 // CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3497 // CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3498 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0
3499 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3500 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
3501 // CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3502 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0
3503 // CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
3504 // CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
3505 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
3506 // CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
3507 // CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
3508 // CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
3509 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1
3510 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[ADD]])
3511 // CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3512 // CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
3513 // CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3514 // CHECK12: omp_offload.failed:
3515 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
3516 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
3517 // CHECK12: omp_offload.cont:
3518 // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
3519 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]])
3520 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
3521 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3522 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]])
3523 // CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4
3524 // CHECK12-NEXT: ret i32 [[TMP53]]
3525 //
3526 //
3527 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
3528 // CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
3529 // CHECK12-NEXT: entry:
3530 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3531 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
3532 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3533 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3534 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
3535 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
3536 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
3537 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3538 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
3539 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3540 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3541 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
3542 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3543 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3544 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
3545 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3546 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
3547 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
3548 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4
3549 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4
3550 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4
3551 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]])
3552 // CHECK12-NEXT: ret void
3553 //
3554 //
3555 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
3556 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
3557 // CHECK12-NEXT: entry:
3558 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3559 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3560 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3561 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
3562 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3563 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3564 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
3565 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
3566 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
3567 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
3568 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3569 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3570 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
3571 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
3572 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
3573 // CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
3574 // CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
3575 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3576 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3577 // CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4
3578 // CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4
3579 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
3580 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
3581 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3582 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3583 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3584 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
3585 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3586 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3587 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
3588 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3589 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3590 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
3591 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3592 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
3593 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4
3594 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3595 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3596 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
3597 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3598 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
3599 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3600 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0
3601 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
3602 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
3603 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
3604 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
3605 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
3606 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4
3607 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4
3608 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3609 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
3610 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
3611 // CHECK12: land.lhs.true:
3612 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3613 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]
3614 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
3615 // CHECK12: omp.precond.then:
3616 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_COMB_LB]], align 8
3617 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3618 // CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_COMB_UB]], align 8
3619 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3620 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3621 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3622 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
3623 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_COMB_LB]], i64* [[DOTOMP_COMB_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3624 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
3625 // CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3626 // CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
3627 // CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3628 // CHECK12: cond.true:
3629 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3630 // CHECK12-NEXT: br label [[COND_END:%.*]]
3631 // CHECK12: cond.false:
3632 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
3633 // CHECK12-NEXT: br label [[COND_END]]
3634 // CHECK12: cond.end:
3635 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
3636 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_COMB_UB]], align 8
3637 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
3638 // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
3639 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3640 // CHECK12: omp.inner.for.cond:
3641 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3642 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
3643 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
3644 // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3645 // CHECK12: omp.inner.for.body:
3646 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
3647 // CHECK12-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
3648 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
3649 // CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
3650 // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4
3651 // CHECK12-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4
3652 // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4
3653 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4
3654 // CHECK12-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4
3655 // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4
3656 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]])
3657 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3658 // CHECK12: omp.inner.for.inc:
3659 // CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3660 // CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8
3661 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]]
3662 // CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8
3663 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
3664 // CHECK12: omp.inner.for.end:
3665 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3666 // CHECK12: omp.loop.exit:
3667 // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3668 // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
3669 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
3670 // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3671 // CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3672 // CHECK12-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3673 // CHECK12: .omp.final.then:
3674 // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3675 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP33]], 0
3676 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
3677 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
3678 // CHECK12-NEXT: [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
3679 // CHECK12-NEXT: store i32 [[ADD18]], i32* [[I11]], align 4
3680 // CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3681 // CHECK12-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP34]], 0
3682 // CHECK12-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
3683 // CHECK12-NEXT: [[MUL21:%.*]] = mul nsw i32 [[DIV20]], 1
3684 // CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]]
3685 // CHECK12-NEXT: store i32 [[ADD22]], i32* [[J12]], align 4
3686 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]]
3687 // CHECK12: .omp.final.done:
3688 // CHECK12-NEXT: br label [[OMP_PRECOND_END]]
3689 // CHECK12: omp.precond.end:
3690 // CHECK12-NEXT: ret void
3691 //
3692 //
3693 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
3694 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
3695 // CHECK12-NEXT: entry:
3696 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3697 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3698 // CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3699 // CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3700 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3701 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
3702 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3703 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3704 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
3705 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
3706 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
3707 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
3708 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3709 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3710 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
3711 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
3712 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
3713 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
3714 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
3715 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3716 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3717 // CHECK12-NEXT: [[I13:%.*]] = alloca i32, align 4
3718 // CHECK12-NEXT: [[J14:%.*]] = alloca i32, align 4
3719 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3720 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3721 // CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3722 // CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3723 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
3724 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
3725 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3726 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3727 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
3728 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3729 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3730 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
3731 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3732 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
3733 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4
3734 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3735 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3736 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
3737 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3738 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
3739 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3740 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0
3741 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
3742 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
3743 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
3744 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
3745 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
3746 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4
3747 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4
3748 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3749 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
3750 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
3751 // CHECK12: land.lhs.true:
3752 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3753 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]
3754 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
3755 // CHECK12: omp.precond.then:
3756 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
3757 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3758 // CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8
3759 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3760 // CHECK12-NEXT: [[CONV11:%.*]] = zext i32 [[TMP10]] to i64
3761 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3762 // CHECK12-NEXT: [[CONV12:%.*]] = zext i32 [[TMP11]] to i64
3763 // CHECK12-NEXT: store i64 [[CONV11]], i64* [[DOTOMP_LB]], align 8
3764 // CHECK12-NEXT: store i64 [[CONV12]], i64* [[DOTOMP_UB]], align 8
3765 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3766 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3767 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3768 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
3769 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3770 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3771 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3772 // CHECK12-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
3773 // CHECK12-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3774 // CHECK12: cond.true:
3775 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
3776 // CHECK12-NEXT: br label [[COND_END:%.*]]
3777 // CHECK12: cond.false:
3778 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3779 // CHECK12-NEXT: br label [[COND_END]]
3780 // CHECK12: cond.end:
3781 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
3782 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3783 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3784 // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
3785 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3786 // CHECK12: omp.inner.for.cond:
3787 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3788 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3789 // CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
3790 // CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3791 // CHECK12: omp.inner.for.body:
3792 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3793 // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3794 // CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0
3795 // CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1
3796 // CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]]
3797 // CHECK12-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64
3798 // CHECK12-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP21]], [[CONV20]]
3799 // CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1
3800 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]]
3801 // CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32
3802 // CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4
3803 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3804 // CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3805 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3806 // CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0
3807 // CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
3808 // CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
3809 // CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
3810 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]]
3811 // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3812 // CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0
3813 // CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1
3814 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]]
3815 // CHECK12-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64
3816 // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]]
3817 // CHECK12-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP23]], [[MUL33]]
3818 // CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1
3819 // CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
3820 // CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
3821 // CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4
3822 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4
3823 // CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]]
3824 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]]
3825 // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4
3826 // CHECK12-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]]
3827 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4
3828 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3829 // CHECK12: omp.body.continue:
3830 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3831 // CHECK12: omp.inner.for.inc:
3832 // CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
3833 // CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1
3834 // CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8
3835 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3836 // CHECK12: omp.inner.for.end:
3837 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3838 // CHECK12: omp.loop.exit:
3839 // CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3840 // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
3841 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
3842 // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3843 // CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
3844 // CHECK12-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3845 // CHECK12: .omp.final.then:
3846 // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3847 // CHECK12-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP35]], 0
3848 // CHECK12-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
3849 // CHECK12-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
3850 // CHECK12-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
3851 // CHECK12-NEXT: store i32 [[ADD43]], i32* [[I13]], align 4
3852 // CHECK12-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3853 // CHECK12-NEXT: [[SUB44:%.*]] = sub nsw i32 [[TMP36]], 0
3854 // CHECK12-NEXT: [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1
3855 // CHECK12-NEXT: [[MUL46:%.*]] = mul nsw i32 [[DIV45]], 1
3856 // CHECK12-NEXT: [[ADD47:%.*]] = add nsw i32 0, [[MUL46]]
3857 // CHECK12-NEXT: store i32 [[ADD47]], i32* [[J14]], align 4
3858 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]]
3859 // CHECK12: .omp.final.done:
3860 // CHECK12-NEXT: br label [[OMP_PRECOND_END]]
3861 // CHECK12: omp.precond.end:
3862 // CHECK12-NEXT: ret void
3863 //
3864 //
3865 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
3866 // CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
3867 // CHECK12-NEXT: entry:
3868 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
3869 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
3870 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
3871 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
3872 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
3873 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
3874 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3875 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
3876 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3877 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
3878 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4
3879 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3880 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
3881 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4
3882 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3883 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4
3884 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3885 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3886 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 20)
3887 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3888 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
3889 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3890 // CHECK12: omp_offload.failed:
3891 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
3892 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
3893 // CHECK12: omp_offload.cont:
3894 // CHECK12-NEXT: ret i32 0
3895 //
3896 //
3897 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
3898 // CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
3899 // CHECK12-NEXT: entry:
3900 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
3901 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
3902 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
3903 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
3904 // CHECK12-NEXT: ret void
3905 //
3906 //
3907 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
3908 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
3909 // CHECK12-NEXT: entry:
3910 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3911 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3912 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
3913 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3914 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
3915 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3916 // CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3917 // CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3918 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3919 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3920 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
3921 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
3922 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3923 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3924 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
3925 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
3926 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3927 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_COMB_UB]], align 4
3928 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3929 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3930 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3931 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3932 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3933 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3934 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
3935 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3936 // CHECK12: cond.true:
3937 // CHECK12-NEXT: br label [[COND_END:%.*]]
3938 // CHECK12: cond.false:
3939 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3940 // CHECK12-NEXT: br label [[COND_END]]
3941 // CHECK12: cond.end:
3942 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3943 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3944 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3945 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3946 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3947 // CHECK12: omp.inner.for.cond:
3948 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3949 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3950 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3951 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3952 // CHECK12: omp.inner.for.body:
3953 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3954 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3955 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]])
3956 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3957 // CHECK12: omp.inner.for.inc:
3958 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3959 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3960 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
3961 // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3962 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
3963 // CHECK12: omp.inner.for.end:
3964 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3965 // CHECK12: omp.loop.exit:
3966 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3967 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3968 // CHECK12-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
3969 // CHECK12-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3970 // CHECK12: .omp.final.then:
3971 // CHECK12-NEXT: store i32 10, i32* [[I]], align 4
3972 // CHECK12-NEXT: store i32 2, i32* [[J]], align 4
3973 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]]
3974 // CHECK12: .omp.final.done:
3975 // CHECK12-NEXT: ret void
3976 //
3977 //
3978 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
3979 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
3980 // CHECK12-NEXT: entry:
3981 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3982 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3983 // CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3984 // CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3985 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
3986 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3987 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
3988 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3989 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3990 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3991 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3992 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3993 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
3994 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
3995 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3996 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3997 // CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3998 // CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3999 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
4000 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
4001 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4002 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
4003 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4004 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4005 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_LB]], align 4
4006 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
4007 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4008 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4009 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4010 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
4011 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4012 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4013 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19
4014 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4015 // CHECK12: cond.true:
4016 // CHECK12-NEXT: br label [[COND_END:%.*]]
4017 // CHECK12: cond.false:
4018 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4019 // CHECK12-NEXT: br label [[COND_END]]
4020 // CHECK12: cond.end:
4021 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
4022 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4023 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4024 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
4025 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4026 // CHECK12: omp.inner.for.cond:
4027 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4028 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4029 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
4030 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4031 // CHECK12: omp.inner.for.body:
4032 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4033 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2
4034 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4035 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4036 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4037 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4038 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4039 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2
4040 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
4041 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]]
4042 // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
4043 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
4044 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
4045 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
4046 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]]
4047 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4
4048 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]]
4049 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
4050 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4051 // CHECK12: omp.body.continue:
4052 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4053 // CHECK12: omp.inner.for.inc:
4054 // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4055 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
4056 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
4057 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4058 // CHECK12: omp.inner.for.end:
4059 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4060 // CHECK12: omp.loop.exit:
4061 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
4062 // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4063 // CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
4064 // CHECK12-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4065 // CHECK12: .omp.final.then:
4066 // CHECK12-NEXT: store i32 10, i32* [[I]], align 4
4067 // CHECK12-NEXT: store i32 2, i32* [[J]], align 4
4068 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]]
4069 // CHECK12: .omp.final.done:
4070 // CHECK12-NEXT: ret void
4071 //
4072 //
4073 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4074 // CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
4075 // CHECK12-NEXT: entry:
4076 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
4077 // CHECK12-NEXT: ret void
4078 //
4079 //
4080 // CHECK13-LABEL: define {{[^@]+}}@main
4081 // CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
4082 // CHECK13-NEXT: entry:
4083 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4084 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4085 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
4086 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4
4087 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4
4088 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
4089 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4090 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
4091 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
4092 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4093 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4094 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4095 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4096 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4097 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4098 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
4099 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4
4100 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4101 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4
4102 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4
4103 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4
4104 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4105 // CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
4106 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4
4107 // CHECK13-NEXT: store i32 2, i32* [[M]], align 4
4108 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
4109 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
4110 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4
4111 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
4112 // CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
4113 // CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
4114 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
4115 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
4116 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
4117 // CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
4118 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4
4119 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
4120 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4
4121 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4122 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4123 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0
4124 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4125 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
4126 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4127 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0
4128 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
4129 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
4130 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
4131 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
4132 // CHECK13-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
4133 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4134 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
4135 // CHECK13-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8
4136 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4
4137 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4
4138 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4139 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]]
4140 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
4141 // CHECK13: land.lhs.true:
4142 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4143 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]]
4144 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
4145 // CHECK13: simd.if.then:
4146 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4147 // CHECK13-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8
4148 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4149 // CHECK13: omp.inner.for.cond:
4150 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4151 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2
4152 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]
4153 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4154 // CHECK13: omp.inner.for.body:
4155 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4156 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2
4157 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0
4158 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
4159 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
4160 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
4161 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]]
4162 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
4163 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
4164 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
4165 // CHECK13-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2
4166 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4167 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4168 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2
4169 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0
4170 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
4171 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
4172 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
4173 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]]
4174 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2
4175 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0
4176 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
4177 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
4178 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
4179 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
4180 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]]
4181 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
4182 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
4183 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
4184 // CHECK13-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2
4185 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2
4186 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
4187 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
4188 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]]
4189 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2
4190 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64
4191 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]]
4192 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2
4193 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4194 // CHECK13: omp.body.continue:
4195 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4196 // CHECK13: omp.inner.for.inc:
4197 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4198 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1
4199 // CHECK13-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4200 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4201 // CHECK13: omp.inner.for.end:
4202 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4203 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0
4204 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1
4205 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1
4206 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]]
4207 // CHECK13-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4
4208 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4209 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0
4210 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
4211 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
4212 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
4213 // CHECK13-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4
4214 // CHECK13-NEXT: br label [[SIMD_IF_END]]
4215 // CHECK13: simd.if.end:
4216 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
4217 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]])
4218 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
4219 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4220 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]])
4221 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
4222 // CHECK13-NEXT: ret i32 [[TMP30]]
4223 //
4224 //
4225 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
4226 // CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
4227 // CHECK13-NEXT: entry:
4228 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4229 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
4230 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
4231 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4232 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4233 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4234 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4235 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
4236 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4
4237 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4238 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4239 // CHECK13-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
4240 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4241 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4242 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4243 // CHECK13: omp.inner.for.cond:
4244 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4245 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
4246 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4247 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4248 // CHECK13: omp.inner.for.body:
4249 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4250 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
4251 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4252 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4253 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
4254 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4255 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4256 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
4257 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
4258 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
4259 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
4260 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
4261 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6
4262 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
4263 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
4264 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
4265 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6
4266 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64
4267 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]]
4268 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6
4269 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4270 // CHECK13: omp.body.continue:
4271 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4272 // CHECK13: omp.inner.for.inc:
4273 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4274 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
4275 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4276 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
4277 // CHECK13: omp.inner.for.end:
4278 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4
4279 // CHECK13-NEXT: store i32 2, i32* [[J]], align 4
4280 // CHECK13-NEXT: ret i32 0
4281 //
4282 //
4283 // CHECK14-LABEL: define {{[^@]+}}@main
4284 // CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
4285 // CHECK14-NEXT: entry:
4286 // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4287 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4288 // CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
4289 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4
4290 // CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4
4291 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
4292 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4293 // CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
4294 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
4295 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4296 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4297 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4298 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4299 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4300 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4301 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
4302 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4
4303 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4304 // CHECK14-NEXT: [[I9:%.*]] = alloca i32, align 4
4305 // CHECK14-NEXT: [[J10:%.*]] = alloca i32, align 4
4306 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4
4307 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4308 // CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
4309 // CHECK14-NEXT: store i32 100, i32* [[N]], align 4
4310 // CHECK14-NEXT: store i32 2, i32* [[M]], align 4
4311 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
4312 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
4313 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4
4314 // CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
4315 // CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
4316 // CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
4317 // CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
4318 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
4319 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
4320 // CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
4321 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4
4322 // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
4323 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4
4324 // CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4325 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4326 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0
4327 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4328 // CHECK14-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
4329 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4330 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0
4331 // CHECK14-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
4332 // CHECK14-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
4333 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
4334 // CHECK14-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
4335 // CHECK14-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
4336 // CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4337 // CHECK14-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
4338 // CHECK14-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8
4339 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4
4340 // CHECK14-NEXT: store i32 0, i32* [[J]], align 4
4341 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4342 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]]
4343 // CHECK14-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
4344 // CHECK14: land.lhs.true:
4345 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4346 // CHECK14-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]]
4347 // CHECK14-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
4348 // CHECK14: simd.if.then:
4349 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4350 // CHECK14-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8
4351 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4352 // CHECK14: omp.inner.for.cond:
4353 // CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4354 // CHECK14-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2
4355 // CHECK14-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]
4356 // CHECK14-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4357 // CHECK14: omp.inner.for.body:
4358 // CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4359 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2
4360 // CHECK14-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0
4361 // CHECK14-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
4362 // CHECK14-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
4363 // CHECK14-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
4364 // CHECK14-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]]
4365 // CHECK14-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
4366 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
4367 // CHECK14-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
4368 // CHECK14-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2
4369 // CHECK14-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4370 // CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4371 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2
4372 // CHECK14-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0
4373 // CHECK14-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
4374 // CHECK14-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
4375 // CHECK14-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
4376 // CHECK14-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]]
4377 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2
4378 // CHECK14-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0
4379 // CHECK14-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
4380 // CHECK14-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
4381 // CHECK14-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
4382 // CHECK14-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
4383 // CHECK14-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]]
4384 // CHECK14-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
4385 // CHECK14-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
4386 // CHECK14-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
4387 // CHECK14-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2
4388 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2
4389 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
4390 // CHECK14-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
4391 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]]
4392 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2
4393 // CHECK14-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64
4394 // CHECK14-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]]
4395 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2
4396 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4397 // CHECK14: omp.body.continue:
4398 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4399 // CHECK14: omp.inner.for.inc:
4400 // CHECK14-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4401 // CHECK14-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1
4402 // CHECK14-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2
4403 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4404 // CHECK14: omp.inner.for.end:
4405 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4406 // CHECK14-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0
4407 // CHECK14-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1
4408 // CHECK14-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1
4409 // CHECK14-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]]
4410 // CHECK14-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4
4411 // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4412 // CHECK14-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0
4413 // CHECK14-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
4414 // CHECK14-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
4415 // CHECK14-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
4416 // CHECK14-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4
4417 // CHECK14-NEXT: br label [[SIMD_IF_END]]
4418 // CHECK14: simd.if.end:
4419 // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
4420 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]])
4421 // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
4422 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4423 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]])
4424 // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
4425 // CHECK14-NEXT: ret i32 [[TMP30]]
4426 //
4427 //
4428 // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
4429 // CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
4430 // CHECK14-NEXT: entry:
4431 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4432 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
4433 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
4434 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4435 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4436 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4437 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4438 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
4439 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4
4440 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4441 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4442 // CHECK14-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
4443 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4444 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4445 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4446 // CHECK14: omp.inner.for.cond:
4447 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4448 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
4449 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4450 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4451 // CHECK14: omp.inner.for.body:
4452 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4453 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
4454 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4455 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4456 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
4457 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4458 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4459 // CHECK14-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
4460 // CHECK14-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
4461 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
4462 // CHECK14-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
4463 // CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
4464 // CHECK14-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6
4465 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
4466 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
4467 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
4468 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6
4469 // CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64
4470 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]]
4471 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6
4472 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4473 // CHECK14: omp.body.continue:
4474 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4475 // CHECK14: omp.inner.for.inc:
4476 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4477 // CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
4478 // CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4479 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
4480 // CHECK14: omp.inner.for.end:
4481 // CHECK14-NEXT: store i32 10, i32* [[I]], align 4
4482 // CHECK14-NEXT: store i32 2, i32* [[J]], align 4
4483 // CHECK14-NEXT: ret i32 0
4484 //
4485 //
4486 // CHECK15-LABEL: define {{[^@]+}}@main
4487 // CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
4488 // CHECK15-NEXT: entry:
4489 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4490 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4491 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
4492 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4
4493 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4
4494 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
4495 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4496 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
4497 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
4498 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4499 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4500 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4501 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4502 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4503 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4504 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
4505 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4
4506 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4507 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4
4508 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4
4509 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4
4510 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4511 // CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
4512 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4
4513 // CHECK15-NEXT: store i32 2, i32* [[M]], align 4
4514 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
4515 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4
4516 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
4517 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4518 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
4519 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
4520 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
4521 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4
4522 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
4523 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
4524 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4
4525 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4526 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4527 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0
4528 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4529 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
4530 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4531 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0
4532 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
4533 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
4534 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
4535 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
4536 // CHECK15-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
4537 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4538 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
4539 // CHECK15-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8
4540 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4
4541 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4
4542 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4543 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
4544 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
4545 // CHECK15: land.lhs.true:
4546 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4547 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]]
4548 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
4549 // CHECK15: simd.if.then:
4550 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4551 // CHECK15-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8
4552 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4553 // CHECK15: omp.inner.for.cond:
4554 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4555 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3
4556 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]]
4557 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4558 // CHECK15: omp.inner.for.body:
4559 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4560 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
4561 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0
4562 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
4563 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
4564 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
4565 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]]
4566 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
4567 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
4568 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
4569 // CHECK15-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3
4570 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4571 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4572 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
4573 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0
4574 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
4575 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
4576 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
4577 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]]
4578 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
4579 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0
4580 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
4581 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
4582 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
4583 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
4584 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]]
4585 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
4586 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
4587 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
4588 // CHECK15-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3
4589 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3
4590 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]]
4591 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]]
4592 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3
4593 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]]
4594 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3
4595 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4596 // CHECK15: omp.body.continue:
4597 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4598 // CHECK15: omp.inner.for.inc:
4599 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4600 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1
4601 // CHECK15-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4602 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4603 // CHECK15: omp.inner.for.end:
4604 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4605 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0
4606 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1
4607 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1
4608 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]]
4609 // CHECK15-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4
4610 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4611 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0
4612 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1
4613 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1
4614 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
4615 // CHECK15-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4
4616 // CHECK15-NEXT: br label [[SIMD_IF_END]]
4617 // CHECK15: simd.if.end:
4618 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
4619 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]])
4620 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
4621 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4622 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]])
4623 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4
4624 // CHECK15-NEXT: ret i32 [[TMP28]]
4625 //
4626 //
4627 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
4628 // CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
4629 // CHECK15-NEXT: entry:
4630 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4631 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
4632 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
4633 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4634 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4635 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4636 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4637 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
4638 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4
4639 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4640 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4641 // CHECK15-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
4642 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4643 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4644 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4645 // CHECK15: omp.inner.for.cond:
4646 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4647 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
4648 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4649 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4650 // CHECK15: omp.inner.for.body:
4651 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4652 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
4653 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4654 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4655 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
4656 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4657 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4658 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
4659 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
4660 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
4661 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
4662 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
4663 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7
4664 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4665 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]]
4666 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7
4667 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]]
4668 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7
4669 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4670 // CHECK15: omp.body.continue:
4671 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4672 // CHECK15: omp.inner.for.inc:
4673 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4674 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1
4675 // CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4676 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4677 // CHECK15: omp.inner.for.end:
4678 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4
4679 // CHECK15-NEXT: store i32 2, i32* [[J]], align 4
4680 // CHECK15-NEXT: ret i32 0
4681 //
4682 //
4683 // CHECK16-LABEL: define {{[^@]+}}@main
4684 // CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
4685 // CHECK16-NEXT: entry:
4686 // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4687 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4688 // CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
4689 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4
4690 // CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4
4691 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
4692 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4693 // CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
4694 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
4695 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4696 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4697 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4698 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4699 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
4700 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
4701 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
4702 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4
4703 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
4704 // CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4
4705 // CHECK16-NEXT: [[J10:%.*]] = alloca i32, align 4
4706 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4
4707 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4708 // CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
4709 // CHECK16-NEXT: store i32 100, i32* [[N]], align 4
4710 // CHECK16-NEXT: store i32 2, i32* [[M]], align 4
4711 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
4712 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4
4713 // CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
4714 // CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4715 // CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
4716 // CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
4717 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
4718 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4
4719 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
4720 // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
4721 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4
4722 // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4723 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4724 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0
4725 // CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4726 // CHECK16-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
4727 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4728 // CHECK16-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0
4729 // CHECK16-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
4730 // CHECK16-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
4731 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
4732 // CHECK16-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
4733 // CHECK16-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
4734 // CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
4735 // CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
4736 // CHECK16-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8
4737 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4
4738 // CHECK16-NEXT: store i32 0, i32* [[J]], align 4
4739 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4740 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
4741 // CHECK16-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
4742 // CHECK16: land.lhs.true:
4743 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4744 // CHECK16-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]]
4745 // CHECK16-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
4746 // CHECK16: simd.if.then:
4747 // CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4748 // CHECK16-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8
4749 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4750 // CHECK16: omp.inner.for.cond:
4751 // CHECK16-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4752 // CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3
4753 // CHECK16-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]]
4754 // CHECK16-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4755 // CHECK16: omp.inner.for.body:
4756 // CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4757 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
4758 // CHECK16-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0
4759 // CHECK16-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
4760 // CHECK16-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
4761 // CHECK16-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
4762 // CHECK16-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]]
4763 // CHECK16-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
4764 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
4765 // CHECK16-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
4766 // CHECK16-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3
4767 // CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4768 // CHECK16-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4769 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
4770 // CHECK16-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0
4771 // CHECK16-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
4772 // CHECK16-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
4773 // CHECK16-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
4774 // CHECK16-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]]
4775 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
4776 // CHECK16-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0
4777 // CHECK16-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
4778 // CHECK16-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
4779 // CHECK16-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
4780 // CHECK16-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
4781 // CHECK16-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]]
4782 // CHECK16-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
4783 // CHECK16-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
4784 // CHECK16-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
4785 // CHECK16-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3
4786 // CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3
4787 // CHECK16-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]]
4788 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]]
4789 // CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3
4790 // CHECK16-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]]
4791 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3
4792 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4793 // CHECK16: omp.body.continue:
4794 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4795 // CHECK16: omp.inner.for.inc:
4796 // CHECK16-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4797 // CHECK16-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1
4798 // CHECK16-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3
4799 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4800 // CHECK16: omp.inner.for.end:
4801 // CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4802 // CHECK16-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0
4803 // CHECK16-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1
4804 // CHECK16-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1
4805 // CHECK16-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]]
4806 // CHECK16-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4
4807 // CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4808 // CHECK16-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0
4809 // CHECK16-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1
4810 // CHECK16-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1
4811 // CHECK16-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
4812 // CHECK16-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4
4813 // CHECK16-NEXT: br label [[SIMD_IF_END]]
4814 // CHECK16: simd.if.end:
4815 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
4816 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]])
4817 // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
4818 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4819 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]])
4820 // CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4
4821 // CHECK16-NEXT: ret i32 [[TMP28]]
4822 //
4823 //
4824 // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
4825 // CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
4826 // CHECK16-NEXT: entry:
4827 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
4828 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
4829 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
4830 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4831 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4832 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4833 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4834 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
4835 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4
4836 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
4837 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4838 // CHECK16-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
4839 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4840 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4841 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4842 // CHECK16: omp.inner.for.cond:
4843 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4844 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
4845 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4846 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4847 // CHECK16: omp.inner.for.body:
4848 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4849 // CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
4850 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4851 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4852 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
4853 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4854 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4855 // CHECK16-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
4856 // CHECK16-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
4857 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
4858 // CHECK16-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
4859 // CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
4860 // CHECK16-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7
4861 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4862 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]]
4863 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7
4864 // CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]]
4865 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7
4866 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4867 // CHECK16: omp.body.continue:
4868 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4869 // CHECK16: omp.inner.for.inc:
4870 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4871 // CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1
4872 // CHECK16-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4873 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4874 // CHECK16: omp.inner.for.end:
4875 // CHECK16-NEXT: store i32 10, i32* [[I]], align 4
4876 // CHECK16-NEXT: store i32 2, i32* [[J]], align 4
4877 // CHECK16-NEXT: ret i32 0
4878 //
4879