1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // expected-no-diagnostics
3 #ifndef HEADER
4 #define HEADER
5
6 // Test host codegen.
7 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
10 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
13
14 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
20 #ifdef CK1
21
22 template <typename T, int X, long long Y>
23 struct SS{
24 T a[X][Y];
25
fooSS26 int foo(void) {
27
28 #pragma omp target
29 #pragma omp teams distribute collapse(2)
30 for(int i = 0; i < X; i++) {
31 for(int j = 0; j < Y; j++) {
32 a[i][j] = (T)0;
33 }
34 }
35
36 // discard loop variables not needed here
37
38 return a[0][0];
39 }
40 };
41
teams_template_struct(void)42 int teams_template_struct(void) {
43 SS<int, 123, 456> V;
44 return V.foo();
45
46 }
47 #endif // CK1
48
49 // Test host codegen.
50 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
51 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
52 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
53 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
54 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
55 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
56
57 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
58 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
59 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
60 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
61 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
62 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
63 #ifdef CK2
64
65 template <typename T, int n, int m>
tmain(T argc)66 int tmain(T argc) {
67 T a[n][m];
68 #pragma omp target
69 #pragma omp teams distribute collapse(2)
70 for(int i = 0; i < n; i++) {
71 for(int j = 0; j < m; j++) {
72 a[i][j] = (T)0;
73 }
74 }
75 return 0;
76 }
77
main(int argc,char ** argv)78 int main (int argc, char **argv) {
79 int n = 100;
80 int m = 2;
81 int a[n][m];
82 #pragma omp target
83 #pragma omp teams distribute collapse(2)
84 for(int i = 0; i < n; i++) {
85 for(int j = 0; j < m; j++) {
86 a[i][j] = 0;
87 }
88 }
89 return tmain<int, 10, 2>(argc);
90 }
91
92
93
94
95
96 // discard loop variables not needed here
97
98 #endif // CK2
99 #endif // #ifndef HEADER
100 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv
101 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
102 // CHECK1-NEXT: entry:
103 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
104 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
105 // CHECK1-NEXT: ret i32 [[CALL]]
106 //
107 //
108 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
109 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
110 // CHECK1-NEXT: entry:
111 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
112 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
113 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
114 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
115 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
116 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
117 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
118 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
119 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
120 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
121 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
122 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8
123 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
124 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
125 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8
126 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
127 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8
128 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
129 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
130 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088)
131 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
132 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
133 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
134 // CHECK1: omp_offload.failed:
135 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
136 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
137 // CHECK1: omp_offload.cont:
138 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
139 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0
140 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0
141 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
142 // CHECK1-NEXT: ret i32 [[TMP9]]
143 //
144 //
145 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
146 // CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
147 // CHECK1-NEXT: entry:
148 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
149 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
150 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
151 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
152 // CHECK1-NEXT: ret void
153 //
154 //
155 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
156 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
157 // CHECK1-NEXT: entry:
158 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
159 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
160 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
161 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
162 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
163 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
164 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
165 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
166 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
167 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
168 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
169 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
170 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
171 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
172 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
173 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
174 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
175 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
176 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
177 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
178 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
179 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
180 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
181 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
182 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
183 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
184 // CHECK1: cond.true:
185 // CHECK1-NEXT: br label [[COND_END:%.*]]
186 // CHECK1: cond.false:
187 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
188 // CHECK1-NEXT: br label [[COND_END]]
189 // CHECK1: cond.end:
190 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
191 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
192 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
193 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
194 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
195 // CHECK1: omp.inner.for.cond:
196 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
197 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
198 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
199 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
200 // CHECK1: omp.inner.for.body:
201 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
202 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
203 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
204 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
205 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
206 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
207 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
208 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
209 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
210 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
211 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
212 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
213 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
214 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
215 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
216 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
217 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
218 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
219 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
220 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
221 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4
222 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
223 // CHECK1: omp.body.continue:
224 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
225 // CHECK1: omp.inner.for.inc:
226 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
227 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
228 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
229 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
230 // CHECK1: omp.inner.for.end:
231 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
232 // CHECK1: omp.loop.exit:
233 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
234 // CHECK1-NEXT: ret void
235 //
236 //
237 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
238 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
239 // CHECK1-NEXT: entry:
240 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
241 // CHECK1-NEXT: ret void
242 //
243 //
244 // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv
245 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
246 // CHECK2-NEXT: entry:
247 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
248 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
249 // CHECK2-NEXT: ret i32 [[CALL]]
250 //
251 //
252 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
253 // CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
254 // CHECK2-NEXT: entry:
255 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
256 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
257 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
258 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
259 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
260 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
261 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
262 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
263 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
264 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
265 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
266 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8
267 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
268 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
269 // CHECK2-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8
270 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
271 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8
272 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
273 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
274 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088)
275 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
276 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
277 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
278 // CHECK2: omp_offload.failed:
279 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
280 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
281 // CHECK2: omp_offload.cont:
282 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
283 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0
284 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0
285 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
286 // CHECK2-NEXT: ret i32 [[TMP9]]
287 //
288 //
289 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
290 // CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
291 // CHECK2-NEXT: entry:
292 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
293 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
294 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
295 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
296 // CHECK2-NEXT: ret void
297 //
298 //
299 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
300 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
301 // CHECK2-NEXT: entry:
302 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
303 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
304 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
305 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
306 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
307 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
308 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
309 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
310 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
311 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
312 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
313 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
314 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
315 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
316 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
317 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
318 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
319 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
320 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
321 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
322 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
323 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
324 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
325 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
326 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
327 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
328 // CHECK2: cond.true:
329 // CHECK2-NEXT: br label [[COND_END:%.*]]
330 // CHECK2: cond.false:
331 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
332 // CHECK2-NEXT: br label [[COND_END]]
333 // CHECK2: cond.end:
334 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
335 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
336 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
337 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
338 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
339 // CHECK2: omp.inner.for.cond:
340 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
341 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
342 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
343 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
344 // CHECK2: omp.inner.for.body:
345 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
346 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
347 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
348 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
349 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
350 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
351 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
352 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
353 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
354 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
355 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
356 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
357 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
358 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
359 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
360 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
361 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]]
362 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
363 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
364 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
365 // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4
366 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
367 // CHECK2: omp.body.continue:
368 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
369 // CHECK2: omp.inner.for.inc:
370 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
371 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
372 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
373 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
374 // CHECK2: omp.inner.for.end:
375 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
376 // CHECK2: omp.loop.exit:
377 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
378 // CHECK2-NEXT: ret void
379 //
380 //
381 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
382 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
383 // CHECK2-NEXT: entry:
384 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
385 // CHECK2-NEXT: ret void
386 //
387 //
388 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv
389 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
390 // CHECK3-NEXT: entry:
391 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
392 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
393 // CHECK3-NEXT: ret i32 [[CALL]]
394 //
395 //
396 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
397 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
398 // CHECK3-NEXT: entry:
399 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
400 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
401 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
402 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
403 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
404 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
405 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
406 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
407 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
408 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
409 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
410 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4
411 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
412 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
413 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4
414 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
415 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4
416 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
417 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
418 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088)
419 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
420 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
421 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
422 // CHECK3: omp_offload.failed:
423 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
424 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
425 // CHECK3: omp_offload.cont:
426 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
427 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0
428 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0
429 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
430 // CHECK3-NEXT: ret i32 [[TMP9]]
431 //
432 //
433 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
434 // CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
435 // CHECK3-NEXT: entry:
436 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
437 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
438 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
439 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
440 // CHECK3-NEXT: ret void
441 //
442 //
443 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
444 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
445 // CHECK3-NEXT: entry:
446 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
447 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
448 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
449 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
450 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
451 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
452 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
453 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
454 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
455 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
456 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
457 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4
458 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
459 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
460 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
461 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
462 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
463 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
464 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
465 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
466 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
467 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
468 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
469 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
470 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
471 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
472 // CHECK3: cond.true:
473 // CHECK3-NEXT: br label [[COND_END:%.*]]
474 // CHECK3: cond.false:
475 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
476 // CHECK3-NEXT: br label [[COND_END]]
477 // CHECK3: cond.end:
478 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
479 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
480 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
481 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
482 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
483 // CHECK3: omp.inner.for.cond:
484 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
485 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
486 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
487 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
488 // CHECK3: omp.inner.for.body:
489 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
490 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
491 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
492 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
493 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
494 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
495 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
496 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
497 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
498 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
499 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
500 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
501 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
502 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
503 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
504 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]]
505 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
506 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]]
507 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
508 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
509 // CHECK3: omp.body.continue:
510 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
511 // CHECK3: omp.inner.for.inc:
512 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
513 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
514 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
515 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
516 // CHECK3: omp.inner.for.end:
517 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
518 // CHECK3: omp.loop.exit:
519 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
520 // CHECK3-NEXT: ret void
521 //
522 //
523 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
524 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
525 // CHECK3-NEXT: entry:
526 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
527 // CHECK3-NEXT: ret void
528 //
529 //
530 // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv
531 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
532 // CHECK4-NEXT: entry:
533 // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
534 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]])
535 // CHECK4-NEXT: ret i32 [[CALL]]
536 //
537 //
538 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
539 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
540 // CHECK4-NEXT: entry:
541 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
542 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
543 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
544 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
545 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
546 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
547 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
548 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
549 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
550 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
551 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
552 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4
553 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
554 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]**
555 // CHECK4-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4
556 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
557 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4
558 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
559 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
560 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088)
561 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
562 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
563 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
564 // CHECK4: omp_offload.failed:
565 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
566 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
567 // CHECK4: omp_offload.cont:
568 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
569 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0
570 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0
571 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
572 // CHECK4-NEXT: ret i32 [[TMP9]]
573 //
574 //
575 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
576 // CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
577 // CHECK4-NEXT: entry:
578 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
579 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
580 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
581 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
582 // CHECK4-NEXT: ret void
583 //
584 //
585 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
586 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
587 // CHECK4-NEXT: entry:
588 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
589 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
590 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
591 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
592 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
593 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
594 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
595 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
596 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
597 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
598 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
599 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4
600 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
601 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
602 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
603 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
604 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
605 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4
606 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
607 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
608 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
609 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
610 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
611 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
612 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
613 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
614 // CHECK4: cond.true:
615 // CHECK4-NEXT: br label [[COND_END:%.*]]
616 // CHECK4: cond.false:
617 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
618 // CHECK4-NEXT: br label [[COND_END]]
619 // CHECK4: cond.end:
620 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
621 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
622 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
623 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
624 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
625 // CHECK4: omp.inner.for.cond:
626 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
627 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
628 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
629 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
630 // CHECK4: omp.inner.for.body:
631 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
632 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
633 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
634 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
635 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
636 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
637 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
638 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
639 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
640 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
641 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
642 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
643 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
644 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
645 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
646 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]]
647 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
648 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]]
649 // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
650 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
651 // CHECK4: omp.body.continue:
652 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
653 // CHECK4: omp.inner.for.inc:
654 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
655 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
656 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
657 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
658 // CHECK4: omp.inner.for.end:
659 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
660 // CHECK4: omp.loop.exit:
661 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
662 // CHECK4-NEXT: ret void
663 //
664 //
665 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
666 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
667 // CHECK4-NEXT: entry:
668 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
669 // CHECK4-NEXT: ret void
670 //
671 //
672 // CHECK9-LABEL: define {{[^@]+}}@main
673 // CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
674 // CHECK9-NEXT: entry:
675 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
676 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
677 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
678 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
679 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4
680 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
681 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
682 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
683 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
684 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
685 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
686 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
687 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
688 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
689 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
690 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
691 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
692 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
693 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
694 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
695 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
696 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
697 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4
698 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4
699 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
700 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
701 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4
702 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
703 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
704 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
705 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
706 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
707 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
708 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
709 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4
710 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
711 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
712 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
713 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4
714 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32*
715 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4
716 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8
717 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
718 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4
719 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
720 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
721 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8
722 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
723 // CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
724 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8
725 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
726 // CHECK9-NEXT: store i64 4, i64* [[TMP16]], align 8
727 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
728 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8
729 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
730 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
731 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8
732 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
733 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
734 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8
735 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
736 // CHECK9-NEXT: store i64 4, i64* [[TMP22]], align 8
737 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
738 // CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8
739 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
740 // CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
741 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8
742 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
743 // CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
744 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8
745 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
746 // CHECK9-NEXT: store i64 8, i64* [[TMP28]], align 8
747 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
748 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8
749 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
750 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
751 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8
752 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
753 // CHECK9-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
754 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8
755 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
756 // CHECK9-NEXT: store i64 8, i64* [[TMP34]], align 8
757 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
758 // CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8
759 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
760 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32**
761 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8
762 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
763 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32**
764 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8
765 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
766 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8
767 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
768 // CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8
769 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
770 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
771 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
772 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4
773 // CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4
774 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4
775 // CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4
776 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
777 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0
778 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
779 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64
780 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
781 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0
782 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
783 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
784 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]]
785 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
786 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8
787 // CHECK9-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8
788 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1
789 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]])
790 // CHECK9-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
791 // CHECK9-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
792 // CHECK9-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
793 // CHECK9: omp_offload.failed:
794 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
795 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
796 // CHECK9: omp_offload.cont:
797 // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
798 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]])
799 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
800 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
801 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]])
802 // CHECK9-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4
803 // CHECK9-NEXT: ret i32 [[TMP54]]
804 //
805 //
806 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82
807 // CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
808 // CHECK9-NEXT: entry:
809 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
810 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
811 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
812 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
813 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
814 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
815 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
816 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
817 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
818 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
819 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
820 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
821 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
822 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
823 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
824 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
825 // CHECK9-NEXT: ret void
826 //
827 //
828 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
829 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
830 // CHECK9-NEXT: entry:
831 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
832 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
833 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
834 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8
835 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
836 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
837 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
838 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
839 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
840 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
841 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
842 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
843 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
844 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
845 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
846 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
847 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
848 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
849 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
850 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4
851 // CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4
852 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
853 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
854 // CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
855 // CHECK9-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8
856 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
857 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
858 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
859 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
860 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8
861 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
862 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
863 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8
864 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
865 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
866 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4
867 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4
868 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
869 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0
870 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
871 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
872 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
873 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0
874 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
875 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
876 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
877 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
878 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
879 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4
880 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4
881 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
882 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
883 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
884 // CHECK9: land.lhs.true:
885 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
886 // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]
887 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
888 // CHECK9: omp.precond.then:
889 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
890 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
891 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8
892 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
893 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
894 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
895 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
896 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
897 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
898 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
899 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
900 // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
901 // CHECK9: cond.true:
902 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
903 // CHECK9-NEXT: br label [[COND_END:%.*]]
904 // CHECK9: cond.false:
905 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
906 // CHECK9-NEXT: br label [[COND_END]]
907 // CHECK9: cond.end:
908 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
909 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
910 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
911 // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
912 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
913 // CHECK9: omp.inner.for.cond:
914 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
915 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
916 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
917 // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
918 // CHECK9: omp.inner.for.body:
919 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
920 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
921 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
922 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
923 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
924 // CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
925 // CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
926 // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
927 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
928 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
929 // CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4
930 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
931 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
932 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
933 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
934 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
935 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
936 // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
937 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
938 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
939 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
940 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
941 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
942 // CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
943 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
944 // CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
945 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
946 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
947 // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
948 // CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4
949 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4
950 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
951 // CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
952 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]]
953 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4
954 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64
955 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]]
956 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4
957 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
958 // CHECK9: omp.body.continue:
959 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
960 // CHECK9: omp.inner.for.inc:
961 // CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
962 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1
963 // CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8
964 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
965 // CHECK9: omp.inner.for.end:
966 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
967 // CHECK9: omp.loop.exit:
968 // CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
969 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
970 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
971 // CHECK9-NEXT: br label [[OMP_PRECOND_END]]
972 // CHECK9: omp.precond.end:
973 // CHECK9-NEXT: ret void
974 //
975 //
976 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
977 // CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
978 // CHECK9-NEXT: entry:
979 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
980 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
981 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
982 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
983 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
984 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
985 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
986 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
987 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
988 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
989 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8
990 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
991 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
992 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8
993 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
994 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8
995 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
996 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
997 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20)
998 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
999 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
1000 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1001 // CHECK9: omp_offload.failed:
1002 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
1003 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
1004 // CHECK9: omp_offload.cont:
1005 // CHECK9-NEXT: ret i32 0
1006 //
1007 //
1008 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
1009 // CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1010 // CHECK9-NEXT: entry:
1011 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1012 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1013 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1014 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
1015 // CHECK9-NEXT: ret void
1016 //
1017 //
1018 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
1019 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1020 // CHECK9-NEXT: entry:
1021 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1022 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1023 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1024 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1025 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
1026 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1027 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1028 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1029 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1030 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1031 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1032 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
1033 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1034 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1035 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1036 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1037 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1038 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
1039 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1040 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1041 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1042 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1043 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1044 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1045 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1046 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1047 // CHECK9: cond.true:
1048 // CHECK9-NEXT: br label [[COND_END:%.*]]
1049 // CHECK9: cond.false:
1050 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1051 // CHECK9-NEXT: br label [[COND_END]]
1052 // CHECK9: cond.end:
1053 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1054 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1055 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1056 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1057 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1058 // CHECK9: omp.inner.for.cond:
1059 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1060 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1061 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1062 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1063 // CHECK9: omp.inner.for.body:
1064 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1065 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1066 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1067 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1068 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1069 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1070 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1071 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1072 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1073 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1074 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1075 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1076 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
1077 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1078 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1079 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
1080 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
1081 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
1082 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
1083 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4
1084 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1085 // CHECK9: omp.body.continue:
1086 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1087 // CHECK9: omp.inner.for.inc:
1088 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1089 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
1090 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
1091 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
1092 // CHECK9: omp.inner.for.end:
1093 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1094 // CHECK9: omp.loop.exit:
1095 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1096 // CHECK9-NEXT: ret void
1097 //
1098 //
1099 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1100 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
1101 // CHECK9-NEXT: entry:
1102 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
1103 // CHECK9-NEXT: ret void
1104 //
1105 //
1106 // CHECK10-LABEL: define {{[^@]+}}@main
1107 // CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1108 // CHECK10-NEXT: entry:
1109 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1110 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1111 // CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
1112 // CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
1113 // CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4
1114 // CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
1115 // CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1116 // CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1117 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
1118 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
1119 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1120 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1121 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1122 // CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1123 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
1124 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1125 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1126 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
1127 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
1128 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
1129 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1130 // CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
1131 // CHECK10-NEXT: store i32 100, i32* [[N]], align 4
1132 // CHECK10-NEXT: store i32 2, i32* [[M]], align 4
1133 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
1134 // CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1135 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4
1136 // CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
1137 // CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
1138 // CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
1139 // CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
1140 // CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
1141 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
1142 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8
1143 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4
1144 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1145 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
1146 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
1147 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4
1148 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32*
1149 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4
1150 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8
1151 // CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
1152 // CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4
1153 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1154 // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1155 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP13]], align 8
1156 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1157 // CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1158 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP15]], align 8
1159 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1160 // CHECK10-NEXT: store i64 4, i64* [[TMP16]], align 8
1161 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1162 // CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8
1163 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1164 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1165 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8
1166 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1167 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
1168 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8
1169 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1170 // CHECK10-NEXT: store i64 4, i64* [[TMP22]], align 8
1171 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1172 // CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8
1173 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1174 // CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1175 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP25]], align 8
1176 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1177 // CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1178 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8
1179 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1180 // CHECK10-NEXT: store i64 8, i64* [[TMP28]], align 8
1181 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1182 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8
1183 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1184 // CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1185 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8
1186 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1187 // CHECK10-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
1188 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP33]], align 8
1189 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1190 // CHECK10-NEXT: store i64 8, i64* [[TMP34]], align 8
1191 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1192 // CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8
1193 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1194 // CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32**
1195 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP37]], align 8
1196 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1197 // CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32**
1198 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP39]], align 8
1199 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1200 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP40]], align 8
1201 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1202 // CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8
1203 // CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1204 // CHECK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1205 // CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1206 // CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[N]], align 4
1207 // CHECK10-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_]], align 4
1208 // CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[M]], align 4
1209 // CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_3]], align 4
1210 // CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1211 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP47]], 0
1212 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1213 // CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64
1214 // CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1215 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP48]], 0
1216 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
1217 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
1218 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]]
1219 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
1220 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8
1221 // CHECK10-NEXT: [[TMP49:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8
1222 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP49]], 1
1223 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]])
1224 // CHECK10-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP42]], i8** [[TMP43]], i64* [[TMP44]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1225 // CHECK10-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
1226 // CHECK10-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1227 // CHECK10: omp_offload.failed:
1228 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
1229 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
1230 // CHECK10: omp_offload.cont:
1231 // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1232 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]])
1233 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
1234 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1235 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]])
1236 // CHECK10-NEXT: [[TMP54:%.*]] = load i32, i32* [[RETVAL]], align 4
1237 // CHECK10-NEXT: ret i32 [[TMP54]]
1238 //
1239 //
1240 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82
1241 // CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
1242 // CHECK10-NEXT: entry:
1243 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
1244 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
1245 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1246 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1247 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
1248 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
1249 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8
1250 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1251 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1252 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
1253 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1254 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32*
1255 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1256 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1257 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
1258 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]])
1259 // CHECK10-NEXT: ret void
1260 //
1261 //
1262 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
1263 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
1264 // CHECK10-NEXT: entry:
1265 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1266 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1267 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
1268 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8
1269 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1270 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1271 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
1272 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1273 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
1274 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
1275 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1276 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1277 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
1278 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
1279 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4
1280 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1281 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1282 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1283 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1284 // CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4
1285 // CHECK10-NEXT: [[J12:%.*]] = alloca i32, align 4
1286 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1287 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1288 // CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
1289 // CHECK10-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8
1290 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1291 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1292 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
1293 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
1294 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8
1295 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1296 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1297 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8
1298 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
1299 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
1300 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4
1301 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1302 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1303 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0
1304 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1305 // CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1306 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1307 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0
1308 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
1309 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
1310 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
1311 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
1312 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
1313 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4
1314 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4
1315 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1316 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
1317 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1318 // CHECK10: land.lhs.true:
1319 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1320 // CHECK10-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]
1321 // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1322 // CHECK10: omp.precond.then:
1323 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
1324 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1325 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8
1326 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1327 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1328 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1329 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
1330 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1331 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1332 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1333 // CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
1334 // CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1335 // CHECK10: cond.true:
1336 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1337 // CHECK10-NEXT: br label [[COND_END:%.*]]
1338 // CHECK10: cond.false:
1339 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1340 // CHECK10-NEXT: br label [[COND_END]]
1341 // CHECK10: cond.end:
1342 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
1343 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1344 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1345 // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
1346 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1347 // CHECK10: omp.inner.for.cond:
1348 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1349 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1350 // CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
1351 // CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1352 // CHECK10: omp.inner.for.body:
1353 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1354 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1355 // CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
1356 // CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
1357 // CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
1358 // CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
1359 // CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
1360 // CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
1361 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
1362 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
1363 // CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4
1364 // CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1365 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1366 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1367 // CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
1368 // CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
1369 // CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
1370 // CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
1371 // CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
1372 // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1373 // CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
1374 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
1375 // CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
1376 // CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
1377 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
1378 // CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
1379 // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
1380 // CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
1381 // CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
1382 // CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4
1383 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4
1384 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64
1385 // CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
1386 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]]
1387 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4
1388 // CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64
1389 // CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]]
1390 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4
1391 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1392 // CHECK10: omp.body.continue:
1393 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1394 // CHECK10: omp.inner.for.inc:
1395 // CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1396 // CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1
1397 // CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8
1398 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
1399 // CHECK10: omp.inner.for.end:
1400 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1401 // CHECK10: omp.loop.exit:
1402 // CHECK10-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1403 // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
1404 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
1405 // CHECK10-NEXT: br label [[OMP_PRECOND_END]]
1406 // CHECK10: omp.precond.end:
1407 // CHECK10-NEXT: ret void
1408 //
1409 //
1410 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1411 // CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
1412 // CHECK10-NEXT: entry:
1413 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1414 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1415 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1416 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1417 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1418 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
1419 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1420 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1421 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1422 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
1423 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8
1424 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1425 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
1426 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8
1427 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1428 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8
1429 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1430 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1431 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20)
1432 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1433 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
1434 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1435 // CHECK10: omp_offload.failed:
1436 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
1437 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
1438 // CHECK10: omp_offload.cont:
1439 // CHECK10-NEXT: ret i32 0
1440 //
1441 //
1442 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
1443 // CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1444 // CHECK10-NEXT: entry:
1445 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1446 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1447 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1448 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
1449 // CHECK10-NEXT: ret void
1450 //
1451 //
1452 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
1453 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1454 // CHECK10-NEXT: entry:
1455 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1456 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1457 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8
1458 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1459 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
1460 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1461 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1462 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1463 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1464 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1465 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
1466 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4
1467 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1468 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1469 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8
1470 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8
1471 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1472 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
1473 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1474 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1475 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1476 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1477 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1478 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1479 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1480 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1481 // CHECK10: cond.true:
1482 // CHECK10-NEXT: br label [[COND_END:%.*]]
1483 // CHECK10: cond.false:
1484 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1485 // CHECK10-NEXT: br label [[COND_END]]
1486 // CHECK10: cond.end:
1487 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1488 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1489 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1490 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1491 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1492 // CHECK10: omp.inner.for.cond:
1493 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1494 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1495 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1496 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1497 // CHECK10: omp.inner.for.body:
1498 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1499 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1500 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1501 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1502 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1503 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1504 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1505 // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1506 // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1507 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1508 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1509 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1510 // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
1511 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1512 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1513 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]]
1514 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
1515 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
1516 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
1517 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4
1518 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1519 // CHECK10: omp.body.continue:
1520 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1521 // CHECK10: omp.inner.for.inc:
1522 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1523 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
1524 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
1525 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
1526 // CHECK10: omp.inner.for.end:
1527 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1528 // CHECK10: omp.loop.exit:
1529 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1530 // CHECK10-NEXT: ret void
1531 //
1532 //
1533 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1534 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] {
1535 // CHECK10-NEXT: entry:
1536 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
1537 // CHECK10-NEXT: ret void
1538 //
1539 //
1540 // CHECK11-LABEL: define {{[^@]+}}@main
1541 // CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1542 // CHECK11-NEXT: entry:
1543 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1544 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1545 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
1546 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
1547 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4
1548 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
1549 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1550 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1551 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
1552 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
1553 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
1554 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
1555 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
1556 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
1557 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1558 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1559 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1560 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1561 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1562 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
1563 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1564 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
1565 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4
1566 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4
1567 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
1568 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4
1569 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
1570 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
1571 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1572 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
1573 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
1574 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4
1575 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
1576 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4
1577 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4
1578 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4
1579 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4
1580 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4
1581 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1582 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
1583 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
1584 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1585 // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
1586 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4
1587 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1588 // CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
1589 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4
1590 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1591 // CHECK11-NEXT: store i64 4, i64* [[TMP15]], align 4
1592 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1593 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4
1594 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1595 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
1596 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4
1597 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1598 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
1599 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4
1600 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1601 // CHECK11-NEXT: store i64 4, i64* [[TMP21]], align 4
1602 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1603 // CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4
1604 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1605 // CHECK11-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
1606 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4
1607 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1608 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
1609 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4
1610 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1611 // CHECK11-NEXT: store i64 4, i64* [[TMP27]], align 4
1612 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1613 // CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4
1614 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1615 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
1616 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4
1617 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1618 // CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
1619 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4
1620 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1621 // CHECK11-NEXT: store i64 4, i64* [[TMP33]], align 4
1622 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1623 // CHECK11-NEXT: store i8* null, i8** [[TMP34]], align 4
1624 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1625 // CHECK11-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32**
1626 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4
1627 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1628 // CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32**
1629 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4
1630 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1631 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4
1632 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1633 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4
1634 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1635 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1636 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1637 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4
1638 // CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
1639 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4
1640 // CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1641 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1642 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0
1643 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1644 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1645 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1646 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0
1647 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1648 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1649 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1650 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1651 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
1652 // CHECK11-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
1653 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1
1654 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]])
1655 // CHECK11-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1656 // CHECK11-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
1657 // CHECK11-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1658 // CHECK11: omp_offload.failed:
1659 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
1660 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
1661 // CHECK11: omp_offload.cont:
1662 // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1663 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]])
1664 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
1665 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
1666 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]])
1667 // CHECK11-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4
1668 // CHECK11-NEXT: ret i32 [[TMP53]]
1669 //
1670 //
1671 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82
1672 // CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
1673 // CHECK11-NEXT: entry:
1674 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1675 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
1676 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
1677 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
1678 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1679 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
1680 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
1681 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
1682 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
1683 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1684 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
1685 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
1686 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1687 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]])
1688 // CHECK11-NEXT: ret void
1689 //
1690 //
1691 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
1692 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
1693 // CHECK11-NEXT: entry:
1694 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1695 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1696 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
1697 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4
1698 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
1699 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
1700 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1701 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1702 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1703 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
1704 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1705 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1706 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
1707 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
1708 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
1709 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1710 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1711 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1712 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1713 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4
1714 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4
1715 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1716 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1717 // CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
1718 // CHECK11-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4
1719 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
1720 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
1721 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1722 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
1723 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4
1724 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
1725 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
1726 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1727 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
1728 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
1729 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4
1730 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1731 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1732 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0
1733 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1734 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1735 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1736 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0
1737 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
1738 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
1739 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
1740 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
1741 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
1742 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4
1743 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4
1744 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1745 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
1746 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1747 // CHECK11: land.lhs.true:
1748 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1749 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]
1750 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1751 // CHECK11: omp.precond.then:
1752 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
1753 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1754 // CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8
1755 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1756 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1757 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1758 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
1759 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1760 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1761 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1762 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
1763 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1764 // CHECK11: cond.true:
1765 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1766 // CHECK11-NEXT: br label [[COND_END:%.*]]
1767 // CHECK11: cond.false:
1768 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1769 // CHECK11-NEXT: br label [[COND_END]]
1770 // CHECK11: cond.end:
1771 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
1772 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1773 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1774 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
1775 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1776 // CHECK11: omp.inner.for.cond:
1777 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1778 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1779 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
1780 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1781 // CHECK11: omp.inner.for.body:
1782 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1783 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1784 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
1785 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
1786 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
1787 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
1788 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
1789 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
1790 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
1791 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
1792 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4
1793 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1794 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1795 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1796 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
1797 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
1798 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
1799 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
1800 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
1801 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1802 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
1803 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
1804 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
1805 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
1806 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
1807 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
1808 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
1809 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
1810 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
1811 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4
1812 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4
1813 // CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]
1814 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]]
1815 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4
1816 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]]
1817 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4
1818 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1819 // CHECK11: omp.body.continue:
1820 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1821 // CHECK11: omp.inner.for.inc:
1822 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1823 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1
1824 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8
1825 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
1826 // CHECK11: omp.inner.for.end:
1827 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1828 // CHECK11: omp.loop.exit:
1829 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1830 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
1831 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
1832 // CHECK11-NEXT: br label [[OMP_PRECOND_END]]
1833 // CHECK11: omp.precond.end:
1834 // CHECK11-NEXT: ret void
1835 //
1836 //
1837 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1838 // CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
1839 // CHECK11-NEXT: entry:
1840 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1841 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1842 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
1843 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
1844 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
1845 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1846 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1847 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1848 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1849 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
1850 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4
1851 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1852 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
1853 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4
1854 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1855 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4
1856 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1857 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1858 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20)
1859 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1860 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
1861 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1862 // CHECK11: omp_offload.failed:
1863 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
1864 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
1865 // CHECK11: omp_offload.cont:
1866 // CHECK11-NEXT: ret i32 0
1867 //
1868 //
1869 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
1870 // CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1871 // CHECK11-NEXT: entry:
1872 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
1873 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
1874 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
1875 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
1876 // CHECK11-NEXT: ret void
1877 //
1878 //
1879 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
1880 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1881 // CHECK11-NEXT: entry:
1882 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1883 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1884 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
1885 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1886 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1887 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1888 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1889 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1890 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1891 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1892 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
1893 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
1894 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1895 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1896 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
1897 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
1898 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1899 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
1900 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1901 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1902 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1903 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1904 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1905 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1906 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1907 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1908 // CHECK11: cond.true:
1909 // CHECK11-NEXT: br label [[COND_END:%.*]]
1910 // CHECK11: cond.false:
1911 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1912 // CHECK11-NEXT: br label [[COND_END]]
1913 // CHECK11: cond.end:
1914 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1915 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1916 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1917 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1918 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1919 // CHECK11: omp.inner.for.cond:
1920 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1921 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1922 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1923 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1924 // CHECK11: omp.inner.for.body:
1925 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1926 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1927 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1928 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1929 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1930 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1931 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1932 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1933 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1934 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1935 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1936 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1937 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
1938 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1939 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]]
1940 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
1941 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]]
1942 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
1943 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1944 // CHECK11: omp.body.continue:
1945 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1946 // CHECK11: omp.inner.for.inc:
1947 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1948 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
1949 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
1950 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
1951 // CHECK11: omp.inner.for.end:
1952 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1953 // CHECK11: omp.loop.exit:
1954 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1955 // CHECK11-NEXT: ret void
1956 //
1957 //
1958 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1959 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] {
1960 // CHECK11-NEXT: entry:
1961 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1)
1962 // CHECK11-NEXT: ret void
1963 //
1964 //
1965 // CHECK12-LABEL: define {{[^@]+}}@main
1966 // CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1967 // CHECK12-NEXT: entry:
1968 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1969 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1970 // CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
1971 // CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
1972 // CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4
1973 // CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
1974 // CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1975 // CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1976 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
1977 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
1978 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
1979 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
1980 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
1981 // CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
1982 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
1983 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1984 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1985 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1986 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1987 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
1988 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1989 // CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
1990 // CHECK12-NEXT: store i32 100, i32* [[N]], align 4
1991 // CHECK12-NEXT: store i32 2, i32* [[M]], align 4
1992 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
1993 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4
1994 // CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
1995 // CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
1996 // CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1997 // CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
1998 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
1999 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4
2000 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
2001 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4
2002 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4
2003 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4
2004 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4
2005 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4
2006 // CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
2007 // CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
2008 // CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
2009 // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2010 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
2011 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP12]], align 4
2012 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2013 // CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
2014 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP14]], align 4
2015 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2016 // CHECK12-NEXT: store i64 4, i64* [[TMP15]], align 4
2017 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2018 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4
2019 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2020 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
2021 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4
2022 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2023 // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
2024 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4
2025 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2026 // CHECK12-NEXT: store i64 4, i64* [[TMP21]], align 4
2027 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2028 // CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4
2029 // CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2030 // CHECK12-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
2031 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP24]], align 4
2032 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2033 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
2034 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4
2035 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2036 // CHECK12-NEXT: store i64 4, i64* [[TMP27]], align 4
2037 // CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2038 // CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4
2039 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2040 // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
2041 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4
2042 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2043 // CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
2044 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4
2045 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2046 // CHECK12-NEXT: store i64 4, i64* [[TMP33]], align 4
2047 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2048 // CHECK12-NEXT: store i8* null, i8** [[TMP34]], align 4
2049 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2050 // CHECK12-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32**
2051 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 4
2052 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2053 // CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32**
2054 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP38]], align 4
2055 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2056 // CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP39]], align 4
2057 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2058 // CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4
2059 // CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2060 // CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2061 // CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2062 // CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[N]], align 4
2063 // CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
2064 // CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[M]], align 4
2065 // CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2066 // CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2067 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP46]], 0
2068 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2069 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
2070 // CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2071 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP47]], 0
2072 // CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
2073 // CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
2074 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
2075 // CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
2076 // CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8
2077 // CHECK12-NEXT: [[TMP48:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8
2078 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP48]], 1
2079 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]])
2080 // CHECK12-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82.region_id, i32 5, i8** [[TMP41]], i8** [[TMP42]], i64* [[TMP43]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2081 // CHECK12-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
2082 // CHECK12-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2083 // CHECK12: omp_offload.failed:
2084 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
2085 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
2086 // CHECK12: omp_offload.cont:
2087 // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
2088 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]])
2089 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
2090 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
2091 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]])
2092 // CHECK12-NEXT: [[TMP53:%.*]] = load i32, i32* [[RETVAL]], align 4
2093 // CHECK12-NEXT: ret i32 [[TMP53]]
2094 //
2095 //
2096 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82
2097 // CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
2098 // CHECK12-NEXT: entry:
2099 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2100 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
2101 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2102 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2103 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
2104 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
2105 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4
2106 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2107 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2108 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
2109 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2110 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2111 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
2112 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]])
2113 // CHECK12-NEXT: ret void
2114 //
2115 //
2116 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
2117 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
2118 // CHECK12-NEXT: entry:
2119 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2120 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2121 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
2122 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4
2123 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2124 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2125 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
2126 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
2127 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
2128 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
2129 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2130 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
2131 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
2132 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
2133 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
2134 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2135 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2136 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2137 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2138 // CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4
2139 // CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4
2140 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2141 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2142 // CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
2143 // CHECK12-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4
2144 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2145 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2146 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
2147 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
2148 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4
2149 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2150 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2151 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4
2152 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
2153 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
2154 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4
2155 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4
2156 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2157 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0
2158 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2159 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
2160 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2161 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0
2162 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
2163 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
2164 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
2165 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
2166 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
2167 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4
2168 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4
2169 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2170 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
2171 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2172 // CHECK12: land.lhs.true:
2173 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2174 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]
2175 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2176 // CHECK12: omp.precond.then:
2177 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
2178 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
2179 // CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8
2180 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2181 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2182 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2183 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
2184 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2185 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2186 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
2187 // CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]
2188 // CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2189 // CHECK12: cond.true:
2190 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
2191 // CHECK12-NEXT: br label [[COND_END:%.*]]
2192 // CHECK12: cond.false:
2193 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2194 // CHECK12-NEXT: br label [[COND_END]]
2195 // CHECK12: cond.end:
2196 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]
2197 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
2198 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
2199 // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8
2200 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2201 // CHECK12: omp.inner.for.cond:
2202 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2203 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2204 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]
2205 // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2206 // CHECK12: omp.inner.for.body:
2207 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2208 // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2209 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0
2210 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
2211 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
2212 // CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
2213 // CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]
2214 // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
2215 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
2216 // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
2217 // CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4
2218 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2219 // CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2220 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2221 // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0
2222 // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
2223 // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
2224 // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
2225 // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]
2226 // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2227 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0
2228 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
2229 // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
2230 // CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
2231 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
2232 // CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]
2233 // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
2234 // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
2235 // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
2236 // CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4
2237 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4
2238 // CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]
2239 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]]
2240 // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4
2241 // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]]
2242 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4
2243 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2244 // CHECK12: omp.body.continue:
2245 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2246 // CHECK12: omp.inner.for.inc:
2247 // CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
2248 // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1
2249 // CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8
2250 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
2251 // CHECK12: omp.inner.for.end:
2252 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2253 // CHECK12: omp.loop.exit:
2254 // CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2255 // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4
2256 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]])
2257 // CHECK12-NEXT: br label [[OMP_PRECOND_END]]
2258 // CHECK12: omp.precond.end:
2259 // CHECK12-NEXT: ret void
2260 //
2261 //
2262 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
2263 // CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
2264 // CHECK12-NEXT: entry:
2265 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
2266 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
2267 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
2268 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
2269 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
2270 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
2271 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2272 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
2273 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2274 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]**
2275 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4
2276 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2277 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]**
2278 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4
2279 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2280 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4
2281 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2282 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2283 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20)
2284 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2285 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
2286 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2287 // CHECK12: omp_offload.failed:
2288 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68([10 x [2 x i32]]* [[A]]) #[[ATTR3]]
2289 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
2290 // CHECK12: omp_offload.cont:
2291 // CHECK12-NEXT: ret i32 0
2292 //
2293 //
2294 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68
2295 // CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
2296 // CHECK12-NEXT: entry:
2297 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
2298 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
2299 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
2300 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]])
2301 // CHECK12-NEXT: ret void
2302 //
2303 //
2304 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
2305 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
2306 // CHECK12-NEXT: entry:
2307 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2308 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2309 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4
2310 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2311 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
2312 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2313 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2314 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2315 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2316 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2317 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
2318 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
2319 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2320 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2321 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4
2322 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4
2323 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2324 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4
2325 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2326 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2327 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2328 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2329 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2330 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2331 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
2332 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2333 // CHECK12: cond.true:
2334 // CHECK12-NEXT: br label [[COND_END:%.*]]
2335 // CHECK12: cond.false:
2336 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2337 // CHECK12-NEXT: br label [[COND_END]]
2338 // CHECK12: cond.end:
2339 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2340 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2341 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2342 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
2343 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2344 // CHECK12: omp.inner.for.cond:
2345 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2346 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2347 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2348 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2349 // CHECK12: omp.inner.for.body:
2350 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2351 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
2352 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
2353 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2354 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2355 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2356 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2357 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
2358 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
2359 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
2360 // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
2361 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
2362 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4
2363 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2364 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]]
2365 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
2366 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]]
2367 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
2368 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2369 // CHECK12: omp.body.continue:
2370 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2371 // CHECK12: omp.inner.for.inc:
2372 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2373 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
2374 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
2375 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
2376 // CHECK12: omp.inner.for.end:
2377 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2378 // CHECK12: omp.loop.exit:
2379 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
2380 // CHECK12-NEXT: ret void
2381 //
2382 //
2383 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2384 // CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
2385 // CHECK12-NEXT: entry:
2386 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
2387 // CHECK12-NEXT: ret void
2388 //
2389 //