1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute parallel for simd private(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global, bound tid and loop vars
80
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84
85 // Skip global, bound tid and loop vars
86 [&]() {
87 g = 2;
88 g1 = 2;
89 sivar = 4;
90
91 }();
92 }
93 }();
94 return 0;
95
96
97 #else
98 #pragma omp target
99 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var, sivar)
100 for (int i = 0; i < 2; ++i) {
101 vec[i] = t_var;
102 s_arr[i] = var;
103 sivar += i;
104 }
105 return tmain<int>();
106 #endif
107 }
108
109
110
111 // Skip global, bound tid and loop vars
112
113 // private(s_arr)
114
115 // private(var)
116
117
118 // Skip global, bound tid and loop vars
119
120 // private(s_arr)
121
122 // private(var)
123
124
125
126
127 // Skip global, bound tid and loop vars
128
129 // private(s_arr)
130
131
132 // private(var)
133
134
135 // Skip global, bound tid and loop vars
136 // prev lb and ub
137 // iter variables
138
139 // private(s_arr)
140
141
142 // private(var)
143
144
145
146 #endif
147 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
148 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
149 // CHECK1-NEXT: entry:
150 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
151 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
152 // CHECK1-NEXT: ret void
153 //
154 //
155 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
156 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
157 // CHECK1-NEXT: entry:
158 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
159 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
160 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
161 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
162 // CHECK1-NEXT: ret void
163 //
164 //
165 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
166 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
167 // CHECK1-NEXT: entry:
168 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
169 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
170 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
171 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
172 // CHECK1-NEXT: ret void
173 //
174 //
175 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
176 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
177 // CHECK1-NEXT: entry:
178 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
179 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
180 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
181 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
182 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
183 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
184 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
185 // CHECK1-NEXT: ret void
186 //
187 //
188 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
189 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
190 // CHECK1-NEXT: entry:
191 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
192 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
193 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
194 // CHECK1-NEXT: ret void
195 //
196 //
197 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
198 // CHECK1-SAME: () #[[ATTR0]] {
199 // CHECK1-NEXT: entry:
200 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
201 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
202 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
203 // CHECK1-NEXT: ret void
204 //
205 //
206 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
207 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
208 // CHECK1-NEXT: entry:
209 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
210 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
211 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
212 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
213 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
214 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
215 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
216 // CHECK1-NEXT: ret void
217 //
218 //
219 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
220 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
221 // CHECK1-NEXT: entry:
222 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
223 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
224 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
225 // CHECK1: arraydestroy.body:
226 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
227 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
228 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
229 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
230 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
231 // CHECK1: arraydestroy.done1:
232 // CHECK1-NEXT: ret void
233 //
234 //
235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
236 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
237 // CHECK1-NEXT: entry:
238 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
239 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
240 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
241 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
242 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
243 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
244 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
245 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
246 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
247 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
248 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
249 // CHECK1-NEXT: ret void
250 //
251 //
252 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
253 // CHECK1-SAME: () #[[ATTR0]] {
254 // CHECK1-NEXT: entry:
255 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
256 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
257 // CHECK1-NEXT: ret void
258 //
259 //
260 // CHECK1-LABEL: define {{[^@]+}}@main
261 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
262 // CHECK1-NEXT: entry:
263 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
265 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
266 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
267 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
268 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
269 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
270 // CHECK1: omp_offload.failed:
271 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
272 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
273 // CHECK1: omp_offload.cont:
274 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
275 // CHECK1-NEXT: ret i32 [[CALL]]
276 //
277 //
278 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
279 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
280 // CHECK1-NEXT: entry:
281 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
282 // CHECK1-NEXT: ret void
283 //
284 //
285 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
286 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
287 // CHECK1-NEXT: entry:
288 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
289 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
290 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
291 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
292 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
293 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
294 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
295 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
296 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
297 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
298 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
299 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
300 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
303 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
304 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
305 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
306 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
307 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
308 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
309 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
310 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
311 // CHECK1: arrayctor.loop:
312 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
313 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
314 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
315 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
316 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
317 // CHECK1: arrayctor.cont:
318 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
319 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
320 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
321 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
322 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
323 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
324 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
325 // CHECK1: cond.true:
326 // CHECK1-NEXT: br label [[COND_END:%.*]]
327 // CHECK1: cond.false:
328 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
329 // CHECK1-NEXT: br label [[COND_END]]
330 // CHECK1: cond.end:
331 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
332 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
333 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
334 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
335 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
336 // CHECK1: omp.inner.for.cond:
337 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
338 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
339 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
340 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
341 // CHECK1: omp.inner.for.cond.cleanup:
342 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
343 // CHECK1: omp.inner.for.body:
344 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
345 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
346 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
347 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
348 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
349 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
350 // CHECK1: omp.inner.for.inc:
351 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
352 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
353 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
354 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
355 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
356 // CHECK1: omp.inner.for.end:
357 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
358 // CHECK1: omp.loop.exit:
359 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
360 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
361 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
362 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
363 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
364 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
365 // CHECK1: .omp.final.then:
366 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
367 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
368 // CHECK1: .omp.final.done:
369 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
370 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
371 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2
372 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
373 // CHECK1: arraydestroy.body:
374 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
375 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
376 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
377 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
378 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
379 // CHECK1: arraydestroy.done3:
380 // CHECK1-NEXT: ret void
381 //
382 //
383 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
384 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
385 // CHECK1-NEXT: entry:
386 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
387 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
388 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
389 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
390 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
391 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
392 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
393 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
394 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
395 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
396 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
397 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
398 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
399 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
400 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
401 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
402 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
403 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
404 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
405 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
406 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
407 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
408 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
409 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
410 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
411 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
412 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
413 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
414 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
415 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
416 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
417 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
418 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
419 // CHECK1: arrayctor.loop:
420 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
421 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
422 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
423 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
424 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
425 // CHECK1: arrayctor.cont:
426 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
427 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
428 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
429 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
430 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
431 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
432 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
433 // CHECK1: cond.true:
434 // CHECK1-NEXT: br label [[COND_END:%.*]]
435 // CHECK1: cond.false:
436 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
437 // CHECK1-NEXT: br label [[COND_END]]
438 // CHECK1: cond.end:
439 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
440 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
441 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
442 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
443 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
444 // CHECK1: omp.inner.for.cond:
445 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
446 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
447 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
448 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
449 // CHECK1: omp.inner.for.cond.cleanup:
450 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
451 // CHECK1: omp.inner.for.body:
452 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
453 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
454 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
455 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
456 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
457 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
458 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
459 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
460 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
461 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
462 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
463 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
464 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8*
465 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
466 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false)
467 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
468 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
469 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
470 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4
471 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
472 // CHECK1: omp.body.continue:
473 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
474 // CHECK1: omp.inner.for.inc:
475 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
476 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
477 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
478 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
479 // CHECK1: omp.inner.for.end:
480 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
481 // CHECK1: omp.loop.exit:
482 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
483 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
484 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
485 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
486 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
487 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
488 // CHECK1: .omp.final.then:
489 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
490 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
491 // CHECK1: .omp.final.done:
492 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
493 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
494 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2
495 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
496 // CHECK1: arraydestroy.body:
497 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
498 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
499 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
500 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
501 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
502 // CHECK1: arraydestroy.done8:
503 // CHECK1-NEXT: ret void
504 //
505 //
506 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
507 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
508 // CHECK1-NEXT: entry:
509 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
510 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
511 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
512 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
513 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
514 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
515 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
516 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
517 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
518 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
519 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
520 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
521 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
522 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
523 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
524 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
525 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
526 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
527 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
528 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
529 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
530 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
531 // CHECK1: omp_offload.failed:
532 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
533 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
534 // CHECK1: omp_offload.cont:
535 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
536 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
537 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
538 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
539 // CHECK1: arraydestroy.body:
540 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
541 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
542 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
543 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
544 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
545 // CHECK1: arraydestroy.done2:
546 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
547 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
548 // CHECK1-NEXT: ret i32 [[TMP4]]
549 //
550 //
551 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
552 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
553 // CHECK1-NEXT: entry:
554 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
555 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
556 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
557 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
558 // CHECK1-NEXT: ret void
559 //
560 //
561 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
562 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
563 // CHECK1-NEXT: entry:
564 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
565 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
566 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
567 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
568 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
569 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
570 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
571 // CHECK1-NEXT: ret void
572 //
573 //
574 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
575 // CHECK1-SAME: () #[[ATTR4]] {
576 // CHECK1-NEXT: entry:
577 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
578 // CHECK1-NEXT: ret void
579 //
580 //
581 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
582 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
583 // CHECK1-NEXT: entry:
584 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
585 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
586 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
587 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
588 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
589 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
590 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
591 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
592 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
593 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
594 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
595 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
596 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
597 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
598 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
599 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
600 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
601 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
602 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
603 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
604 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
605 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
606 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
607 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
608 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
609 // CHECK1: arrayctor.loop:
610 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
611 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
612 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
613 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
614 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
615 // CHECK1: arrayctor.cont:
616 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
617 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
618 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
619 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
620 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
621 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
622 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
623 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
624 // CHECK1: cond.true:
625 // CHECK1-NEXT: br label [[COND_END:%.*]]
626 // CHECK1: cond.false:
627 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
628 // CHECK1-NEXT: br label [[COND_END]]
629 // CHECK1: cond.end:
630 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
631 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
632 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
633 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
634 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
635 // CHECK1: omp.inner.for.cond:
636 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
637 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
638 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
639 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
640 // CHECK1: omp.inner.for.cond.cleanup:
641 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
642 // CHECK1: omp.inner.for.body:
643 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
644 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
645 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
646 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
647 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
648 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
649 // CHECK1: omp.inner.for.inc:
650 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
651 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
652 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
653 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
654 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
655 // CHECK1: omp.inner.for.end:
656 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
657 // CHECK1: omp.loop.exit:
658 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
659 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
660 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
661 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
662 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
663 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
664 // CHECK1: .omp.final.then:
665 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
666 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
667 // CHECK1: .omp.final.done:
668 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
669 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
670 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2
671 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
672 // CHECK1: arraydestroy.body:
673 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
674 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
675 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
676 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
677 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
678 // CHECK1: arraydestroy.done5:
679 // CHECK1-NEXT: ret void
680 //
681 //
682 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
683 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
684 // CHECK1-NEXT: entry:
685 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
686 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
687 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
688 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
689 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
690 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
691 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
692 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
693 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
694 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
695 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
696 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
697 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
698 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
699 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
700 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8
701 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
702 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
703 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
704 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
705 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
706 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
707 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
708 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
709 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
710 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
711 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
712 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
713 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
714 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
715 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
716 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
717 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
718 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
719 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
720 // CHECK1: arrayctor.loop:
721 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
722 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
723 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
724 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
725 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
726 // CHECK1: arrayctor.cont:
727 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
728 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8
729 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
730 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
731 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
732 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
733 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
734 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
735 // CHECK1: cond.true:
736 // CHECK1-NEXT: br label [[COND_END:%.*]]
737 // CHECK1: cond.false:
738 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
739 // CHECK1-NEXT: br label [[COND_END]]
740 // CHECK1: cond.end:
741 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
742 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
743 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
744 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
745 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
746 // CHECK1: omp.inner.for.cond:
747 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
748 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
749 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
750 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
751 // CHECK1: omp.inner.for.cond.cleanup:
752 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
753 // CHECK1: omp.inner.for.body:
754 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
755 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
756 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
757 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
758 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
759 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
760 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
761 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
762 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
763 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8
764 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
765 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
766 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]]
767 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8*
768 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
769 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)
770 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
771 // CHECK1: omp.body.continue:
772 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
773 // CHECK1: omp.inner.for.inc:
774 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
775 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
776 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
777 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
778 // CHECK1: omp.inner.for.end:
779 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
780 // CHECK1: omp.loop.exit:
781 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
782 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
783 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
784 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
785 // CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
786 // CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
787 // CHECK1: .omp.final.then:
788 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
789 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
790 // CHECK1: .omp.final.done:
791 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
792 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
793 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2
794 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
795 // CHECK1: arraydestroy.body:
796 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
797 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
798 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
799 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
800 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
801 // CHECK1: arraydestroy.done9:
802 // CHECK1-NEXT: ret void
803 //
804 //
805 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
806 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
807 // CHECK1-NEXT: entry:
808 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
809 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
810 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
811 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
812 // CHECK1-NEXT: ret void
813 //
814 //
815 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
816 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
817 // CHECK1-NEXT: entry:
818 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
819 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
820 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
821 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
822 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
823 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
824 // CHECK1-NEXT: ret void
825 //
826 //
827 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
828 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
829 // CHECK1-NEXT: entry:
830 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
831 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
832 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
833 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
834 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
835 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
836 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
837 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
838 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
839 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
840 // CHECK1-NEXT: ret void
841 //
842 //
843 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
844 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
845 // CHECK1-NEXT: entry:
846 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
847 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
848 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
849 // CHECK1-NEXT: ret void
850 //
851 //
852 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
853 // CHECK1-SAME: () #[[ATTR0]] {
854 // CHECK1-NEXT: entry:
855 // CHECK1-NEXT: call void @__cxx_global_var_init()
856 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
857 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
858 // CHECK1-NEXT: ret void
859 //
860 //
861 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
862 // CHECK1-SAME: () #[[ATTR0]] {
863 // CHECK1-NEXT: entry:
864 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
865 // CHECK1-NEXT: ret void
866 //
867 //
868 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
869 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
870 // CHECK2-NEXT: entry:
871 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
872 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
873 // CHECK2-NEXT: ret void
874 //
875 //
876 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
877 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
878 // CHECK2-NEXT: entry:
879 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
880 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
881 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
882 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
883 // CHECK2-NEXT: ret void
884 //
885 //
886 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
887 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
888 // CHECK2-NEXT: entry:
889 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
890 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
891 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
892 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
893 // CHECK2-NEXT: ret void
894 //
895 //
896 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
897 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
898 // CHECK2-NEXT: entry:
899 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
900 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
901 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
902 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
903 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
904 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
905 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
906 // CHECK2-NEXT: ret void
907 //
908 //
909 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
910 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
911 // CHECK2-NEXT: entry:
912 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
913 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
914 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
915 // CHECK2-NEXT: ret void
916 //
917 //
918 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
919 // CHECK2-SAME: () #[[ATTR0]] {
920 // CHECK2-NEXT: entry:
921 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
922 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
923 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
924 // CHECK2-NEXT: ret void
925 //
926 //
927 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
928 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
929 // CHECK2-NEXT: entry:
930 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
931 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
932 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
933 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
934 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
935 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
936 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
937 // CHECK2-NEXT: ret void
938 //
939 //
940 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
941 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
942 // CHECK2-NEXT: entry:
943 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
944 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
945 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
946 // CHECK2: arraydestroy.body:
947 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
948 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
949 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
950 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
951 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
952 // CHECK2: arraydestroy.done1:
953 // CHECK2-NEXT: ret void
954 //
955 //
956 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
957 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
958 // CHECK2-NEXT: entry:
959 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
960 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
961 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
962 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
963 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
964 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
965 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
966 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
967 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
968 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
969 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
970 // CHECK2-NEXT: ret void
971 //
972 //
973 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
974 // CHECK2-SAME: () #[[ATTR0]] {
975 // CHECK2-NEXT: entry:
976 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
977 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
978 // CHECK2-NEXT: ret void
979 //
980 //
981 // CHECK2-LABEL: define {{[^@]+}}@main
982 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
983 // CHECK2-NEXT: entry:
984 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
985 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
986 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
987 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
988 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
989 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
990 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
991 // CHECK2: omp_offload.failed:
992 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
993 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
994 // CHECK2: omp_offload.cont:
995 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
996 // CHECK2-NEXT: ret i32 [[CALL]]
997 //
998 //
999 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
1000 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
1001 // CHECK2-NEXT: entry:
1002 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1003 // CHECK2-NEXT: ret void
1004 //
1005 //
1006 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1007 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1008 // CHECK2-NEXT: entry:
1009 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1010 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1011 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1012 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1013 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1014 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1015 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1016 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1017 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1018 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1019 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1020 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1021 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1022 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1023 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1024 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1025 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1026 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1027 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1028 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1029 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1030 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1031 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1032 // CHECK2: arrayctor.loop:
1033 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1034 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1035 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1036 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1037 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1038 // CHECK2: arrayctor.cont:
1039 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1040 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1041 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1042 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1043 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1044 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1045 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1046 // CHECK2: cond.true:
1047 // CHECK2-NEXT: br label [[COND_END:%.*]]
1048 // CHECK2: cond.false:
1049 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1050 // CHECK2-NEXT: br label [[COND_END]]
1051 // CHECK2: cond.end:
1052 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1053 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1054 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1055 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1056 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1057 // CHECK2: omp.inner.for.cond:
1058 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1059 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1060 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1061 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1062 // CHECK2: omp.inner.for.cond.cleanup:
1063 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1064 // CHECK2: omp.inner.for.body:
1065 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1066 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1067 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1068 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1069 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
1070 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1071 // CHECK2: omp.inner.for.inc:
1072 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1073 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1074 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1075 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1076 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1077 // CHECK2: omp.inner.for.end:
1078 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1079 // CHECK2: omp.loop.exit:
1080 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1081 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
1082 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
1083 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1084 // CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
1085 // CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1086 // CHECK2: .omp.final.then:
1087 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1088 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1089 // CHECK2: .omp.final.done:
1090 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1091 // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1092 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2
1093 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1094 // CHECK2: arraydestroy.body:
1095 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1096 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1097 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1098 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1099 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1100 // CHECK2: arraydestroy.done3:
1101 // CHECK2-NEXT: ret void
1102 //
1103 //
1104 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1105 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1106 // CHECK2-NEXT: entry:
1107 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1108 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1109 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1110 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1111 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1112 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1113 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1114 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1115 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1116 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1117 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1118 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1119 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1120 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1121 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1122 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1123 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1124 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1125 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1126 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1127 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1128 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1129 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1130 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1131 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1132 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1133 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1134 // CHECK2-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1135 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1136 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1137 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1138 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1139 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1140 // CHECK2: arrayctor.loop:
1141 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1142 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1143 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1144 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1145 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1146 // CHECK2: arrayctor.cont:
1147 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1148 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1149 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1150 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1151 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1152 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1153 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1154 // CHECK2: cond.true:
1155 // CHECK2-NEXT: br label [[COND_END:%.*]]
1156 // CHECK2: cond.false:
1157 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1158 // CHECK2-NEXT: br label [[COND_END]]
1159 // CHECK2: cond.end:
1160 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1161 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1162 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1163 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1164 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1165 // CHECK2: omp.inner.for.cond:
1166 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1167 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1168 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1169 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1170 // CHECK2: omp.inner.for.cond.cleanup:
1171 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1172 // CHECK2: omp.inner.for.body:
1173 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1174 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1175 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1176 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1177 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
1178 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1179 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1180 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1181 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
1182 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
1183 // CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
1184 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
1185 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8*
1186 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1187 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false)
1188 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1189 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
1190 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1191 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4
1192 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1193 // CHECK2: omp.body.continue:
1194 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1195 // CHECK2: omp.inner.for.inc:
1196 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1197 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
1198 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
1199 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1200 // CHECK2: omp.inner.for.end:
1201 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1202 // CHECK2: omp.loop.exit:
1203 // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1204 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
1205 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
1206 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1207 // CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1208 // CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1209 // CHECK2: .omp.final.then:
1210 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1211 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1212 // CHECK2: .omp.final.done:
1213 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1214 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1215 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2
1216 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1217 // CHECK2: arraydestroy.body:
1218 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1219 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1220 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1221 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1222 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1223 // CHECK2: arraydestroy.done8:
1224 // CHECK2-NEXT: ret void
1225 //
1226 //
1227 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1228 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat {
1229 // CHECK2-NEXT: entry:
1230 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1231 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1232 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1233 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1234 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1235 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1236 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1237 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1238 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1239 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
1240 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1241 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1242 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1243 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
1244 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1245 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
1246 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1247 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1248 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1249 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
1250 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1251 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1252 // CHECK2: omp_offload.failed:
1253 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1254 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1255 // CHECK2: omp_offload.cont:
1256 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1257 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1258 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1259 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1260 // CHECK2: arraydestroy.body:
1261 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1262 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1263 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1264 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1265 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1266 // CHECK2: arraydestroy.done2:
1267 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1268 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1269 // CHECK2-NEXT: ret i32 [[TMP4]]
1270 //
1271 //
1272 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1273 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1274 // CHECK2-NEXT: entry:
1275 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1276 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1277 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1278 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1279 // CHECK2-NEXT: ret void
1280 //
1281 //
1282 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1283 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1284 // CHECK2-NEXT: entry:
1285 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1286 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1287 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1288 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1289 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1290 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1291 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
1292 // CHECK2-NEXT: ret void
1293 //
1294 //
1295 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1296 // CHECK2-SAME: () #[[ATTR4]] {
1297 // CHECK2-NEXT: entry:
1298 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1299 // CHECK2-NEXT: ret void
1300 //
1301 //
1302 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1303 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1304 // CHECK2-NEXT: entry:
1305 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1306 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1307 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1308 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1309 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1310 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1311 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1312 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1313 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1314 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1315 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1316 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1317 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1318 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
1319 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1320 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1321 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1322 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1323 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1324 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1325 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1326 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1327 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1328 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1329 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1330 // CHECK2: arrayctor.loop:
1331 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1332 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1333 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1334 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1335 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1336 // CHECK2: arrayctor.cont:
1337 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1338 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
1339 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1340 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1341 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1342 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1343 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1344 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1345 // CHECK2: cond.true:
1346 // CHECK2-NEXT: br label [[COND_END:%.*]]
1347 // CHECK2: cond.false:
1348 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1349 // CHECK2-NEXT: br label [[COND_END]]
1350 // CHECK2: cond.end:
1351 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1352 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1353 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1354 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1355 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1356 // CHECK2: omp.inner.for.cond:
1357 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1358 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1359 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1360 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1361 // CHECK2: omp.inner.for.cond.cleanup:
1362 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1363 // CHECK2: omp.inner.for.body:
1364 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1365 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1366 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1367 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1368 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
1369 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1370 // CHECK2: omp.inner.for.inc:
1371 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1372 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1373 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1374 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1375 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
1376 // CHECK2: omp.inner.for.end:
1377 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1378 // CHECK2: omp.loop.exit:
1379 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1380 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
1381 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
1382 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1383 // CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
1384 // CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1385 // CHECK2: .omp.final.then:
1386 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1387 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1388 // CHECK2: .omp.final.done:
1389 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1390 // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1391 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2
1392 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1393 // CHECK2: arraydestroy.body:
1394 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1395 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1396 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1397 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1398 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1399 // CHECK2: arraydestroy.done5:
1400 // CHECK2-NEXT: ret void
1401 //
1402 //
1403 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
1404 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1405 // CHECK2-NEXT: entry:
1406 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1407 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1408 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1409 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1410 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1411 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1412 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1413 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1414 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1415 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1416 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1417 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1418 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1419 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1420 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1421 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8
1422 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1423 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1424 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1425 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1426 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1427 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1428 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1429 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1430 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1431 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1432 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1433 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
1434 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1435 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
1436 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1437 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1438 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1439 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1440 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1441 // CHECK2: arrayctor.loop:
1442 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1443 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1444 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1445 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1446 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1447 // CHECK2: arrayctor.cont:
1448 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1449 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8
1450 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1451 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1452 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1453 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1454 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1455 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1456 // CHECK2: cond.true:
1457 // CHECK2-NEXT: br label [[COND_END:%.*]]
1458 // CHECK2: cond.false:
1459 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1460 // CHECK2-NEXT: br label [[COND_END]]
1461 // CHECK2: cond.end:
1462 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1463 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1464 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1465 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1466 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1467 // CHECK2: omp.inner.for.cond:
1468 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1469 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1470 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1471 // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1472 // CHECK2: omp.inner.for.cond.cleanup:
1473 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1474 // CHECK2: omp.inner.for.body:
1475 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1476 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1477 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1478 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1479 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
1480 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1481 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1482 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1483 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
1484 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8
1485 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1486 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
1487 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]]
1488 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8*
1489 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
1490 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)
1491 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1492 // CHECK2: omp.body.continue:
1493 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1494 // CHECK2: omp.inner.for.inc:
1495 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1496 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
1497 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
1498 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1499 // CHECK2: omp.inner.for.end:
1500 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1501 // CHECK2: omp.loop.exit:
1502 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1503 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
1504 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
1505 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1506 // CHECK2-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
1507 // CHECK2-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1508 // CHECK2: .omp.final.then:
1509 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1510 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1511 // CHECK2: .omp.final.done:
1512 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1513 // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1514 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2
1515 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1516 // CHECK2: arraydestroy.body:
1517 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1518 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1519 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1520 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
1521 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
1522 // CHECK2: arraydestroy.done9:
1523 // CHECK2-NEXT: ret void
1524 //
1525 //
1526 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1527 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1528 // CHECK2-NEXT: entry:
1529 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1530 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1531 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1532 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1533 // CHECK2-NEXT: ret void
1534 //
1535 //
1536 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1537 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1538 // CHECK2-NEXT: entry:
1539 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1540 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1541 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1542 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1543 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1544 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1545 // CHECK2-NEXT: ret void
1546 //
1547 //
1548 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1549 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1550 // CHECK2-NEXT: entry:
1551 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1552 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1553 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1554 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1555 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1556 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1557 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1558 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1559 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1560 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1561 // CHECK2-NEXT: ret void
1562 //
1563 //
1564 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1565 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1566 // CHECK2-NEXT: entry:
1567 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1568 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1569 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1570 // CHECK2-NEXT: ret void
1571 //
1572 //
1573 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
1574 // CHECK2-SAME: () #[[ATTR0]] {
1575 // CHECK2-NEXT: entry:
1576 // CHECK2-NEXT: call void @__cxx_global_var_init()
1577 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
1578 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
1579 // CHECK2-NEXT: ret void
1580 //
1581 //
1582 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1583 // CHECK2-SAME: () #[[ATTR0]] {
1584 // CHECK2-NEXT: entry:
1585 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
1586 // CHECK2-NEXT: ret void
1587 //
1588 //
1589 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1590 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1591 // CHECK3-NEXT: entry:
1592 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1593 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1594 // CHECK3-NEXT: ret void
1595 //
1596 //
1597 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1598 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1599 // CHECK3-NEXT: entry:
1600 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1601 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1602 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1603 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1604 // CHECK3-NEXT: ret void
1605 //
1606 //
1607 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1608 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1609 // CHECK3-NEXT: entry:
1610 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1611 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1612 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1613 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1614 // CHECK3-NEXT: ret void
1615 //
1616 //
1617 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1618 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1619 // CHECK3-NEXT: entry:
1620 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1621 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1622 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1623 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1624 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1625 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1626 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
1627 // CHECK3-NEXT: ret void
1628 //
1629 //
1630 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1631 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1632 // CHECK3-NEXT: entry:
1633 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1634 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1635 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1636 // CHECK3-NEXT: ret void
1637 //
1638 //
1639 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1640 // CHECK3-SAME: () #[[ATTR0]] {
1641 // CHECK3-NEXT: entry:
1642 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1643 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1644 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1645 // CHECK3-NEXT: ret void
1646 //
1647 //
1648 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1649 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1650 // CHECK3-NEXT: entry:
1651 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1652 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1653 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1654 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1655 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1656 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1657 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1658 // CHECK3-NEXT: ret void
1659 //
1660 //
1661 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1662 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1663 // CHECK3-NEXT: entry:
1664 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1665 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1666 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1667 // CHECK3: arraydestroy.body:
1668 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1669 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1670 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1671 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1672 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1673 // CHECK3: arraydestroy.done1:
1674 // CHECK3-NEXT: ret void
1675 //
1676 //
1677 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1678 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1679 // CHECK3-NEXT: entry:
1680 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1681 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1682 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1683 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1684 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1685 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1686 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1687 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1688 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1689 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1690 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1691 // CHECK3-NEXT: ret void
1692 //
1693 //
1694 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1695 // CHECK3-SAME: () #[[ATTR0]] {
1696 // CHECK3-NEXT: entry:
1697 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1698 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1699 // CHECK3-NEXT: ret void
1700 //
1701 //
1702 // CHECK3-LABEL: define {{[^@]+}}@main
1703 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1704 // CHECK3-NEXT: entry:
1705 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1706 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1707 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1708 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
1709 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
1710 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
1711 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1712 // CHECK3: omp_offload.failed:
1713 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
1714 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1715 // CHECK3: omp_offload.cont:
1716 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1717 // CHECK3-NEXT: ret i32 [[CALL]]
1718 //
1719 //
1720 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
1721 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1722 // CHECK3-NEXT: entry:
1723 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1724 // CHECK3-NEXT: ret void
1725 //
1726 //
1727 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1728 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1729 // CHECK3-NEXT: entry:
1730 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1731 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1732 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1733 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1734 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1735 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1736 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1737 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1738 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1739 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1740 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1741 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1742 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1743 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1744 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1745 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1746 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1747 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1748 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1749 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1750 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1751 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1752 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1753 // CHECK3: arrayctor.loop:
1754 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1755 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1756 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1757 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1758 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1759 // CHECK3: arrayctor.cont:
1760 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1761 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1762 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1763 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1764 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1765 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1766 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1767 // CHECK3: cond.true:
1768 // CHECK3-NEXT: br label [[COND_END:%.*]]
1769 // CHECK3: cond.false:
1770 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1771 // CHECK3-NEXT: br label [[COND_END]]
1772 // CHECK3: cond.end:
1773 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1774 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1775 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1776 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1777 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1778 // CHECK3: omp.inner.for.cond:
1779 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1780 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1781 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1782 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1783 // CHECK3: omp.inner.for.cond.cleanup:
1784 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1785 // CHECK3: omp.inner.for.body:
1786 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1787 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1788 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
1789 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1790 // CHECK3: omp.inner.for.inc:
1791 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1792 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1793 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1794 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1795 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
1796 // CHECK3: omp.inner.for.end:
1797 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1798 // CHECK3: omp.loop.exit:
1799 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1800 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1801 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
1802 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1803 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1804 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1805 // CHECK3: .omp.final.then:
1806 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1807 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1808 // CHECK3: .omp.final.done:
1809 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1810 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1811 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2
1812 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1813 // CHECK3: arraydestroy.body:
1814 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1815 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1816 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1817 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1818 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1819 // CHECK3: arraydestroy.done3:
1820 // CHECK3-NEXT: ret void
1821 //
1822 //
1823 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1824 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1825 // CHECK3-NEXT: entry:
1826 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1827 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1828 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1829 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1830 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1831 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1832 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1833 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1834 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1835 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1836 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1837 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1838 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1839 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1840 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1841 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1842 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1843 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1844 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1845 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1846 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1847 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1848 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1849 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1850 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
1851 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
1852 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1853 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1854 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1855 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1856 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1857 // CHECK3: arrayctor.loop:
1858 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1859 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1860 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1861 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1862 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1863 // CHECK3: arrayctor.cont:
1864 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1865 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1866 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1867 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1868 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1869 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1870 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1871 // CHECK3: cond.true:
1872 // CHECK3-NEXT: br label [[COND_END:%.*]]
1873 // CHECK3: cond.false:
1874 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1875 // CHECK3-NEXT: br label [[COND_END]]
1876 // CHECK3: cond.end:
1877 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1878 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1879 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1880 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1881 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1882 // CHECK3: omp.inner.for.cond:
1883 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1884 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1885 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1886 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1887 // CHECK3: omp.inner.for.cond.cleanup:
1888 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1889 // CHECK3: omp.inner.for.body:
1890 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1891 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1892 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1893 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1894 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
1895 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1896 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
1897 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
1898 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
1899 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]]
1900 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1901 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1902 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false)
1903 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1904 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
1905 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1906 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
1907 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1908 // CHECK3: omp.body.continue:
1909 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1910 // CHECK3: omp.inner.for.inc:
1911 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1912 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1
1913 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
1914 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1915 // CHECK3: omp.inner.for.end:
1916 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1917 // CHECK3: omp.loop.exit:
1918 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1919 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
1920 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
1921 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1922 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1923 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1924 // CHECK3: .omp.final.then:
1925 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1926 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1927 // CHECK3: .omp.final.done:
1928 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1929 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1930 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1931 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1932 // CHECK3: arraydestroy.body:
1933 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1934 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1935 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1936 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1937 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1938 // CHECK3: arraydestroy.done6:
1939 // CHECK3-NEXT: ret void
1940 //
1941 //
1942 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1943 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1944 // CHECK3-NEXT: entry:
1945 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1946 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1947 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1948 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1949 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1950 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1951 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1952 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1953 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1954 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1955 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1956 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1957 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1958 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1959 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1960 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1961 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1962 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1963 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1964 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
1965 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1966 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1967 // CHECK3: omp_offload.failed:
1968 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1969 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1970 // CHECK3: omp_offload.cont:
1971 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1972 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1973 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1974 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1975 // CHECK3: arraydestroy.body:
1976 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1977 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1978 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1979 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1980 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1981 // CHECK3: arraydestroy.done2:
1982 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1983 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1984 // CHECK3-NEXT: ret i32 [[TMP4]]
1985 //
1986 //
1987 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1988 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1989 // CHECK3-NEXT: entry:
1990 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1991 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1992 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1993 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1994 // CHECK3-NEXT: ret void
1995 //
1996 //
1997 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1998 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1999 // CHECK3-NEXT: entry:
2000 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2001 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2002 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2003 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2004 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2005 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2006 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2007 // CHECK3-NEXT: ret void
2008 //
2009 //
2010 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
2011 // CHECK3-SAME: () #[[ATTR4]] {
2012 // CHECK3-NEXT: entry:
2013 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
2014 // CHECK3-NEXT: ret void
2015 //
2016 //
2017 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
2018 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
2019 // CHECK3-NEXT: entry:
2020 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2021 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2022 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2023 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2024 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2025 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2026 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2027 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2028 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2029 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2030 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2031 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2032 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2033 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2034 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2035 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2036 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2037 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2038 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2039 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2040 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2041 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2042 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2043 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2044 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2045 // CHECK3: arrayctor.loop:
2046 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2047 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2048 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2049 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2050 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2051 // CHECK3: arrayctor.cont:
2052 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2053 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2054 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2055 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2056 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2057 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2058 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2059 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2060 // CHECK3: cond.true:
2061 // CHECK3-NEXT: br label [[COND_END:%.*]]
2062 // CHECK3: cond.false:
2063 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2064 // CHECK3-NEXT: br label [[COND_END]]
2065 // CHECK3: cond.end:
2066 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2067 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2068 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2069 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2070 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2071 // CHECK3: omp.inner.for.cond:
2072 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2073 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2074 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2075 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2076 // CHECK3: omp.inner.for.cond.cleanup:
2077 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2078 // CHECK3: omp.inner.for.body:
2079 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2080 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2081 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
2082 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2083 // CHECK3: omp.inner.for.inc:
2084 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2085 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2086 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2087 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2088 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2089 // CHECK3: omp.inner.for.end:
2090 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2091 // CHECK3: omp.loop.exit:
2092 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2093 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2094 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
2095 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2096 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2097 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2098 // CHECK3: .omp.final.then:
2099 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
2100 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2101 // CHECK3: .omp.final.done:
2102 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2103 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2104 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2
2105 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2106 // CHECK3: arraydestroy.body:
2107 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2108 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2109 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2110 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2111 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2112 // CHECK3: arraydestroy.done5:
2113 // CHECK3-NEXT: ret void
2114 //
2115 //
2116 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
2117 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
2118 // CHECK3-NEXT: entry:
2119 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2120 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2121 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2122 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2123 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2124 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2125 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2126 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2127 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2128 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2129 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2130 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2131 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2132 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2133 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2134 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2135 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2136 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2137 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2138 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2139 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2140 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2141 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2142 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2143 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2144 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2145 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
2146 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
2147 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2148 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2149 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2150 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2151 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2152 // CHECK3: arrayctor.loop:
2153 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2154 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2155 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2156 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2157 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2158 // CHECK3: arrayctor.cont:
2159 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2160 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2161 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2162 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2163 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2164 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2165 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2166 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2167 // CHECK3: cond.true:
2168 // CHECK3-NEXT: br label [[COND_END:%.*]]
2169 // CHECK3: cond.false:
2170 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2171 // CHECK3-NEXT: br label [[COND_END]]
2172 // CHECK3: cond.end:
2173 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2174 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2175 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2176 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2177 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2178 // CHECK3: omp.inner.for.cond:
2179 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2180 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2181 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2182 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2183 // CHECK3: omp.inner.for.cond.cleanup:
2184 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2185 // CHECK3: omp.inner.for.body:
2186 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2187 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2188 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2189 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2190 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
2191 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2192 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
2193 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
2194 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
2195 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2196 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]]
2197 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
2198 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
2199 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)
2200 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2201 // CHECK3: omp.body.continue:
2202 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2203 // CHECK3: omp.inner.for.inc:
2204 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2205 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
2206 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
2207 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
2208 // CHECK3: omp.inner.for.end:
2209 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2210 // CHECK3: omp.loop.exit:
2211 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2212 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
2213 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
2214 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2215 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
2216 // CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2217 // CHECK3: .omp.final.then:
2218 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
2219 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2220 // CHECK3: .omp.final.done:
2221 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2222 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2223 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
2224 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2225 // CHECK3: arraydestroy.body:
2226 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2227 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2228 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2229 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2230 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2231 // CHECK3: arraydestroy.done7:
2232 // CHECK3-NEXT: ret void
2233 //
2234 //
2235 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2236 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2237 // CHECK3-NEXT: entry:
2238 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2239 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2240 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2241 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2242 // CHECK3-NEXT: ret void
2243 //
2244 //
2245 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2246 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2247 // CHECK3-NEXT: entry:
2248 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2249 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2250 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2251 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2252 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2253 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2254 // CHECK3-NEXT: ret void
2255 //
2256 //
2257 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2258 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2259 // CHECK3-NEXT: entry:
2260 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2261 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2262 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2263 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2264 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2265 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2266 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2267 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2268 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2269 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2270 // CHECK3-NEXT: ret void
2271 //
2272 //
2273 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2274 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2275 // CHECK3-NEXT: entry:
2276 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2277 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2278 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2279 // CHECK3-NEXT: ret void
2280 //
2281 //
2282 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2283 // CHECK3-SAME: () #[[ATTR0]] {
2284 // CHECK3-NEXT: entry:
2285 // CHECK3-NEXT: call void @__cxx_global_var_init()
2286 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
2287 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
2288 // CHECK3-NEXT: ret void
2289 //
2290 //
2291 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2292 // CHECK3-SAME: () #[[ATTR0]] {
2293 // CHECK3-NEXT: entry:
2294 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2295 // CHECK3-NEXT: ret void
2296 //
2297 //
2298 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
2299 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
2300 // CHECK4-NEXT: entry:
2301 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2302 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2303 // CHECK4-NEXT: ret void
2304 //
2305 //
2306 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2307 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2308 // CHECK4-NEXT: entry:
2309 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2310 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2311 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2312 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2313 // CHECK4-NEXT: ret void
2314 //
2315 //
2316 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2317 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2318 // CHECK4-NEXT: entry:
2319 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2320 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2321 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2322 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2323 // CHECK4-NEXT: ret void
2324 //
2325 //
2326 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2327 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2328 // CHECK4-NEXT: entry:
2329 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2330 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2331 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2332 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2333 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2334 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2335 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
2336 // CHECK4-NEXT: ret void
2337 //
2338 //
2339 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2340 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2341 // CHECK4-NEXT: entry:
2342 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2343 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2344 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2345 // CHECK4-NEXT: ret void
2346 //
2347 //
2348 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2349 // CHECK4-SAME: () #[[ATTR0]] {
2350 // CHECK4-NEXT: entry:
2351 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2352 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2353 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2354 // CHECK4-NEXT: ret void
2355 //
2356 //
2357 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2358 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2359 // CHECK4-NEXT: entry:
2360 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2361 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2362 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2363 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2364 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2365 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2366 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2367 // CHECK4-NEXT: ret void
2368 //
2369 //
2370 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2371 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2372 // CHECK4-NEXT: entry:
2373 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2374 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2375 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2376 // CHECK4: arraydestroy.body:
2377 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2378 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2379 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2380 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2381 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2382 // CHECK4: arraydestroy.done1:
2383 // CHECK4-NEXT: ret void
2384 //
2385 //
2386 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2387 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2388 // CHECK4-NEXT: entry:
2389 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2390 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2391 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2392 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2393 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2394 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2395 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2396 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2397 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2398 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2399 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
2400 // CHECK4-NEXT: ret void
2401 //
2402 //
2403 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2404 // CHECK4-SAME: () #[[ATTR0]] {
2405 // CHECK4-NEXT: entry:
2406 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2407 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2408 // CHECK4-NEXT: ret void
2409 //
2410 //
2411 // CHECK4-LABEL: define {{[^@]+}}@main
2412 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
2413 // CHECK4-NEXT: entry:
2414 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2415 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2416 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
2417 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
2418 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
2419 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
2420 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2421 // CHECK4: omp_offload.failed:
2422 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
2423 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
2424 // CHECK4: omp_offload.cont:
2425 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
2426 // CHECK4-NEXT: ret i32 [[CALL]]
2427 //
2428 //
2429 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
2430 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
2431 // CHECK4-NEXT: entry:
2432 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2433 // CHECK4-NEXT: ret void
2434 //
2435 //
2436 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
2437 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
2438 // CHECK4-NEXT: entry:
2439 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2440 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2441 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2442 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2443 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2444 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2445 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2446 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2447 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2448 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2449 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2450 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2451 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2452 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2453 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2454 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2455 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2456 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2457 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2458 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2459 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2460 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2461 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2462 // CHECK4: arrayctor.loop:
2463 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2464 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2465 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2466 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2467 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2468 // CHECK4: arrayctor.cont:
2469 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2470 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2471 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2472 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2473 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2474 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2475 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2476 // CHECK4: cond.true:
2477 // CHECK4-NEXT: br label [[COND_END:%.*]]
2478 // CHECK4: cond.false:
2479 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2480 // CHECK4-NEXT: br label [[COND_END]]
2481 // CHECK4: cond.end:
2482 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2483 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2484 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2485 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2486 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2487 // CHECK4: omp.inner.for.cond:
2488 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2489 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2490 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2491 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2492 // CHECK4: omp.inner.for.cond.cleanup:
2493 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2494 // CHECK4: omp.inner.for.body:
2495 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2496 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2497 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
2498 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2499 // CHECK4: omp.inner.for.inc:
2500 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2501 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2502 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2503 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2504 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2505 // CHECK4: omp.inner.for.end:
2506 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2507 // CHECK4: omp.loop.exit:
2508 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2509 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2510 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
2511 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2512 // CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2513 // CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2514 // CHECK4: .omp.final.then:
2515 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2516 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2517 // CHECK4: .omp.final.done:
2518 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2519 // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2520 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2
2521 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2522 // CHECK4: arraydestroy.body:
2523 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2524 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2525 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2526 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
2527 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
2528 // CHECK4: arraydestroy.done3:
2529 // CHECK4-NEXT: ret void
2530 //
2531 //
2532 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
2533 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
2534 // CHECK4-NEXT: entry:
2535 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2536 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2537 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2538 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2539 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2540 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2541 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2542 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2543 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2544 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2545 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2546 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2547 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2548 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2549 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2550 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2551 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2552 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2553 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2554 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2555 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2556 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2557 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2558 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2559 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
2560 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
2561 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2562 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2563 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2564 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2565 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2566 // CHECK4: arrayctor.loop:
2567 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2568 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2569 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2570 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2571 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2572 // CHECK4: arrayctor.cont:
2573 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2574 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2575 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2576 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2577 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2578 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2579 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2580 // CHECK4: cond.true:
2581 // CHECK4-NEXT: br label [[COND_END:%.*]]
2582 // CHECK4: cond.false:
2583 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2584 // CHECK4-NEXT: br label [[COND_END]]
2585 // CHECK4: cond.end:
2586 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2587 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2588 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2589 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2590 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2591 // CHECK4: omp.inner.for.cond:
2592 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2593 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2594 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2595 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2596 // CHECK4: omp.inner.for.cond.cleanup:
2597 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2598 // CHECK4: omp.inner.for.body:
2599 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2600 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2601 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2602 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2603 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
2604 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2605 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
2606 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
2607 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
2608 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]]
2609 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2610 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2611 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false)
2612 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2613 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
2614 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
2615 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
2616 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2617 // CHECK4: omp.body.continue:
2618 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2619 // CHECK4: omp.inner.for.inc:
2620 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2621 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1
2622 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
2623 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2624 // CHECK4: omp.inner.for.end:
2625 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2626 // CHECK4: omp.loop.exit:
2627 // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2628 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
2629 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
2630 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2631 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2632 // CHECK4-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2633 // CHECK4: .omp.final.then:
2634 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2635 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2636 // CHECK4: .omp.final.done:
2637 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2638 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2639 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
2640 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2641 // CHECK4: arraydestroy.body:
2642 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2643 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2644 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2645 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2646 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2647 // CHECK4: arraydestroy.done6:
2648 // CHECK4-NEXT: ret void
2649 //
2650 //
2651 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2652 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat {
2653 // CHECK4-NEXT: entry:
2654 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2655 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2656 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2657 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2658 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2659 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2660 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2661 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2662 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2663 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
2664 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2665 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2666 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2667 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
2668 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2669 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
2670 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2671 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2672 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
2673 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
2674 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
2675 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2676 // CHECK4: omp_offload.failed:
2677 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
2678 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
2679 // CHECK4: omp_offload.cont:
2680 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
2681 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2682 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2683 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2684 // CHECK4: arraydestroy.body:
2685 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2686 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2687 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2688 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2689 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2690 // CHECK4: arraydestroy.done2:
2691 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2692 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
2693 // CHECK4-NEXT: ret i32 [[TMP4]]
2694 //
2695 //
2696 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2697 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2698 // CHECK4-NEXT: entry:
2699 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2700 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2701 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2702 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2703 // CHECK4-NEXT: ret void
2704 //
2705 //
2706 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2707 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2708 // CHECK4-NEXT: entry:
2709 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2710 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2711 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2712 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2713 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2714 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2715 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2716 // CHECK4-NEXT: ret void
2717 //
2718 //
2719 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
2720 // CHECK4-SAME: () #[[ATTR4]] {
2721 // CHECK4-NEXT: entry:
2722 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
2723 // CHECK4-NEXT: ret void
2724 //
2725 //
2726 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
2727 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
2728 // CHECK4-NEXT: entry:
2729 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2730 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2731 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2732 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2733 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2734 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2735 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2736 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2737 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2738 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2739 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2740 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2741 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2742 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2743 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2744 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2745 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2746 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2747 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2748 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2749 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2750 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2751 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2752 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2753 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2754 // CHECK4: arrayctor.loop:
2755 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2756 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2757 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2758 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2759 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2760 // CHECK4: arrayctor.cont:
2761 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2762 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2763 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2764 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2765 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2766 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2767 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2768 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2769 // CHECK4: cond.true:
2770 // CHECK4-NEXT: br label [[COND_END:%.*]]
2771 // CHECK4: cond.false:
2772 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2773 // CHECK4-NEXT: br label [[COND_END]]
2774 // CHECK4: cond.end:
2775 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2776 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2777 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2778 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2779 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2780 // CHECK4: omp.inner.for.cond:
2781 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2782 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2783 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2784 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2785 // CHECK4: omp.inner.for.cond.cleanup:
2786 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2787 // CHECK4: omp.inner.for.body:
2788 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2789 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2790 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
2791 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2792 // CHECK4: omp.inner.for.inc:
2793 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2794 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2795 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2796 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2797 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2798 // CHECK4: omp.inner.for.end:
2799 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2800 // CHECK4: omp.loop.exit:
2801 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2802 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2803 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
2804 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2805 // CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2806 // CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2807 // CHECK4: .omp.final.then:
2808 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2809 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2810 // CHECK4: .omp.final.done:
2811 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2812 // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2813 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2
2814 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2815 // CHECK4: arraydestroy.body:
2816 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2817 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2818 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2819 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2820 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2821 // CHECK4: arraydestroy.done5:
2822 // CHECK4-NEXT: ret void
2823 //
2824 //
2825 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5
2826 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
2827 // CHECK4-NEXT: entry:
2828 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2829 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2830 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2831 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2832 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2833 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2834 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2835 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2836 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2837 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2838 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2839 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2840 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2841 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2842 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2843 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2844 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2845 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2846 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2847 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2848 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2849 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2850 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2851 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2852 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2853 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2854 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
2855 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
2856 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2857 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2858 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2859 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2860 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2861 // CHECK4: arrayctor.loop:
2862 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2863 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2864 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2865 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2866 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2867 // CHECK4: arrayctor.cont:
2868 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2869 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2870 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2871 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2872 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2873 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2874 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2875 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2876 // CHECK4: cond.true:
2877 // CHECK4-NEXT: br label [[COND_END:%.*]]
2878 // CHECK4: cond.false:
2879 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2880 // CHECK4-NEXT: br label [[COND_END]]
2881 // CHECK4: cond.end:
2882 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2883 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2884 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2885 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2886 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2887 // CHECK4: omp.inner.for.cond:
2888 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2889 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2890 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2891 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2892 // CHECK4: omp.inner.for.cond.cleanup:
2893 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2894 // CHECK4: omp.inner.for.body:
2895 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2896 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2897 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2898 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2899 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
2900 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2901 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
2902 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
2903 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
2904 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2905 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]]
2906 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
2907 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
2908 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)
2909 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2910 // CHECK4: omp.body.continue:
2911 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2912 // CHECK4: omp.inner.for.inc:
2913 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2914 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
2915 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
2916 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
2917 // CHECK4: omp.inner.for.end:
2918 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2919 // CHECK4: omp.loop.exit:
2920 // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2921 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
2922 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
2923 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2924 // CHECK4-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
2925 // CHECK4-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2926 // CHECK4: .omp.final.then:
2927 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2928 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2929 // CHECK4: .omp.final.done:
2930 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2931 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2932 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
2933 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2934 // CHECK4: arraydestroy.body:
2935 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2936 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2937 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2938 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2939 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2940 // CHECK4: arraydestroy.done7:
2941 // CHECK4-NEXT: ret void
2942 //
2943 //
2944 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2945 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2946 // CHECK4-NEXT: entry:
2947 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2948 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2949 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2950 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2951 // CHECK4-NEXT: ret void
2952 //
2953 //
2954 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2955 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2956 // CHECK4-NEXT: entry:
2957 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2958 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2959 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2960 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2961 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2962 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2963 // CHECK4-NEXT: ret void
2964 //
2965 //
2966 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2967 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2968 // CHECK4-NEXT: entry:
2969 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2970 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2971 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2972 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2973 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2974 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2975 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2976 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2977 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2978 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2979 // CHECK4-NEXT: ret void
2980 //
2981 //
2982 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2983 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2984 // CHECK4-NEXT: entry:
2985 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2986 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2987 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2988 // CHECK4-NEXT: ret void
2989 //
2990 //
2991 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2992 // CHECK4-SAME: () #[[ATTR0]] {
2993 // CHECK4-NEXT: entry:
2994 // CHECK4-NEXT: call void @__cxx_global_var_init()
2995 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
2996 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
2997 // CHECK4-NEXT: ret void
2998 //
2999 //
3000 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3001 // CHECK4-SAME: () #[[ATTR0]] {
3002 // CHECK4-NEXT: entry:
3003 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
3004 // CHECK4-NEXT: ret void
3005 //
3006 //
3007 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
3008 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
3009 // CHECK5-NEXT: entry:
3010 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3011 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3012 // CHECK5-NEXT: ret void
3013 //
3014 //
3015 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3016 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3017 // CHECK5-NEXT: entry:
3018 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3019 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3020 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3021 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3022 // CHECK5-NEXT: ret void
3023 //
3024 //
3025 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3026 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3027 // CHECK5-NEXT: entry:
3028 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3029 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3030 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3031 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3032 // CHECK5-NEXT: ret void
3033 //
3034 //
3035 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3036 // CHECK5-SAME: () #[[ATTR0]] {
3037 // CHECK5-NEXT: entry:
3038 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3039 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3040 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3041 // CHECK5-NEXT: ret void
3042 //
3043 //
3044 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3045 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3046 // CHECK5-NEXT: entry:
3047 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3048 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3049 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3050 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3051 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3052 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3053 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3054 // CHECK5-NEXT: ret void
3055 //
3056 //
3057 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3058 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3059 // CHECK5-NEXT: entry:
3060 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3061 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3062 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3063 // CHECK5: arraydestroy.body:
3064 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3065 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3066 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3067 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3068 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3069 // CHECK5: arraydestroy.done1:
3070 // CHECK5-NEXT: ret void
3071 //
3072 //
3073 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3074 // CHECK5-SAME: () #[[ATTR0]] {
3075 // CHECK5-NEXT: entry:
3076 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3077 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3078 // CHECK5-NEXT: ret void
3079 //
3080 //
3081 // CHECK5-LABEL: define {{[^@]+}}@main
3082 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
3083 // CHECK5-NEXT: entry:
3084 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3085 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3086 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3087 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3088 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3089 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3090 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3091 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3092 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3093 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3094 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3095 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
3096 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3097 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3098 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3099 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3100 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3101 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
3102 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3103 // CHECK5: arrayctor.loop:
3104 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3105 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3106 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
3107 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3108 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3109 // CHECK5: arrayctor.cont:
3110 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
3111 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3112 // CHECK5: omp.inner.for.cond:
3113 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3114 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
3115 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3116 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3117 // CHECK5: omp.inner.for.cond.cleanup:
3118 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3119 // CHECK5: omp.inner.for.body:
3120 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3121 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3122 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3123 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
3124 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
3125 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3126 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
3127 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
3128 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
3129 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3130 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
3131 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
3132 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
3133 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3134 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
3135 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3136 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
3137 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3138 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
3139 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3140 // CHECK5: omp.body.continue:
3141 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3142 // CHECK5: omp.inner.for.inc:
3143 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3144 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
3145 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3146 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
3147 // CHECK5: omp.inner.for.end:
3148 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
3149 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3150 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3151 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
3152 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3153 // CHECK5: arraydestroy.body:
3154 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3155 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3156 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3157 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
3158 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
3159 // CHECK5: arraydestroy.done6:
3160 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
3161 // CHECK5-NEXT: ret i32 [[CALL]]
3162 //
3163 //
3164 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3165 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
3166 // CHECK5-NEXT: entry:
3167 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3168 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3169 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3170 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3171 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3172 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
3173 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3174 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
3175 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3176 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3177 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3178 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3179 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3180 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3181 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3182 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3183 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
3184 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3185 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
3186 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3187 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
3188 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
3189 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
3190 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
3191 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
3192 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
3193 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
3194 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3195 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3196 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3197 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3198 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3199 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
3200 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3201 // CHECK5: arrayctor.loop:
3202 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3203 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3204 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
3205 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3206 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3207 // CHECK5: arrayctor.cont:
3208 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3209 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
3210 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3211 // CHECK5: omp.inner.for.cond:
3212 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3213 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
3214 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3215 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3216 // CHECK5: omp.inner.for.cond.cleanup:
3217 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3218 // CHECK5: omp.inner.for.body:
3219 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3220 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3221 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3222 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
3223 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
3224 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3225 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
3226 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
3227 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
3228 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
3229 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3230 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
3231 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
3232 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
3233 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3234 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
3235 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3236 // CHECK5: omp.body.continue:
3237 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3238 // CHECK5: omp.inner.for.inc:
3239 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3240 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
3241 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3242 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3243 // CHECK5: omp.inner.for.end:
3244 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
3245 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3246 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3247 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
3248 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3249 // CHECK5: arraydestroy.body:
3250 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3251 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3252 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3253 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
3254 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
3255 // CHECK5: arraydestroy.done11:
3256 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
3257 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3258 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
3259 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
3260 // CHECK5: arraydestroy.body13:
3261 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
3262 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
3263 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
3264 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
3265 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
3266 // CHECK5: arraydestroy.done17:
3267 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3268 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
3269 // CHECK5-NEXT: ret i32 [[TMP14]]
3270 //
3271 //
3272 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3273 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3274 // CHECK5-NEXT: entry:
3275 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3276 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3277 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3278 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3279 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3280 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3281 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
3282 // CHECK5-NEXT: ret void
3283 //
3284 //
3285 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3286 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3287 // CHECK5-NEXT: entry:
3288 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3289 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3290 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3291 // CHECK5-NEXT: ret void
3292 //
3293 //
3294 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3295 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3296 // CHECK5-NEXT: entry:
3297 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3298 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3299 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3300 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3301 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3302 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3303 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3304 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3305 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3306 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3307 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
3308 // CHECK5-NEXT: ret void
3309 //
3310 //
3311 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3312 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3313 // CHECK5-NEXT: entry:
3314 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3315 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3316 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3317 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3318 // CHECK5-NEXT: ret void
3319 //
3320 //
3321 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3322 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3323 // CHECK5-NEXT: entry:
3324 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3325 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3326 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3327 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3328 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3329 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3330 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
3331 // CHECK5-NEXT: ret void
3332 //
3333 //
3334 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3335 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3336 // CHECK5-NEXT: entry:
3337 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3338 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3339 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3340 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3341 // CHECK5-NEXT: ret void
3342 //
3343 //
3344 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3345 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3346 // CHECK5-NEXT: entry:
3347 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3348 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3349 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3350 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3351 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3352 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3353 // CHECK5-NEXT: ret void
3354 //
3355 //
3356 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3357 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3358 // CHECK5-NEXT: entry:
3359 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3360 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3361 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3362 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3363 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3364 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3365 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3366 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3367 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3368 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3369 // CHECK5-NEXT: ret void
3370 //
3371 //
3372 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3373 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3374 // CHECK5-NEXT: entry:
3375 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3376 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3377 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3378 // CHECK5-NEXT: ret void
3379 //
3380 //
3381 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
3382 // CHECK5-SAME: () #[[ATTR0]] {
3383 // CHECK5-NEXT: entry:
3384 // CHECK5-NEXT: call void @__cxx_global_var_init()
3385 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
3386 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
3387 // CHECK5-NEXT: ret void
3388 //
3389 //
3390 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
3391 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
3392 // CHECK6-NEXT: entry:
3393 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3394 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3395 // CHECK6-NEXT: ret void
3396 //
3397 //
3398 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3399 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3400 // CHECK6-NEXT: entry:
3401 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3402 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3403 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3404 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3405 // CHECK6-NEXT: ret void
3406 //
3407 //
3408 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3409 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3410 // CHECK6-NEXT: entry:
3411 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3412 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3413 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3414 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3415 // CHECK6-NEXT: ret void
3416 //
3417 //
3418 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3419 // CHECK6-SAME: () #[[ATTR0]] {
3420 // CHECK6-NEXT: entry:
3421 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3422 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3423 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3424 // CHECK6-NEXT: ret void
3425 //
3426 //
3427 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3428 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3429 // CHECK6-NEXT: entry:
3430 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3431 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3432 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3433 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3434 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3435 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3436 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3437 // CHECK6-NEXT: ret void
3438 //
3439 //
3440 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3441 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3442 // CHECK6-NEXT: entry:
3443 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3444 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3445 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3446 // CHECK6: arraydestroy.body:
3447 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3448 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3449 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3450 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3451 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3452 // CHECK6: arraydestroy.done1:
3453 // CHECK6-NEXT: ret void
3454 //
3455 //
3456 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3457 // CHECK6-SAME: () #[[ATTR0]] {
3458 // CHECK6-NEXT: entry:
3459 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3460 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3461 // CHECK6-NEXT: ret void
3462 //
3463 //
3464 // CHECK6-LABEL: define {{[^@]+}}@main
3465 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
3466 // CHECK6-NEXT: entry:
3467 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3468 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
3469 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3470 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3471 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3472 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
3473 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3474 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3475 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3476 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3477 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3478 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
3479 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3480 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3481 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3482 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3483 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3484 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
3485 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3486 // CHECK6: arrayctor.loop:
3487 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3488 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3489 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
3490 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3491 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3492 // CHECK6: arrayctor.cont:
3493 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
3494 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3495 // CHECK6: omp.inner.for.cond:
3496 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3497 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
3498 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3499 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3500 // CHECK6: omp.inner.for.cond.cleanup:
3501 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3502 // CHECK6: omp.inner.for.body:
3503 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3504 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3505 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3506 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
3507 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
3508 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3509 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
3510 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
3511 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
3512 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3513 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
3514 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
3515 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
3516 // CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3517 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
3518 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3519 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
3520 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3521 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
3522 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3523 // CHECK6: omp.body.continue:
3524 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3525 // CHECK6: omp.inner.for.inc:
3526 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3527 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
3528 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3529 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
3530 // CHECK6: omp.inner.for.end:
3531 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
3532 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3533 // CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3534 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
3535 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3536 // CHECK6: arraydestroy.body:
3537 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3538 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3539 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3540 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
3541 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
3542 // CHECK6: arraydestroy.done6:
3543 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
3544 // CHECK6-NEXT: ret i32 [[CALL]]
3545 //
3546 //
3547 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3548 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat {
3549 // CHECK6-NEXT: entry:
3550 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3551 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3552 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3553 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3554 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3555 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
3556 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
3557 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
3558 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3559 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3560 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3561 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
3562 // CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3563 // CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3564 // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3565 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3566 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
3567 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3568 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
3569 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3570 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
3571 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
3572 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
3573 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
3574 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
3575 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
3576 // CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
3577 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3578 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3579 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3580 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3581 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3582 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
3583 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3584 // CHECK6: arrayctor.loop:
3585 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3586 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3587 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
3588 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3589 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3590 // CHECK6: arrayctor.cont:
3591 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3592 // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
3593 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3594 // CHECK6: omp.inner.for.cond:
3595 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3596 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
3597 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3598 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3599 // CHECK6: omp.inner.for.cond.cleanup:
3600 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3601 // CHECK6: omp.inner.for.body:
3602 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3603 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3604 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3605 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
3606 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
3607 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3608 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
3609 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
3610 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
3611 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
3612 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3613 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
3614 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
3615 // CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
3616 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3617 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
3618 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3619 // CHECK6: omp.body.continue:
3620 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3621 // CHECK6: omp.inner.for.inc:
3622 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3623 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
3624 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3625 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3626 // CHECK6: omp.inner.for.end:
3627 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
3628 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3629 // CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3630 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
3631 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3632 // CHECK6: arraydestroy.body:
3633 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3634 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3635 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3636 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
3637 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
3638 // CHECK6: arraydestroy.done11:
3639 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
3640 // CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3641 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
3642 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
3643 // CHECK6: arraydestroy.body13:
3644 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
3645 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
3646 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
3647 // CHECK6-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
3648 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
3649 // CHECK6: arraydestroy.done17:
3650 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3651 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
3652 // CHECK6-NEXT: ret i32 [[TMP14]]
3653 //
3654 //
3655 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3656 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3657 // CHECK6-NEXT: entry:
3658 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3659 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3660 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3661 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3662 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3663 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3664 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4
3665 // CHECK6-NEXT: ret void
3666 //
3667 //
3668 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3669 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3670 // CHECK6-NEXT: entry:
3671 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3672 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3673 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3674 // CHECK6-NEXT: ret void
3675 //
3676 //
3677 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3678 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3679 // CHECK6-NEXT: entry:
3680 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3681 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3682 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3683 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3684 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3685 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3686 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3687 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3688 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3689 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3690 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4
3691 // CHECK6-NEXT: ret void
3692 //
3693 //
3694 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3695 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3696 // CHECK6-NEXT: entry:
3697 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3698 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3699 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3700 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3701 // CHECK6-NEXT: ret void
3702 //
3703 //
3704 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3705 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3706 // CHECK6-NEXT: entry:
3707 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3708 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3709 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3710 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3711 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3712 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3713 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
3714 // CHECK6-NEXT: ret void
3715 //
3716 //
3717 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3718 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3719 // CHECK6-NEXT: entry:
3720 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3721 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3722 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3723 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3724 // CHECK6-NEXT: ret void
3725 //
3726 //
3727 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3728 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3729 // CHECK6-NEXT: entry:
3730 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3731 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3732 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3733 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3734 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3735 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3736 // CHECK6-NEXT: ret void
3737 //
3738 //
3739 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3740 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3741 // CHECK6-NEXT: entry:
3742 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3743 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3744 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3745 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3746 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3747 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3748 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3749 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3750 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3751 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3752 // CHECK6-NEXT: ret void
3753 //
3754 //
3755 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3756 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3757 // CHECK6-NEXT: entry:
3758 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3759 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3760 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3761 // CHECK6-NEXT: ret void
3762 //
3763 //
3764 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
3765 // CHECK6-SAME: () #[[ATTR0]] {
3766 // CHECK6-NEXT: entry:
3767 // CHECK6-NEXT: call void @__cxx_global_var_init()
3768 // CHECK6-NEXT: call void @__cxx_global_var_init.1()
3769 // CHECK6-NEXT: call void @__cxx_global_var_init.2()
3770 // CHECK6-NEXT: ret void
3771 //
3772 //
3773 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
3774 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
3775 // CHECK7-NEXT: entry:
3776 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3777 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3778 // CHECK7-NEXT: ret void
3779 //
3780 //
3781 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3782 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3783 // CHECK7-NEXT: entry:
3784 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3785 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3786 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3787 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3788 // CHECK7-NEXT: ret void
3789 //
3790 //
3791 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3792 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3793 // CHECK7-NEXT: entry:
3794 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3795 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3796 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3797 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3798 // CHECK7-NEXT: ret void
3799 //
3800 //
3801 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3802 // CHECK7-SAME: () #[[ATTR0]] {
3803 // CHECK7-NEXT: entry:
3804 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
3805 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
3806 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3807 // CHECK7-NEXT: ret void
3808 //
3809 //
3810 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3811 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3812 // CHECK7-NEXT: entry:
3813 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3814 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3815 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3816 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3817 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3818 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3819 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3820 // CHECK7-NEXT: ret void
3821 //
3822 //
3823 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3824 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3825 // CHECK7-NEXT: entry:
3826 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
3827 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
3828 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3829 // CHECK7: arraydestroy.body:
3830 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3831 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3832 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3833 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3834 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3835 // CHECK7: arraydestroy.done1:
3836 // CHECK7-NEXT: ret void
3837 //
3838 //
3839 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3840 // CHECK7-SAME: () #[[ATTR0]] {
3841 // CHECK7-NEXT: entry:
3842 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3843 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3844 // CHECK7-NEXT: ret void
3845 //
3846 //
3847 // CHECK7-LABEL: define {{[^@]+}}@main
3848 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
3849 // CHECK7-NEXT: entry:
3850 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3851 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3852 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3853 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3854 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3855 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3856 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3857 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3858 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3859 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3860 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3861 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
3862 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3863 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3864 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3865 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3866 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3867 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3868 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3869 // CHECK7: arrayctor.loop:
3870 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3871 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3872 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
3873 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3874 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3875 // CHECK7: arrayctor.cont:
3876 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
3877 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3878 // CHECK7: omp.inner.for.cond:
3879 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3880 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
3881 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3882 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3883 // CHECK7: omp.inner.for.cond.cleanup:
3884 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3885 // CHECK7: omp.inner.for.body:
3886 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3887 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3888 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3889 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
3890 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
3891 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3892 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
3893 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
3894 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3895 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
3896 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
3897 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3898 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
3899 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3900 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
3901 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3902 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
3903 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3904 // CHECK7: omp.body.continue:
3905 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3906 // CHECK7: omp.inner.for.inc:
3907 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3908 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
3909 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3910 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3911 // CHECK7: omp.inner.for.end:
3912 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
3913 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3914 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3915 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
3916 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3917 // CHECK7: arraydestroy.body:
3918 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3919 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3920 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3921 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
3922 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
3923 // CHECK7: arraydestroy.done5:
3924 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3925 // CHECK7-NEXT: ret i32 [[CALL]]
3926 //
3927 //
3928 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3929 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
3930 // CHECK7-NEXT: entry:
3931 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3932 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3933 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3934 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3935 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3936 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3937 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3938 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
3939 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3940 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3941 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3942 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3943 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3944 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3945 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3946 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3947 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
3948 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3949 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
3950 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3951 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3952 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3953 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3954 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3955 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3956 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3957 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
3958 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3959 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3960 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3961 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3962 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3963 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3964 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3965 // CHECK7: arrayctor.loop:
3966 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3967 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3968 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
3969 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3970 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3971 // CHECK7: arrayctor.cont:
3972 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3973 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
3974 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3975 // CHECK7: omp.inner.for.cond:
3976 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3977 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
3978 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3979 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3980 // CHECK7: omp.inner.for.cond.cleanup:
3981 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3982 // CHECK7: omp.inner.for.body:
3983 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3984 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3985 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3986 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
3987 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
3988 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3989 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
3990 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
3991 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
3992 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3993 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
3994 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
3995 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3996 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
3997 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3998 // CHECK7: omp.body.continue:
3999 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4000 // CHECK7: omp.inner.for.inc:
4001 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4002 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
4003 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4004 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4005 // CHECK7: omp.inner.for.end:
4006 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
4007 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
4008 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4009 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
4010 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4011 // CHECK7: arraydestroy.body:
4012 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4013 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4014 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4015 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
4016 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
4017 // CHECK7: arraydestroy.done10:
4018 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
4019 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4020 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
4021 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
4022 // CHECK7: arraydestroy.body12:
4023 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
4024 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
4025 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
4026 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
4027 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
4028 // CHECK7: arraydestroy.done16:
4029 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
4030 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
4031 // CHECK7-NEXT: ret i32 [[TMP14]]
4032 //
4033 //
4034 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4035 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4036 // CHECK7-NEXT: entry:
4037 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4038 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4039 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4040 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4041 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4042 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4043 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
4044 // CHECK7-NEXT: ret void
4045 //
4046 //
4047 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4048 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4049 // CHECK7-NEXT: entry:
4050 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4051 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4052 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4053 // CHECK7-NEXT: ret void
4054 //
4055 //
4056 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4057 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4058 // CHECK7-NEXT: entry:
4059 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4060 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4061 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4062 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4063 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4064 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4065 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4066 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4067 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4068 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4069 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
4070 // CHECK7-NEXT: ret void
4071 //
4072 //
4073 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4074 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4075 // CHECK7-NEXT: entry:
4076 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4077 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4078 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4079 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4080 // CHECK7-NEXT: ret void
4081 //
4082 //
4083 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4084 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4085 // CHECK7-NEXT: entry:
4086 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4087 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4088 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4089 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4090 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4091 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4092 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4093 // CHECK7-NEXT: ret void
4094 //
4095 //
4096 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4097 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4098 // CHECK7-NEXT: entry:
4099 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4100 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4101 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4102 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4103 // CHECK7-NEXT: ret void
4104 //
4105 //
4106 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4107 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4108 // CHECK7-NEXT: entry:
4109 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4110 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4111 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4112 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4113 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4114 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4115 // CHECK7-NEXT: ret void
4116 //
4117 //
4118 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4119 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4120 // CHECK7-NEXT: entry:
4121 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4122 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4123 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4124 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4125 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4126 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4127 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4128 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4129 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4130 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4131 // CHECK7-NEXT: ret void
4132 //
4133 //
4134 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4135 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4136 // CHECK7-NEXT: entry:
4137 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4138 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4139 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4140 // CHECK7-NEXT: ret void
4141 //
4142 //
4143 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
4144 // CHECK7-SAME: () #[[ATTR0]] {
4145 // CHECK7-NEXT: entry:
4146 // CHECK7-NEXT: call void @__cxx_global_var_init()
4147 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
4148 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
4149 // CHECK7-NEXT: ret void
4150 //
4151 //
4152 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init
4153 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
4154 // CHECK8-NEXT: entry:
4155 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4156 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4157 // CHECK8-NEXT: ret void
4158 //
4159 //
4160 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4161 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4162 // CHECK8-NEXT: entry:
4163 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4164 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4165 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4166 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4167 // CHECK8-NEXT: ret void
4168 //
4169 //
4170 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4171 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4172 // CHECK8-NEXT: entry:
4173 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4174 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4175 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4176 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4177 // CHECK8-NEXT: ret void
4178 //
4179 //
4180 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4181 // CHECK8-SAME: () #[[ATTR0]] {
4182 // CHECK8-NEXT: entry:
4183 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
4184 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
4185 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4186 // CHECK8-NEXT: ret void
4187 //
4188 //
4189 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4190 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4191 // CHECK8-NEXT: entry:
4192 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4193 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4194 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4195 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4196 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4197 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4198 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4199 // CHECK8-NEXT: ret void
4200 //
4201 //
4202 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4203 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4204 // CHECK8-NEXT: entry:
4205 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
4206 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
4207 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4208 // CHECK8: arraydestroy.body:
4209 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4210 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4211 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4212 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4213 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4214 // CHECK8: arraydestroy.done1:
4215 // CHECK8-NEXT: ret void
4216 //
4217 //
4218 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4219 // CHECK8-SAME: () #[[ATTR0]] {
4220 // CHECK8-NEXT: entry:
4221 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4222 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4223 // CHECK8-NEXT: ret void
4224 //
4225 //
4226 // CHECK8-LABEL: define {{[^@]+}}@main
4227 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] {
4228 // CHECK8-NEXT: entry:
4229 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4230 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
4231 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4232 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4233 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4234 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4235 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4236 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4237 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
4238 // CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
4239 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
4240 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
4241 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4242 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4243 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4244 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4245 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
4246 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
4247 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
4248 // CHECK8: arrayctor.loop:
4249 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4250 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
4251 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
4252 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
4253 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4254 // CHECK8: arrayctor.cont:
4255 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
4256 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4257 // CHECK8: omp.inner.for.cond:
4258 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4259 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
4260 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4261 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4262 // CHECK8: omp.inner.for.cond.cleanup:
4263 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4264 // CHECK8: omp.inner.for.body:
4265 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4266 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4267 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4268 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
4269 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
4270 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4271 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
4272 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
4273 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4274 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
4275 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
4276 // CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
4277 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
4278 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4279 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
4280 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
4281 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
4282 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4283 // CHECK8: omp.body.continue:
4284 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4285 // CHECK8: omp.inner.for.inc:
4286 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4287 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
4288 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4289 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4290 // CHECK8: omp.inner.for.end:
4291 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
4292 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
4293 // CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
4294 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
4295 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4296 // CHECK8: arraydestroy.body:
4297 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4298 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4299 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4300 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
4301 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
4302 // CHECK8: arraydestroy.done5:
4303 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
4304 // CHECK8-NEXT: ret i32 [[CALL]]
4305 //
4306 //
4307 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
4308 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
4309 // CHECK8-NEXT: entry:
4310 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4311 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4312 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4313 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4314 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
4315 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
4316 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
4317 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
4318 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4319 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4320 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4321 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4322 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
4323 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
4324 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
4325 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
4326 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
4327 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
4328 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
4329 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4330 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
4331 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4332 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
4333 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
4334 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
4335 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
4336 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
4337 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4338 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4339 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4340 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
4341 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4342 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4343 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
4344 // CHECK8: arrayctor.loop:
4345 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4346 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
4347 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
4348 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
4349 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4350 // CHECK8: arrayctor.cont:
4351 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
4352 // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
4353 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4354 // CHECK8: omp.inner.for.cond:
4355 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4356 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
4357 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
4358 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4359 // CHECK8: omp.inner.for.cond.cleanup:
4360 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4361 // CHECK8: omp.inner.for.body:
4362 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4363 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
4364 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4365 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
4366 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
4367 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4368 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
4369 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
4370 // CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
4371 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4372 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
4373 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
4374 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
4375 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
4376 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4377 // CHECK8: omp.body.continue:
4378 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4379 // CHECK8: omp.inner.for.inc:
4380 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4381 // CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
4382 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4383 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4384 // CHECK8: omp.inner.for.end:
4385 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
4386 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
4387 // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4388 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
4389 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4390 // CHECK8: arraydestroy.body:
4391 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4392 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4393 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4394 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
4395 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
4396 // CHECK8: arraydestroy.done10:
4397 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
4398 // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4399 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
4400 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
4401 // CHECK8: arraydestroy.body12:
4402 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
4403 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
4404 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
4405 // CHECK8-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
4406 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
4407 // CHECK8: arraydestroy.done16:
4408 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
4409 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
4410 // CHECK8-NEXT: ret i32 [[TMP14]]
4411 //
4412 //
4413 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4414 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4415 // CHECK8-NEXT: entry:
4416 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4417 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4418 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4419 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4420 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4421 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4422 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4
4423 // CHECK8-NEXT: ret void
4424 //
4425 //
4426 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4427 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4428 // CHECK8-NEXT: entry:
4429 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4430 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4431 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4432 // CHECK8-NEXT: ret void
4433 //
4434 //
4435 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4436 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4437 // CHECK8-NEXT: entry:
4438 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4439 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4440 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4441 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4442 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4443 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4444 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4445 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4446 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4447 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4448 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4
4449 // CHECK8-NEXT: ret void
4450 //
4451 //
4452 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4453 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4454 // CHECK8-NEXT: entry:
4455 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4456 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4457 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4458 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4459 // CHECK8-NEXT: ret void
4460 //
4461 //
4462 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4463 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4464 // CHECK8-NEXT: entry:
4465 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4466 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4467 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4468 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4469 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4470 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4471 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4472 // CHECK8-NEXT: ret void
4473 //
4474 //
4475 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4476 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4477 // CHECK8-NEXT: entry:
4478 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4479 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4480 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4481 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4482 // CHECK8-NEXT: ret void
4483 //
4484 //
4485 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4486 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4487 // CHECK8-NEXT: entry:
4488 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4489 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4490 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4491 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4492 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4493 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4494 // CHECK8-NEXT: ret void
4495 //
4496 //
4497 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4498 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4499 // CHECK8-NEXT: entry:
4500 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4501 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4502 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4503 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4504 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4505 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4506 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4507 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4508 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4509 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4510 // CHECK8-NEXT: ret void
4511 //
4512 //
4513 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4514 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4515 // CHECK8-NEXT: entry:
4516 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4517 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4518 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4519 // CHECK8-NEXT: ret void
4520 //
4521 //
4522 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
4523 // CHECK8-SAME: () #[[ATTR0]] {
4524 // CHECK8-NEXT: entry:
4525 // CHECK8-NEXT: call void @__cxx_global_var_init()
4526 // CHECK8-NEXT: call void @__cxx_global_var_init.1()
4527 // CHECK8-NEXT: call void @__cxx_global_var_init.2()
4528 // CHECK8-NEXT: ret void
4529 //
4530 //
4531 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
4532 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
4533 // CHECK9-NEXT: entry:
4534 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4535 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4536 // CHECK9-NEXT: ret void
4537 //
4538 //
4539 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4540 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4541 // CHECK9-NEXT: entry:
4542 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4543 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4544 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4545 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4546 // CHECK9-NEXT: ret void
4547 //
4548 //
4549 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4550 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4551 // CHECK9-NEXT: entry:
4552 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4553 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4554 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4555 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4556 // CHECK9-NEXT: ret void
4557 //
4558 //
4559 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4560 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4561 // CHECK9-NEXT: entry:
4562 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4563 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4564 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4565 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4566 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4567 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4568 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
4569 // CHECK9-NEXT: ret void
4570 //
4571 //
4572 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4573 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4574 // CHECK9-NEXT: entry:
4575 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4576 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4577 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4578 // CHECK9-NEXT: ret void
4579 //
4580 //
4581 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4582 // CHECK9-SAME: () #[[ATTR0]] {
4583 // CHECK9-NEXT: entry:
4584 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4585 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4586 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4587 // CHECK9-NEXT: ret void
4588 //
4589 //
4590 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4591 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4592 // CHECK9-NEXT: entry:
4593 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4594 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4595 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4596 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4597 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4598 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4599 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4600 // CHECK9-NEXT: ret void
4601 //
4602 //
4603 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4604 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4605 // CHECK9-NEXT: entry:
4606 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4607 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4608 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4609 // CHECK9: arraydestroy.body:
4610 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4611 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4612 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4613 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4614 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4615 // CHECK9: arraydestroy.done1:
4616 // CHECK9-NEXT: ret void
4617 //
4618 //
4619 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4620 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4621 // CHECK9-NEXT: entry:
4622 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4623 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4624 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4625 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4626 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4627 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4628 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4629 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4630 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4631 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4632 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
4633 // CHECK9-NEXT: ret void
4634 //
4635 //
4636 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4637 // CHECK9-SAME: () #[[ATTR0]] {
4638 // CHECK9-NEXT: entry:
4639 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4640 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4641 // CHECK9-NEXT: ret void
4642 //
4643 //
4644 // CHECK9-LABEL: define {{[^@]+}}@main
4645 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
4646 // CHECK9-NEXT: entry:
4647 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4648 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4649 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
4650 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4651 // CHECK9-NEXT: ret i32 0
4652 //
4653 //
4654 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
4655 // CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
4656 // CHECK9-NEXT: entry:
4657 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4658 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4659 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4660 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4661 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
4662 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
4663 // CHECK9-NEXT: ret void
4664 //
4665 //
4666 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
4667 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
4668 // CHECK9-NEXT: entry:
4669 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4670 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4671 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4672 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4673 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
4674 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4675 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4676 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4677 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4678 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
4679 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
4680 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
4681 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
4682 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4683 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4684 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4685 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
4686 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4687 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4688 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4689 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4690 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
4691 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4692 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4693 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4694 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4695 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
4696 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4697 // CHECK9: cond.true:
4698 // CHECK9-NEXT: br label [[COND_END:%.*]]
4699 // CHECK9: cond.false:
4700 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4701 // CHECK9-NEXT: br label [[COND_END]]
4702 // CHECK9: cond.end:
4703 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4704 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4705 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4706 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4707 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4708 // CHECK9: omp.inner.for.cond:
4709 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4710 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4711 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4712 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4713 // CHECK9: omp.inner.for.body:
4714 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4715 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
4716 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4717 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
4718 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
4719 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4720 // CHECK9: omp.inner.for.inc:
4721 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4722 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4723 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
4724 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4725 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4726 // CHECK9: omp.inner.for.end:
4727 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4728 // CHECK9: omp.loop.exit:
4729 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4730 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4731 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
4732 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4733 // CHECK9: .omp.final.then:
4734 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
4735 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
4736 // CHECK9: .omp.final.done:
4737 // CHECK9-NEXT: ret void
4738 //
4739 //
4740 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
4741 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
4742 // CHECK9-NEXT: entry:
4743 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4744 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4745 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
4746 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
4747 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4748 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4749 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
4750 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4751 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4752 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4753 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4754 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
4755 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
4756 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
4757 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
4758 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4759 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
4760 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4761 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4762 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
4763 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
4764 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
4765 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4766 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4767 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
4768 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
4769 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
4770 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
4771 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
4772 // CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
4773 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4774 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4775 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8
4776 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4777 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4778 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4779 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4780 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
4781 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4782 // CHECK9: cond.true:
4783 // CHECK9-NEXT: br label [[COND_END:%.*]]
4784 // CHECK9: cond.false:
4785 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4786 // CHECK9-NEXT: br label [[COND_END]]
4787 // CHECK9: cond.end:
4788 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4789 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4790 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4791 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
4792 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4793 // CHECK9: omp.inner.for.cond:
4794 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4795 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4796 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4797 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4798 // CHECK9: omp.inner.for.body:
4799 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4800 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
4801 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4802 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4803 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4
4804 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8
4805 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
4806 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4
4807 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
4808 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8
4809 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
4810 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8
4811 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
4812 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
4813 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8
4814 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
4815 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4816 // CHECK9: omp.body.continue:
4817 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4818 // CHECK9: omp.inner.for.inc:
4819 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4820 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
4821 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
4822 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
4823 // CHECK9: omp.inner.for.end:
4824 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4825 // CHECK9: omp.loop.exit:
4826 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4827 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4828 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
4829 // CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4830 // CHECK9: .omp.final.then:
4831 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
4832 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
4833 // CHECK9: .omp.final.done:
4834 // CHECK9-NEXT: ret void
4835 //
4836 //
4837 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
4838 // CHECK9-SAME: () #[[ATTR0]] {
4839 // CHECK9-NEXT: entry:
4840 // CHECK9-NEXT: call void @__cxx_global_var_init()
4841 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
4842 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
4843 // CHECK9-NEXT: ret void
4844 //
4845 //
4846 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4847 // CHECK9-SAME: () #[[ATTR0]] {
4848 // CHECK9-NEXT: entry:
4849 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
4850 // CHECK9-NEXT: ret void
4851 //
4852 //
4853 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init
4854 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
4855 // CHECK10-NEXT: entry:
4856 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4857 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4858 // CHECK10-NEXT: ret void
4859 //
4860 //
4861 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4862 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4863 // CHECK10-NEXT: entry:
4864 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4865 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4866 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4867 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4868 // CHECK10-NEXT: ret void
4869 //
4870 //
4871 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4872 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4873 // CHECK10-NEXT: entry:
4874 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4875 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4876 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4877 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4878 // CHECK10-NEXT: ret void
4879 //
4880 //
4881 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4882 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4883 // CHECK10-NEXT: entry:
4884 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4885 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4886 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4887 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4888 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4889 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4890 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4
4891 // CHECK10-NEXT: ret void
4892 //
4893 //
4894 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4895 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4896 // CHECK10-NEXT: entry:
4897 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4898 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4899 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4900 // CHECK10-NEXT: ret void
4901 //
4902 //
4903 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4904 // CHECK10-SAME: () #[[ATTR0]] {
4905 // CHECK10-NEXT: entry:
4906 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4907 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4908 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4909 // CHECK10-NEXT: ret void
4910 //
4911 //
4912 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4913 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4914 // CHECK10-NEXT: entry:
4915 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4916 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4917 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4918 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4919 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4920 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4921 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4922 // CHECK10-NEXT: ret void
4923 //
4924 //
4925 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4926 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4927 // CHECK10-NEXT: entry:
4928 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4929 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4930 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4931 // CHECK10: arraydestroy.body:
4932 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4933 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4934 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4935 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4936 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4937 // CHECK10: arraydestroy.done1:
4938 // CHECK10-NEXT: ret void
4939 //
4940 //
4941 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4942 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4943 // CHECK10-NEXT: entry:
4944 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4945 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4946 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4947 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4948 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4949 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4950 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4951 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4952 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4953 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4954 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4
4955 // CHECK10-NEXT: ret void
4956 //
4957 //
4958 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4959 // CHECK10-SAME: () #[[ATTR0]] {
4960 // CHECK10-NEXT: entry:
4961 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4962 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4963 // CHECK10-NEXT: ret void
4964 //
4965 //
4966 // CHECK10-LABEL: define {{[^@]+}}@main
4967 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
4968 // CHECK10-NEXT: entry:
4969 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4970 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4971 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
4972 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4973 // CHECK10-NEXT: ret i32 0
4974 //
4975 //
4976 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
4977 // CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
4978 // CHECK10-NEXT: entry:
4979 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4980 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4981 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4982 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4983 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
4984 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
4985 // CHECK10-NEXT: ret void
4986 //
4987 //
4988 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
4989 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
4990 // CHECK10-NEXT: entry:
4991 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4992 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4993 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4994 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
4995 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
4996 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4997 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4998 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4999 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5000 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4
5001 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4
5002 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
5003 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
5004 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
5005 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5006 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5007 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8
5008 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5009 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5010 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5011 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5012 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
5013 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5014 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5015 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5016 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5017 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
5018 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5019 // CHECK10: cond.true:
5020 // CHECK10-NEXT: br label [[COND_END:%.*]]
5021 // CHECK10: cond.false:
5022 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5023 // CHECK10-NEXT: br label [[COND_END]]
5024 // CHECK10: cond.end:
5025 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5026 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
5027 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5028 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5029 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5030 // CHECK10: omp.inner.for.cond:
5031 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5032 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5033 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5034 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5035 // CHECK10: omp.inner.for.body:
5036 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5037 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
5038 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5039 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
5040 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
5041 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5042 // CHECK10: omp.inner.for.inc:
5043 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5044 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5045 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
5046 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5047 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
5048 // CHECK10: omp.inner.for.end:
5049 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5050 // CHECK10: omp.loop.exit:
5051 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5052 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5053 // CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5054 // CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5055 // CHECK10: .omp.final.then:
5056 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
5057 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
5058 // CHECK10: .omp.final.done:
5059 // CHECK10-NEXT: ret void
5060 //
5061 //
5062 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
5063 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
5064 // CHECK10-NEXT: entry:
5065 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5066 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5067 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
5068 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
5069 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5070 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
5071 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
5072 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5073 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5074 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5075 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5076 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4
5077 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4
5078 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
5079 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
5080 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
5081 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
5082 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5083 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5084 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5085 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5086 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8
5087 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5088 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5089 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
5090 // CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
5091 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
5092 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
5093 // CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
5094 // CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
5095 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5096 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5097 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8
5098 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5099 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5100 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5101 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5102 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
5103 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5104 // CHECK10: cond.true:
5105 // CHECK10-NEXT: br label [[COND_END:%.*]]
5106 // CHECK10: cond.false:
5107 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5108 // CHECK10-NEXT: br label [[COND_END]]
5109 // CHECK10: cond.end:
5110 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5111 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5112 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5113 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
5114 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5115 // CHECK10: omp.inner.for.cond:
5116 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5117 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5118 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
5119 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5120 // CHECK10: omp.inner.for.body:
5121 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5122 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
5123 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5124 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5125 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4
5126 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8
5127 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
5128 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4
5129 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
5130 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP11]], align 8
5131 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
5132 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8
5133 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
5134 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
5135 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8
5136 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
5137 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5138 // CHECK10: omp.body.continue:
5139 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5140 // CHECK10: omp.inner.for.inc:
5141 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5142 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
5143 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
5144 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
5145 // CHECK10: omp.inner.for.end:
5146 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5147 // CHECK10: omp.loop.exit:
5148 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
5149 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5150 // CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
5151 // CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5152 // CHECK10: .omp.final.then:
5153 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
5154 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
5155 // CHECK10: .omp.final.done:
5156 // CHECK10-NEXT: ret void
5157 //
5158 //
5159 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
5160 // CHECK10-SAME: () #[[ATTR0]] {
5161 // CHECK10-NEXT: entry:
5162 // CHECK10-NEXT: call void @__cxx_global_var_init()
5163 // CHECK10-NEXT: call void @__cxx_global_var_init.1()
5164 // CHECK10-NEXT: call void @__cxx_global_var_init.2()
5165 // CHECK10-NEXT: ret void
5166 //
5167 //
5168 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5169 // CHECK10-SAME: () #[[ATTR0]] {
5170 // CHECK10-NEXT: entry:
5171 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
5172 // CHECK10-NEXT: ret void
5173 //
5174 //
5175 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
5176 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
5177 // CHECK11-NEXT: entry:
5178 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5179 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5180 // CHECK11-NEXT: ret void
5181 //
5182 //
5183 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5184 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5185 // CHECK11-NEXT: entry:
5186 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5187 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5188 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5189 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5190 // CHECK11-NEXT: ret void
5191 //
5192 //
5193 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5194 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5195 // CHECK11-NEXT: entry:
5196 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5197 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5198 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5199 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5200 // CHECK11-NEXT: ret void
5201 //
5202 //
5203 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5204 // CHECK11-SAME: () #[[ATTR0]] {
5205 // CHECK11-NEXT: entry:
5206 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
5207 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
5208 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5209 // CHECK11-NEXT: ret void
5210 //
5211 //
5212 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5213 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5214 // CHECK11-NEXT: entry:
5215 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5216 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5217 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5218 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5219 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5220 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5221 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5222 // CHECK11-NEXT: ret void
5223 //
5224 //
5225 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5226 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5227 // CHECK11-NEXT: entry:
5228 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
5229 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
5230 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5231 // CHECK11: arraydestroy.body:
5232 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5233 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5234 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5235 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5236 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5237 // CHECK11: arraydestroy.done1:
5238 // CHECK11-NEXT: ret void
5239 //
5240 //
5241 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5242 // CHECK11-SAME: () #[[ATTR0]] {
5243 // CHECK11-NEXT: entry:
5244 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5245 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5246 // CHECK11-NEXT: ret void
5247 //
5248 //
5249 // CHECK11-LABEL: define {{[^@]+}}@main
5250 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
5251 // CHECK11-NEXT: entry:
5252 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5253 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
5254 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
5255 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
5256 // CHECK11-NEXT: ret i32 0
5257 //
5258 //
5259 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5260 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5261 // CHECK11-NEXT: entry:
5262 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5263 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5264 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5265 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5266 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5267 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5268 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
5269 // CHECK11-NEXT: ret void
5270 //
5271 //
5272 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5273 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5274 // CHECK11-NEXT: entry:
5275 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5276 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5277 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5278 // CHECK11-NEXT: ret void
5279 //
5280 //
5281 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5282 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5283 // CHECK11-NEXT: entry:
5284 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5285 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5286 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5287 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5288 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5289 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5290 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5291 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5292 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5293 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5294 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
5295 // CHECK11-NEXT: ret void
5296 //
5297 //
5298 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
5299 // CHECK11-SAME: () #[[ATTR0]] {
5300 // CHECK11-NEXT: entry:
5301 // CHECK11-NEXT: call void @__cxx_global_var_init()
5302 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
5303 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
5304 // CHECK11-NEXT: ret void
5305 //
5306 //
5307 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init
5308 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
5309 // CHECK12-NEXT: entry:
5310 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5311 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5312 // CHECK12-NEXT: ret void
5313 //
5314 //
5315 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5316 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5317 // CHECK12-NEXT: entry:
5318 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5319 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5320 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5321 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5322 // CHECK12-NEXT: ret void
5323 //
5324 //
5325 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5326 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5327 // CHECK12-NEXT: entry:
5328 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5329 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5330 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5331 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5332 // CHECK12-NEXT: ret void
5333 //
5334 //
5335 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5336 // CHECK12-SAME: () #[[ATTR0]] {
5337 // CHECK12-NEXT: entry:
5338 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
5339 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
5340 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5341 // CHECK12-NEXT: ret void
5342 //
5343 //
5344 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5345 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5346 // CHECK12-NEXT: entry:
5347 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5348 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5349 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5350 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5351 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5352 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5353 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5354 // CHECK12-NEXT: ret void
5355 //
5356 //
5357 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5358 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5359 // CHECK12-NEXT: entry:
5360 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
5361 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
5362 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5363 // CHECK12: arraydestroy.body:
5364 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5365 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5366 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5367 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5368 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5369 // CHECK12: arraydestroy.done1:
5370 // CHECK12-NEXT: ret void
5371 //
5372 //
5373 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5374 // CHECK12-SAME: () #[[ATTR0]] {
5375 // CHECK12-NEXT: entry:
5376 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5377 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5378 // CHECK12-NEXT: ret void
5379 //
5380 //
5381 // CHECK12-LABEL: define {{[^@]+}}@main
5382 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
5383 // CHECK12-NEXT: entry:
5384 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5385 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
5386 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
5387 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
5388 // CHECK12-NEXT: ret i32 0
5389 //
5390 //
5391 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5392 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5393 // CHECK12-NEXT: entry:
5394 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5395 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5396 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5397 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5398 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5399 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5400 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4
5401 // CHECK12-NEXT: ret void
5402 //
5403 //
5404 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5405 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5406 // CHECK12-NEXT: entry:
5407 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5408 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5409 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5410 // CHECK12-NEXT: ret void
5411 //
5412 //
5413 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5414 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5415 // CHECK12-NEXT: entry:
5416 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5417 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5418 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5419 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5420 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5421 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5422 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5423 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5424 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5425 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5426 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4
5427 // CHECK12-NEXT: ret void
5428 //
5429 //
5430 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
5431 // CHECK12-SAME: () #[[ATTR0]] {
5432 // CHECK12-NEXT: entry:
5433 // CHECK12-NEXT: call void @__cxx_global_var_init()
5434 // CHECK12-NEXT: call void @__cxx_global_var_init.1()
5435 // CHECK12-NEXT: call void @__cxx_global_var_init.2()
5436 // CHECK12-NEXT: ret void
5437 //
5438