1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute simd firstprivate(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global and bound tid vars
80 // skip loop vars
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84 [&]() {
85 g = 2;
86 g1 = 2;
87 sivar = 4;
88
89 }();
90 }
91 }();
92 return 0;
93 #else
94 #pragma omp target
95 #pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar)
96 for (int i = 0; i < 2; ++i) {
97 vec[i] = t_var;
98 s_arr[i] = var;
99 sivar += i;
100 }
101 return tmain<int>();
102 #endif
103 }
104
105
106
107
108
109 // Skip global and bound tid vars
110 // Skip temp vars for loop
111
112 // param copy
113
114 // T_VAR and SIVAR
115
116 // preparation vars
117
118 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
119
120 // firstprivate(s_arr)
121
122 // firstprivate(var)
123
124
125
126
127
128
129 // Skip global and bound tid vars
130 // Skip temp vars for loop
131
132 // param copy
133
134
135 // T_VAR and preparation variables
136
137 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
138
139 // firstprivate(s_arr)
140
141 // firstprivate(var)
142
143
144 #endif
145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
147 // CHECK1-NEXT: entry:
148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
150 // CHECK1-NEXT: ret void
151 //
152 //
153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
154 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
155 // CHECK1-NEXT: entry:
156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
160 // CHECK1-NEXT: ret void
161 //
162 //
163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
164 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
165 // CHECK1-NEXT: entry:
166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
170 // CHECK1-NEXT: ret void
171 //
172 //
173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
174 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
175 // CHECK1-NEXT: entry:
176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
177 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
178 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
182 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
183 // CHECK1-NEXT: ret void
184 //
185 //
186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
187 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
188 // CHECK1-NEXT: entry:
189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
192 // CHECK1-NEXT: ret void
193 //
194 //
195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
196 // CHECK1-SAME: () #[[ATTR0]] {
197 // CHECK1-NEXT: entry:
198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
201 // CHECK1-NEXT: ret void
202 //
203 //
204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
205 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
206 // CHECK1-NEXT: entry:
207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
209 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
210 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
211 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
214 // CHECK1-NEXT: ret void
215 //
216 //
217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
218 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
219 // CHECK1-NEXT: entry:
220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
221 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
223 // CHECK1: arraydestroy.body:
224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
229 // CHECK1: arraydestroy.done1:
230 // CHECK1-NEXT: ret void
231 //
232 //
233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
234 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
235 // CHECK1-NEXT: entry:
236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
238 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
239 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
240 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
246 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
247 // CHECK1-NEXT: ret void
248 //
249 //
250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
251 // CHECK1-SAME: () #[[ATTR0]] {
252 // CHECK1-NEXT: entry:
253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
255 // CHECK1-NEXT: ret void
256 //
257 //
258 // CHECK1-LABEL: define {{[^@]+}}@main
259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
260 // CHECK1-NEXT: entry:
261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
262 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
263 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
264 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
265 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
266 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
267 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
268 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
269 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
270 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
271 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
272 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
273 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
274 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
275 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
276 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
277 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
278 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
279 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
280 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
281 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
282 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
283 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
284 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
285 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
286 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
287 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8
288 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
289 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
290 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8
291 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
292 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
293 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
294 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
295 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
296 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
297 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
298 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
299 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
300 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
301 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
302 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
303 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
304 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
305 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
306 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
307 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
308 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
309 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
310 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
311 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
312 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
313 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
314 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
315 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
316 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8
317 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
318 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
319 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
320 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
321 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
322 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
323 // CHECK1: omp_offload.failed:
324 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
325 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
326 // CHECK1: omp_offload.cont:
327 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
328 // CHECK1-NEXT: ret i32 [[CALL]]
329 //
330 //
331 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
332 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
333 // CHECK1-NEXT: entry:
334 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
335 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
336 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
337 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
338 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
339 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
340 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
341 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
342 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
343 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
344 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
345 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
346 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
347 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
348 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
349 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
350 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
351 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
352 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
353 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
354 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
355 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
356 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
357 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
358 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
359 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
360 // CHECK1-NEXT: ret void
361 //
362 //
363 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
364 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
365 // CHECK1-NEXT: entry:
366 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
367 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
368 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
369 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
370 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
371 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
372 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
373 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
374 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
375 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
376 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
377 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
378 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
379 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
380 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
381 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
382 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
383 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
384 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
385 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
386 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
387 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
388 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
389 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
390 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
391 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
392 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
393 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
394 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
395 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
396 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
398 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
399 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
400 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
401 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
402 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
403 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
404 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
405 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
406 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
407 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
408 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
409 // CHECK1: omp.arraycpy.body:
410 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
411 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
412 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
413 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
414 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
415 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
416 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
417 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
418 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
419 // CHECK1: omp.arraycpy.done4:
420 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
421 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
422 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
423 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
424 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
425 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
426 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
427 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
428 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
429 // CHECK1: cond.true:
430 // CHECK1-NEXT: br label [[COND_END:%.*]]
431 // CHECK1: cond.false:
432 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
433 // CHECK1-NEXT: br label [[COND_END]]
434 // CHECK1: cond.end:
435 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
436 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
437 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
438 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
439 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
440 // CHECK1: omp.inner.for.cond:
441 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
442 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
443 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
444 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
445 // CHECK1: omp.inner.for.cond.cleanup:
446 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
447 // CHECK1: omp.inner.for.body:
448 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
449 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
450 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
451 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
452 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
453 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
454 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
455 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
456 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
457 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
458 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
459 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
460 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
461 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
462 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
463 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
464 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
465 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
466 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8
467 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
468 // CHECK1: omp.body.continue:
469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
470 // CHECK1: omp.inner.for.inc:
471 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
472 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
473 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
474 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
475 // CHECK1: omp.inner.for.end:
476 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
477 // CHECK1: omp.loop.exit:
478 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
479 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
480 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
481 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
482 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
483 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
484 // CHECK1: .omp.final.then:
485 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
486 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
487 // CHECK1: .omp.final.done:
488 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
489 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
490 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
491 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
492 // CHECK1: arraydestroy.body:
493 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
494 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
495 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
496 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
497 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
498 // CHECK1: arraydestroy.done13:
499 // CHECK1-NEXT: ret void
500 //
501 //
502 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
503 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
504 // CHECK1-NEXT: entry:
505 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
506 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
507 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
508 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
509 // CHECK1-NEXT: ret void
510 //
511 //
512 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
513 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
514 // CHECK1-NEXT: entry:
515 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
516 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
517 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
518 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
519 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
520 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
521 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
522 // CHECK1-NEXT: ret void
523 //
524 //
525 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
526 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
527 // CHECK1-NEXT: entry:
528 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
529 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
530 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
531 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
532 // CHECK1-NEXT: ret void
533 //
534 //
535 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
536 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
537 // CHECK1-NEXT: entry:
538 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
539 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
540 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
541 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
542 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
543 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
544 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
545 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
546 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
547 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
548 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
549 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
550 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
551 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
552 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
553 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
554 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
555 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
556 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
557 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
558 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
559 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
560 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
561 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
562 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
563 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
564 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
565 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
566 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
567 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
568 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
569 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
570 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8
571 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
572 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
573 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
574 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
575 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
576 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
577 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
578 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8
579 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
580 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
581 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8
582 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
583 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
584 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
585 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
586 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
587 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
588 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
589 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8
590 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
591 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
592 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
593 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
594 // CHECK1-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8
595 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
596 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
597 // CHECK1-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8
598 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
599 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
600 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
601 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
602 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
603 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
604 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
605 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
606 // CHECK1: omp_offload.failed:
607 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
608 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
609 // CHECK1: omp_offload.cont:
610 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
611 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
612 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
613 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
614 // CHECK1: arraydestroy.body:
615 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
616 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
617 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
618 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
619 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
620 // CHECK1: arraydestroy.done2:
621 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
622 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
623 // CHECK1-NEXT: ret i32 [[TMP32]]
624 //
625 //
626 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
627 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
628 // CHECK1-NEXT: entry:
629 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
630 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
631 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
632 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
633 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
634 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
635 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4
636 // CHECK1-NEXT: ret void
637 //
638 //
639 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
640 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
641 // CHECK1-NEXT: entry:
642 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
643 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
644 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
645 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
646 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
647 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
648 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
649 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
650 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
651 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
652 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
653 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
654 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
655 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
656 // CHECK1-NEXT: ret void
657 //
658 //
659 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
660 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
661 // CHECK1-NEXT: entry:
662 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
663 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
664 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
665 // CHECK1-NEXT: ret void
666 //
667 //
668 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
669 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
670 // CHECK1-NEXT: entry:
671 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
672 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
673 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
674 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
675 // CHECK1-NEXT: ret void
676 //
677 //
678 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
679 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
680 // CHECK1-NEXT: entry:
681 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
682 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
683 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
684 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
685 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
686 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
687 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
688 // CHECK1-NEXT: ret void
689 //
690 //
691 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
692 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
693 // CHECK1-NEXT: entry:
694 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
695 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
696 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
697 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
698 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
699 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
700 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
701 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
702 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
703 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
704 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
705 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
706 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
707 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
708 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
709 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
710 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
711 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
712 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
713 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
714 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
715 // CHECK1-NEXT: ret void
716 //
717 //
718 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
719 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
720 // CHECK1-NEXT: entry:
721 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
722 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
723 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
724 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
725 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
726 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
727 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
728 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
729 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
730 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
731 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
732 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
733 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
734 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
735 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
736 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
737 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
738 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
739 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
740 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
741 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
742 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
743 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
744 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
745 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
746 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
747 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
748 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
749 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
750 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
751 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
752 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
753 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
754 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
755 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
756 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
757 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
758 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
759 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
760 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
761 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
762 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
763 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
764 // CHECK1: omp.arraycpy.body:
765 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
766 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
767 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
768 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
769 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
770 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
771 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
772 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
773 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
774 // CHECK1: omp.arraycpy.done4:
775 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
776 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
777 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
778 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
779 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
780 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
781 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
782 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
783 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
784 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
785 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
786 // CHECK1: cond.true:
787 // CHECK1-NEXT: br label [[COND_END:%.*]]
788 // CHECK1: cond.false:
789 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
790 // CHECK1-NEXT: br label [[COND_END]]
791 // CHECK1: cond.end:
792 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
793 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
794 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
795 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
796 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
797 // CHECK1: omp.inner.for.cond:
798 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
799 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
800 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
801 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
802 // CHECK1: omp.inner.for.cond.cleanup:
803 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
804 // CHECK1: omp.inner.for.body:
805 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
806 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
807 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
808 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
809 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8
810 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
811 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
812 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
813 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
814 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
815 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
816 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
817 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
818 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8*
819 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8*
820 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
821 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
822 // CHECK1: omp.body.continue:
823 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
824 // CHECK1: omp.inner.for.inc:
825 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
826 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
827 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
828 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
829 // CHECK1: omp.inner.for.end:
830 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
831 // CHECK1: omp.loop.exit:
832 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
833 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
834 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
835 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
836 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
837 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
838 // CHECK1: .omp.final.then:
839 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
840 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
841 // CHECK1: .omp.final.done:
842 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
843 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
844 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
845 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
846 // CHECK1: arraydestroy.body:
847 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
848 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
849 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
850 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
851 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
852 // CHECK1: arraydestroy.done13:
853 // CHECK1-NEXT: ret void
854 //
855 //
856 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
857 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
858 // CHECK1-NEXT: entry:
859 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
860 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
861 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
862 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
863 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
864 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
865 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
866 // CHECK1-NEXT: ret void
867 //
868 //
869 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
870 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
871 // CHECK1-NEXT: entry:
872 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
873 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
874 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
875 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
876 // CHECK1-NEXT: ret void
877 //
878 //
879 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
880 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
881 // CHECK1-NEXT: entry:
882 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
883 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
884 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
885 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
886 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
887 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
888 // CHECK1-NEXT: ret void
889 //
890 //
891 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
892 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
893 // CHECK1-NEXT: entry:
894 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
895 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
896 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
897 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
898 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
899 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
900 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
901 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
902 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
903 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
904 // CHECK1-NEXT: ret void
905 //
906 //
907 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
908 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
909 // CHECK1-NEXT: entry:
910 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
911 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
912 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
913 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
914 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
915 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
916 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
917 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
918 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
919 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
920 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
921 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
922 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
923 // CHECK1-NEXT: ret void
924 //
925 //
926 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
927 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
928 // CHECK1-NEXT: entry:
929 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
930 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
931 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
932 // CHECK1-NEXT: ret void
933 //
934 //
935 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
936 // CHECK1-SAME: () #[[ATTR0]] {
937 // CHECK1-NEXT: entry:
938 // CHECK1-NEXT: call void @__cxx_global_var_init()
939 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
940 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
941 // CHECK1-NEXT: ret void
942 //
943 //
944 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
945 // CHECK1-SAME: () #[[ATTR0]] {
946 // CHECK1-NEXT: entry:
947 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
948 // CHECK1-NEXT: ret void
949 //
950 //
951 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
952 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
953 // CHECK2-NEXT: entry:
954 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
955 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
956 // CHECK2-NEXT: ret void
957 //
958 //
959 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
960 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
961 // CHECK2-NEXT: entry:
962 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
963 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
964 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
965 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
966 // CHECK2-NEXT: ret void
967 //
968 //
969 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
970 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
971 // CHECK2-NEXT: entry:
972 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
973 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
974 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
975 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
976 // CHECK2-NEXT: ret void
977 //
978 //
979 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
980 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
981 // CHECK2-NEXT: entry:
982 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
983 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
984 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
985 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
986 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
987 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
988 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
989 // CHECK2-NEXT: ret void
990 //
991 //
992 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
993 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
994 // CHECK2-NEXT: entry:
995 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
996 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
997 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
998 // CHECK2-NEXT: ret void
999 //
1000 //
1001 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1002 // CHECK2-SAME: () #[[ATTR0]] {
1003 // CHECK2-NEXT: entry:
1004 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
1005 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
1006 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1007 // CHECK2-NEXT: ret void
1008 //
1009 //
1010 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1011 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1012 // CHECK2-NEXT: entry:
1013 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1014 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1015 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1016 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1017 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1018 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1019 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1020 // CHECK2-NEXT: ret void
1021 //
1022 //
1023 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1024 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1025 // CHECK2-NEXT: entry:
1026 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1027 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1028 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1029 // CHECK2: arraydestroy.body:
1030 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1031 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1032 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1033 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1034 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1035 // CHECK2: arraydestroy.done1:
1036 // CHECK2-NEXT: ret void
1037 //
1038 //
1039 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1040 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1041 // CHECK2-NEXT: entry:
1042 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1043 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1044 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1045 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1046 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1047 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1048 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1049 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1050 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1051 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1052 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
1053 // CHECK2-NEXT: ret void
1054 //
1055 //
1056 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1057 // CHECK2-SAME: () #[[ATTR0]] {
1058 // CHECK2-NEXT: entry:
1059 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1060 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1061 // CHECK2-NEXT: ret void
1062 //
1063 //
1064 // CHECK2-LABEL: define {{[^@]+}}@main
1065 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
1066 // CHECK2-NEXT: entry:
1067 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1068 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1069 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1070 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1071 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1072 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1073 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1074 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1075 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
1076 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1077 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1078 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1079 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1080 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1081 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
1082 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1083 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1084 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
1085 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
1086 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1087 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
1088 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
1089 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1090 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1091 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1092 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
1093 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8
1094 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1095 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
1096 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8
1097 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1098 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1099 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1100 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
1101 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
1102 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1103 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
1104 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
1105 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1106 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
1107 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1108 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
1109 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
1110 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1111 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
1112 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
1113 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1114 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
1115 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1116 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1117 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
1118 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1119 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1120 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
1121 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1122 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8
1123 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1124 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1125 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
1126 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1127 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1128 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1129 // CHECK2: omp_offload.failed:
1130 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
1131 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1132 // CHECK2: omp_offload.cont:
1133 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
1134 // CHECK2-NEXT: ret i32 [[CALL]]
1135 //
1136 //
1137 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
1138 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1139 // CHECK2-NEXT: entry:
1140 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1141 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1142 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1143 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1144 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1145 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1146 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1147 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1148 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1149 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1150 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1151 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1152 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1153 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1154 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1155 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1156 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1157 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1158 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1159 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
1160 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1161 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
1162 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1163 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
1164 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1165 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
1166 // CHECK2-NEXT: ret void
1167 //
1168 //
1169 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1170 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
1171 // CHECK2-NEXT: entry:
1172 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1173 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1174 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1175 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1176 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1177 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1178 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1179 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1180 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1181 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1182 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1183 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1184 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1185 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1186 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
1187 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1188 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1189 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1190 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1191 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1192 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1193 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1194 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1195 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1196 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1197 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1198 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1199 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1200 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1201 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1202 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1203 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1204 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1205 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1206 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1207 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
1208 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1209 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
1210 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1211 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1212 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1213 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
1214 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1215 // CHECK2: omp.arraycpy.body:
1216 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1217 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1218 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1219 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1220 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1221 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1222 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1223 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1224 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
1225 // CHECK2: omp.arraycpy.done4:
1226 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
1227 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
1228 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
1229 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1230 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1231 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1232 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1233 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1234 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1235 // CHECK2: cond.true:
1236 // CHECK2-NEXT: br label [[COND_END:%.*]]
1237 // CHECK2: cond.false:
1238 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1239 // CHECK2-NEXT: br label [[COND_END]]
1240 // CHECK2: cond.end:
1241 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1242 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1243 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1244 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1245 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1246 // CHECK2: omp.inner.for.cond:
1247 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1248 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1249 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1250 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1251 // CHECK2: omp.inner.for.cond.cleanup:
1252 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1253 // CHECK2: omp.inner.for.body:
1254 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1255 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
1256 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1257 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1258 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
1259 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
1260 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
1261 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
1262 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
1263 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
1264 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64
1265 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
1266 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
1267 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
1268 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
1269 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
1270 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
1271 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
1272 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8
1273 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1274 // CHECK2: omp.body.continue:
1275 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1276 // CHECK2: omp.inner.for.inc:
1277 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1278 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
1279 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
1280 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1281 // CHECK2: omp.inner.for.end:
1282 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1283 // CHECK2: omp.loop.exit:
1284 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1285 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
1286 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
1287 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1288 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1289 // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1290 // CHECK2: .omp.final.then:
1291 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1292 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1293 // CHECK2: .omp.final.done:
1294 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1295 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1296 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
1297 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1298 // CHECK2: arraydestroy.body:
1299 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1300 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1301 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1302 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
1303 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
1304 // CHECK2: arraydestroy.done13:
1305 // CHECK2-NEXT: ret void
1306 //
1307 //
1308 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1309 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1310 // CHECK2-NEXT: entry:
1311 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1312 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1313 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1314 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
1315 // CHECK2-NEXT: ret void
1316 //
1317 //
1318 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1319 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1320 // CHECK2-NEXT: entry:
1321 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1322 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1323 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1324 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1325 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1326 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1327 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1328 // CHECK2-NEXT: ret void
1329 //
1330 //
1331 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1332 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1333 // CHECK2-NEXT: entry:
1334 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1335 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1336 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1337 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1338 // CHECK2-NEXT: ret void
1339 //
1340 //
1341 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1342 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat {
1343 // CHECK2-NEXT: entry:
1344 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1345 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1346 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1347 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1348 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1349 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1350 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1351 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1352 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1353 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1354 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1355 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1356 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1357 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
1358 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1359 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1360 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1361 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
1362 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1363 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
1364 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1365 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
1366 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
1367 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1368 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1369 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
1370 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1371 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1372 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1373 // CHECK2-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1374 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1375 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1376 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8
1377 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1378 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1379 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
1380 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1381 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8
1382 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1383 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
1384 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8
1385 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1386 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
1387 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8
1388 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1389 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8
1390 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1391 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1392 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
1393 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1394 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
1395 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8
1396 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1397 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
1398 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1399 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1400 // CHECK2-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8
1401 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1402 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
1403 // CHECK2-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8
1404 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1405 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8
1406 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1407 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1408 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
1409 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1410 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1411 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1412 // CHECK2: omp_offload.failed:
1413 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
1414 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1415 // CHECK2: omp_offload.cont:
1416 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1417 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1418 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1419 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1420 // CHECK2: arraydestroy.body:
1421 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1422 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1423 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1424 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1425 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1426 // CHECK2: arraydestroy.done2:
1427 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1428 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
1429 // CHECK2-NEXT: ret i32 [[TMP32]]
1430 //
1431 //
1432 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1433 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1434 // CHECK2-NEXT: entry:
1435 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1436 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1437 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1438 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1439 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
1440 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1441 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4
1442 // CHECK2-NEXT: ret void
1443 //
1444 //
1445 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1446 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1447 // CHECK2-NEXT: entry:
1448 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1449 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1450 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1451 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1452 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1453 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1454 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1455 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
1456 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
1457 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1458 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1459 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1460 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1461 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
1462 // CHECK2-NEXT: ret void
1463 //
1464 //
1465 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1466 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1467 // CHECK2-NEXT: entry:
1468 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1469 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1470 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1471 // CHECK2-NEXT: ret void
1472 //
1473 //
1474 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1475 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1476 // CHECK2-NEXT: entry:
1477 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1478 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1479 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1480 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1481 // CHECK2-NEXT: ret void
1482 //
1483 //
1484 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1485 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1486 // CHECK2-NEXT: entry:
1487 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1488 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1489 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1490 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1491 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1492 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1493 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
1494 // CHECK2-NEXT: ret void
1495 //
1496 //
1497 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1498 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1499 // CHECK2-NEXT: entry:
1500 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1501 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1502 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1503 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1504 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1505 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1506 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1507 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1508 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1509 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1510 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1511 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1512 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1513 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1514 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1515 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1516 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1517 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
1518 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1519 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1520 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
1521 // CHECK2-NEXT: ret void
1522 //
1523 //
1524 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1525 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1526 // CHECK2-NEXT: entry:
1527 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1528 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1529 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1530 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1531 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1532 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1533 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1534 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1535 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1536 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1537 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1538 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1539 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1540 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1541 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
1542 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1543 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1544 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1545 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
1546 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1547 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1548 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1549 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1550 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1551 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1552 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1553 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1554 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1555 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1556 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1557 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1558 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1559 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1560 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1561 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1562 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
1563 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1564 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
1565 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
1566 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
1567 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1568 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
1569 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1570 // CHECK2: omp.arraycpy.body:
1571 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1572 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1573 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1574 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1575 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1576 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1577 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1578 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1579 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
1580 // CHECK2: omp.arraycpy.done4:
1581 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1582 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
1583 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
1584 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
1585 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
1586 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1587 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1588 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1589 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1590 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
1591 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1592 // CHECK2: cond.true:
1593 // CHECK2-NEXT: br label [[COND_END:%.*]]
1594 // CHECK2: cond.false:
1595 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1596 // CHECK2-NEXT: br label [[COND_END]]
1597 // CHECK2: cond.end:
1598 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1599 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1600 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1601 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
1602 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1603 // CHECK2: omp.inner.for.cond:
1604 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1605 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1606 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1607 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1608 // CHECK2: omp.inner.for.cond.cleanup:
1609 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1610 // CHECK2: omp.inner.for.body:
1611 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1612 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
1613 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1614 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1615 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8
1616 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
1617 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
1618 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
1619 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
1620 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
1621 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1622 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64
1623 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]]
1624 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8*
1625 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8*
1626 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
1627 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1628 // CHECK2: omp.body.continue:
1629 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1630 // CHECK2: omp.inner.for.inc:
1631 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1632 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1
1633 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4
1634 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1635 // CHECK2: omp.inner.for.end:
1636 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1637 // CHECK2: omp.loop.exit:
1638 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1639 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
1640 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
1641 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1642 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1643 // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1644 // CHECK2: .omp.final.then:
1645 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1646 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1647 // CHECK2: .omp.final.done:
1648 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1649 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
1650 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
1651 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1652 // CHECK2: arraydestroy.body:
1653 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1654 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1655 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1656 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
1657 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
1658 // CHECK2: arraydestroy.done13:
1659 // CHECK2-NEXT: ret void
1660 //
1661 //
1662 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1663 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1664 // CHECK2-NEXT: entry:
1665 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1666 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1667 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1668 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1669 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1670 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1671 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1672 // CHECK2-NEXT: ret void
1673 //
1674 //
1675 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1676 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1677 // CHECK2-NEXT: entry:
1678 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1679 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1680 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1681 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1682 // CHECK2-NEXT: ret void
1683 //
1684 //
1685 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1686 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1687 // CHECK2-NEXT: entry:
1688 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1689 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1690 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1691 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1692 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1693 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1694 // CHECK2-NEXT: ret void
1695 //
1696 //
1697 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1698 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1699 // CHECK2-NEXT: entry:
1700 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1701 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1702 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1703 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1704 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1705 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1706 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1707 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1708 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1709 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1710 // CHECK2-NEXT: ret void
1711 //
1712 //
1713 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1714 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1715 // CHECK2-NEXT: entry:
1716 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1717 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1718 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1719 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1720 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1721 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1722 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1723 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
1724 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
1725 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1726 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1727 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1728 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1729 // CHECK2-NEXT: ret void
1730 //
1731 //
1732 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1733 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1734 // CHECK2-NEXT: entry:
1735 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1736 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1737 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1738 // CHECK2-NEXT: ret void
1739 //
1740 //
1741 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
1742 // CHECK2-SAME: () #[[ATTR0]] {
1743 // CHECK2-NEXT: entry:
1744 // CHECK2-NEXT: call void @__cxx_global_var_init()
1745 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
1746 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
1747 // CHECK2-NEXT: ret void
1748 //
1749 //
1750 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1751 // CHECK2-SAME: () #[[ATTR0]] {
1752 // CHECK2-NEXT: entry:
1753 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
1754 // CHECK2-NEXT: ret void
1755 //
1756 //
1757 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1758 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1759 // CHECK3-NEXT: entry:
1760 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1761 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1762 // CHECK3-NEXT: ret void
1763 //
1764 //
1765 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1766 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1767 // CHECK3-NEXT: entry:
1768 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1769 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1770 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1771 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1772 // CHECK3-NEXT: ret void
1773 //
1774 //
1775 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1776 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1777 // CHECK3-NEXT: entry:
1778 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1779 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1780 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1781 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1782 // CHECK3-NEXT: ret void
1783 //
1784 //
1785 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1786 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1787 // CHECK3-NEXT: entry:
1788 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1789 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1790 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1791 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1792 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1793 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1794 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
1795 // CHECK3-NEXT: ret void
1796 //
1797 //
1798 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1799 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1800 // CHECK3-NEXT: entry:
1801 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1802 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1803 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1804 // CHECK3-NEXT: ret void
1805 //
1806 //
1807 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1808 // CHECK3-SAME: () #[[ATTR0]] {
1809 // CHECK3-NEXT: entry:
1810 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1811 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1812 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1813 // CHECK3-NEXT: ret void
1814 //
1815 //
1816 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1817 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1818 // CHECK3-NEXT: entry:
1819 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1820 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1821 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1822 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1823 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1824 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1825 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1826 // CHECK3-NEXT: ret void
1827 //
1828 //
1829 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1830 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1831 // CHECK3-NEXT: entry:
1832 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1833 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1834 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1835 // CHECK3: arraydestroy.body:
1836 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1837 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1838 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1839 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1840 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1841 // CHECK3: arraydestroy.done1:
1842 // CHECK3-NEXT: ret void
1843 //
1844 //
1845 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1846 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1847 // CHECK3-NEXT: entry:
1848 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1849 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1850 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1851 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1852 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1853 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1854 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1855 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1856 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1857 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1858 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1859 // CHECK3-NEXT: ret void
1860 //
1861 //
1862 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1863 // CHECK3-SAME: () #[[ATTR0]] {
1864 // CHECK3-NEXT: entry:
1865 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1866 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1867 // CHECK3-NEXT: ret void
1868 //
1869 //
1870 // CHECK3-LABEL: define {{[^@]+}}@main
1871 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1872 // CHECK3-NEXT: entry:
1873 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1874 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1875 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1876 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
1877 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
1878 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
1879 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1880 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1881 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
1882 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
1883 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1884 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1885 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
1886 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1887 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1888 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1889 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
1890 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1891 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
1892 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
1893 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1894 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1895 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1896 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
1897 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4
1898 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1899 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
1900 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4
1901 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1902 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1903 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1904 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
1905 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
1906 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1907 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
1908 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
1909 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1910 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
1911 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1912 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
1913 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
1914 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1915 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
1916 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
1917 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1918 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1919 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1920 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
1921 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
1922 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1923 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
1924 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
1925 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1926 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
1927 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1928 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1929 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
1930 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1931 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1932 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1933 // CHECK3: omp_offload.failed:
1934 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
1935 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1936 // CHECK3: omp_offload.cont:
1937 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1938 // CHECK3-NEXT: ret i32 [[CALL]]
1939 //
1940 //
1941 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
1942 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1943 // CHECK3-NEXT: entry:
1944 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1945 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1946 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1947 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1948 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1949 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1950 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1951 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1952 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1953 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1954 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1955 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1956 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1957 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1958 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
1959 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
1960 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
1961 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
1962 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
1963 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
1964 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
1965 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
1966 // CHECK3-NEXT: ret void
1967 //
1968 //
1969 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1970 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
1971 // CHECK3-NEXT: entry:
1972 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1973 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1974 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
1975 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1976 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
1977 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
1978 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1979 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1980 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1981 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1982 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1983 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1984 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1985 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
1986 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1987 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1988 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1989 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1990 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1991 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1992 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1993 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
1994 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
1995 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
1996 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
1997 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
1998 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
1999 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2000 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2001 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2002 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2003 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2004 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2005 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
2006 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2007 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2008 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2009 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
2010 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2011 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
2012 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2013 // CHECK3: omp.arraycpy.body:
2014 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2015 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2016 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2017 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2018 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2019 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2020 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2021 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2022 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
2023 // CHECK3: omp.arraycpy.done3:
2024 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
2025 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
2026 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
2027 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2028 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2029 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2030 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2031 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2032 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2033 // CHECK3: cond.true:
2034 // CHECK3-NEXT: br label [[COND_END:%.*]]
2035 // CHECK3: cond.false:
2036 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2037 // CHECK3-NEXT: br label [[COND_END]]
2038 // CHECK3: cond.end:
2039 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2040 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2041 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2042 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
2043 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2044 // CHECK3: omp.inner.for.cond:
2045 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2046 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2047 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2048 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2049 // CHECK3: omp.inner.for.cond.cleanup:
2050 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2051 // CHECK3: omp.inner.for.body:
2052 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2053 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
2054 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2055 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2056 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2057 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
2058 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]]
2059 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
2060 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2061 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]]
2062 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
2063 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
2064 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
2065 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
2066 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2067 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
2068 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
2069 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2070 // CHECK3: omp.body.continue:
2071 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2072 // CHECK3: omp.inner.for.inc:
2073 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2074 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1
2075 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
2076 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2077 // CHECK3: omp.inner.for.end:
2078 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2079 // CHECK3: omp.loop.exit:
2080 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2081 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
2082 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
2083 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2084 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2085 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2086 // CHECK3: .omp.final.then:
2087 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
2088 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2089 // CHECK3: .omp.final.done:
2090 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
2091 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2092 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
2093 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2094 // CHECK3: arraydestroy.body:
2095 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2096 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2097 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2098 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2099 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2100 // CHECK3: arraydestroy.done11:
2101 // CHECK3-NEXT: ret void
2102 //
2103 //
2104 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
2105 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2106 // CHECK3-NEXT: entry:
2107 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2108 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2109 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2110 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
2111 // CHECK3-NEXT: ret void
2112 //
2113 //
2114 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
2115 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2116 // CHECK3-NEXT: entry:
2117 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2118 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2119 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2120 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2121 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2122 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2123 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2124 // CHECK3-NEXT: ret void
2125 //
2126 //
2127 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
2128 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2129 // CHECK3-NEXT: entry:
2130 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2131 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2132 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2133 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
2134 // CHECK3-NEXT: ret void
2135 //
2136 //
2137 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2138 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
2139 // CHECK3-NEXT: entry:
2140 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2141 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2142 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2143 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2144 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2145 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2146 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2147 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2148 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2149 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2150 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2151 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2152 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2153 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
2154 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2155 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2156 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2157 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
2158 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2159 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
2160 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2161 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
2162 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
2163 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2164 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
2165 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2166 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2167 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2168 // CHECK3-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2169 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2170 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
2171 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4
2172 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2173 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
2174 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
2175 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2176 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
2177 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2178 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
2179 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4
2180 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2181 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
2182 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4
2183 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2184 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
2185 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2186 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
2187 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
2188 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2189 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
2190 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4
2191 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2192 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
2193 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2194 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
2195 // CHECK3-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4
2196 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2197 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
2198 // CHECK3-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4
2199 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2200 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
2201 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2202 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2203 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
2204 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2205 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2206 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2207 // CHECK3: omp_offload.failed:
2208 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
2209 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2210 // CHECK3: omp_offload.cont:
2211 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
2212 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2213 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2214 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2215 // CHECK3: arraydestroy.body:
2216 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2217 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2218 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2219 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2220 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2221 // CHECK3: arraydestroy.done2:
2222 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2223 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
2224 // CHECK3-NEXT: ret i32 [[TMP32]]
2225 //
2226 //
2227 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
2228 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2229 // CHECK3-NEXT: entry:
2230 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2231 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2232 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2233 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
2234 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
2235 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
2236 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4
2237 // CHECK3-NEXT: ret void
2238 //
2239 //
2240 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
2241 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2242 // CHECK3-NEXT: entry:
2243 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2244 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2245 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2246 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2247 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2248 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2249 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2250 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
2251 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
2252 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2253 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2254 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
2255 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
2256 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
2257 // CHECK3-NEXT: ret void
2258 //
2259 //
2260 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
2261 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2262 // CHECK3-NEXT: entry:
2263 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2264 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2265 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2266 // CHECK3-NEXT: ret void
2267 //
2268 //
2269 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2270 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2271 // CHECK3-NEXT: entry:
2272 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2273 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2274 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2275 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2276 // CHECK3-NEXT: ret void
2277 //
2278 //
2279 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2280 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2281 // CHECK3-NEXT: entry:
2282 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2283 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2284 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2285 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2286 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2287 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2288 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2289 // CHECK3-NEXT: ret void
2290 //
2291 //
2292 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
2293 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2294 // CHECK3-NEXT: entry:
2295 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2296 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2297 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2298 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2299 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2300 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2301 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2302 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2303 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2304 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2305 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2306 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2307 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2308 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2309 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2310 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
2311 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2312 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2313 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
2314 // CHECK3-NEXT: ret void
2315 //
2316 //
2317 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
2318 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2319 // CHECK3-NEXT: entry:
2320 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2321 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2322 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2323 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2324 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
2325 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
2326 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2327 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2328 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2329 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2330 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2331 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2332 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2333 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
2334 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2335 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2336 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2337 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2338 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
2339 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2340 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2341 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2342 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2343 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2344 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2345 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
2346 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2347 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
2348 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
2349 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
2350 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2351 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2352 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2353 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2354 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2355 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2356 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2357 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2358 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2359 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2360 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
2361 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2362 // CHECK3: omp.arraycpy.body:
2363 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2364 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2365 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2366 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2367 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2368 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2369 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2370 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2371 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2372 // CHECK3: omp.arraycpy.done4:
2373 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2374 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2375 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
2376 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2377 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
2378 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2379 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
2380 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2381 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2382 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
2383 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2384 // CHECK3: cond.true:
2385 // CHECK3-NEXT: br label [[COND_END:%.*]]
2386 // CHECK3: cond.false:
2387 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2388 // CHECK3-NEXT: br label [[COND_END]]
2389 // CHECK3: cond.end:
2390 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2391 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2392 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2393 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
2394 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2395 // CHECK3: omp.inner.for.cond:
2396 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2397 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2398 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2399 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2400 // CHECK3: omp.inner.for.cond.cleanup:
2401 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2402 // CHECK3: omp.inner.for.body:
2403 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2404 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
2405 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2406 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2407 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2408 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2409 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]]
2410 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
2411 // CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
2412 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2413 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]]
2414 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
2415 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8*
2416 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
2417 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2418 // CHECK3: omp.body.continue:
2419 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2420 // CHECK3: omp.inner.for.inc:
2421 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2422 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1
2423 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
2424 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2425 // CHECK3: omp.inner.for.end:
2426 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2427 // CHECK3: omp.loop.exit:
2428 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2429 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
2430 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
2431 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2432 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2433 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2434 // CHECK3: .omp.final.then:
2435 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
2436 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2437 // CHECK3: .omp.final.done:
2438 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2439 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2440 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
2441 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2442 // CHECK3: arraydestroy.body:
2443 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2444 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2445 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2446 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2447 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2448 // CHECK3: arraydestroy.done12:
2449 // CHECK3-NEXT: ret void
2450 //
2451 //
2452 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2453 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2454 // CHECK3-NEXT: entry:
2455 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2456 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
2457 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2458 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
2459 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2460 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
2461 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2462 // CHECK3-NEXT: ret void
2463 //
2464 //
2465 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2466 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2467 // CHECK3-NEXT: entry:
2468 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2469 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2470 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2471 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2472 // CHECK3-NEXT: ret void
2473 //
2474 //
2475 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2476 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2477 // CHECK3-NEXT: entry:
2478 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2479 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2480 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2481 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2482 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2483 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2484 // CHECK3-NEXT: ret void
2485 //
2486 //
2487 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2488 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2489 // CHECK3-NEXT: entry:
2490 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2491 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2492 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2493 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2494 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2495 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2496 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2497 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2498 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2499 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2500 // CHECK3-NEXT: ret void
2501 //
2502 //
2503 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2504 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2505 // CHECK3-NEXT: entry:
2506 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2507 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
2508 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2509 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
2510 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2511 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2512 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
2513 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
2514 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
2515 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2516 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2517 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2518 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2519 // CHECK3-NEXT: ret void
2520 //
2521 //
2522 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2523 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2524 // CHECK3-NEXT: entry:
2525 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2526 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2527 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2528 // CHECK3-NEXT: ret void
2529 //
2530 //
2531 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
2532 // CHECK3-SAME: () #[[ATTR0]] {
2533 // CHECK3-NEXT: entry:
2534 // CHECK3-NEXT: call void @__cxx_global_var_init()
2535 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
2536 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
2537 // CHECK3-NEXT: ret void
2538 //
2539 //
2540 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2541 // CHECK3-SAME: () #[[ATTR0]] {
2542 // CHECK3-NEXT: entry:
2543 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2544 // CHECK3-NEXT: ret void
2545 //
2546 //
2547 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
2548 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
2549 // CHECK4-NEXT: entry:
2550 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2551 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2552 // CHECK4-NEXT: ret void
2553 //
2554 //
2555 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2556 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2557 // CHECK4-NEXT: entry:
2558 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2559 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2560 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2561 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2562 // CHECK4-NEXT: ret void
2563 //
2564 //
2565 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2566 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2567 // CHECK4-NEXT: entry:
2568 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2569 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2570 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2571 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2572 // CHECK4-NEXT: ret void
2573 //
2574 //
2575 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2576 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2577 // CHECK4-NEXT: entry:
2578 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2579 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2580 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2581 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2582 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2583 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2584 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
2585 // CHECK4-NEXT: ret void
2586 //
2587 //
2588 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2589 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2590 // CHECK4-NEXT: entry:
2591 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2592 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2593 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2594 // CHECK4-NEXT: ret void
2595 //
2596 //
2597 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2598 // CHECK4-SAME: () #[[ATTR0]] {
2599 // CHECK4-NEXT: entry:
2600 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2601 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2602 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2603 // CHECK4-NEXT: ret void
2604 //
2605 //
2606 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2607 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2608 // CHECK4-NEXT: entry:
2609 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2610 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2611 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2612 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2613 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2614 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2615 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2616 // CHECK4-NEXT: ret void
2617 //
2618 //
2619 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2620 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2621 // CHECK4-NEXT: entry:
2622 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2623 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2624 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2625 // CHECK4: arraydestroy.body:
2626 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2627 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2628 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2629 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2630 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2631 // CHECK4: arraydestroy.done1:
2632 // CHECK4-NEXT: ret void
2633 //
2634 //
2635 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2636 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2637 // CHECK4-NEXT: entry:
2638 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2639 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2640 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2641 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2642 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2643 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2644 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2645 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2646 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2647 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2648 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
2649 // CHECK4-NEXT: ret void
2650 //
2651 //
2652 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2653 // CHECK4-SAME: () #[[ATTR0]] {
2654 // CHECK4-NEXT: entry:
2655 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2656 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2657 // CHECK4-NEXT: ret void
2658 //
2659 //
2660 // CHECK4-LABEL: define {{[^@]+}}@main
2661 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
2662 // CHECK4-NEXT: entry:
2663 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2664 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2665 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2666 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
2667 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
2668 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
2669 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2670 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
2671 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
2672 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
2673 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2674 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
2675 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
2676 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2677 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2678 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
2679 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
2680 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2681 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
2682 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
2683 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2684 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
2685 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2686 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
2687 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4
2688 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2689 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
2690 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4
2691 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2692 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
2693 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2694 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
2695 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
2696 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2697 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
2698 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
2699 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2700 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
2701 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2702 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
2703 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
2704 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2705 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
2706 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
2707 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2708 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
2709 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2710 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
2711 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
2712 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2713 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
2714 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
2715 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2716 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4
2717 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2718 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2719 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
2720 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2721 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2722 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2723 // CHECK4: omp_offload.failed:
2724 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
2725 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
2726 // CHECK4: omp_offload.cont:
2727 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
2728 // CHECK4-NEXT: ret i32 [[CALL]]
2729 //
2730 //
2731 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
2732 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
2733 // CHECK4-NEXT: entry:
2734 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2735 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2736 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2737 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2738 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2739 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2740 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2741 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2742 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2743 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2744 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2745 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2746 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2747 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2748 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2749 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2750 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
2751 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2752 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2753 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
2754 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2755 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
2756 // CHECK4-NEXT: ret void
2757 //
2758 //
2759 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
2760 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
2761 // CHECK4-NEXT: entry:
2762 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2763 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2764 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2765 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2766 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2767 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2768 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2769 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2770 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2771 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2772 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2773 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2774 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2775 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
2776 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
2777 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2778 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2779 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
2780 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2781 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2782 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2783 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2784 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2785 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2786 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2787 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2788 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2789 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2790 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2791 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2792 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2793 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2794 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2795 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
2796 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2797 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2798 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2799 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
2800 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2801 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
2802 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2803 // CHECK4: omp.arraycpy.body:
2804 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2805 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2806 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2807 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2808 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2809 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2810 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2811 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2812 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
2813 // CHECK4: omp.arraycpy.done3:
2814 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
2815 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
2816 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
2817 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2818 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2819 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2820 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2821 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2822 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2823 // CHECK4: cond.true:
2824 // CHECK4-NEXT: br label [[COND_END:%.*]]
2825 // CHECK4: cond.false:
2826 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2827 // CHECK4-NEXT: br label [[COND_END]]
2828 // CHECK4: cond.end:
2829 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2830 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2831 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2832 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
2833 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2834 // CHECK4: omp.inner.for.cond:
2835 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2836 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2837 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2838 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2839 // CHECK4: omp.inner.for.cond.cleanup:
2840 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2841 // CHECK4: omp.inner.for.body:
2842 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2843 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
2844 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2845 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2846 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2847 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
2848 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]]
2849 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4
2850 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2851 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]]
2852 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
2853 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
2854 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
2855 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
2856 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2857 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
2858 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
2859 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2860 // CHECK4: omp.body.continue:
2861 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2862 // CHECK4: omp.inner.for.inc:
2863 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2864 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1
2865 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
2866 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2867 // CHECK4: omp.inner.for.end:
2868 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2869 // CHECK4: omp.loop.exit:
2870 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2871 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
2872 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
2873 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2874 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2875 // CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2876 // CHECK4: .omp.final.then:
2877 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2878 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2879 // CHECK4: .omp.final.done:
2880 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
2881 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2882 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
2883 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2884 // CHECK4: arraydestroy.body:
2885 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2886 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2887 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2888 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2889 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2890 // CHECK4: arraydestroy.done11:
2891 // CHECK4-NEXT: ret void
2892 //
2893 //
2894 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev
2895 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2896 // CHECK4-NEXT: entry:
2897 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2898 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2899 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2900 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
2901 // CHECK4-NEXT: ret void
2902 //
2903 //
2904 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
2905 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2906 // CHECK4-NEXT: entry:
2907 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2908 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2909 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2910 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2911 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2912 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2913 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2914 // CHECK4-NEXT: ret void
2915 //
2916 //
2917 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev
2918 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2919 // CHECK4-NEXT: entry:
2920 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2921 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2922 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2923 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
2924 // CHECK4-NEXT: ret void
2925 //
2926 //
2927 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2928 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat {
2929 // CHECK4-NEXT: entry:
2930 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2931 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2932 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2933 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2934 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2935 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2936 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2937 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2938 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2939 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2940 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2941 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2942 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2943 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
2944 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2945 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2946 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2947 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
2948 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2949 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
2950 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2951 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
2952 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
2953 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2954 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
2955 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2956 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2957 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2958 // CHECK4-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2959 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2960 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
2961 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4
2962 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2963 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
2964 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
2965 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2966 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4
2967 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2968 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
2969 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4
2970 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2971 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
2972 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4
2973 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2974 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4
2975 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2976 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
2977 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
2978 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2979 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
2980 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4
2981 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2982 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
2983 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2984 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
2985 // CHECK4-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4
2986 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2987 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
2988 // CHECK4-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4
2989 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2990 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4
2991 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2992 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2993 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
2994 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2995 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2996 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2997 // CHECK4: omp_offload.failed:
2998 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
2999 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3000 // CHECK4: omp_offload.cont:
3001 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
3002 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3003 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3004 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3005 // CHECK4: arraydestroy.body:
3006 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3007 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3008 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3009 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3010 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
3011 // CHECK4: arraydestroy.done2:
3012 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3013 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
3014 // CHECK4-NEXT: ret i32 [[TMP32]]
3015 //
3016 //
3017 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev
3018 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3019 // CHECK4-NEXT: entry:
3020 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3021 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3022 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3023 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
3024 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
3025 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
3026 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4
3027 // CHECK4-NEXT: ret void
3028 //
3029 //
3030 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
3031 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3032 // CHECK4-NEXT: entry:
3033 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3034 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
3035 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3036 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
3037 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3038 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3039 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
3040 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
3041 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
3042 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
3043 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3044 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
3045 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
3046 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
3047 // CHECK4-NEXT: ret void
3048 //
3049 //
3050 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev
3051 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3052 // CHECK4-NEXT: entry:
3053 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3054 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3055 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3056 // CHECK4-NEXT: ret void
3057 //
3058 //
3059 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3060 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3061 // CHECK4-NEXT: entry:
3062 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3063 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3064 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3065 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3066 // CHECK4-NEXT: ret void
3067 //
3068 //
3069 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3070 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3071 // CHECK4-NEXT: entry:
3072 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3073 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3074 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3075 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3076 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3077 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3078 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3079 // CHECK4-NEXT: ret void
3080 //
3081 //
3082 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
3083 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3084 // CHECK4-NEXT: entry:
3085 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3086 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3087 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3088 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3089 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3090 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3091 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3092 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3093 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3094 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3095 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3096 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3097 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3098 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3099 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3100 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
3101 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3102 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3103 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
3104 // CHECK4-NEXT: ret void
3105 //
3106 //
3107 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
3108 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3109 // CHECK4-NEXT: entry:
3110 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3111 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3112 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3113 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3114 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3115 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3116 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3117 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3118 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3119 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3120 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3121 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3122 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3123 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
3124 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
3125 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3126 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3127 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3128 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
3129 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3130 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3131 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3132 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3133 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3134 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3135 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3136 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3137 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3138 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3139 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3140 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3141 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3142 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3143 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3144 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3145 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3146 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
3147 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3148 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
3149 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3150 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
3151 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3152 // CHECK4: omp.arraycpy.body:
3153 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3154 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3155 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3156 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3157 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3158 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3159 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3160 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
3161 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
3162 // CHECK4: omp.arraycpy.done4:
3163 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3164 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
3165 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
3166 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
3167 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
3168 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3169 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
3170 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3171 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3172 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
3173 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3174 // CHECK4: cond.true:
3175 // CHECK4-NEXT: br label [[COND_END:%.*]]
3176 // CHECK4: cond.false:
3177 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3178 // CHECK4-NEXT: br label [[COND_END]]
3179 // CHECK4: cond.end:
3180 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
3181 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3182 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3183 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
3184 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3185 // CHECK4: omp.inner.for.cond:
3186 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3187 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3188 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
3189 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3190 // CHECK4: omp.inner.for.cond.cleanup:
3191 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3192 // CHECK4: omp.inner.for.body:
3193 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3194 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
3195 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3196 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3197 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3198 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
3199 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]]
3200 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4
3201 // CHECK4-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
3202 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3203 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]]
3204 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
3205 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8*
3206 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
3207 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3208 // CHECK4: omp.body.continue:
3209 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3210 // CHECK4: omp.inner.for.inc:
3211 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3212 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1
3213 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
3214 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
3215 // CHECK4: omp.inner.for.end:
3216 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3217 // CHECK4: omp.loop.exit:
3218 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3219 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4
3220 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]])
3221 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3222 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
3223 // CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3224 // CHECK4: .omp.final.then:
3225 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
3226 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3227 // CHECK4: .omp.final.done:
3228 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3229 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3230 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3231 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3232 // CHECK4: arraydestroy.body:
3233 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3234 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3235 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3236 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
3237 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
3238 // CHECK4: arraydestroy.done12:
3239 // CHECK4-NEXT: ret void
3240 //
3241 //
3242 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
3243 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3244 // CHECK4-NEXT: entry:
3245 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3246 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
3247 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3248 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
3249 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3250 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
3251 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
3252 // CHECK4-NEXT: ret void
3253 //
3254 //
3255 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3256 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3257 // CHECK4-NEXT: entry:
3258 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3259 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3260 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3261 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3262 // CHECK4-NEXT: ret void
3263 //
3264 //
3265 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3266 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3267 // CHECK4-NEXT: entry:
3268 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3269 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3270 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3271 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3272 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3273 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3274 // CHECK4-NEXT: ret void
3275 //
3276 //
3277 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3278 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3279 // CHECK4-NEXT: entry:
3280 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3281 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3282 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3283 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3284 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3285 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3286 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3287 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3288 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3289 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3290 // CHECK4-NEXT: ret void
3291 //
3292 //
3293 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
3294 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3295 // CHECK4-NEXT: entry:
3296 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3297 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
3298 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3299 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
3300 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3301 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3302 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
3303 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
3304 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
3305 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
3306 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3307 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
3308 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3309 // CHECK4-NEXT: ret void
3310 //
3311 //
3312 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3313 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3314 // CHECK4-NEXT: entry:
3315 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3316 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3317 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3318 // CHECK4-NEXT: ret void
3319 //
3320 //
3321 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
3322 // CHECK4-SAME: () #[[ATTR0]] {
3323 // CHECK4-NEXT: entry:
3324 // CHECK4-NEXT: call void @__cxx_global_var_init()
3325 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
3326 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
3327 // CHECK4-NEXT: ret void
3328 //
3329 //
3330 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3331 // CHECK4-SAME: () #[[ATTR0]] {
3332 // CHECK4-NEXT: entry:
3333 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
3334 // CHECK4-NEXT: ret void
3335 //
3336 //
3337 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
3338 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
3339 // CHECK5-NEXT: entry:
3340 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3341 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3342 // CHECK5-NEXT: ret void
3343 //
3344 //
3345 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3346 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3347 // CHECK5-NEXT: entry:
3348 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3349 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3350 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3351 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3352 // CHECK5-NEXT: ret void
3353 //
3354 //
3355 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3356 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3357 // CHECK5-NEXT: entry:
3358 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3359 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3360 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3361 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3362 // CHECK5-NEXT: ret void
3363 //
3364 //
3365 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3366 // CHECK5-SAME: () #[[ATTR0]] {
3367 // CHECK5-NEXT: entry:
3368 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3369 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3370 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3371 // CHECK5-NEXT: ret void
3372 //
3373 //
3374 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3375 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3376 // CHECK5-NEXT: entry:
3377 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3378 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3379 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3380 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3381 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3382 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3383 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3384 // CHECK5-NEXT: ret void
3385 //
3386 //
3387 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3388 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3389 // CHECK5-NEXT: entry:
3390 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3391 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3392 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3393 // CHECK5: arraydestroy.body:
3394 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3395 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3396 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3397 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3398 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3399 // CHECK5: arraydestroy.done1:
3400 // CHECK5-NEXT: ret void
3401 //
3402 //
3403 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3404 // CHECK5-SAME: () #[[ATTR0]] {
3405 // CHECK5-NEXT: entry:
3406 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3407 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3408 // CHECK5-NEXT: ret void
3409 //
3410 //
3411 // CHECK5-LABEL: define {{[^@]+}}@main
3412 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
3413 // CHECK5-NEXT: entry:
3414 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3415 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3416 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3417 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3418 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3419 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3420 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
3421 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3422 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3423 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3424 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3425 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3426 // CHECK5: omp.inner.for.cond:
3427 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3428 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
3429 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3430 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3431 // CHECK5: omp.inner.for.body:
3432 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3433 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3434 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3435 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
3436 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2
3437 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3438 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
3439 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]]
3440 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
3441 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3442 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
3443 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]]
3444 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
3445 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2
3446 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3447 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
3448 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
3449 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
3450 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3451 // CHECK5: omp.body.continue:
3452 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3453 // CHECK5: omp.inner.for.inc:
3454 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3455 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
3456 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3457 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
3458 // CHECK5: omp.inner.for.end:
3459 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
3460 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
3461 // CHECK5-NEXT: ret i32 [[CALL]]
3462 //
3463 //
3464 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3465 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
3466 // CHECK5-NEXT: entry:
3467 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3468 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3469 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3470 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3471 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3472 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
3473 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
3474 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
3475 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
3476 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3477 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3478 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3479 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3480 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3481 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
3482 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3483 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
3484 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
3485 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
3486 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
3487 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
3488 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
3489 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
3490 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
3491 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
3492 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
3493 // CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8
3494 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3495 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3496 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3497 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3498 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3499 // CHECK5: omp.inner.for.cond:
3500 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3501 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
3502 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3503 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3504 // CHECK5: omp.inner.for.body:
3505 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3506 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3507 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3508 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
3509 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
3510 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3511 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
3512 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
3513 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
3514 // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8, !llvm.access.group !6
3515 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3516 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP11]] to i64
3517 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
3518 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
3519 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
3520 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6
3521 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3522 // CHECK5: omp.body.continue:
3523 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3524 // CHECK5: omp.inner.for.inc:
3525 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3526 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
3527 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3528 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3529 // CHECK5: omp.inner.for.end:
3530 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
3531 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
3532 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3533 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
3534 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3535 // CHECK5: arraydestroy.body:
3536 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3537 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3538 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3539 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3540 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
3541 // CHECK5: arraydestroy.done6:
3542 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3543 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4
3544 // CHECK5-NEXT: ret i32 [[TMP16]]
3545 //
3546 //
3547 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3548 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3549 // CHECK5-NEXT: entry:
3550 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3551 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3552 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3553 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3554 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3555 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3556 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
3557 // CHECK5-NEXT: ret void
3558 //
3559 //
3560 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3561 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3562 // CHECK5-NEXT: entry:
3563 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3564 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3565 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3566 // CHECK5-NEXT: ret void
3567 //
3568 //
3569 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3570 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3571 // CHECK5-NEXT: entry:
3572 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3573 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3574 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3575 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3576 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3577 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3578 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3579 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3580 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3581 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3582 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
3583 // CHECK5-NEXT: ret void
3584 //
3585 //
3586 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3587 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3588 // CHECK5-NEXT: entry:
3589 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3590 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3591 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3592 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3593 // CHECK5-NEXT: ret void
3594 //
3595 //
3596 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3597 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3598 // CHECK5-NEXT: entry:
3599 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3600 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3601 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3602 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3603 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3604 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3605 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
3606 // CHECK5-NEXT: ret void
3607 //
3608 //
3609 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3610 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3611 // CHECK5-NEXT: entry:
3612 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3613 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3614 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3615 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3616 // CHECK5-NEXT: ret void
3617 //
3618 //
3619 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3620 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3621 // CHECK5-NEXT: entry:
3622 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3623 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3624 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3625 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3626 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3627 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3628 // CHECK5-NEXT: ret void
3629 //
3630 //
3631 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3632 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3633 // CHECK5-NEXT: entry:
3634 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3635 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3636 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3637 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3638 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3639 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3640 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3641 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3642 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3643 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3644 // CHECK5-NEXT: ret void
3645 //
3646 //
3647 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3648 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3649 // CHECK5-NEXT: entry:
3650 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3651 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3652 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3653 // CHECK5-NEXT: ret void
3654 //
3655 //
3656 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
3657 // CHECK5-SAME: () #[[ATTR0]] {
3658 // CHECK5-NEXT: entry:
3659 // CHECK5-NEXT: call void @__cxx_global_var_init()
3660 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
3661 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
3662 // CHECK5-NEXT: ret void
3663 //
3664 //
3665 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
3666 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
3667 // CHECK6-NEXT: entry:
3668 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3669 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3670 // CHECK6-NEXT: ret void
3671 //
3672 //
3673 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3674 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3675 // CHECK6-NEXT: entry:
3676 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3677 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3678 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3679 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3680 // CHECK6-NEXT: ret void
3681 //
3682 //
3683 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3684 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3685 // CHECK6-NEXT: entry:
3686 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3687 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3688 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3689 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3690 // CHECK6-NEXT: ret void
3691 //
3692 //
3693 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3694 // CHECK6-SAME: () #[[ATTR0]] {
3695 // CHECK6-NEXT: entry:
3696 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3697 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3698 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3699 // CHECK6-NEXT: ret void
3700 //
3701 //
3702 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3703 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3704 // CHECK6-NEXT: entry:
3705 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3706 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3707 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3708 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3709 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3710 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3711 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3712 // CHECK6-NEXT: ret void
3713 //
3714 //
3715 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3716 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3717 // CHECK6-NEXT: entry:
3718 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3719 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3720 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3721 // CHECK6: arraydestroy.body:
3722 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3723 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3724 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3725 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3726 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3727 // CHECK6: arraydestroy.done1:
3728 // CHECK6-NEXT: ret void
3729 //
3730 //
3731 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3732 // CHECK6-SAME: () #[[ATTR0]] {
3733 // CHECK6-NEXT: entry:
3734 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3735 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3736 // CHECK6-NEXT: ret void
3737 //
3738 //
3739 // CHECK6-LABEL: define {{[^@]+}}@main
3740 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
3741 // CHECK6-NEXT: entry:
3742 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3743 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
3744 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3745 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3746 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3747 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
3748 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
3749 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3750 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3751 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3752 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3753 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3754 // CHECK6: omp.inner.for.cond:
3755 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3756 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
3757 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3758 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3759 // CHECK6: omp.inner.for.body:
3760 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3761 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3762 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3763 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
3764 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2
3765 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3766 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
3767 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]]
3768 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
3769 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3770 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
3771 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]]
3772 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
3773 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2
3774 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
3775 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
3776 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
3777 // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
3778 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3779 // CHECK6: omp.body.continue:
3780 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3781 // CHECK6: omp.inner.for.inc:
3782 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3783 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
3784 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
3785 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
3786 // CHECK6: omp.inner.for.end:
3787 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
3788 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
3789 // CHECK6-NEXT: ret i32 [[CALL]]
3790 //
3791 //
3792 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3793 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat {
3794 // CHECK6-NEXT: entry:
3795 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3796 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3797 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3798 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3799 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3800 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
3801 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
3802 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
3803 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
3804 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3805 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3806 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3807 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
3808 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3809 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
3810 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3811 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
3812 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
3813 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
3814 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
3815 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
3816 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
3817 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
3818 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
3819 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
3820 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
3821 // CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8
3822 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3823 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3824 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3825 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3826 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3827 // CHECK6: omp.inner.for.cond:
3828 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3829 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
3830 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3831 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3832 // CHECK6: omp.inner.for.body:
3833 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3834 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3835 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3836 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
3837 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
3838 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3839 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
3840 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
3841 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
3842 // CHECK6-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8, !llvm.access.group !6
3843 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
3844 // CHECK6-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP11]] to i64
3845 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
3846 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
3847 // CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
3848 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6
3849 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3850 // CHECK6: omp.body.continue:
3851 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3852 // CHECK6: omp.inner.for.inc:
3853 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3854 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
3855 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
3856 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3857 // CHECK6: omp.inner.for.end:
3858 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
3859 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
3860 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3861 // CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
3862 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3863 // CHECK6: arraydestroy.body:
3864 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3865 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3866 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3867 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3868 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
3869 // CHECK6: arraydestroy.done6:
3870 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3871 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4
3872 // CHECK6-NEXT: ret i32 [[TMP16]]
3873 //
3874 //
3875 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3876 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3877 // CHECK6-NEXT: entry:
3878 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3879 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3880 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3881 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3882 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3883 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3884 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4
3885 // CHECK6-NEXT: ret void
3886 //
3887 //
3888 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3889 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3890 // CHECK6-NEXT: entry:
3891 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3892 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3893 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3894 // CHECK6-NEXT: ret void
3895 //
3896 //
3897 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3898 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3899 // CHECK6-NEXT: entry:
3900 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3901 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3902 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3903 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3904 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3905 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3906 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3907 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3908 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3909 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3910 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4
3911 // CHECK6-NEXT: ret void
3912 //
3913 //
3914 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3915 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3916 // CHECK6-NEXT: entry:
3917 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3918 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3919 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3920 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3921 // CHECK6-NEXT: ret void
3922 //
3923 //
3924 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3925 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3926 // CHECK6-NEXT: entry:
3927 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3928 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3929 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3930 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3931 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3932 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3933 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
3934 // CHECK6-NEXT: ret void
3935 //
3936 //
3937 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3938 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3939 // CHECK6-NEXT: entry:
3940 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3941 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3942 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3943 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3944 // CHECK6-NEXT: ret void
3945 //
3946 //
3947 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3948 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3949 // CHECK6-NEXT: entry:
3950 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3951 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3952 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3953 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3954 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3955 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3956 // CHECK6-NEXT: ret void
3957 //
3958 //
3959 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3960 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3961 // CHECK6-NEXT: entry:
3962 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3963 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3964 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3965 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3966 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3967 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3968 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3969 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3970 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3971 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3972 // CHECK6-NEXT: ret void
3973 //
3974 //
3975 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3976 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3977 // CHECK6-NEXT: entry:
3978 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3979 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3980 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3981 // CHECK6-NEXT: ret void
3982 //
3983 //
3984 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
3985 // CHECK6-SAME: () #[[ATTR0]] {
3986 // CHECK6-NEXT: entry:
3987 // CHECK6-NEXT: call void @__cxx_global_var_init()
3988 // CHECK6-NEXT: call void @__cxx_global_var_init.1()
3989 // CHECK6-NEXT: call void @__cxx_global_var_init.2()
3990 // CHECK6-NEXT: ret void
3991 //
3992 //
3993 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
3994 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
3995 // CHECK7-NEXT: entry:
3996 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3997 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3998 // CHECK7-NEXT: ret void
3999 //
4000 //
4001 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4002 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4003 // CHECK7-NEXT: entry:
4004 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4005 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4006 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4007 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4008 // CHECK7-NEXT: ret void
4009 //
4010 //
4011 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4012 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4013 // CHECK7-NEXT: entry:
4014 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4015 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4016 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4017 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4018 // CHECK7-NEXT: ret void
4019 //
4020 //
4021 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4022 // CHECK7-SAME: () #[[ATTR0]] {
4023 // CHECK7-NEXT: entry:
4024 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
4025 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
4026 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4027 // CHECK7-NEXT: ret void
4028 //
4029 //
4030 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4031 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4032 // CHECK7-NEXT: entry:
4033 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4034 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4035 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4036 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4037 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4038 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4039 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4040 // CHECK7-NEXT: ret void
4041 //
4042 //
4043 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4044 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4045 // CHECK7-NEXT: entry:
4046 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
4047 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
4048 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4049 // CHECK7: arraydestroy.body:
4050 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4051 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4052 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4053 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4054 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4055 // CHECK7: arraydestroy.done1:
4056 // CHECK7-NEXT: ret void
4057 //
4058 //
4059 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4060 // CHECK7-SAME: () #[[ATTR0]] {
4061 // CHECK7-NEXT: entry:
4062 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4063 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4064 // CHECK7-NEXT: ret void
4065 //
4066 //
4067 // CHECK7-LABEL: define {{[^@]+}}@main
4068 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
4069 // CHECK7-NEXT: entry:
4070 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4071 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
4072 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4073 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4074 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4075 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
4076 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
4077 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4078 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4079 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4080 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4081 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4082 // CHECK7: omp.inner.for.cond:
4083 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4084 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
4085 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4086 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4087 // CHECK7: omp.inner.for.body:
4088 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4089 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4090 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4091 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
4092 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3
4093 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4094 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]]
4095 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
4096 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4097 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]]
4098 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
4099 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3
4100 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4101 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
4102 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
4103 // CHECK7-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
4104 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4105 // CHECK7: omp.body.continue:
4106 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4107 // CHECK7: omp.inner.for.inc:
4108 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4109 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
4110 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4111 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4112 // CHECK7: omp.inner.for.end:
4113 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
4114 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
4115 // CHECK7-NEXT: ret i32 [[CALL]]
4116 //
4117 //
4118 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
4119 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
4120 // CHECK7-NEXT: entry:
4121 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4122 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4123 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4124 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4125 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
4126 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
4127 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4128 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
4129 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
4130 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4131 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4132 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4133 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
4134 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
4135 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
4136 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4137 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
4138 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4139 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
4140 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
4141 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
4142 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
4143 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
4144 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
4145 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
4146 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4147 // CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4
4148 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4149 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4150 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4151 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4152 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4153 // CHECK7: omp.inner.for.cond:
4154 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4155 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
4156 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4157 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4158 // CHECK7: omp.inner.for.body:
4159 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4160 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4161 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4162 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
4163 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7
4164 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4165 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
4166 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
4167 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4, !llvm.access.group !7
4168 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4169 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
4170 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8*
4171 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
4172 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7
4173 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4174 // CHECK7: omp.body.continue:
4175 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4176 // CHECK7: omp.inner.for.inc:
4177 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4178 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
4179 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4180 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4181 // CHECK7: omp.inner.for.end:
4182 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
4183 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
4184 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4185 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4186 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4187 // CHECK7: arraydestroy.body:
4188 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4189 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4190 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4191 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
4192 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
4193 // CHECK7: arraydestroy.done5:
4194 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
4195 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4
4196 // CHECK7-NEXT: ret i32 [[TMP16]]
4197 //
4198 //
4199 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4200 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4201 // CHECK7-NEXT: entry:
4202 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4203 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4204 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4205 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4206 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4207 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4208 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
4209 // CHECK7-NEXT: ret void
4210 //
4211 //
4212 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4213 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4214 // CHECK7-NEXT: entry:
4215 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4216 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4217 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4218 // CHECK7-NEXT: ret void
4219 //
4220 //
4221 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4222 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4223 // CHECK7-NEXT: entry:
4224 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4225 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4226 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4227 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4228 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4229 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4230 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4231 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4232 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4233 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4234 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
4235 // CHECK7-NEXT: ret void
4236 //
4237 //
4238 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4239 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4240 // CHECK7-NEXT: entry:
4241 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4242 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4243 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4244 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4245 // CHECK7-NEXT: ret void
4246 //
4247 //
4248 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4249 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4250 // CHECK7-NEXT: entry:
4251 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4252 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4253 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4254 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4255 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4256 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4257 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4258 // CHECK7-NEXT: ret void
4259 //
4260 //
4261 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4262 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4263 // CHECK7-NEXT: entry:
4264 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4265 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4266 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4267 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4268 // CHECK7-NEXT: ret void
4269 //
4270 //
4271 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4272 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4273 // CHECK7-NEXT: entry:
4274 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4275 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4276 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4277 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4278 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4279 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4280 // CHECK7-NEXT: ret void
4281 //
4282 //
4283 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4284 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4285 // CHECK7-NEXT: entry:
4286 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4287 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4288 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4289 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4290 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4291 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4292 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4293 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4294 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4295 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4296 // CHECK7-NEXT: ret void
4297 //
4298 //
4299 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4300 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4301 // CHECK7-NEXT: entry:
4302 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4303 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4304 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4305 // CHECK7-NEXT: ret void
4306 //
4307 //
4308 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
4309 // CHECK7-SAME: () #[[ATTR0]] {
4310 // CHECK7-NEXT: entry:
4311 // CHECK7-NEXT: call void @__cxx_global_var_init()
4312 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
4313 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
4314 // CHECK7-NEXT: ret void
4315 //
4316 //
4317 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init
4318 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
4319 // CHECK8-NEXT: entry:
4320 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4321 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4322 // CHECK8-NEXT: ret void
4323 //
4324 //
4325 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4326 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4327 // CHECK8-NEXT: entry:
4328 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4329 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4330 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4331 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4332 // CHECK8-NEXT: ret void
4333 //
4334 //
4335 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4336 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4337 // CHECK8-NEXT: entry:
4338 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4339 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4340 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4341 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4342 // CHECK8-NEXT: ret void
4343 //
4344 //
4345 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4346 // CHECK8-SAME: () #[[ATTR0]] {
4347 // CHECK8-NEXT: entry:
4348 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
4349 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
4350 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4351 // CHECK8-NEXT: ret void
4352 //
4353 //
4354 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4355 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4356 // CHECK8-NEXT: entry:
4357 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4358 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4359 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4360 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4361 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4362 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4363 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4364 // CHECK8-NEXT: ret void
4365 //
4366 //
4367 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4368 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4369 // CHECK8-NEXT: entry:
4370 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
4371 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
4372 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4373 // CHECK8: arraydestroy.body:
4374 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4375 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4376 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4377 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4378 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4379 // CHECK8: arraydestroy.done1:
4380 // CHECK8-NEXT: ret void
4381 //
4382 //
4383 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4384 // CHECK8-SAME: () #[[ATTR0]] {
4385 // CHECK8-NEXT: entry:
4386 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4387 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4388 // CHECK8-NEXT: ret void
4389 //
4390 //
4391 // CHECK8-LABEL: define {{[^@]+}}@main
4392 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] {
4393 // CHECK8-NEXT: entry:
4394 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4395 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
4396 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4397 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4398 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4399 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4400 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
4401 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4402 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4403 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4404 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4405 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4406 // CHECK8: omp.inner.for.cond:
4407 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4408 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
4409 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4410 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4411 // CHECK8: omp.inner.for.body:
4412 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4413 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4414 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4415 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
4416 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3
4417 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4418 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]]
4419 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
4420 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4421 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]]
4422 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
4423 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3
4424 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
4425 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
4426 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
4427 // CHECK8-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
4428 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4429 // CHECK8: omp.body.continue:
4430 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4431 // CHECK8: omp.inner.for.inc:
4432 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4433 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
4434 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
4435 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
4436 // CHECK8: omp.inner.for.end:
4437 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
4438 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
4439 // CHECK8-NEXT: ret i32 [[CALL]]
4440 //
4441 //
4442 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
4443 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
4444 // CHECK8-NEXT: entry:
4445 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4446 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4447 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4448 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4449 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
4450 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
4451 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4452 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
4453 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
4454 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4455 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4456 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4457 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4458 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
4459 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
4460 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4461 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
4462 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4463 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
4464 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
4465 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
4466 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
4467 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
4468 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
4469 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
4470 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4471 // CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4
4472 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4473 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4474 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4475 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4476 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4477 // CHECK8: omp.inner.for.cond:
4478 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4479 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
4480 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4481 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4482 // CHECK8: omp.inner.for.body:
4483 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4484 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4485 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4486 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
4487 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7
4488 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4489 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
4490 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
4491 // CHECK8-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4, !llvm.access.group !7
4492 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
4493 // CHECK8-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
4494 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8*
4495 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
4496 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7
4497 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4498 // CHECK8: omp.body.continue:
4499 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4500 // CHECK8: omp.inner.for.inc:
4501 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4502 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
4503 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
4504 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
4505 // CHECK8: omp.inner.for.end:
4506 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
4507 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
4508 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4509 // CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4510 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4511 // CHECK8: arraydestroy.body:
4512 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4513 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4514 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4515 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
4516 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
4517 // CHECK8: arraydestroy.done5:
4518 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
4519 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4
4520 // CHECK8-NEXT: ret i32 [[TMP16]]
4521 //
4522 //
4523 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4524 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4525 // CHECK8-NEXT: entry:
4526 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4527 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4528 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4529 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4530 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4531 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4532 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4
4533 // CHECK8-NEXT: ret void
4534 //
4535 //
4536 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4537 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4538 // CHECK8-NEXT: entry:
4539 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4540 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4541 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4542 // CHECK8-NEXT: ret void
4543 //
4544 //
4545 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4546 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4547 // CHECK8-NEXT: entry:
4548 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4549 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4550 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4551 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4552 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4553 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4554 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4555 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4556 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4557 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4558 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4
4559 // CHECK8-NEXT: ret void
4560 //
4561 //
4562 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4563 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4564 // CHECK8-NEXT: entry:
4565 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4566 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4567 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4568 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4569 // CHECK8-NEXT: ret void
4570 //
4571 //
4572 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4573 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4574 // CHECK8-NEXT: entry:
4575 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4576 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4577 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4578 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4579 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4580 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4581 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4582 // CHECK8-NEXT: ret void
4583 //
4584 //
4585 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4586 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4587 // CHECK8-NEXT: entry:
4588 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4589 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4590 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4591 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4592 // CHECK8-NEXT: ret void
4593 //
4594 //
4595 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4596 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4597 // CHECK8-NEXT: entry:
4598 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4599 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4600 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4601 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4602 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4603 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4604 // CHECK8-NEXT: ret void
4605 //
4606 //
4607 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4608 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4609 // CHECK8-NEXT: entry:
4610 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4611 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4612 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4613 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4614 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4615 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4616 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4617 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4618 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4619 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4620 // CHECK8-NEXT: ret void
4621 //
4622 //
4623 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4624 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4625 // CHECK8-NEXT: entry:
4626 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4627 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4628 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4629 // CHECK8-NEXT: ret void
4630 //
4631 //
4632 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
4633 // CHECK8-SAME: () #[[ATTR0]] {
4634 // CHECK8-NEXT: entry:
4635 // CHECK8-NEXT: call void @__cxx_global_var_init()
4636 // CHECK8-NEXT: call void @__cxx_global_var_init.1()
4637 // CHECK8-NEXT: call void @__cxx_global_var_init.2()
4638 // CHECK8-NEXT: ret void
4639 //
4640 //
4641 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
4642 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
4643 // CHECK9-NEXT: entry:
4644 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4645 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4646 // CHECK9-NEXT: ret void
4647 //
4648 //
4649 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4650 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4651 // CHECK9-NEXT: entry:
4652 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4653 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4654 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4655 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4656 // CHECK9-NEXT: ret void
4657 //
4658 //
4659 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4660 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4661 // CHECK9-NEXT: entry:
4662 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4663 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4664 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4665 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4666 // CHECK9-NEXT: ret void
4667 //
4668 //
4669 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4670 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4671 // CHECK9-NEXT: entry:
4672 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4673 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4674 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4675 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4676 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4677 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4678 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
4679 // CHECK9-NEXT: ret void
4680 //
4681 //
4682 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4683 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4684 // CHECK9-NEXT: entry:
4685 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4686 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4687 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4688 // CHECK9-NEXT: ret void
4689 //
4690 //
4691 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4692 // CHECK9-SAME: () #[[ATTR0]] {
4693 // CHECK9-NEXT: entry:
4694 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4695 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4696 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4697 // CHECK9-NEXT: ret void
4698 //
4699 //
4700 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4701 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4702 // CHECK9-NEXT: entry:
4703 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4704 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4705 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4706 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4707 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4708 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4709 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4710 // CHECK9-NEXT: ret void
4711 //
4712 //
4713 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4714 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4715 // CHECK9-NEXT: entry:
4716 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4717 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4718 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4719 // CHECK9: arraydestroy.body:
4720 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4721 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4722 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4723 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4724 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4725 // CHECK9: arraydestroy.done1:
4726 // CHECK9-NEXT: ret void
4727 //
4728 //
4729 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4730 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4731 // CHECK9-NEXT: entry:
4732 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4733 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4734 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4735 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4736 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4737 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4738 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4739 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4740 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4741 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4742 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
4743 // CHECK9-NEXT: ret void
4744 //
4745 //
4746 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4747 // CHECK9-SAME: () #[[ATTR0]] {
4748 // CHECK9-NEXT: entry:
4749 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4750 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4751 // CHECK9-NEXT: ret void
4752 //
4753 //
4754 // CHECK9-LABEL: define {{[^@]+}}@main
4755 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
4756 // CHECK9-NEXT: entry:
4757 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4758 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4759 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
4760 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4761 // CHECK9-NEXT: ret i32 0
4762 //
4763 //
4764 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
4765 // CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
4766 // CHECK9-NEXT: entry:
4767 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4768 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4769 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4770 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4771 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
4772 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
4773 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
4774 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4775 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4776 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4777 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4778 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4779 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4780 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
4781 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
4782 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
4783 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
4784 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
4785 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
4786 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
4787 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
4788 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
4789 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
4790 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
4791 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
4792 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
4793 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
4794 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
4795 // CHECK9-NEXT: ret void
4796 //
4797 //
4798 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
4799 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
4800 // CHECK9-NEXT: entry:
4801 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4802 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4803 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
4804 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4805 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
4806 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4807 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4808 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
4809 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4810 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4811 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4812 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4813 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4814 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
4815 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4816 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4817 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
4818 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4819 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
4820 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
4821 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4822 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
4823 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
4824 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4825 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4826 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4827 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4828 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4829 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4830 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4831 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4832 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
4833 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4834 // CHECK9: cond.true:
4835 // CHECK9-NEXT: br label [[COND_END:%.*]]
4836 // CHECK9: cond.false:
4837 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4838 // CHECK9-NEXT: br label [[COND_END]]
4839 // CHECK9: cond.end:
4840 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4841 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4842 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4843 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4844 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4845 // CHECK9: omp.inner.for.cond:
4846 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4847 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4848 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4849 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4850 // CHECK9: omp.inner.for.body:
4851 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4852 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4853 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4854 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4855 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8
4856 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
4857 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
4858 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8
4859 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
4860 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
4861 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
4862 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8
4863 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
4864 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
4865 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8
4866 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
4867 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4868 // CHECK9: omp.body.continue:
4869 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4870 // CHECK9: omp.inner.for.inc:
4871 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4872 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
4873 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
4874 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4875 // CHECK9: omp.inner.for.end:
4876 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4877 // CHECK9: omp.loop.exit:
4878 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4879 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4880 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
4881 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4882 // CHECK9: .omp.final.then:
4883 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
4884 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
4885 // CHECK9: .omp.final.done:
4886 // CHECK9-NEXT: ret void
4887 //
4888 //
4889 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
4890 // CHECK9-SAME: () #[[ATTR0]] {
4891 // CHECK9-NEXT: entry:
4892 // CHECK9-NEXT: call void @__cxx_global_var_init()
4893 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
4894 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
4895 // CHECK9-NEXT: ret void
4896 //
4897 //
4898 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4899 // CHECK9-SAME: () #[[ATTR0]] {
4900 // CHECK9-NEXT: entry:
4901 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
4902 // CHECK9-NEXT: ret void
4903 //
4904 //
4905 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init
4906 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
4907 // CHECK10-NEXT: entry:
4908 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4909 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4910 // CHECK10-NEXT: ret void
4911 //
4912 //
4913 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4914 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4915 // CHECK10-NEXT: entry:
4916 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4917 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4918 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4919 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4920 // CHECK10-NEXT: ret void
4921 //
4922 //
4923 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4924 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4925 // CHECK10-NEXT: entry:
4926 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4927 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4928 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4929 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4930 // CHECK10-NEXT: ret void
4931 //
4932 //
4933 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4934 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4935 // CHECK10-NEXT: entry:
4936 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4937 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4938 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4939 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4940 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4941 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4942 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4
4943 // CHECK10-NEXT: ret void
4944 //
4945 //
4946 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4947 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4948 // CHECK10-NEXT: entry:
4949 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4950 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4951 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4952 // CHECK10-NEXT: ret void
4953 //
4954 //
4955 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4956 // CHECK10-SAME: () #[[ATTR0]] {
4957 // CHECK10-NEXT: entry:
4958 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4959 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4960 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4961 // CHECK10-NEXT: ret void
4962 //
4963 //
4964 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4965 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4966 // CHECK10-NEXT: entry:
4967 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4968 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4969 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4970 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4971 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4972 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4973 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4974 // CHECK10-NEXT: ret void
4975 //
4976 //
4977 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4978 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4979 // CHECK10-NEXT: entry:
4980 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4981 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4982 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4983 // CHECK10: arraydestroy.body:
4984 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4985 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4986 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4987 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4988 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4989 // CHECK10: arraydestroy.done1:
4990 // CHECK10-NEXT: ret void
4991 //
4992 //
4993 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4994 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4995 // CHECK10-NEXT: entry:
4996 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4997 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4998 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4999 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5000 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5001 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5002 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5003 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5004 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5005 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5006 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4
5007 // CHECK10-NEXT: ret void
5008 //
5009 //
5010 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5011 // CHECK10-SAME: () #[[ATTR0]] {
5012 // CHECK10-NEXT: entry:
5013 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5014 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5015 // CHECK10-NEXT: ret void
5016 //
5017 //
5018 // CHECK10-LABEL: define {{[^@]+}}@main
5019 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
5020 // CHECK10-NEXT: entry:
5021 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5022 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
5023 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
5024 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
5025 // CHECK10-NEXT: ret i32 0
5026 //
5027 //
5028 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
5029 // CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
5030 // CHECK10-NEXT: entry:
5031 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
5032 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5033 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
5034 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
5035 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
5036 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
5037 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5038 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
5039 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5040 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
5041 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5042 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5043 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5044 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
5045 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5046 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
5047 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
5048 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
5049 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
5050 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
5051 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
5052 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
5053 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
5054 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
5055 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5056 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
5057 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5058 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
5059 // CHECK10-NEXT: ret void
5060 //
5061 //
5062 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
5063 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
5064 // CHECK10-NEXT: entry:
5065 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5066 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5067 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
5068 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
5069 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5070 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
5071 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5072 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
5073 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5074 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5075 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5076 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5077 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
5078 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
5079 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5080 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5081 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
5082 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
5083 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5084 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5085 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5086 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5087 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
5088 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5089 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5090 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5091 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5092 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5093 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5094 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5095 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5096 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
5097 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5098 // CHECK10: cond.true:
5099 // CHECK10-NEXT: br label [[COND_END:%.*]]
5100 // CHECK10: cond.false:
5101 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5102 // CHECK10-NEXT: br label [[COND_END]]
5103 // CHECK10: cond.end:
5104 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5105 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5106 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5107 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5108 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5109 // CHECK10: omp.inner.for.cond:
5110 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5111 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5112 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5113 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5114 // CHECK10: omp.inner.for.body:
5115 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5116 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
5117 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5118 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5119 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8
5120 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
5121 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
5122 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8
5123 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
5124 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
5125 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
5126 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8
5127 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
5128 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
5129 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8
5130 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
5131 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5132 // CHECK10: omp.body.continue:
5133 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5134 // CHECK10: omp.inner.for.inc:
5135 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5136 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
5137 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
5138 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
5139 // CHECK10: omp.inner.for.end:
5140 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5141 // CHECK10: omp.loop.exit:
5142 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5143 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5144 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
5145 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5146 // CHECK10: .omp.final.then:
5147 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
5148 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
5149 // CHECK10: .omp.final.done:
5150 // CHECK10-NEXT: ret void
5151 //
5152 //
5153 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
5154 // CHECK10-SAME: () #[[ATTR0]] {
5155 // CHECK10-NEXT: entry:
5156 // CHECK10-NEXT: call void @__cxx_global_var_init()
5157 // CHECK10-NEXT: call void @__cxx_global_var_init.1()
5158 // CHECK10-NEXT: call void @__cxx_global_var_init.2()
5159 // CHECK10-NEXT: ret void
5160 //
5161 //
5162 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5163 // CHECK10-SAME: () #[[ATTR0]] {
5164 // CHECK10-NEXT: entry:
5165 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
5166 // CHECK10-NEXT: ret void
5167 //
5168 //
5169 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
5170 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
5171 // CHECK11-NEXT: entry:
5172 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5173 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5174 // CHECK11-NEXT: ret void
5175 //
5176 //
5177 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5178 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5179 // CHECK11-NEXT: entry:
5180 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5181 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5182 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5183 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5184 // CHECK11-NEXT: ret void
5185 //
5186 //
5187 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5188 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5189 // CHECK11-NEXT: entry:
5190 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5191 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5192 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5193 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5194 // CHECK11-NEXT: ret void
5195 //
5196 //
5197 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5198 // CHECK11-SAME: () #[[ATTR0]] {
5199 // CHECK11-NEXT: entry:
5200 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
5201 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
5202 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5203 // CHECK11-NEXT: ret void
5204 //
5205 //
5206 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5207 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5208 // CHECK11-NEXT: entry:
5209 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5210 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5211 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5212 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5213 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5214 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5215 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5216 // CHECK11-NEXT: ret void
5217 //
5218 //
5219 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5220 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5221 // CHECK11-NEXT: entry:
5222 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
5223 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
5224 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5225 // CHECK11: arraydestroy.body:
5226 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5227 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5228 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5229 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5230 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5231 // CHECK11: arraydestroy.done1:
5232 // CHECK11-NEXT: ret void
5233 //
5234 //
5235 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5236 // CHECK11-SAME: () #[[ATTR0]] {
5237 // CHECK11-NEXT: entry:
5238 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5239 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5240 // CHECK11-NEXT: ret void
5241 //
5242 //
5243 // CHECK11-LABEL: define {{[^@]+}}@main
5244 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
5245 // CHECK11-NEXT: entry:
5246 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5247 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
5248 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
5249 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
5250 // CHECK11-NEXT: ret i32 0
5251 //
5252 //
5253 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5254 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5255 // CHECK11-NEXT: entry:
5256 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5257 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5258 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5259 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5260 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5261 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5262 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
5263 // CHECK11-NEXT: ret void
5264 //
5265 //
5266 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5267 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5268 // CHECK11-NEXT: entry:
5269 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5270 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5271 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5272 // CHECK11-NEXT: ret void
5273 //
5274 //
5275 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5276 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5277 // CHECK11-NEXT: entry:
5278 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5279 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5280 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5281 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5282 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5283 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5284 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5285 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5286 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5287 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5288 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
5289 // CHECK11-NEXT: ret void
5290 //
5291 //
5292 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
5293 // CHECK11-SAME: () #[[ATTR0]] {
5294 // CHECK11-NEXT: entry:
5295 // CHECK11-NEXT: call void @__cxx_global_var_init()
5296 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
5297 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
5298 // CHECK11-NEXT: ret void
5299 //
5300 //
5301 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init
5302 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
5303 // CHECK12-NEXT: entry:
5304 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5305 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5306 // CHECK12-NEXT: ret void
5307 //
5308 //
5309 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5310 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5311 // CHECK12-NEXT: entry:
5312 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5313 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5314 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5315 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5316 // CHECK12-NEXT: ret void
5317 //
5318 //
5319 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5320 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5321 // CHECK12-NEXT: entry:
5322 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5323 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5324 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5325 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5326 // CHECK12-NEXT: ret void
5327 //
5328 //
5329 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5330 // CHECK12-SAME: () #[[ATTR0]] {
5331 // CHECK12-NEXT: entry:
5332 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
5333 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
5334 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5335 // CHECK12-NEXT: ret void
5336 //
5337 //
5338 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5339 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5340 // CHECK12-NEXT: entry:
5341 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5342 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5343 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5344 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5345 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5346 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5347 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5348 // CHECK12-NEXT: ret void
5349 //
5350 //
5351 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5352 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5353 // CHECK12-NEXT: entry:
5354 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
5355 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
5356 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5357 // CHECK12: arraydestroy.body:
5358 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5359 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5360 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5361 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5362 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5363 // CHECK12: arraydestroy.done1:
5364 // CHECK12-NEXT: ret void
5365 //
5366 //
5367 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5368 // CHECK12-SAME: () #[[ATTR0]] {
5369 // CHECK12-NEXT: entry:
5370 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5371 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5372 // CHECK12-NEXT: ret void
5373 //
5374 //
5375 // CHECK12-LABEL: define {{[^@]+}}@main
5376 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
5377 // CHECK12-NEXT: entry:
5378 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5379 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
5380 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
5381 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
5382 // CHECK12-NEXT: ret i32 0
5383 //
5384 //
5385 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5386 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5387 // CHECK12-NEXT: entry:
5388 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5389 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5390 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5391 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5392 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5393 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5394 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4
5395 // CHECK12-NEXT: ret void
5396 //
5397 //
5398 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5399 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5400 // CHECK12-NEXT: entry:
5401 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5402 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5403 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5404 // CHECK12-NEXT: ret void
5405 //
5406 //
5407 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5408 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5409 // CHECK12-NEXT: entry:
5410 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5411 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5412 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5413 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5414 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5415 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5416 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5417 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5418 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5419 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5420 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4
5421 // CHECK12-NEXT: ret void
5422 //
5423 //
5424 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp
5425 // CHECK12-SAME: () #[[ATTR0]] {
5426 // CHECK12-NEXT: entry:
5427 // CHECK12-NEXT: call void @__cxx_global_var_init()
5428 // CHECK12-NEXT: call void @__cxx_global_var_init.1()
5429 // CHECK12-NEXT: call void @__cxx_global_var_init.2()
5430 // CHECK12-NEXT: ret void
5431 //
5432