1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", F), 24 A>; 25 26// Register classes for RegCall 27class RC_X86_RegCall { 28 list<Register> GPR_8 = []; 29 list<Register> GPR_16 = []; 30 list<Register> GPR_32 = []; 31 list<Register> GPR_64 = []; 32 list<Register> FP_CALL = [FP0]; 33 list<Register> FP_RET = [FP0, FP1]; 34 list<Register> XMM = []; 35 list<Register> YMM = []; 36 list<Register> ZMM = []; 37} 38 39// RegCall register classes for 32 bits 40def RC_X86_32_RegCall : RC_X86_RegCall { 41 let GPR_8 = [AL, CL, DL, DIL, SIL]; 42 let GPR_16 = [AX, CX, DX, DI, SI]; 43 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 44 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 45 ///< \todo Fix AssignToReg to enable empty lists 46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 47 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 48 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 49} 50 51class RC_X86_64_RegCall : RC_X86_RegCall { 52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 53 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 55 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 56 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 57 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 58} 59 60def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 61 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 62 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 63 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 65} 66 67def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 68 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 72} 73 74// X86-64 Intel regcall calling convention. 75multiclass X86_RegCall_base<RC_X86_RegCall RC> { 76def CC_#NAME : CallingConv<[ 77 // Handles byval parameters. 78 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 79 CCIfByVal<CCPassByVal<4, 4>>, 80 81 // Promote i1/i8/i16/v1i1 arguments to i32. 82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 83 84 // Promote v8i1/v16i1/v32i1 arguments to i32. 85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 86 87 // bool, char, int, enum, long, pointer --> GPR 88 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 89 90 // long long, __int64 --> GPR 91 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 92 93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 94 CCIfType<[v64i1], CCPromoteToType<i64>>, 95 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 96 CCAssignToReg<RC.GPR_64>>>, 97 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 98 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 99 100 // float, double, float128 --> XMM 101 // In the case of SSE disabled --> save to stack 102 CCIfType<[f32, f64, f128], 103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 104 105 // long double --> FP 106 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 107 108 // __m128, __m128i, __m128d --> XMM 109 // In the case of SSE disabled --> save to stack 110 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 112 113 // __m256, __m256i, __m256d --> YMM 114 // In the case of SSE disabled --> save to stack 115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 116 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 117 118 // __m512, __m512i, __m512d --> ZMM 119 // In the case of SSE disabled --> save to stack 120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 121 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 122 123 // If no register was found -> assign to stack 124 125 // In 64 bit, assign 64/32 bit values to 8 byte stack 126 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 127 CCAssignToStack<8, 8>>>, 128 129 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 130 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 131 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 132 133 // MMX type gets 8 byte slot in stack , while alignment depends on target 134 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, 135 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 136 137 // float 128 get stack slots whose size and alignment depends 138 // on the subtarget. 139 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 140 141 // Vectors get 16-byte stack slots that are 16-byte aligned. 142 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 143 CCAssignToStack<16, 16>>, 144 145 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 147 CCAssignToStack<32, 32>>, 148 149 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 151 CCAssignToStack<64, 64>> 152]>; 153 154def RetCC_#NAME : CallingConv<[ 155 // Promote i1, v1i1, v8i1 arguments to i8. 156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 157 158 // Promote v16i1 arguments to i16. 159 CCIfType<[v16i1], CCPromoteToType<i16>>, 160 161 // Promote v32i1 arguments to i32. 162 CCIfType<[v32i1], CCPromoteToType<i32>>, 163 164 // bool, char, int, enum, long, pointer --> GPR 165 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 166 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 167 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 168 169 // long long, __int64 --> GPR 170 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 171 172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 173 CCIfType<[v64i1], CCPromoteToType<i64>>, 174 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 175 CCAssignToReg<RC.GPR_64>>>, 176 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 177 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 178 179 // long double --> FP 180 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 181 182 // float, double, float128 --> XMM 183 CCIfType<[f32, f64, f128], 184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 185 186 // __m128, __m128i, __m128d --> XMM 187 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 188 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 189 190 // __m256, __m256i, __m256d --> YMM 191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 192 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 193 194 // __m512, __m512i, __m512d --> ZMM 195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 196 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 197]>; 198} 199 200//===----------------------------------------------------------------------===// 201// Return Value Calling Conventions 202//===----------------------------------------------------------------------===// 203 204// Return-value conventions common to all X86 CC's. 205def RetCC_X86Common : CallingConv<[ 206 // Scalar values are returned in AX first, then DX. For i8, the ABI 207 // requires the values to be in AL and AH, however this code uses AL and DL 208 // instead. This is because using AH for the second register conflicts with 209 // the way LLVM does multiple return values -- a return of {i16,i8} would end 210 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 211 // for functions that return two i8 values are currently expected to pack the 212 // values into an i16 (which uses AX, and thus AL:AH). 213 // 214 // For code that doesn't care about the ABI, we allow returning more than two 215 // integer values in registers. 216 CCIfType<[v1i1], CCPromoteToType<i8>>, 217 CCIfType<[i1], CCPromoteToType<i8>>, 218 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 219 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 220 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 222 223 // Boolean vectors of AVX-512 are returned in SIMD registers. 224 // The call from AVX to AVX-512 function should work, 225 // since the boolean types in AVX/AVX2 are promoted by default. 226 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 227 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 228 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 229 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 230 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 231 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 232 233 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 234 // can only be used by ABI non-compliant code. If the target doesn't have XMM 235 // registers, it won't have vector types. 236 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 237 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 238 239 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 240 // can only be used by ABI non-compliant code. This vector type is only 241 // supported while using the AVX target feature. 242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 243 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 244 245 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 246 // can only be used by ABI non-compliant code. This vector type is only 247 // supported while using the AVX-512 target feature. 248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 249 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 250 251 // MMX vector types are always returned in MM0. If the target doesn't have 252 // MM0, it doesn't support these vector types. 253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 254 255 // Long double types are always returned in FP0 (even with SSE), 256 // except on Win64. 257 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 258]>; 259 260// X86-32 C return-value convention. 261def RetCC_X86_32_C : CallingConv<[ 262 // The X86-32 calling convention returns FP values in FP0, unless marked 263 // with "inreg" (used here to distinguish one kind of reg from another, 264 // weirdly; this is really the sse-regparm calling convention) in which 265 // case they use XMM0, otherwise it is the same as the common X86 calling 266 // conv. 267 CCIfInReg<CCIfSubtarget<"hasSSE2()", 268 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 269 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, 270 CCDelegateTo<RetCC_X86Common> 271]>; 272 273// X86-32 FastCC return-value convention. 274def RetCC_X86_32_Fast : CallingConv<[ 275 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 276 // SSE2. 277 // This can happen when a float, 2 x float, or 3 x float vector is split by 278 // target lowering, and is returned in 1-3 sse regs. 279 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 280 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 281 282 // For integers, ECX can be used as an extra return register 283 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 284 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 285 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 286 287 // Otherwise, it is the same as the common X86 calling convention. 288 CCDelegateTo<RetCC_X86Common> 289]>; 290 291// Intel_OCL_BI return-value convention. 292def RetCC_Intel_OCL_BI : CallingConv<[ 293 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 294 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 295 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 296 297 // 256-bit FP vectors 298 // No more than 4 registers 299 CCIfType<[v8f32, v4f64, v8i32, v4i64], 300 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 301 302 // 512-bit FP vectors 303 CCIfType<[v16f32, v8f64, v16i32, v8i64], 304 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 305 306 // i32, i64 in the standard way 307 CCDelegateTo<RetCC_X86Common> 308]>; 309 310// X86-32 HiPE return-value convention. 311def RetCC_X86_32_HiPE : CallingConv<[ 312 // Promote all types to i32 313 CCIfType<[i8, i16], CCPromoteToType<i32>>, 314 315 // Return: HP, P, VAL1, VAL2 316 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 317]>; 318 319// X86-32 Vectorcall return-value convention. 320def RetCC_X86_32_VectorCall : CallingConv<[ 321 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 322 CCIfType<[f32, f64, f128], 323 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 324 325 // Return integers in the standard way. 326 CCDelegateTo<RetCC_X86Common> 327]>; 328 329// X86-64 C return-value convention. 330def RetCC_X86_64_C : CallingConv<[ 331 // The X86-64 calling convention always returns FP values in XMM0. 332 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 333 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 334 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 335 336 // MMX vector types are always returned in XMM0. 337 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 338 339 // Pointers are always returned in full 64-bit registers. 340 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 341 342 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 343 344 CCDelegateTo<RetCC_X86Common> 345]>; 346 347// X86-Win64 C return-value convention. 348def RetCC_X86_Win64_C : CallingConv<[ 349 // The X86-Win64 calling convention always returns __m64 values in RAX. 350 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 351 352 // GCC returns FP values in RAX on Win64. 353 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 354 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 355 356 // Otherwise, everything is the same as 'normal' X86-64 C CC. 357 CCDelegateTo<RetCC_X86_64_C> 358]>; 359 360// X86-64 vectorcall return-value convention. 361def RetCC_X86_64_Vectorcall : CallingConv<[ 362 // Vectorcall calling convention always returns FP values in XMMs. 363 CCIfType<[f32, f64, f128], 364 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 365 366 // Otherwise, everything is the same as Windows X86-64 C CC. 367 CCDelegateTo<RetCC_X86_Win64_C> 368]>; 369 370// X86-64 HiPE return-value convention. 371def RetCC_X86_64_HiPE : CallingConv<[ 372 // Promote all types to i64 373 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 374 375 // Return: HP, P, VAL1, VAL2 376 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 377]>; 378 379// X86-64 WebKit_JS return-value convention. 380def RetCC_X86_64_WebKit_JS : CallingConv<[ 381 // Promote all types to i64 382 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 383 384 // Return: RAX 385 CCIfType<[i64], CCAssignToReg<[RAX]>> 386]>; 387 388def RetCC_X86_64_Swift : CallingConv<[ 389 390 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 391 392 // For integers, ECX, R8D can be used as extra return registers. 393 CCIfType<[v1i1], CCPromoteToType<i8>>, 394 CCIfType<[i1], CCPromoteToType<i8>>, 395 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 396 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 397 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 398 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 399 400 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 401 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 402 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 403 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 404 405 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. 406 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 407 CCDelegateTo<RetCC_X86Common> 408]>; 409 410// X86-64 AnyReg return-value convention. No explicit register is specified for 411// the return-value. The register allocator is allowed and expected to choose 412// any free register. 413// 414// This calling convention is currently only supported by the stackmap and 415// patchpoint intrinsics. All other uses will result in an assert on Debug 416// builds. On Release builds we fallback to the X86 C calling convention. 417def RetCC_X86_64_AnyReg : CallingConv<[ 418 CCCustom<"CC_X86_AnyReg_Error"> 419]>; 420 421// X86-64 HHVM return-value convention. 422def RetCC_X86_64_HHVM: CallingConv<[ 423 // Promote all types to i64 424 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 425 426 // Return: could return in any GP register save RSP and R12. 427 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, 428 RAX, R10, R11, R13, R14, R15]>> 429]>; 430 431 432defm X86_32_RegCall : 433 X86_RegCall_base<RC_X86_32_RegCall>; 434defm X86_Win64_RegCall : 435 X86_RegCall_base<RC_X86_64_RegCall_Win>; 436defm X86_SysV64_RegCall : 437 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 438 439// This is the root return-value convention for the X86-32 backend. 440def RetCC_X86_32 : CallingConv<[ 441 // If FastCC, use RetCC_X86_32_Fast. 442 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 443 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 444 // CFGuard_Check never returns a value so does not need a RetCC. 445 // If HiPE, use RetCC_X86_32_HiPE. 446 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 447 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 448 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 449 450 // Otherwise, use RetCC_X86_32_C. 451 CCDelegateTo<RetCC_X86_32_C> 452]>; 453 454// This is the root return-value convention for the X86-64 backend. 455def RetCC_X86_64 : CallingConv<[ 456 // HiPE uses RetCC_X86_64_HiPE 457 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 458 459 // Handle JavaScript calls. 460 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 461 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 462 463 // Handle Swift calls. 464 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 465 CCIfCC<"CallingConv::SwiftTail", CCDelegateTo<RetCC_X86_64_Swift>>, 466 467 // Handle explicit CC selection 468 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 469 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 470 471 // Handle Vectorcall CC 472 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 473 474 // Handle HHVM calls. 475 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>, 476 477 CCIfCC<"CallingConv::X86_RegCall", 478 CCIfSubtarget<"isTargetWin64()", 479 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 480 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 481 482 // Mingw64 and native Win64 use Win64 CC 483 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 484 485 // Otherwise, drop to normal X86-64 CC 486 CCDelegateTo<RetCC_X86_64_C> 487]>; 488 489// This is the return-value convention used for the entire X86 backend. 490let Entry = 1 in 491def RetCC_X86 : CallingConv<[ 492 493 // Check if this is the Intel OpenCL built-ins calling convention 494 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 495 496 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 497 CCDelegateTo<RetCC_X86_32> 498]>; 499 500//===----------------------------------------------------------------------===// 501// X86-64 Argument Calling Conventions 502//===----------------------------------------------------------------------===// 503 504def CC_X86_64_C : CallingConv<[ 505 // Handles byval parameters. 506 CCIfByVal<CCPassByVal<8, 8>>, 507 508 // Promote i1/i8/i16/v1i1 arguments to i32. 509 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 510 511 // The 'nest' parameter, if any, is passed in R10. 512 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 513 CCIfNest<CCAssignToReg<[R10]>>, 514 515 // Pass SwiftSelf in a callee saved register. 516 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 517 518 // A SwiftError is passed in R12. 519 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 520 521 // Pass SwiftAsync in an otherwise callee saved register so that calls to 522 // normal functions don't need to save it somewhere. 523 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 524 525 // For Swift Calling Conventions, pass sret in %rax. 526 CCIfCC<"CallingConv::Swift", 527 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 528 CCIfCC<"CallingConv::SwiftTail", 529 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 530 531 // Pointers are always passed in full 64-bit registers. 532 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 533 534 // The first 6 integer arguments are passed in integer registers. 535 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 536 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 537 538 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 539 CCIfType<[x86mmx], 540 CCIfSubtarget<"isTargetDarwin()", 541 CCIfSubtarget<"hasSSE2()", 542 CCPromoteToType<v2i64>>>>, 543 544 // Boolean vectors of AVX-512 are passed in SIMD registers. 545 // The call from AVX to AVX-512 function should work, 546 // since the boolean types in AVX/AVX2 are promoted by default. 547 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 548 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 549 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 550 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 551 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 552 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 553 554 // The first 8 FP/Vector arguments are passed in XMM registers. 555 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 556 CCIfSubtarget<"hasSSE1()", 557 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 558 559 // The first 8 256-bit vector arguments are passed in YMM registers, unless 560 // this is a vararg function. 561 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 562 // fixed arguments to vararg functions are supposed to be passed in 563 // registers. Actually modeling that would be a lot of work, though. 564 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 565 CCIfSubtarget<"hasAVX()", 566 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 567 YMM4, YMM5, YMM6, YMM7]>>>>, 568 569 // The first 8 512-bit vector arguments are passed in ZMM registers. 570 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 571 CCIfSubtarget<"hasAVX512()", 572 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 573 574 // Integer/FP values get stored in stack slots that are 8 bytes in size and 575 // 8-byte aligned if there are no more registers to hold them. 576 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 577 578 // Long doubles get stack slots whose size and alignment depends on the 579 // subtarget. 580 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 581 582 // Vectors get 16-byte stack slots that are 16-byte aligned. 583 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 584 585 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 586 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 587 CCAssignToStack<32, 32>>, 588 589 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 590 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 591 CCAssignToStack<64, 64>> 592]>; 593 594// Calling convention for X86-64 HHVM. 595def CC_X86_64_HHVM : CallingConv<[ 596 // Use all/any GP registers for args, except RSP. 597 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, 598 RDI, RSI, RDX, RCX, R8, R9, 599 RAX, R10, R11, R13, R14]>> 600]>; 601 602// Calling convention for helper functions in HHVM. 603def CC_X86_64_HHVM_C : CallingConv<[ 604 // Pass the first argument in RBP. 605 CCIfType<[i64], CCAssignToReg<[RBP]>>, 606 607 // Otherwise it's the same as the regular C calling convention. 608 CCDelegateTo<CC_X86_64_C> 609]>; 610 611// Calling convention used on Win64 612def CC_X86_Win64_C : CallingConv<[ 613 // FIXME: Handle varargs. 614 615 // Byval aggregates are passed by pointer 616 CCIfByVal<CCPassIndirect<i64>>, 617 618 // Promote i1/v1i1 arguments to i8. 619 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 620 621 // The 'nest' parameter, if any, is passed in R10. 622 CCIfNest<CCAssignToReg<[R10]>>, 623 624 // A SwiftError is passed in R12. 625 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 626 627 // Pass SwiftSelf in a callee saved register. 628 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 629 630 // Pass SwiftAsync in an otherwise callee saved register so that calls to 631 // normal functions don't need to save it somewhere. 632 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 633 634 // The 'CFGuardTarget' parameter, if any, is passed in RAX. 635 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>, 636 637 // 128 bit vectors are passed by pointer 638 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>, 639 640 // 256 bit vectors are passed by pointer 641 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 642 643 // 512 bit vectors are passed by pointer 644 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 645 646 // Long doubles are passed by pointer 647 CCIfType<[f80], CCPassIndirect<i64>>, 648 649 // The first 4 MMX vector arguments are passed in GPRs. 650 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 651 652 // If SSE was disabled, pass FP values smaller than 64-bits as integers in 653 // GPRs or on the stack. 654 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 655 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 656 657 // The first 4 FP/Vector arguments are passed in XMM registers. 658 CCIfType<[f32, f64], 659 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 660 [RCX , RDX , R8 , R9 ]>>, 661 662 // The first 4 integer arguments are passed in integer registers. 663 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 664 [XMM0, XMM1, XMM2, XMM3]>>, 665 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 666 [XMM0, XMM1, XMM2, XMM3]>>, 667 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 668 [XMM0, XMM1, XMM2, XMM3]>>, 669 670 // Do not pass the sret argument in RCX, the Win64 thiscall calling 671 // convention requires "this" to be passed in RCX. 672 CCIfCC<"CallingConv::X86_ThisCall", 673 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 674 [XMM1, XMM2, XMM3]>>>>, 675 676 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 677 [XMM0, XMM1, XMM2, XMM3]>>, 678 679 // Integer/FP values get stored in stack slots that are 8 bytes in size and 680 // 8-byte aligned if there are no more registers to hold them. 681 CCIfType<[i8, i16, i32, i64, f32, f64], CCAssignToStack<8, 8>> 682]>; 683 684def CC_X86_Win64_VectorCall : CallingConv<[ 685 CCCustom<"CC_X86_64_VectorCall">, 686 687 // Delegate to fastcall to handle integer types. 688 CCDelegateTo<CC_X86_Win64_C> 689]>; 690 691 692def CC_X86_64_GHC : CallingConv<[ 693 // Promote i8/i16/i32 arguments to i64. 694 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 695 696 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 697 CCIfType<[i64], 698 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 699 700 // Pass in STG registers: F1, F2, F3, F4, D1, D2 701 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 702 CCIfSubtarget<"hasSSE1()", 703 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 704 // AVX 705 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 706 CCIfSubtarget<"hasAVX()", 707 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 708 // AVX-512 709 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 710 CCIfSubtarget<"hasAVX512()", 711 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 712]>; 713 714def CC_X86_64_HiPE : CallingConv<[ 715 // Promote i8/i16/i32 arguments to i64. 716 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 717 718 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 719 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 720 721 // Integer/FP values get stored in stack slots that are 8 bytes in size and 722 // 8-byte aligned if there are no more registers to hold them. 723 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 724]>; 725 726def CC_X86_64_WebKit_JS : CallingConv<[ 727 // Promote i8/i16 arguments to i32. 728 CCIfType<[i8, i16], CCPromoteToType<i32>>, 729 730 // Only the first integer argument is passed in register. 731 CCIfType<[i32], CCAssignToReg<[EAX]>>, 732 CCIfType<[i64], CCAssignToReg<[RAX]>>, 733 734 // The remaining integer arguments are passed on the stack. 32bit integer and 735 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 736 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 737 // in 8 byte stack slots. 738 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 739 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 740]>; 741 742// No explicit register is specified for the AnyReg calling convention. The 743// register allocator may assign the arguments to any free register. 744// 745// This calling convention is currently only supported by the stackmap and 746// patchpoint intrinsics. All other uses will result in an assert on Debug 747// builds. On Release builds we fallback to the X86 C calling convention. 748def CC_X86_64_AnyReg : CallingConv<[ 749 CCCustom<"CC_X86_AnyReg_Error"> 750]>; 751 752//===----------------------------------------------------------------------===// 753// X86 C Calling Convention 754//===----------------------------------------------------------------------===// 755 756/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 757/// values are spilled on the stack. 758def CC_X86_32_Vector_Common : CallingConv<[ 759 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 760 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 761 762 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 763 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 764 CCAssignToStack<32, 32>>, 765 766 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 767 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 768 CCAssignToStack<64, 64>> 769]>; 770 771// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 772// vector registers 773def CC_X86_32_Vector_Standard : CallingConv<[ 774 // SSE vector arguments are passed in XMM registers. 775 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 776 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 777 778 // AVX 256-bit vector arguments are passed in YMM registers. 779 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 780 CCIfSubtarget<"hasAVX()", 781 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 782 783 // AVX 512-bit vector arguments are passed in ZMM registers. 784 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 785 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 786 787 CCDelegateTo<CC_X86_32_Vector_Common> 788]>; 789 790// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 791// vector registers. 792def CC_X86_32_Vector_Darwin : CallingConv<[ 793 // SSE vector arguments are passed in XMM registers. 794 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 795 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 796 797 // AVX 256-bit vector arguments are passed in YMM registers. 798 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 799 CCIfSubtarget<"hasAVX()", 800 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 801 802 // AVX 512-bit vector arguments are passed in ZMM registers. 803 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 804 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 805 806 CCDelegateTo<CC_X86_32_Vector_Common> 807]>; 808 809/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 810/// values are spilled on the stack. 811def CC_X86_32_Common : CallingConv<[ 812 // Handles byval/preallocated parameters. 813 CCIfByVal<CCPassByVal<4, 4>>, 814 CCIfPreallocated<CCPassByVal<4, 4>>, 815 816 // The first 3 float or double arguments, if marked 'inreg' and if the call 817 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 818 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 819 CCIfSubtarget<"hasSSE2()", 820 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 821 822 // The first 3 __m64 vector arguments are passed in mmx registers if the 823 // call is not a vararg call. 824 CCIfNotVarArg<CCIfType<[x86mmx], 825 CCAssignToReg<[MM0, MM1, MM2]>>>, 826 827 // Integer/Float values get stored in stack slots that are 4 bytes in 828 // size and 4-byte aligned. 829 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 830 831 // Doubles get 8-byte slots that are 4-byte aligned. 832 CCIfType<[f64], CCAssignToStack<8, 4>>, 833 834 // Long doubles get slots whose size depends on the subtarget. 835 CCIfType<[f80], CCAssignToStack<0, 4>>, 836 837 // Boolean vectors of AVX-512 are passed in SIMD registers. 838 // The call from AVX to AVX-512 function should work, 839 // since the boolean types in AVX/AVX2 are promoted by default. 840 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 841 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 842 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 843 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 844 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 845 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 846 847 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 848 // passed in the parameter area. 849 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 850 851 // Darwin passes vectors in a form that differs from the i386 psABI 852 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 853 854 // Otherwise, drop to 'normal' X86-32 CC 855 CCDelegateTo<CC_X86_32_Vector_Standard> 856]>; 857 858def CC_X86_32_C : CallingConv<[ 859 // Promote i1/i8/i16/v1i1 arguments to i32. 860 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 861 862 // The 'nest' parameter, if any, is passed in ECX. 863 CCIfNest<CCAssignToReg<[ECX]>>, 864 865 // On swifttailcc pass swiftself in ECX. 866 CCIfCC<"CallingConv::SwiftTail", 867 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[ECX]>>>>, 868 869 // The first 3 integer arguments, if marked 'inreg' and if the call is not 870 // a vararg call, are passed in integer registers. 871 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 872 873 // Otherwise, same as everything else. 874 CCDelegateTo<CC_X86_32_Common> 875]>; 876 877def CC_X86_32_MCU : CallingConv<[ 878 // Handles byval parameters. Note that, like FastCC, we can't rely on 879 // the delegation to CC_X86_32_Common because that happens after code that 880 // puts arguments in registers. 881 CCIfByVal<CCPassByVal<4, 4>>, 882 883 // Promote i1/i8/i16/v1i1 arguments to i32. 884 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 885 886 // If the call is not a vararg call, some arguments may be passed 887 // in integer registers. 888 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 889 890 // Otherwise, same as everything else. 891 CCDelegateTo<CC_X86_32_Common> 892]>; 893 894def CC_X86_32_FastCall : CallingConv<[ 895 // Promote i1 to i8. 896 CCIfType<[i1], CCPromoteToType<i8>>, 897 898 // The 'nest' parameter, if any, is passed in EAX. 899 CCIfNest<CCAssignToReg<[EAX]>>, 900 901 // The first 2 integer arguments are passed in ECX/EDX 902 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 903 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 904 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 905 906 // Otherwise, same as everything else. 907 CCDelegateTo<CC_X86_32_Common> 908]>; 909 910def CC_X86_Win32_VectorCall : CallingConv<[ 911 // Pass floating point in XMMs 912 CCCustom<"CC_X86_32_VectorCall">, 913 914 // Delegate to fastcall to handle integer types. 915 CCDelegateTo<CC_X86_32_FastCall> 916]>; 917 918def CC_X86_32_ThisCall_Common : CallingConv<[ 919 // The first integer argument is passed in ECX 920 CCIfType<[i32], CCAssignToReg<[ECX]>>, 921 922 // Otherwise, same as everything else. 923 CCDelegateTo<CC_X86_32_Common> 924]>; 925 926def CC_X86_32_ThisCall_Mingw : CallingConv<[ 927 // Promote i1/i8/i16/v1i1 arguments to i32. 928 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 929 930 CCDelegateTo<CC_X86_32_ThisCall_Common> 931]>; 932 933def CC_X86_32_ThisCall_Win : CallingConv<[ 934 // Promote i1/i8/i16/v1i1 arguments to i32. 935 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 936 937 // Pass sret arguments indirectly through stack. 938 CCIfSRet<CCAssignToStack<4, 4>>, 939 940 CCDelegateTo<CC_X86_32_ThisCall_Common> 941]>; 942 943def CC_X86_32_ThisCall : CallingConv<[ 944 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 945 CCDelegateTo<CC_X86_32_ThisCall_Win> 946]>; 947 948def CC_X86_32_FastCC : CallingConv<[ 949 // Handles byval parameters. Note that we can't rely on the delegation 950 // to CC_X86_32_Common for this because that happens after code that 951 // puts arguments in registers. 952 CCIfByVal<CCPassByVal<4, 4>>, 953 954 // Promote i1/i8/i16/v1i1 arguments to i32. 955 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 956 957 // The 'nest' parameter, if any, is passed in EAX. 958 CCIfNest<CCAssignToReg<[EAX]>>, 959 960 // The first 2 integer arguments are passed in ECX/EDX 961 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 962 963 // The first 3 float or double arguments, if the call is not a vararg 964 // call and if SSE2 is available, are passed in SSE registers. 965 CCIfNotVarArg<CCIfType<[f32,f64], 966 CCIfSubtarget<"hasSSE2()", 967 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 968 969 // Doubles get 8-byte slots that are 8-byte aligned. 970 CCIfType<[f64], CCAssignToStack<8, 8>>, 971 972 // Otherwise, same as everything else. 973 CCDelegateTo<CC_X86_32_Common> 974]>; 975 976def CC_X86_Win32_CFGuard_Check : CallingConv<[ 977 // The CFGuard check call takes exactly one integer argument 978 // (i.e. the target function address), which is passed in ECX. 979 CCIfType<[i32], CCAssignToReg<[ECX]>> 980]>; 981 982def CC_X86_32_GHC : CallingConv<[ 983 // Promote i8/i16 arguments to i32. 984 CCIfType<[i8, i16], CCPromoteToType<i32>>, 985 986 // Pass in STG registers: Base, Sp, Hp, R1 987 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 988]>; 989 990def CC_X86_32_HiPE : CallingConv<[ 991 // Promote i8/i16 arguments to i32. 992 CCIfType<[i8, i16], CCPromoteToType<i32>>, 993 994 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 995 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 996 997 // Integer/Float values get stored in stack slots that are 4 bytes in 998 // size and 4-byte aligned. 999 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 1000]>; 1001 1002// X86-64 Intel OpenCL built-ins calling convention. 1003def CC_Intel_OCL_BI : CallingConv<[ 1004 1005 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 1006 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 1007 1008 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 1009 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 1010 1011 CCIfType<[i32], CCAssignToStack<4, 4>>, 1012 1013 // The SSE vector arguments are passed in XMM registers. 1014 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 1015 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 1016 1017 // The 256-bit vector arguments are passed in YMM registers. 1018 CCIfType<[v8f32, v4f64, v8i32, v4i64], 1019 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 1020 1021 // The 512-bit vector arguments are passed in ZMM registers. 1022 CCIfType<[v16f32, v8f64, v16i32, v8i64], 1023 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 1024 1025 // Pass masks in mask registers 1026 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 1027 1028 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1029 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 1030 CCDelegateTo<CC_X86_32_C> 1031]>; 1032 1033//===----------------------------------------------------------------------===// 1034// X86 Root Argument Calling Conventions 1035//===----------------------------------------------------------------------===// 1036 1037// This is the root argument convention for the X86-32 backend. 1038def CC_X86_32 : CallingConv<[ 1039 // X86_INTR calling convention is valid in MCU target and should override the 1040 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 1041 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1042 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1043 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1044 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1045 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1046 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>, 1047 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1048 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1049 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1050 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1051 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1052 1053 // Otherwise, drop to normal X86-32 CC 1054 CCDelegateTo<CC_X86_32_C> 1055]>; 1056 1057// This is the root argument convention for the X86-64 backend. 1058def CC_X86_64 : CallingConv<[ 1059 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1060 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1061 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 1062 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1063 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1064 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1065 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1066 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>, 1067 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>, 1068 CCIfCC<"CallingConv::X86_RegCall", 1069 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1070 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1071 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1072 1073 // Mingw64 and native Win64 use Win64 CC 1074 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1075 1076 // Otherwise, drop to normal X86-64 CC 1077 CCDelegateTo<CC_X86_64_C> 1078]>; 1079 1080// This is the argument convention used for the entire X86 backend. 1081let Entry = 1 in 1082def CC_X86 : CallingConv<[ 1083 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1084 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1085 CCDelegateTo<CC_X86_32> 1086]>; 1087 1088//===----------------------------------------------------------------------===// 1089// Callee-saved Registers. 1090//===----------------------------------------------------------------------===// 1091 1092def CSR_NoRegs : CalleeSavedRegs<(add)>; 1093 1094def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1095def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1096 1097def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1098def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>; 1099 1100def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1101def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1102 1103def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1104 1105def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1106 (sequence "XMM%u", 6, 15))>; 1107 1108def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1109def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>; 1110 1111// The function used by Darwin to obtain the address of a thread-local variable 1112// uses rdi to pass a single parameter and rax for the return value. All other 1113// GPRs are preserved. 1114def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1115 R8, R9, R10, R11)>; 1116 1117// CSRs that are handled by prologue, epilogue. 1118def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1119 1120// CSRs that are handled explicitly via copies. 1121def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1122 1123// All GPRs - except r11 1124def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1125 R8, R9, R10)>; 1126 1127// All registers - except r11 1128def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1129 (sequence "XMM%u", 0, 15))>; 1130def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1131 (sequence "YMM%u", 0, 15))>; 1132 1133def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1134 R11, R12, R13, R14, R15, RBP, 1135 (sequence "XMM%u", 0, 15))>; 1136 1137def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1138 EDI)>; 1139def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1140 (sequence "XMM%u", 0, 7))>; 1141def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1142 (sequence "YMM%u", 0, 7))>; 1143def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1144 (sequence "ZMM%u", 0, 7), 1145 (sequence "K%u", 0, 7))>; 1146 1147def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1148def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1149 R10, R11, R12, R13, R14, R15, RBP)>; 1150def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1151 (sequence "YMM%u", 0, 15)), 1152 (sequence "XMM%u", 0, 15))>; 1153def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1154 (sequence "ZMM%u", 0, 31), 1155 (sequence "K%u", 0, 7)), 1156 (sequence "XMM%u", 0, 15))>; 1157 1158// Standard C + YMM6-15 1159def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1160 R13, R14, R15, 1161 (sequence "YMM%u", 6, 15))>; 1162 1163def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1164 R12, R13, R14, R15, 1165 (sequence "ZMM%u", 6, 21), 1166 K4, K5, K6, K7)>; 1167//Standard C + XMM 8-15 1168def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1169 (sequence "XMM%u", 8, 15))>; 1170 1171//Standard C + YMM 8-15 1172def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1173 (sequence "YMM%u", 8, 15))>; 1174 1175def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15, 1176 (sequence "ZMM%u", 16, 31), 1177 K4, K5, K6, K7)>; 1178 1179// Only R12 is preserved for PHP calls in HHVM. 1180def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; 1181 1182// Register calling convention preserves few GPR and XMM8-15 1183def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1184def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1185 (sequence "XMM%u", 4, 7))>; 1186def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>; 1187def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>; 1188def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1189 (sequence "R%u", 10, 15))>; 1190def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1191 (sequence "XMM%u", 8, 15))>; 1192def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1193 (sequence "R%u", 12, 15))>; 1194def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1195 (sequence "XMM%u", 8, 15))>; 1196